157e252bfSMichael Neumann /*
257e252bfSMichael Neumann * Copyright 2011 Advanced Micro Devices, Inc.
357e252bfSMichael Neumann *
457e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a
557e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"),
657e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation
757e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense,
857e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the
957e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions:
1057e252bfSMichael Neumann *
1157e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in
1257e252bfSMichael Neumann * all copies or substantial portions of the Software.
1357e252bfSMichael Neumann *
1457e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1557e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1657e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1757e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1857e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1957e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2057e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE.
2157e252bfSMichael Neumann *
2257e252bfSMichael Neumann * Authors: Alex Deucher
2357e252bfSMichael Neumann */
2457e252bfSMichael Neumann
2557e252bfSMichael Neumann #include <linux/firmware.h>
26*3f2dd94aSFrançois Tigeot #include <drm/drmP.h>
2757e252bfSMichael Neumann #include "radeon.h"
2857e252bfSMichael Neumann #include "sid.h"
2957e252bfSMichael Neumann #include "ppsmc.h"
3057e252bfSMichael Neumann #include "radeon_ucode.h"
31c6f73aabSFrançois Tigeot #include "sislands_smc.h"
3257e252bfSMichael Neumann
si_set_smc_sram_address(struct radeon_device * rdev,u32 smc_address,u32 limit)33c6f73aabSFrançois Tigeot static int si_set_smc_sram_address(struct radeon_device *rdev,
3457e252bfSMichael Neumann u32 smc_address, u32 limit)
3557e252bfSMichael Neumann {
3657e252bfSMichael Neumann if (smc_address & 3)
3757e252bfSMichael Neumann return -EINVAL;
3857e252bfSMichael Neumann if ((smc_address + 3) > limit)
3957e252bfSMichael Neumann return -EINVAL;
4057e252bfSMichael Neumann
4157e252bfSMichael Neumann WREG32(SMC_IND_INDEX_0, smc_address);
4257e252bfSMichael Neumann WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
4357e252bfSMichael Neumann
4457e252bfSMichael Neumann return 0;
4557e252bfSMichael Neumann }
4657e252bfSMichael Neumann
si_copy_bytes_to_smc(struct radeon_device * rdev,u32 smc_start_address,const u8 * src,u32 byte_count,u32 limit)4757e252bfSMichael Neumann int si_copy_bytes_to_smc(struct radeon_device *rdev,
4857e252bfSMichael Neumann u32 smc_start_address,
4957e252bfSMichael Neumann const u8 *src, u32 byte_count, u32 limit)
5057e252bfSMichael Neumann {
51a85cb24fSFrançois Tigeot unsigned long flags;
52c6f73aabSFrançois Tigeot int ret = 0;
5357e252bfSMichael Neumann u32 data, original_data, addr, extra_shift;
5457e252bfSMichael Neumann
5557e252bfSMichael Neumann if (smc_start_address & 3)
5657e252bfSMichael Neumann return -EINVAL;
5757e252bfSMichael Neumann if ((smc_start_address + byte_count) > limit)
5857e252bfSMichael Neumann return -EINVAL;
5957e252bfSMichael Neumann
6057e252bfSMichael Neumann addr = smc_start_address;
6157e252bfSMichael Neumann
62a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->smc_idx_lock, flags);
6357e252bfSMichael Neumann while (byte_count >= 4) {
6457e252bfSMichael Neumann /* SMC address space is BE */
6557e252bfSMichael Neumann data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
6657e252bfSMichael Neumann
6757e252bfSMichael Neumann ret = si_set_smc_sram_address(rdev, addr, limit);
6857e252bfSMichael Neumann if (ret)
69c6f73aabSFrançois Tigeot goto done;
7057e252bfSMichael Neumann
7157e252bfSMichael Neumann WREG32(SMC_IND_DATA_0, data);
7257e252bfSMichael Neumann
7357e252bfSMichael Neumann src += 4;
7457e252bfSMichael Neumann byte_count -= 4;
7557e252bfSMichael Neumann addr += 4;
7657e252bfSMichael Neumann }
7757e252bfSMichael Neumann
7857e252bfSMichael Neumann /* RMW for the final bytes */
7957e252bfSMichael Neumann if (byte_count > 0) {
8057e252bfSMichael Neumann data = 0;
8157e252bfSMichael Neumann
8257e252bfSMichael Neumann ret = si_set_smc_sram_address(rdev, addr, limit);
8357e252bfSMichael Neumann if (ret)
84c6f73aabSFrançois Tigeot goto done;
8557e252bfSMichael Neumann
8657e252bfSMichael Neumann original_data = RREG32(SMC_IND_DATA_0);
8757e252bfSMichael Neumann
8857e252bfSMichael Neumann extra_shift = 8 * (4 - byte_count);
8957e252bfSMichael Neumann
9057e252bfSMichael Neumann while (byte_count > 0) {
9157e252bfSMichael Neumann /* SMC address space is BE */
9257e252bfSMichael Neumann data = (data << 8) + *src++;
9357e252bfSMichael Neumann byte_count--;
9457e252bfSMichael Neumann }
9557e252bfSMichael Neumann
9657e252bfSMichael Neumann data <<= extra_shift;
9757e252bfSMichael Neumann
9857e252bfSMichael Neumann data |= (original_data & ~((~0UL) << extra_shift));
9957e252bfSMichael Neumann
10057e252bfSMichael Neumann ret = si_set_smc_sram_address(rdev, addr, limit);
10157e252bfSMichael Neumann if (ret)
102c6f73aabSFrançois Tigeot goto done;
10357e252bfSMichael Neumann
10457e252bfSMichael Neumann WREG32(SMC_IND_DATA_0, data);
10557e252bfSMichael Neumann }
106c6f73aabSFrançois Tigeot
107c6f73aabSFrançois Tigeot done:
108a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
109c6f73aabSFrançois Tigeot
110c6f73aabSFrançois Tigeot return ret;
11157e252bfSMichael Neumann }
11257e252bfSMichael Neumann
si_start_smc(struct radeon_device * rdev)11357e252bfSMichael Neumann void si_start_smc(struct radeon_device *rdev)
11457e252bfSMichael Neumann {
11557e252bfSMichael Neumann u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
11657e252bfSMichael Neumann
11757e252bfSMichael Neumann tmp &= ~RST_REG;
11857e252bfSMichael Neumann
11957e252bfSMichael Neumann WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
12057e252bfSMichael Neumann }
12157e252bfSMichael Neumann
si_reset_smc(struct radeon_device * rdev)12257e252bfSMichael Neumann void si_reset_smc(struct radeon_device *rdev)
12357e252bfSMichael Neumann {
12457e252bfSMichael Neumann u32 tmp;
12557e252bfSMichael Neumann
12657e252bfSMichael Neumann RREG32(CB_CGTT_SCLK_CTRL);
12757e252bfSMichael Neumann RREG32(CB_CGTT_SCLK_CTRL);
12857e252bfSMichael Neumann RREG32(CB_CGTT_SCLK_CTRL);
12957e252bfSMichael Neumann RREG32(CB_CGTT_SCLK_CTRL);
13057e252bfSMichael Neumann
13157e252bfSMichael Neumann tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
13257e252bfSMichael Neumann tmp |= RST_REG;
13357e252bfSMichael Neumann WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
13457e252bfSMichael Neumann }
13557e252bfSMichael Neumann
si_program_jump_on_start(struct radeon_device * rdev)13657e252bfSMichael Neumann int si_program_jump_on_start(struct radeon_device *rdev)
13757e252bfSMichael Neumann {
1387dcf36dcSFrançois Tigeot static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
13957e252bfSMichael Neumann
14057e252bfSMichael Neumann return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
14157e252bfSMichael Neumann }
14257e252bfSMichael Neumann
si_stop_smc_clock(struct radeon_device * rdev)14357e252bfSMichael Neumann void si_stop_smc_clock(struct radeon_device *rdev)
14457e252bfSMichael Neumann {
14557e252bfSMichael Neumann u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
14657e252bfSMichael Neumann
14757e252bfSMichael Neumann tmp |= CK_DISABLE;
14857e252bfSMichael Neumann
14957e252bfSMichael Neumann WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
15057e252bfSMichael Neumann }
15157e252bfSMichael Neumann
si_start_smc_clock(struct radeon_device * rdev)15257e252bfSMichael Neumann void si_start_smc_clock(struct radeon_device *rdev)
15357e252bfSMichael Neumann {
15457e252bfSMichael Neumann u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
15557e252bfSMichael Neumann
15657e252bfSMichael Neumann tmp &= ~CK_DISABLE;
15757e252bfSMichael Neumann
15857e252bfSMichael Neumann WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
15957e252bfSMichael Neumann }
16057e252bfSMichael Neumann
si_is_smc_running(struct radeon_device * rdev)16157e252bfSMichael Neumann bool si_is_smc_running(struct radeon_device *rdev)
16257e252bfSMichael Neumann {
16357e252bfSMichael Neumann u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
16457e252bfSMichael Neumann u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
16557e252bfSMichael Neumann
16657e252bfSMichael Neumann if (!(rst & RST_REG) && !(clk & CK_DISABLE))
16757e252bfSMichael Neumann return true;
16857e252bfSMichael Neumann
16957e252bfSMichael Neumann return false;
17057e252bfSMichael Neumann }
17157e252bfSMichael Neumann
si_send_msg_to_smc(struct radeon_device * rdev,PPSMC_Msg msg)17257e252bfSMichael Neumann PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
17357e252bfSMichael Neumann {
17457e252bfSMichael Neumann u32 tmp;
17557e252bfSMichael Neumann int i;
17657e252bfSMichael Neumann
17757e252bfSMichael Neumann if (!si_is_smc_running(rdev))
17857e252bfSMichael Neumann return PPSMC_Result_Failed;
17957e252bfSMichael Neumann
18057e252bfSMichael Neumann WREG32(SMC_MESSAGE_0, msg);
18157e252bfSMichael Neumann
18257e252bfSMichael Neumann for (i = 0; i < rdev->usec_timeout; i++) {
18357e252bfSMichael Neumann tmp = RREG32(SMC_RESP_0);
18457e252bfSMichael Neumann if (tmp != 0)
18557e252bfSMichael Neumann break;
186c4ef309bSzrj udelay(1);
18757e252bfSMichael Neumann }
18857e252bfSMichael Neumann tmp = RREG32(SMC_RESP_0);
18957e252bfSMichael Neumann
19057e252bfSMichael Neumann return (PPSMC_Result)tmp;
19157e252bfSMichael Neumann }
19257e252bfSMichael Neumann
si_wait_for_smc_inactive(struct radeon_device * rdev)19357e252bfSMichael Neumann PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
19457e252bfSMichael Neumann {
19557e252bfSMichael Neumann u32 tmp;
19657e252bfSMichael Neumann int i;
19757e252bfSMichael Neumann
19857e252bfSMichael Neumann if (!si_is_smc_running(rdev))
19957e252bfSMichael Neumann return PPSMC_Result_OK;
20057e252bfSMichael Neumann
20157e252bfSMichael Neumann for (i = 0; i < rdev->usec_timeout; i++) {
20257e252bfSMichael Neumann tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
20357e252bfSMichael Neumann if ((tmp & CKEN) == 0)
20457e252bfSMichael Neumann break;
205c4ef309bSzrj udelay(1);
20657e252bfSMichael Neumann }
20757e252bfSMichael Neumann
20857e252bfSMichael Neumann return PPSMC_Result_OK;
20957e252bfSMichael Neumann }
21057e252bfSMichael Neumann
si_load_smc_ucode(struct radeon_device * rdev,u32 limit)21157e252bfSMichael Neumann int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
21257e252bfSMichael Neumann {
213a85cb24fSFrançois Tigeot unsigned long flags;
21457e252bfSMichael Neumann u32 ucode_start_address;
21557e252bfSMichael Neumann u32 ucode_size;
21657e252bfSMichael Neumann const u8 *src;
21757e252bfSMichael Neumann u32 data;
21857e252bfSMichael Neumann
21957e252bfSMichael Neumann if (!rdev->smc_fw)
22057e252bfSMichael Neumann return -EINVAL;
22157e252bfSMichael Neumann
222cb754608SImre Vadász if (rdev->new_fw) {
223cb754608SImre Vadász const struct smc_firmware_header_v1_0 *hdr =
224cb754608SImre Vadász (const struct smc_firmware_header_v1_0 *)rdev->smc_fw->data;
225cb754608SImre Vadász
226cb754608SImre Vadász radeon_ucode_print_smc_hdr(&hdr->header);
227cb754608SImre Vadász
228cb754608SImre Vadász ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
229cb754608SImre Vadász ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
230cb754608SImre Vadász src = (const u8 *)
231a85cb24fSFrançois Tigeot (rdev->smc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
232cb754608SImre Vadász } else {
23357e252bfSMichael Neumann switch (rdev->family) {
23457e252bfSMichael Neumann case CHIP_TAHITI:
23557e252bfSMichael Neumann ucode_start_address = TAHITI_SMC_UCODE_START;
23657e252bfSMichael Neumann ucode_size = TAHITI_SMC_UCODE_SIZE;
23757e252bfSMichael Neumann break;
23857e252bfSMichael Neumann case CHIP_PITCAIRN:
23957e252bfSMichael Neumann ucode_start_address = PITCAIRN_SMC_UCODE_START;
24057e252bfSMichael Neumann ucode_size = PITCAIRN_SMC_UCODE_SIZE;
24157e252bfSMichael Neumann break;
24257e252bfSMichael Neumann case CHIP_VERDE:
24357e252bfSMichael Neumann ucode_start_address = VERDE_SMC_UCODE_START;
24457e252bfSMichael Neumann ucode_size = VERDE_SMC_UCODE_SIZE;
24557e252bfSMichael Neumann break;
24657e252bfSMichael Neumann case CHIP_OLAND:
24757e252bfSMichael Neumann ucode_start_address = OLAND_SMC_UCODE_START;
24857e252bfSMichael Neumann ucode_size = OLAND_SMC_UCODE_SIZE;
24957e252bfSMichael Neumann break;
25057e252bfSMichael Neumann case CHIP_HAINAN:
25157e252bfSMichael Neumann ucode_start_address = HAINAN_SMC_UCODE_START;
25257e252bfSMichael Neumann ucode_size = HAINAN_SMC_UCODE_SIZE;
25357e252bfSMichael Neumann break;
25457e252bfSMichael Neumann default:
25557e252bfSMichael Neumann DRM_ERROR("unknown asic in smc ucode loader\n");
25657e252bfSMichael Neumann BUG();
25757e252bfSMichael Neumann }
258cb754608SImre Vadász src = (const u8 *)rdev->smc_fw->data;
259cb754608SImre Vadász }
26057e252bfSMichael Neumann
26157e252bfSMichael Neumann if (ucode_size & 3)
26257e252bfSMichael Neumann return -EINVAL;
26357e252bfSMichael Neumann
264a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->smc_idx_lock, flags);
26557e252bfSMichael Neumann WREG32(SMC_IND_INDEX_0, ucode_start_address);
26657e252bfSMichael Neumann WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
26757e252bfSMichael Neumann while (ucode_size >= 4) {
26857e252bfSMichael Neumann /* SMC address space is BE */
26957e252bfSMichael Neumann data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
27057e252bfSMichael Neumann
27157e252bfSMichael Neumann WREG32(SMC_IND_DATA_0, data);
27257e252bfSMichael Neumann
27357e252bfSMichael Neumann src += 4;
27457e252bfSMichael Neumann ucode_size -= 4;
27557e252bfSMichael Neumann }
27657e252bfSMichael Neumann WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
277a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
27857e252bfSMichael Neumann
27957e252bfSMichael Neumann return 0;
28057e252bfSMichael Neumann }
28157e252bfSMichael Neumann
si_read_smc_sram_dword(struct radeon_device * rdev,u32 smc_address,u32 * value,u32 limit)28257e252bfSMichael Neumann int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
28357e252bfSMichael Neumann u32 *value, u32 limit)
28457e252bfSMichael Neumann {
285a85cb24fSFrançois Tigeot unsigned long flags;
28657e252bfSMichael Neumann int ret;
28757e252bfSMichael Neumann
288a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->smc_idx_lock, flags);
28957e252bfSMichael Neumann ret = si_set_smc_sram_address(rdev, smc_address, limit);
290c6f73aabSFrançois Tigeot if (ret == 0)
29157e252bfSMichael Neumann *value = RREG32(SMC_IND_DATA_0);
292a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
293c6f73aabSFrançois Tigeot
294c6f73aabSFrançois Tigeot return ret;
29557e252bfSMichael Neumann }
29657e252bfSMichael Neumann
si_write_smc_sram_dword(struct radeon_device * rdev,u32 smc_address,u32 value,u32 limit)29757e252bfSMichael Neumann int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
29857e252bfSMichael Neumann u32 value, u32 limit)
29957e252bfSMichael Neumann {
300a85cb24fSFrançois Tigeot unsigned long flags;
30157e252bfSMichael Neumann int ret;
30257e252bfSMichael Neumann
303a85cb24fSFrançois Tigeot spin_lock_irqsave(&rdev->smc_idx_lock, flags);
30457e252bfSMichael Neumann ret = si_set_smc_sram_address(rdev, smc_address, limit);
305c6f73aabSFrançois Tigeot if (ret == 0)
30657e252bfSMichael Neumann WREG32(SMC_IND_DATA_0, value);
307a85cb24fSFrançois Tigeot spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
308c6f73aabSFrançois Tigeot
309c6f73aabSFrançois Tigeot return ret;
31057e252bfSMichael Neumann }
311