xref: /dragonfly/sys/dev/drm/radeon/si_smc.c (revision b0d289c2)
1 /*
2  * Copyright 2011 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/firmware.h>
26 #include <drm/drmP.h>
27 #include "radeon.h"
28 #include "sid.h"
29 #include "ppsmc.h"
30 #include "radeon_ucode.h"
31 
32 int si_set_smc_sram_address(struct radeon_device *rdev,
33 			    u32 smc_address, u32 limit);
34 int si_copy_bytes_to_smc(struct radeon_device *rdev,
35 			 u32 smc_start_address,
36 			 const u8 *src, u32 byte_count, u32 limit);
37 void si_start_smc(struct radeon_device *rdev);
38 void si_reset_smc(struct radeon_device *rdev);
39 int si_program_jump_on_start(struct radeon_device *rdev);
40 void si_stop_smc_clock(struct radeon_device *rdev);
41 void si_start_smc_clock(struct radeon_device *rdev);
42 bool si_is_smc_running(struct radeon_device *rdev);
43 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
44 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev);
45 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit);
46 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
47 			   u32 *value, u32 limit);
48 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
49 			    u32 value, u32 limit);
50 
51 int si_set_smc_sram_address(struct radeon_device *rdev,
52 			    u32 smc_address, u32 limit)
53 {
54 	if (smc_address & 3)
55 		return -EINVAL;
56 	if ((smc_address + 3) > limit)
57 		return -EINVAL;
58 
59 	WREG32(SMC_IND_INDEX_0, smc_address);
60 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
61 
62 	return 0;
63 }
64 
65 int si_copy_bytes_to_smc(struct radeon_device *rdev,
66 			 u32 smc_start_address,
67 			 const u8 *src, u32 byte_count, u32 limit)
68 {
69 	int ret;
70 	u32 data, original_data, addr, extra_shift;
71 
72 	if (smc_start_address & 3)
73 		return -EINVAL;
74 	if ((smc_start_address + byte_count) > limit)
75 		return -EINVAL;
76 
77 	addr = smc_start_address;
78 
79 	while (byte_count >= 4) {
80 		/* SMC address space is BE */
81 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
82 
83 		ret = si_set_smc_sram_address(rdev, addr, limit);
84 		if (ret)
85 			return ret;
86 
87 		WREG32(SMC_IND_DATA_0, data);
88 
89 		src += 4;
90 		byte_count -= 4;
91 		addr += 4;
92 	}
93 
94 	/* RMW for the final bytes */
95 	if (byte_count > 0) {
96 		data = 0;
97 
98 		ret = si_set_smc_sram_address(rdev, addr, limit);
99 		if (ret)
100 			return ret;
101 
102 		original_data = RREG32(SMC_IND_DATA_0);
103 
104 		extra_shift = 8 * (4 - byte_count);
105 
106 		while (byte_count > 0) {
107 			/* SMC address space is BE */
108 			data = (data << 8) + *src++;
109 			byte_count--;
110 		}
111 
112 		data <<= extra_shift;
113 
114 		data |= (original_data & ~((~0UL) << extra_shift));
115 
116 		ret = si_set_smc_sram_address(rdev, addr, limit);
117 		if (ret)
118 			return ret;
119 
120 		WREG32(SMC_IND_DATA_0, data);
121 	}
122 	return 0;
123 }
124 
125 void si_start_smc(struct radeon_device *rdev)
126 {
127 	u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
128 
129 	tmp &= ~RST_REG;
130 
131 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
132 }
133 
134 void si_reset_smc(struct radeon_device *rdev)
135 {
136 	u32 tmp;
137 
138 	RREG32(CB_CGTT_SCLK_CTRL);
139 	RREG32(CB_CGTT_SCLK_CTRL);
140 	RREG32(CB_CGTT_SCLK_CTRL);
141 	RREG32(CB_CGTT_SCLK_CTRL);
142 
143 	tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
144 	tmp |= RST_REG;
145 	WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
146 }
147 
148 int si_program_jump_on_start(struct radeon_device *rdev)
149 {
150 	static u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
151 
152 	return si_copy_bytes_to_smc(rdev, 0x0, data, 4, sizeof(data)+1);
153 }
154 
155 void si_stop_smc_clock(struct radeon_device *rdev)
156 {
157 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
158 
159 	tmp |= CK_DISABLE;
160 
161 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
162 }
163 
164 void si_start_smc_clock(struct radeon_device *rdev)
165 {
166 	u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
167 
168 	tmp &= ~CK_DISABLE;
169 
170 	WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
171 }
172 
173 bool si_is_smc_running(struct radeon_device *rdev)
174 {
175 	u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
176 	u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
177 
178 	if (!(rst & RST_REG) && !(clk & CK_DISABLE))
179 		return true;
180 
181 	return false;
182 }
183 
184 PPSMC_Result si_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg)
185 {
186 	u32 tmp;
187 	int i;
188 
189 	if (!si_is_smc_running(rdev))
190 		return PPSMC_Result_Failed;
191 
192 	WREG32(SMC_MESSAGE_0, msg);
193 
194 	for (i = 0; i < rdev->usec_timeout; i++) {
195 		tmp = RREG32(SMC_RESP_0);
196 		if (tmp != 0)
197 			break;
198 		udelay(1);
199 	}
200 	tmp = RREG32(SMC_RESP_0);
201 
202 	return (PPSMC_Result)tmp;
203 }
204 
205 PPSMC_Result si_wait_for_smc_inactive(struct radeon_device *rdev)
206 {
207 	u32 tmp;
208 	int i;
209 
210 	if (!si_is_smc_running(rdev))
211 		return PPSMC_Result_OK;
212 
213 	for (i = 0; i < rdev->usec_timeout; i++) {
214 		tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
215 		if ((tmp & CKEN) == 0)
216 			break;
217 		udelay(1);
218 	}
219 
220 	return PPSMC_Result_OK;
221 }
222 
223 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit)
224 {
225 	u32 ucode_start_address;
226 	u32 ucode_size;
227 	const u8 *src;
228 	u32 data;
229 
230 	if (!rdev->smc_fw)
231 		return -EINVAL;
232 
233 	switch (rdev->family) {
234 	case CHIP_TAHITI:
235 		ucode_start_address = TAHITI_SMC_UCODE_START;
236 		ucode_size = TAHITI_SMC_UCODE_SIZE;
237 		break;
238 	case CHIP_PITCAIRN:
239 		ucode_start_address = PITCAIRN_SMC_UCODE_START;
240 		ucode_size = PITCAIRN_SMC_UCODE_SIZE;
241 		break;
242 	case CHIP_VERDE:
243 		ucode_start_address = VERDE_SMC_UCODE_START;
244 		ucode_size = VERDE_SMC_UCODE_SIZE;
245 		break;
246 	case CHIP_OLAND:
247 		ucode_start_address = OLAND_SMC_UCODE_START;
248 		ucode_size = OLAND_SMC_UCODE_SIZE;
249 		break;
250 	case CHIP_HAINAN:
251 		ucode_start_address = HAINAN_SMC_UCODE_START;
252 		ucode_size = HAINAN_SMC_UCODE_SIZE;
253 		break;
254 	default:
255 		DRM_ERROR("unknown asic in smc ucode loader\n");
256 		BUG();
257 	}
258 
259 	if (ucode_size & 3)
260 		return -EINVAL;
261 
262 	src = (const u8 *)rdev->smc_fw->data;
263 	WREG32(SMC_IND_INDEX_0, ucode_start_address);
264 	WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
265 	while (ucode_size >= 4) {
266 		/* SMC address space is BE */
267 		data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
268 
269 		WREG32(SMC_IND_DATA_0, data);
270 
271 		src += 4;
272 		ucode_size -= 4;
273 	}
274 	WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
275 
276 	return 0;
277 }
278 
279 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
280 			   u32 *value, u32 limit)
281 {
282 	int ret;
283 
284 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
285 	if (ret)
286 		return ret;
287 
288 	*value = RREG32(SMC_IND_DATA_0);
289 	return 0;
290 }
291 
292 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
293 			    u32 value, u32 limit)
294 {
295 	int ret;
296 
297 	ret = si_set_smc_sram_address(rdev, smc_address, limit);
298 	if (ret)
299 		return ret;
300 
301 	WREG32(SMC_IND_DATA_0, value);
302 	return 0;
303 }
304