1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 * 24 * $FreeBSD: head/sys/dev/drm2/radeon/sid.h 254885 2013-08-25 19:37:15Z dumbbell $ 25 */ 26 #ifndef SI_H 27 #define SI_H 28 29 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 30 31 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 32 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 33 34 #define CG_MULT_THERMAL_STATUS 0x714 35 #define ASIC_MAX_TEMP(x) ((x) << 0) 36 #define ASIC_MAX_TEMP_MASK 0x000001ff 37 #define ASIC_MAX_TEMP_SHIFT 0 38 #define CTF_TEMP(x) ((x) << 9) 39 #define CTF_TEMP_MASK 0x0003fe00 40 #define CTF_TEMP_SHIFT 9 41 42 #define SI_MAX_SH_GPRS 256 43 #define SI_MAX_TEMP_GPRS 16 44 #define SI_MAX_SH_THREADS 256 45 #define SI_MAX_SH_STACK_ENTRIES 4096 46 #define SI_MAX_FRC_EOV_CNT 16384 47 #define SI_MAX_BACKENDS 8 48 #define SI_MAX_BACKENDS_MASK 0xFF 49 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 50 #define SI_MAX_SIMDS 12 51 #define SI_MAX_SIMDS_MASK 0x0FFF 52 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 53 #define SI_MAX_PIPES 8 54 #define SI_MAX_PIPES_MASK 0xFF 55 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 56 #define SI_MAX_LDS_NUM 0xFFFF 57 #define SI_MAX_TCC 16 58 #define SI_MAX_TCC_MASK 0xFFFF 59 60 #define VGA_HDP_CONTROL 0x328 61 #define VGA_MEMORY_DISABLE (1 << 4) 62 63 #define CG_CLKPIN_CNTL 0x660 64 # define XTALIN_DIVIDE (1 << 1) 65 #define CG_CLKPIN_CNTL_2 0x664 66 # define MUX_TCLK_TO_XCLK (1 << 8) 67 68 #define DMIF_ADDR_CONFIG 0xBD4 69 70 #define SRBM_STATUS 0xE50 71 #define GRBM_RQ_PENDING (1 << 5) 72 #define VMC_BUSY (1 << 8) 73 #define MCB_BUSY (1 << 9) 74 #define MCB_NON_DISPLAY_BUSY (1 << 10) 75 #define MCC_BUSY (1 << 11) 76 #define MCD_BUSY (1 << 12) 77 #define SEM_BUSY (1 << 14) 78 #define IH_BUSY (1 << 17) 79 80 #define SRBM_SOFT_RESET 0x0E60 81 #define SOFT_RESET_BIF (1 << 1) 82 #define SOFT_RESET_DC (1 << 5) 83 #define SOFT_RESET_DMA1 (1 << 6) 84 #define SOFT_RESET_GRBM (1 << 8) 85 #define SOFT_RESET_HDP (1 << 9) 86 #define SOFT_RESET_IH (1 << 10) 87 #define SOFT_RESET_MC (1 << 11) 88 #define SOFT_RESET_ROM (1 << 14) 89 #define SOFT_RESET_SEM (1 << 15) 90 #define SOFT_RESET_VMC (1 << 17) 91 #define SOFT_RESET_DMA (1 << 20) 92 #define SOFT_RESET_TST (1 << 21) 93 #define SOFT_RESET_REGBB (1 << 22) 94 #define SOFT_RESET_ORB (1 << 23) 95 96 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 97 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 98 99 #define SRBM_STATUS2 0x0EC4 100 #define DMA_BUSY (1 << 5) 101 #define DMA1_BUSY (1 << 6) 102 103 #define VM_L2_CNTL 0x1400 104 #define ENABLE_L2_CACHE (1 << 0) 105 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 106 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 107 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 108 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 109 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 110 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 111 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 112 #define VM_L2_CNTL2 0x1404 113 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 114 #define INVALIDATE_L2_CACHE (1 << 1) 115 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 116 #define INVALIDATE_PTE_AND_PDE_CACHES 0 117 #define INVALIDATE_ONLY_PTE_CACHES 1 118 #define INVALIDATE_ONLY_PDE_CACHES 2 119 #define VM_L2_CNTL3 0x1408 120 #define BANK_SELECT(x) ((x) << 0) 121 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 122 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 123 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 124 #define VM_L2_STATUS 0x140C 125 #define L2_BUSY (1 << 0) 126 #define VM_CONTEXT0_CNTL 0x1410 127 #define ENABLE_CONTEXT (1 << 0) 128 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 129 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 130 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 131 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 132 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 133 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 134 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 135 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 136 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 137 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 138 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 139 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 140 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 141 #define VM_CONTEXT1_CNTL 0x1414 142 #define VM_CONTEXT0_CNTL2 0x1430 143 #define VM_CONTEXT1_CNTL2 0x1434 144 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 145 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 146 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 147 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 148 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 149 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 150 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 151 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 152 153 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 154 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 155 156 #define VM_INVALIDATE_REQUEST 0x1478 157 #define VM_INVALIDATE_RESPONSE 0x147c 158 159 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 160 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 161 162 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 163 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 164 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 165 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 166 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 167 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 168 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 169 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 170 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 171 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 172 173 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 174 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 175 176 #define MC_SHARED_CHMAP 0x2004 177 #define NOOFCHAN_SHIFT 12 178 #define NOOFCHAN_MASK 0x0000f000 179 #define MC_SHARED_CHREMAP 0x2008 180 181 #define MC_VM_FB_LOCATION 0x2024 182 #define MC_VM_AGP_TOP 0x2028 183 #define MC_VM_AGP_BOT 0x202C 184 #define MC_VM_AGP_BASE 0x2030 185 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 186 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 187 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 188 189 #define MC_VM_MX_L1_TLB_CNTL 0x2064 190 #define ENABLE_L1_TLB (1 << 0) 191 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 192 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 193 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 194 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 195 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 196 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 197 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 198 199 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 200 201 #define MC_ARB_RAMCFG 0x2760 202 #define NOOFBANK_SHIFT 0 203 #define NOOFBANK_MASK 0x00000003 204 #define NOOFRANK_SHIFT 2 205 #define NOOFRANK_MASK 0x00000004 206 #define NOOFROWS_SHIFT 3 207 #define NOOFROWS_MASK 0x00000038 208 #define NOOFCOLS_SHIFT 6 209 #define NOOFCOLS_MASK 0x000000C0 210 #define CHANSIZE_SHIFT 8 211 #define CHANSIZE_MASK 0x00000100 212 #define CHANSIZE_OVERRIDE (1 << 11) 213 #define NOOFGROUPS_SHIFT 12 214 #define NOOFGROUPS_MASK 0x00001000 215 216 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 217 #define TRAIN_DONE_D0 (1 << 30) 218 #define TRAIN_DONE_D1 (1 << 31) 219 220 #define MC_SEQ_SUP_CNTL 0x28c8 221 #define RUN_MASK (1 << 0) 222 #define MC_SEQ_SUP_PGM 0x28cc 223 224 #define MC_IO_PAD_CNTL_D0 0x29d0 225 #define MEM_FALL_OUT_CMD (1 << 8) 226 227 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 228 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 229 230 #define HDP_HOST_PATH_CNTL 0x2C00 231 #define HDP_NONSURFACE_BASE 0x2C04 232 #define HDP_NONSURFACE_INFO 0x2C08 233 #define HDP_NONSURFACE_SIZE 0x2C0C 234 235 #define HDP_ADDR_CONFIG 0x2F48 236 #define HDP_MISC_CNTL 0x2F4C 237 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 238 239 #define IH_RB_CNTL 0x3e00 240 # define IH_RB_ENABLE (1 << 0) 241 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 242 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 243 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 244 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 245 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 246 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 247 #define IH_RB_BASE 0x3e04 248 #define IH_RB_RPTR 0x3e08 249 #define IH_RB_WPTR 0x3e0c 250 # define RB_OVERFLOW (1 << 0) 251 # define WPTR_OFFSET_MASK 0x3fffc 252 #define IH_RB_WPTR_ADDR_HI 0x3e10 253 #define IH_RB_WPTR_ADDR_LO 0x3e14 254 #define IH_CNTL 0x3e18 255 # define ENABLE_INTR (1 << 0) 256 # define IH_MC_SWAP(x) ((x) << 1) 257 # define IH_MC_SWAP_NONE 0 258 # define IH_MC_SWAP_16BIT 1 259 # define IH_MC_SWAP_32BIT 2 260 # define IH_MC_SWAP_64BIT 3 261 # define RPTR_REARM (1 << 4) 262 # define MC_WRREQ_CREDIT(x) ((x) << 15) 263 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 264 # define MC_VMID(x) ((x) << 25) 265 266 #define CONFIG_MEMSIZE 0x5428 267 268 #define INTERRUPT_CNTL 0x5468 269 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 270 # define IH_DUMMY_RD_EN (1 << 1) 271 # define IH_REQ_NONSNOOP_EN (1 << 3) 272 # define GEN_IH_INT_EN (1 << 8) 273 #define INTERRUPT_CNTL2 0x546c 274 275 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 276 277 #define BIF_FB_EN 0x5490 278 #define FB_READ_EN (1 << 0) 279 #define FB_WRITE_EN (1 << 1) 280 281 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 282 283 #define DC_LB_MEMORY_SPLIT 0x6b0c 284 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 285 286 #define PRIORITY_A_CNT 0x6b18 287 #define PRIORITY_MARK_MASK 0x7fff 288 #define PRIORITY_OFF (1 << 16) 289 #define PRIORITY_ALWAYS_ON (1 << 20) 290 #define PRIORITY_B_CNT 0x6b1c 291 292 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 293 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 294 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 295 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 296 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 297 298 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 299 #define VLINE_STATUS 0x6bb8 300 # define VLINE_OCCURRED (1 << 0) 301 # define VLINE_ACK (1 << 4) 302 # define VLINE_STAT (1 << 12) 303 # define VLINE_INTERRUPT (1 << 16) 304 # define VLINE_INTERRUPT_TYPE (1 << 17) 305 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 306 #define VBLANK_STATUS 0x6bbc 307 # define VBLANK_OCCURRED (1 << 0) 308 # define VBLANK_ACK (1 << 4) 309 # define VBLANK_STAT (1 << 12) 310 # define VBLANK_INTERRUPT (1 << 16) 311 # define VBLANK_INTERRUPT_TYPE (1 << 17) 312 313 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 314 #define INT_MASK 0x6b40 315 # define VBLANK_INT_MASK (1 << 0) 316 # define VLINE_INT_MASK (1 << 4) 317 318 #define DISP_INTERRUPT_STATUS 0x60f4 319 # define LB_D1_VLINE_INTERRUPT (1 << 2) 320 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 321 # define DC_HPD1_INTERRUPT (1 << 17) 322 # define DC_HPD1_RX_INTERRUPT (1 << 18) 323 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 324 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 325 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 326 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 327 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 328 # define LB_D2_VLINE_INTERRUPT (1 << 2) 329 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 330 # define DC_HPD2_INTERRUPT (1 << 17) 331 # define DC_HPD2_RX_INTERRUPT (1 << 18) 332 # define DISP_TIMER_INTERRUPT (1 << 24) 333 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 334 # define LB_D3_VLINE_INTERRUPT (1 << 2) 335 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 336 # define DC_HPD3_INTERRUPT (1 << 17) 337 # define DC_HPD3_RX_INTERRUPT (1 << 18) 338 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 339 # define LB_D4_VLINE_INTERRUPT (1 << 2) 340 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 341 # define DC_HPD4_INTERRUPT (1 << 17) 342 # define DC_HPD4_RX_INTERRUPT (1 << 18) 343 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 344 # define LB_D5_VLINE_INTERRUPT (1 << 2) 345 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 346 # define DC_HPD5_INTERRUPT (1 << 17) 347 # define DC_HPD5_RX_INTERRUPT (1 << 18) 348 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 349 # define LB_D6_VLINE_INTERRUPT (1 << 2) 350 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 351 # define DC_HPD6_INTERRUPT (1 << 17) 352 # define DC_HPD6_RX_INTERRUPT (1 << 18) 353 354 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 355 #define GRPH_INT_STATUS 0x6858 356 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 357 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 358 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 359 #define GRPH_INT_CONTROL 0x685c 360 # define GRPH_PFLIP_INT_MASK (1 << 0) 361 # define GRPH_PFLIP_INT_TYPE (1 << 8) 362 363 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 364 365 #define DC_HPD1_INT_STATUS 0x601c 366 #define DC_HPD2_INT_STATUS 0x6028 367 #define DC_HPD3_INT_STATUS 0x6034 368 #define DC_HPD4_INT_STATUS 0x6040 369 #define DC_HPD5_INT_STATUS 0x604c 370 #define DC_HPD6_INT_STATUS 0x6058 371 # define DC_HPDx_INT_STATUS (1 << 0) 372 # define DC_HPDx_SENSE (1 << 1) 373 # define DC_HPDx_RX_INT_STATUS (1 << 8) 374 375 #define DC_HPD1_INT_CONTROL 0x6020 376 #define DC_HPD2_INT_CONTROL 0x602c 377 #define DC_HPD3_INT_CONTROL 0x6038 378 #define DC_HPD4_INT_CONTROL 0x6044 379 #define DC_HPD5_INT_CONTROL 0x6050 380 #define DC_HPD6_INT_CONTROL 0x605c 381 # define DC_HPDx_INT_ACK (1 << 0) 382 # define DC_HPDx_INT_POLARITY (1 << 8) 383 # define DC_HPDx_INT_EN (1 << 16) 384 # define DC_HPDx_RX_INT_ACK (1 << 20) 385 # define DC_HPDx_RX_INT_EN (1 << 24) 386 387 #define DC_HPD1_CONTROL 0x6024 388 #define DC_HPD2_CONTROL 0x6030 389 #define DC_HPD3_CONTROL 0x603c 390 #define DC_HPD4_CONTROL 0x6048 391 #define DC_HPD5_CONTROL 0x6054 392 #define DC_HPD6_CONTROL 0x6060 393 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 394 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 395 # define DC_HPDx_EN (1 << 28) 396 397 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 398 #define CRTC_STATUS_FRAME_COUNT 0x6e98 399 400 #define GRBM_CNTL 0x8000 401 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 402 403 #define GRBM_STATUS2 0x8008 404 #define RLC_RQ_PENDING (1 << 0) 405 #define RLC_BUSY (1 << 8) 406 #define TC_BUSY (1 << 9) 407 408 #define GRBM_STATUS 0x8010 409 #define CMDFIFO_AVAIL_MASK 0x0000000F 410 #define RING2_RQ_PENDING (1 << 4) 411 #define SRBM_RQ_PENDING (1 << 5) 412 #define RING1_RQ_PENDING (1 << 6) 413 #define CF_RQ_PENDING (1 << 7) 414 #define PF_RQ_PENDING (1 << 8) 415 #define GDS_DMA_RQ_PENDING (1 << 9) 416 #define GRBM_EE_BUSY (1 << 10) 417 #define DB_CLEAN (1 << 12) 418 #define CB_CLEAN (1 << 13) 419 #define TA_BUSY (1 << 14) 420 #define GDS_BUSY (1 << 15) 421 #define VGT_BUSY (1 << 17) 422 #define IA_BUSY_NO_DMA (1 << 18) 423 #define IA_BUSY (1 << 19) 424 #define SX_BUSY (1 << 20) 425 #define SPI_BUSY (1 << 22) 426 #define BCI_BUSY (1 << 23) 427 #define SC_BUSY (1 << 24) 428 #define PA_BUSY (1 << 25) 429 #define DB_BUSY (1 << 26) 430 #define CP_COHERENCY_BUSY (1 << 28) 431 #define CP_BUSY (1 << 29) 432 #define CB_BUSY (1 << 30) 433 #define GUI_ACTIVE (1 << 31) 434 #define GRBM_STATUS_SE0 0x8014 435 #define GRBM_STATUS_SE1 0x8018 436 #define SE_DB_CLEAN (1 << 1) 437 #define SE_CB_CLEAN (1 << 2) 438 #define SE_BCI_BUSY (1 << 22) 439 #define SE_VGT_BUSY (1 << 23) 440 #define SE_PA_BUSY (1 << 24) 441 #define SE_TA_BUSY (1 << 25) 442 #define SE_SX_BUSY (1 << 26) 443 #define SE_SPI_BUSY (1 << 27) 444 #define SE_SC_BUSY (1 << 29) 445 #define SE_DB_BUSY (1 << 30) 446 #define SE_CB_BUSY (1 << 31) 447 448 #define GRBM_SOFT_RESET 0x8020 449 #define SOFT_RESET_CP (1 << 0) 450 #define SOFT_RESET_CB (1 << 1) 451 #define SOFT_RESET_RLC (1 << 2) 452 #define SOFT_RESET_DB (1 << 3) 453 #define SOFT_RESET_GDS (1 << 4) 454 #define SOFT_RESET_PA (1 << 5) 455 #define SOFT_RESET_SC (1 << 6) 456 #define SOFT_RESET_BCI (1 << 7) 457 #define SOFT_RESET_SPI (1 << 8) 458 #define SOFT_RESET_SX (1 << 10) 459 #define SOFT_RESET_TC (1 << 11) 460 #define SOFT_RESET_TA (1 << 12) 461 #define SOFT_RESET_VGT (1 << 14) 462 #define SOFT_RESET_IA (1 << 15) 463 464 #define GRBM_GFX_INDEX 0x802C 465 #define INSTANCE_INDEX(x) ((x) << 0) 466 #define SH_INDEX(x) ((x) << 8) 467 #define SE_INDEX(x) ((x) << 16) 468 #define SH_BROADCAST_WRITES (1 << 29) 469 #define INSTANCE_BROADCAST_WRITES (1 << 30) 470 #define SE_BROADCAST_WRITES (1 << 31) 471 472 #define GRBM_INT_CNTL 0x8060 473 # define RDERR_INT_ENABLE (1 << 0) 474 # define GUI_IDLE_INT_ENABLE (1 << 19) 475 476 #define CP_STRMOUT_CNTL 0x84FC 477 #define SCRATCH_REG0 0x8500 478 #define SCRATCH_REG1 0x8504 479 #define SCRATCH_REG2 0x8508 480 #define SCRATCH_REG3 0x850C 481 #define SCRATCH_REG4 0x8510 482 #define SCRATCH_REG5 0x8514 483 #define SCRATCH_REG6 0x8518 484 #define SCRATCH_REG7 0x851C 485 486 #define SCRATCH_UMSK 0x8540 487 #define SCRATCH_ADDR 0x8544 488 489 #define CP_SEM_WAIT_TIMER 0x85BC 490 491 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 492 493 #define CP_ME_CNTL 0x86D8 494 #define CP_CE_HALT (1 << 24) 495 #define CP_PFP_HALT (1 << 26) 496 #define CP_ME_HALT (1 << 28) 497 498 #define CP_COHER_CNTL2 0x85E8 499 500 #define CP_RB2_RPTR 0x86f8 501 #define CP_RB1_RPTR 0x86fc 502 #define CP_RB0_RPTR 0x8700 503 #define CP_RB_WPTR_DELAY 0x8704 504 505 #define CP_QUEUE_THRESHOLDS 0x8760 506 #define ROQ_IB1_START(x) ((x) << 0) 507 #define ROQ_IB2_START(x) ((x) << 8) 508 #define CP_MEQ_THRESHOLDS 0x8764 509 #define MEQ1_START(x) ((x) << 0) 510 #define MEQ2_START(x) ((x) << 8) 511 512 #define CP_PERFMON_CNTL 0x87FC 513 514 #define VGT_VTX_VECT_EJECT_REG 0x88B0 515 516 #define VGT_CACHE_INVALIDATION 0x88C4 517 #define CACHE_INVALIDATION(x) ((x) << 0) 518 #define VC_ONLY 0 519 #define TC_ONLY 1 520 #define VC_AND_TC 2 521 #define AUTO_INVLD_EN(x) ((x) << 6) 522 #define NO_AUTO 0 523 #define ES_AUTO 1 524 #define GS_AUTO 2 525 #define ES_AND_GS_AUTO 3 526 #define VGT_ESGS_RING_SIZE 0x88C8 527 #define VGT_GSVS_RING_SIZE 0x88CC 528 529 #define VGT_GS_VERTEX_REUSE 0x88D4 530 531 #define VGT_PRIMITIVE_TYPE 0x8958 532 #define VGT_INDEX_TYPE 0x895C 533 534 #define VGT_NUM_INDICES 0x8970 535 #define VGT_NUM_INSTANCES 0x8974 536 537 #define VGT_TF_RING_SIZE 0x8988 538 539 #define VGT_HS_OFFCHIP_PARAM 0x89B0 540 541 #define VGT_TF_MEMORY_BASE 0x89B8 542 543 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 544 #define INACTIVE_CUS_MASK 0xFFFF0000 545 #define INACTIVE_CUS_SHIFT 16 546 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 547 548 #define PA_CL_ENHANCE 0x8A14 549 #define CLIP_VTX_REORDER_ENA (1 << 0) 550 #define NUM_CLIP_SEQ(x) ((x) << 1) 551 552 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 553 554 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 555 556 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 557 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 558 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 559 560 #define PA_SC_FIFO_SIZE 0x8BCC 561 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 562 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 563 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 564 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 565 566 #define PA_SC_ENHANCE 0x8BF0 567 568 #define SQ_CONFIG 0x8C00 569 570 #define SQC_CACHES 0x8C08 571 572 #define SX_DEBUG_1 0x9060 573 574 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 575 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 576 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 577 #define SPI_PS_MAX_WAVE_ID 0x90EC 578 579 #define SPI_CONFIG_CNTL 0x9100 580 581 #define SPI_CONFIG_CNTL_1 0x913C 582 #define VTX_DONE_DELAY(x) ((x) << 0) 583 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 584 585 #define CGTS_TCC_DISABLE 0x9148 586 #define CGTS_USER_TCC_DISABLE 0x914C 587 #define TCC_DISABLE_MASK 0xFFFF0000 588 #define TCC_DISABLE_SHIFT 16 589 590 #define TA_CNTL_AUX 0x9508 591 592 #define CC_RB_BACKEND_DISABLE 0x98F4 593 #define BACKEND_DISABLE(x) ((x) << 16) 594 #define GB_ADDR_CONFIG 0x98F8 595 #define NUM_PIPES(x) ((x) << 0) 596 #define NUM_PIPES_MASK 0x00000007 597 #define NUM_PIPES_SHIFT 0 598 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 599 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 600 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 601 #define NUM_SHADER_ENGINES(x) ((x) << 12) 602 #define NUM_SHADER_ENGINES_MASK 0x00003000 603 #define NUM_SHADER_ENGINES_SHIFT 12 604 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 605 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 606 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 607 #define NUM_GPUS(x) ((x) << 20) 608 #define NUM_GPUS_MASK 0x00700000 609 #define NUM_GPUS_SHIFT 20 610 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 611 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 612 #define MULTI_GPU_TILE_SIZE_SHIFT 24 613 #define ROW_SIZE(x) ((x) << 28) 614 #define ROW_SIZE_MASK 0x30000000 615 #define ROW_SIZE_SHIFT 28 616 617 #define GB_TILE_MODE0 0x9910 618 # define MICRO_TILE_MODE(x) ((x) << 0) 619 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 620 # define ADDR_SURF_THIN_MICRO_TILING 1 621 # define ADDR_SURF_DEPTH_MICRO_TILING 2 622 # define ARRAY_MODE(x) ((x) << 2) 623 # define ARRAY_LINEAR_GENERAL 0 624 # define ARRAY_LINEAR_ALIGNED 1 625 # define ARRAY_1D_TILED_THIN1 2 626 # define ARRAY_2D_TILED_THIN1 4 627 # define PIPE_CONFIG(x) ((x) << 6) 628 # define ADDR_SURF_P2 0 629 # define ADDR_SURF_P4_8x16 4 630 # define ADDR_SURF_P4_16x16 5 631 # define ADDR_SURF_P4_16x32 6 632 # define ADDR_SURF_P4_32x32 7 633 # define ADDR_SURF_P8_16x16_8x16 8 634 # define ADDR_SURF_P8_16x32_8x16 9 635 # define ADDR_SURF_P8_32x32_8x16 10 636 # define ADDR_SURF_P8_16x32_16x16 11 637 # define ADDR_SURF_P8_32x32_16x16 12 638 # define ADDR_SURF_P8_32x32_16x32 13 639 # define ADDR_SURF_P8_32x64_32x32 14 640 # define TILE_SPLIT(x) ((x) << 11) 641 # define ADDR_SURF_TILE_SPLIT_64B 0 642 # define ADDR_SURF_TILE_SPLIT_128B 1 643 # define ADDR_SURF_TILE_SPLIT_256B 2 644 # define ADDR_SURF_TILE_SPLIT_512B 3 645 # define ADDR_SURF_TILE_SPLIT_1KB 4 646 # define ADDR_SURF_TILE_SPLIT_2KB 5 647 # define ADDR_SURF_TILE_SPLIT_4KB 6 648 # define BANK_WIDTH(x) ((x) << 14) 649 # define ADDR_SURF_BANK_WIDTH_1 0 650 # define ADDR_SURF_BANK_WIDTH_2 1 651 # define ADDR_SURF_BANK_WIDTH_4 2 652 # define ADDR_SURF_BANK_WIDTH_8 3 653 # define BANK_HEIGHT(x) ((x) << 16) 654 # define ADDR_SURF_BANK_HEIGHT_1 0 655 # define ADDR_SURF_BANK_HEIGHT_2 1 656 # define ADDR_SURF_BANK_HEIGHT_4 2 657 # define ADDR_SURF_BANK_HEIGHT_8 3 658 # define MACRO_TILE_ASPECT(x) ((x) << 18) 659 # define ADDR_SURF_MACRO_ASPECT_1 0 660 # define ADDR_SURF_MACRO_ASPECT_2 1 661 # define ADDR_SURF_MACRO_ASPECT_4 2 662 # define ADDR_SURF_MACRO_ASPECT_8 3 663 # define NUM_BANKS(x) ((x) << 20) 664 # define ADDR_SURF_2_BANK 0 665 # define ADDR_SURF_4_BANK 1 666 # define ADDR_SURF_8_BANK 2 667 # define ADDR_SURF_16_BANK 3 668 669 #define CB_PERFCOUNTER0_SELECT0 0x9a20 670 #define CB_PERFCOUNTER0_SELECT1 0x9a24 671 #define CB_PERFCOUNTER1_SELECT0 0x9a28 672 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 673 #define CB_PERFCOUNTER2_SELECT0 0x9a30 674 #define CB_PERFCOUNTER2_SELECT1 0x9a34 675 #define CB_PERFCOUNTER3_SELECT0 0x9a38 676 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 677 678 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 679 #define BACKEND_DISABLE_MASK 0x00FF0000 680 #define BACKEND_DISABLE_SHIFT 16 681 682 #define TCP_CHAN_STEER_LO 0xac0c 683 #define TCP_CHAN_STEER_HI 0xac10 684 685 #define CP_RB0_BASE 0xC100 686 #define CP_RB0_CNTL 0xC104 687 #define RB_BUFSZ(x) ((x) << 0) 688 #define RB_BLKSZ(x) ((x) << 8) 689 #define BUF_SWAP_32BIT (2 << 16) 690 #define RB_NO_UPDATE (1 << 27) 691 #define RB_RPTR_WR_ENA (1 << 31) 692 693 #define CP_RB0_RPTR_ADDR 0xC10C 694 #define CP_RB0_RPTR_ADDR_HI 0xC110 695 #define CP_RB0_WPTR 0xC114 696 697 #define CP_PFP_UCODE_ADDR 0xC150 698 #define CP_PFP_UCODE_DATA 0xC154 699 #define CP_ME_RAM_RADDR 0xC158 700 #define CP_ME_RAM_WADDR 0xC15C 701 #define CP_ME_RAM_DATA 0xC160 702 703 #define CP_CE_UCODE_ADDR 0xC168 704 #define CP_CE_UCODE_DATA 0xC16C 705 706 #define CP_RB1_BASE 0xC180 707 #define CP_RB1_CNTL 0xC184 708 #define CP_RB1_RPTR_ADDR 0xC188 709 #define CP_RB1_RPTR_ADDR_HI 0xC18C 710 #define CP_RB1_WPTR 0xC190 711 #define CP_RB2_BASE 0xC194 712 #define CP_RB2_CNTL 0xC198 713 #define CP_RB2_RPTR_ADDR 0xC19C 714 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 715 #define CP_RB2_WPTR 0xC1A4 716 #define CP_INT_CNTL_RING0 0xC1A8 717 #define CP_INT_CNTL_RING1 0xC1AC 718 #define CP_INT_CNTL_RING2 0xC1B0 719 # define CNTX_BUSY_INT_ENABLE (1 << 19) 720 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 721 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 722 # define TIME_STAMP_INT_ENABLE (1 << 26) 723 # define CP_RINGID2_INT_ENABLE (1 << 29) 724 # define CP_RINGID1_INT_ENABLE (1 << 30) 725 # define CP_RINGID0_INT_ENABLE (1 << 31) 726 #define CP_INT_STATUS_RING0 0xC1B4 727 #define CP_INT_STATUS_RING1 0xC1B8 728 #define CP_INT_STATUS_RING2 0xC1BC 729 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 730 # define TIME_STAMP_INT_STAT (1 << 26) 731 # define CP_RINGID2_INT_STAT (1 << 29) 732 # define CP_RINGID1_INT_STAT (1 << 30) 733 # define CP_RINGID0_INT_STAT (1 << 31) 734 735 #define CP_DEBUG 0xC1FC 736 737 #define RLC_CNTL 0xC300 738 # define RLC_ENABLE (1 << 0) 739 #define RLC_RL_BASE 0xC304 740 #define RLC_RL_SIZE 0xC308 741 #define RLC_LB_CNTL 0xC30C 742 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 743 #define RLC_LB_CNTR_MAX 0xC314 744 #define RLC_LB_CNTR_INIT 0xC318 745 746 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 747 748 #define RLC_UCODE_ADDR 0xC32C 749 #define RLC_UCODE_DATA 0xC330 750 751 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 752 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 753 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 754 #define RLC_MC_CNTL 0xC344 755 #define RLC_UCODE_CNTL 0xC348 756 757 #define PA_SC_RASTER_CONFIG 0x28350 758 # define RASTER_CONFIG_RB_MAP_0 0 759 # define RASTER_CONFIG_RB_MAP_1 1 760 # define RASTER_CONFIG_RB_MAP_2 2 761 # define RASTER_CONFIG_RB_MAP_3 3 762 763 #define VGT_EVENT_INITIATOR 0x28a90 764 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 765 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 766 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 767 # define CACHE_FLUSH_TS (4 << 0) 768 # define CACHE_FLUSH (6 << 0) 769 # define CS_PARTIAL_FLUSH (7 << 0) 770 # define VGT_STREAMOUT_RESET (10 << 0) 771 # define END_OF_PIPE_INCR_DE (11 << 0) 772 # define END_OF_PIPE_IB_END (12 << 0) 773 # define RST_PIX_CNT (13 << 0) 774 # define VS_PARTIAL_FLUSH (15 << 0) 775 # define PS_PARTIAL_FLUSH (16 << 0) 776 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 777 # define ZPASS_DONE (21 << 0) 778 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 779 # define PERFCOUNTER_START (23 << 0) 780 # define PERFCOUNTER_STOP (24 << 0) 781 # define PIPELINESTAT_START (25 << 0) 782 # define PIPELINESTAT_STOP (26 << 0) 783 # define PERFCOUNTER_SAMPLE (27 << 0) 784 # define SAMPLE_PIPELINESTAT (30 << 0) 785 # define SAMPLE_STREAMOUTSTATS (32 << 0) 786 # define RESET_VTX_CNT (33 << 0) 787 # define VGT_FLUSH (36 << 0) 788 # define BOTTOM_OF_PIPE_TS (40 << 0) 789 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 790 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 791 # define FLUSH_AND_INV_DB_META (44 << 0) 792 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 793 # define FLUSH_AND_INV_CB_META (46 << 0) 794 # define CS_DONE (47 << 0) 795 # define PS_DONE (48 << 0) 796 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 797 # define THREAD_TRACE_START (51 << 0) 798 # define THREAD_TRACE_STOP (52 << 0) 799 # define THREAD_TRACE_FLUSH (54 << 0) 800 # define THREAD_TRACE_FINISH (55 << 0) 801 802 /* 803 * PM4 804 */ 805 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 806 (((reg) >> 2) & 0xFFFF) | \ 807 ((n) & 0x3FFF) << 16) 808 #define CP_PACKET2 0x80000000 809 #define PACKET2_PAD_SHIFT 0 810 #define PACKET2_PAD_MASK (0x3fffffff << 0) 811 812 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 813 814 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 815 (((op) & 0xFF) << 8) | \ 816 ((n) & 0x3FFF) << 16) 817 818 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 819 820 /* Packet 3 types */ 821 #define PACKET3_NOP 0x10 822 #define PACKET3_SET_BASE 0x11 823 #define PACKET3_BASE_INDEX(x) ((x) << 0) 824 #define GDS_PARTITION_BASE 2 825 #define CE_PARTITION_BASE 3 826 #define PACKET3_CLEAR_STATE 0x12 827 #define PACKET3_INDEX_BUFFER_SIZE 0x13 828 #define PACKET3_DISPATCH_DIRECT 0x15 829 #define PACKET3_DISPATCH_INDIRECT 0x16 830 #define PACKET3_ALLOC_GDS 0x1B 831 #define PACKET3_WRITE_GDS_RAM 0x1C 832 #define PACKET3_ATOMIC_GDS 0x1D 833 #define PACKET3_ATOMIC 0x1E 834 #define PACKET3_OCCLUSION_QUERY 0x1F 835 #define PACKET3_SET_PREDICATION 0x20 836 #define PACKET3_REG_RMW 0x21 837 #define PACKET3_COND_EXEC 0x22 838 #define PACKET3_PRED_EXEC 0x23 839 #define PACKET3_DRAW_INDIRECT 0x24 840 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 841 #define PACKET3_INDEX_BASE 0x26 842 #define PACKET3_DRAW_INDEX_2 0x27 843 #define PACKET3_CONTEXT_CONTROL 0x28 844 #define PACKET3_INDEX_TYPE 0x2A 845 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 846 #define PACKET3_DRAW_INDEX_AUTO 0x2D 847 #define PACKET3_DRAW_INDEX_IMMD 0x2E 848 #define PACKET3_NUM_INSTANCES 0x2F 849 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 850 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 851 #define PACKET3_INDIRECT_BUFFER 0x32 852 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 853 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 854 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 855 #define PACKET3_WRITE_DATA 0x37 856 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 857 /* 0 - register 858 * 1 - memory (sync - via GRBM) 859 * 2 - tc/l2 860 * 3 - gds 861 * 4 - reserved 862 * 5 - memory (async - direct) 863 */ 864 #define WR_ONE_ADDR (1 << 16) 865 #define WR_CONFIRM (1 << 20) 866 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 867 /* 0 - me 868 * 1 - pfp 869 * 2 - ce 870 */ 871 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 872 #define PACKET3_MEM_SEMAPHORE 0x39 873 #define PACKET3_MPEG_INDEX 0x3A 874 #define PACKET3_COPY_DW 0x3B 875 #define PACKET3_WAIT_REG_MEM 0x3C 876 #define PACKET3_MEM_WRITE 0x3D 877 #define PACKET3_COPY_DATA 0x40 878 #define PACKET3_CP_DMA 0x41 879 /* 1. header 880 * 2. SRC_ADDR_LO or DATA [31:0] 881 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 882 * SRC_ADDR_HI [7:0] 883 * 4. DST_ADDR_LO [31:0] 884 * 5. DST_ADDR_HI [7:0] 885 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 886 */ 887 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 888 /* 0 - SRC_ADDR 889 * 1 - GDS 890 */ 891 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 892 /* 0 - ME 893 * 1 - PFP 894 */ 895 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 896 /* 0 - SRC_ADDR 897 * 1 - GDS 898 * 2 - DATA 899 */ 900 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 901 /* COMMAND */ 902 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 903 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 904 /* 0 - none 905 * 1 - 8 in 16 906 * 2 - 8 in 32 907 * 3 - 8 in 64 908 */ 909 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 910 /* 0 - none 911 * 1 - 8 in 16 912 * 2 - 8 in 32 913 * 3 - 8 in 64 914 */ 915 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 916 /* 0 - memory 917 * 1 - register 918 */ 919 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 920 /* 0 - memory 921 * 1 - register 922 */ 923 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 924 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 925 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 926 #define PACKET3_PFP_SYNC_ME 0x42 927 #define PACKET3_SURFACE_SYNC 0x43 928 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 929 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 930 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 931 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 932 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 933 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 934 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 935 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 936 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 937 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 938 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 939 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 940 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 941 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 942 # define PACKET3_TC_ACTION_ENA (1 << 23) 943 # define PACKET3_CB_ACTION_ENA (1 << 25) 944 # define PACKET3_DB_ACTION_ENA (1 << 26) 945 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 946 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 947 #define PACKET3_ME_INITIALIZE 0x44 948 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 949 #define PACKET3_COND_WRITE 0x45 950 #define PACKET3_EVENT_WRITE 0x46 951 #define EVENT_TYPE(x) ((x) << 0) 952 #define EVENT_INDEX(x) ((x) << 8) 953 /* 0 - any non-TS event 954 * 1 - ZPASS_DONE 955 * 2 - SAMPLE_PIPELINESTAT 956 * 3 - SAMPLE_STREAMOUTSTAT* 957 * 4 - *S_PARTIAL_FLUSH 958 * 5 - EOP events 959 * 6 - EOS events 960 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 961 */ 962 #define INV_L2 (1 << 20) 963 /* INV TC L2 cache when EVENT_INDEX = 7 */ 964 #define PACKET3_EVENT_WRITE_EOP 0x47 965 #define DATA_SEL(x) ((x) << 29) 966 /* 0 - discard 967 * 1 - send low 32bit data 968 * 2 - send 64bit data 969 * 3 - send 64bit counter value 970 */ 971 #define INT_SEL(x) ((x) << 24) 972 /* 0 - none 973 * 1 - interrupt only (DATA_SEL = 0) 974 * 2 - interrupt when data write is confirmed 975 */ 976 #define PACKET3_EVENT_WRITE_EOS 0x48 977 #define PACKET3_PREAMBLE_CNTL 0x4A 978 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 979 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 980 #define PACKET3_ONE_REG_WRITE 0x57 981 #define PACKET3_LOAD_CONFIG_REG 0x5F 982 #define PACKET3_LOAD_CONTEXT_REG 0x60 983 #define PACKET3_LOAD_SH_REG 0x61 984 #define PACKET3_SET_CONFIG_REG 0x68 985 #define PACKET3_SET_CONFIG_REG_START 0x00008000 986 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 987 #define PACKET3_SET_CONTEXT_REG 0x69 988 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 989 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 990 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 991 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 992 #define PACKET3_SET_SH_REG 0x76 993 #define PACKET3_SET_SH_REG_START 0x0000b000 994 #define PACKET3_SET_SH_REG_END 0x0000c000 995 #define PACKET3_SET_SH_REG_OFFSET 0x77 996 #define PACKET3_ME_WRITE 0x7A 997 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 998 #define PACKET3_SCRATCH_RAM_READ 0x7E 999 #define PACKET3_CE_WRITE 0x7F 1000 #define PACKET3_LOAD_CONST_RAM 0x80 1001 #define PACKET3_WRITE_CONST_RAM 0x81 1002 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1003 #define PACKET3_DUMP_CONST_RAM 0x83 1004 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1005 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1006 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1007 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1008 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1009 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1010 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1011 #define PACKET3_SWITCH_BUFFER 0x8B 1012 1013 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1014 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1015 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1016 1017 #define DMA_RB_CNTL 0xd000 1018 # define DMA_RB_ENABLE (1 << 0) 1019 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1020 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1021 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1022 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1023 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1024 #define DMA_RB_BASE 0xd004 1025 #define DMA_RB_RPTR 0xd008 1026 #define DMA_RB_WPTR 0xd00c 1027 1028 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1029 #define DMA_RB_RPTR_ADDR_LO 0xd020 1030 1031 #define DMA_IB_CNTL 0xd024 1032 # define DMA_IB_ENABLE (1 << 0) 1033 # define DMA_IB_SWAP_ENABLE (1 << 4) 1034 #define DMA_IB_RPTR 0xd028 1035 #define DMA_CNTL 0xd02c 1036 # define TRAP_ENABLE (1 << 0) 1037 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1038 # define SEM_WAIT_INT_ENABLE (1 << 2) 1039 # define DATA_SWAP_ENABLE (1 << 3) 1040 # define FENCE_SWAP_ENABLE (1 << 4) 1041 # define CTXEMPTY_INT_ENABLE (1 << 28) 1042 #define DMA_STATUS_REG 0xd034 1043 # define DMA_IDLE (1 << 0) 1044 #define DMA_TILING_CONFIG 0xd0b8 1045 1046 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1047 (((b) & 0x1) << 26) | \ 1048 (((t) & 0x1) << 23) | \ 1049 (((s) & 0x1) << 22) | \ 1050 (((n) & 0xFFFFF) << 0)) 1051 1052 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1053 (((vmid) & 0xF) << 20) | \ 1054 (((n) & 0xFFFFF) << 0)) 1055 1056 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1057 (1 << 26) | \ 1058 (1 << 21) | \ 1059 (((n) & 0xFFFFF) << 0)) 1060 1061 /* async DMA Packet types */ 1062 #define DMA_PACKET_WRITE 0x2 1063 #define DMA_PACKET_COPY 0x3 1064 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1065 #define DMA_PACKET_SEMAPHORE 0x5 1066 #define DMA_PACKET_FENCE 0x6 1067 #define DMA_PACKET_TRAP 0x7 1068 #define DMA_PACKET_SRBM_WRITE 0x9 1069 #define DMA_PACKET_CONSTANT_FILL 0xd 1070 #define DMA_PACKET_NOP 0xf 1071 1072 #endif 1073