1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 * 24 * $FreeBSD: head/sys/dev/drm2/radeon/sid.h 254885 2013-08-25 19:37:15Z dumbbell $ 25 */ 26 #ifndef SI_H 27 #define SI_H 28 29 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 30 31 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 32 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 33 34 #define CG_MULT_THERMAL_STATUS 0x714 35 #define ASIC_MAX_TEMP(x) ((x) << 0) 36 #define ASIC_MAX_TEMP_MASK 0x000001ff 37 #define ASIC_MAX_TEMP_SHIFT 0 38 #define CTF_TEMP(x) ((x) << 9) 39 #define CTF_TEMP_MASK 0x0003fe00 40 #define CTF_TEMP_SHIFT 9 41 42 #define SI_MAX_SH_GPRS 256 43 #define SI_MAX_TEMP_GPRS 16 44 #define SI_MAX_SH_THREADS 256 45 #define SI_MAX_SH_STACK_ENTRIES 4096 46 #define SI_MAX_FRC_EOV_CNT 16384 47 #define SI_MAX_BACKENDS 8 48 #define SI_MAX_BACKENDS_MASK 0xFF 49 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 50 #define SI_MAX_SIMDS 12 51 #define SI_MAX_SIMDS_MASK 0x0FFF 52 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 53 #define SI_MAX_PIPES 8 54 #define SI_MAX_PIPES_MASK 0xFF 55 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 56 #define SI_MAX_LDS_NUM 0xFFFF 57 #define SI_MAX_TCC 16 58 #define SI_MAX_TCC_MASK 0xFFFF 59 60 #define VGA_HDP_CONTROL 0x328 61 #define VGA_MEMORY_DISABLE (1 << 4) 62 63 #define DMIF_ADDR_CONFIG 0xBD4 64 65 #define SRBM_STATUS 0xE50 66 67 #define SRBM_SOFT_RESET 0x0E60 68 #define SOFT_RESET_BIF (1 << 1) 69 #define SOFT_RESET_DC (1 << 5) 70 #define SOFT_RESET_DMA1 (1 << 6) 71 #define SOFT_RESET_GRBM (1 << 8) 72 #define SOFT_RESET_HDP (1 << 9) 73 #define SOFT_RESET_IH (1 << 10) 74 #define SOFT_RESET_MC (1 << 11) 75 #define SOFT_RESET_ROM (1 << 14) 76 #define SOFT_RESET_SEM (1 << 15) 77 #define SOFT_RESET_VMC (1 << 17) 78 #define SOFT_RESET_DMA (1 << 20) 79 #define SOFT_RESET_TST (1 << 21) 80 #define SOFT_RESET_REGBB (1 << 22) 81 #define SOFT_RESET_ORB (1 << 23) 82 83 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 84 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 85 86 #define VM_L2_CNTL 0x1400 87 #define ENABLE_L2_CACHE (1 << 0) 88 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 89 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 90 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 91 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 92 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 93 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 94 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 95 #define VM_L2_CNTL2 0x1404 96 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 97 #define INVALIDATE_L2_CACHE (1 << 1) 98 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 99 #define INVALIDATE_PTE_AND_PDE_CACHES 0 100 #define INVALIDATE_ONLY_PTE_CACHES 1 101 #define INVALIDATE_ONLY_PDE_CACHES 2 102 #define VM_L2_CNTL3 0x1408 103 #define BANK_SELECT(x) ((x) << 0) 104 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 105 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 106 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 107 #define VM_L2_STATUS 0x140C 108 #define L2_BUSY (1 << 0) 109 #define VM_CONTEXT0_CNTL 0x1410 110 #define ENABLE_CONTEXT (1 << 0) 111 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 112 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 113 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 114 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 115 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 116 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 117 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 118 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 119 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 120 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 121 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 122 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 123 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 124 #define VM_CONTEXT1_CNTL 0x1414 125 #define VM_CONTEXT0_CNTL2 0x1430 126 #define VM_CONTEXT1_CNTL2 0x1434 127 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 128 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 129 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 130 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 131 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 132 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 133 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 134 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 135 136 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 137 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 138 139 #define VM_INVALIDATE_REQUEST 0x1478 140 #define VM_INVALIDATE_RESPONSE 0x147c 141 142 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 143 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 144 145 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 146 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 147 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 148 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 149 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 150 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 151 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 152 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 153 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 154 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 155 156 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 157 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 158 159 #define MC_SHARED_CHMAP 0x2004 160 #define NOOFCHAN_SHIFT 12 161 #define NOOFCHAN_MASK 0x0000f000 162 #define MC_SHARED_CHREMAP 0x2008 163 164 #define MC_VM_FB_LOCATION 0x2024 165 #define MC_VM_AGP_TOP 0x2028 166 #define MC_VM_AGP_BOT 0x202C 167 #define MC_VM_AGP_BASE 0x2030 168 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 169 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 170 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 171 172 #define MC_VM_MX_L1_TLB_CNTL 0x2064 173 #define ENABLE_L1_TLB (1 << 0) 174 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 175 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 176 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 177 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 178 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 179 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 180 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 181 182 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 183 184 #define MC_ARB_RAMCFG 0x2760 185 #define NOOFBANK_SHIFT 0 186 #define NOOFBANK_MASK 0x00000003 187 #define NOOFRANK_SHIFT 2 188 #define NOOFRANK_MASK 0x00000004 189 #define NOOFROWS_SHIFT 3 190 #define NOOFROWS_MASK 0x00000038 191 #define NOOFCOLS_SHIFT 6 192 #define NOOFCOLS_MASK 0x000000C0 193 #define CHANSIZE_SHIFT 8 194 #define CHANSIZE_MASK 0x00000100 195 #define CHANSIZE_OVERRIDE (1 << 11) 196 #define NOOFGROUPS_SHIFT 12 197 #define NOOFGROUPS_MASK 0x00001000 198 199 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808 200 #define TRAIN_DONE_D0 (1 << 30) 201 #define TRAIN_DONE_D1 (1 << 31) 202 203 #define MC_SEQ_SUP_CNTL 0x28c8 204 #define RUN_MASK (1 << 0) 205 #define MC_SEQ_SUP_PGM 0x28cc 206 207 #define MC_IO_PAD_CNTL_D0 0x29d0 208 #define MEM_FALL_OUT_CMD (1 << 8) 209 210 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 211 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 212 213 #define HDP_HOST_PATH_CNTL 0x2C00 214 #define HDP_NONSURFACE_BASE 0x2C04 215 #define HDP_NONSURFACE_INFO 0x2C08 216 #define HDP_NONSURFACE_SIZE 0x2C0C 217 218 #define HDP_ADDR_CONFIG 0x2F48 219 #define HDP_MISC_CNTL 0x2F4C 220 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 221 222 #define IH_RB_CNTL 0x3e00 223 # define IH_RB_ENABLE (1 << 0) 224 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 225 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 226 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 227 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 228 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 229 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 230 #define IH_RB_BASE 0x3e04 231 #define IH_RB_RPTR 0x3e08 232 #define IH_RB_WPTR 0x3e0c 233 # define RB_OVERFLOW (1 << 0) 234 # define WPTR_OFFSET_MASK 0x3fffc 235 #define IH_RB_WPTR_ADDR_HI 0x3e10 236 #define IH_RB_WPTR_ADDR_LO 0x3e14 237 #define IH_CNTL 0x3e18 238 # define ENABLE_INTR (1 << 0) 239 # define IH_MC_SWAP(x) ((x) << 1) 240 # define IH_MC_SWAP_NONE 0 241 # define IH_MC_SWAP_16BIT 1 242 # define IH_MC_SWAP_32BIT 2 243 # define IH_MC_SWAP_64BIT 3 244 # define RPTR_REARM (1 << 4) 245 # define MC_WRREQ_CREDIT(x) ((x) << 15) 246 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 247 # define MC_VMID(x) ((x) << 25) 248 249 #define CONFIG_MEMSIZE 0x5428 250 251 #define INTERRUPT_CNTL 0x5468 252 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 253 # define IH_DUMMY_RD_EN (1 << 1) 254 # define IH_REQ_NONSNOOP_EN (1 << 3) 255 # define GEN_IH_INT_EN (1 << 8) 256 #define INTERRUPT_CNTL2 0x546c 257 258 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 259 260 #define BIF_FB_EN 0x5490 261 #define FB_READ_EN (1 << 0) 262 #define FB_WRITE_EN (1 << 1) 263 264 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 265 266 #define DC_LB_MEMORY_SPLIT 0x6b0c 267 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 268 269 #define PRIORITY_A_CNT 0x6b18 270 #define PRIORITY_MARK_MASK 0x7fff 271 #define PRIORITY_OFF (1 << 16) 272 #define PRIORITY_ALWAYS_ON (1 << 20) 273 #define PRIORITY_B_CNT 0x6b1c 274 275 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 276 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 277 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 278 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 279 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 280 281 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 282 #define VLINE_STATUS 0x6bb8 283 # define VLINE_OCCURRED (1 << 0) 284 # define VLINE_ACK (1 << 4) 285 # define VLINE_STAT (1 << 12) 286 # define VLINE_INTERRUPT (1 << 16) 287 # define VLINE_INTERRUPT_TYPE (1 << 17) 288 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 289 #define VBLANK_STATUS 0x6bbc 290 # define VBLANK_OCCURRED (1 << 0) 291 # define VBLANK_ACK (1 << 4) 292 # define VBLANK_STAT (1 << 12) 293 # define VBLANK_INTERRUPT (1 << 16) 294 # define VBLANK_INTERRUPT_TYPE (1 << 17) 295 296 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 297 #define INT_MASK 0x6b40 298 # define VBLANK_INT_MASK (1 << 0) 299 # define VLINE_INT_MASK (1 << 4) 300 301 #define DISP_INTERRUPT_STATUS 0x60f4 302 # define LB_D1_VLINE_INTERRUPT (1 << 2) 303 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 304 # define DC_HPD1_INTERRUPT (1 << 17) 305 # define DC_HPD1_RX_INTERRUPT (1 << 18) 306 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 307 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 308 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 309 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 310 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 311 # define LB_D2_VLINE_INTERRUPT (1 << 2) 312 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 313 # define DC_HPD2_INTERRUPT (1 << 17) 314 # define DC_HPD2_RX_INTERRUPT (1 << 18) 315 # define DISP_TIMER_INTERRUPT (1 << 24) 316 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 317 # define LB_D3_VLINE_INTERRUPT (1 << 2) 318 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 319 # define DC_HPD3_INTERRUPT (1 << 17) 320 # define DC_HPD3_RX_INTERRUPT (1 << 18) 321 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 322 # define LB_D4_VLINE_INTERRUPT (1 << 2) 323 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 324 # define DC_HPD4_INTERRUPT (1 << 17) 325 # define DC_HPD4_RX_INTERRUPT (1 << 18) 326 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 327 # define LB_D5_VLINE_INTERRUPT (1 << 2) 328 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 329 # define DC_HPD5_INTERRUPT (1 << 17) 330 # define DC_HPD5_RX_INTERRUPT (1 << 18) 331 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 332 # define LB_D6_VLINE_INTERRUPT (1 << 2) 333 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 334 # define DC_HPD6_INTERRUPT (1 << 17) 335 # define DC_HPD6_RX_INTERRUPT (1 << 18) 336 337 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 338 #define GRPH_INT_STATUS 0x6858 339 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 340 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 341 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 342 #define GRPH_INT_CONTROL 0x685c 343 # define GRPH_PFLIP_INT_MASK (1 << 0) 344 # define GRPH_PFLIP_INT_TYPE (1 << 8) 345 346 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 347 348 #define DC_HPD1_INT_STATUS 0x601c 349 #define DC_HPD2_INT_STATUS 0x6028 350 #define DC_HPD3_INT_STATUS 0x6034 351 #define DC_HPD4_INT_STATUS 0x6040 352 #define DC_HPD5_INT_STATUS 0x604c 353 #define DC_HPD6_INT_STATUS 0x6058 354 # define DC_HPDx_INT_STATUS (1 << 0) 355 # define DC_HPDx_SENSE (1 << 1) 356 # define DC_HPDx_RX_INT_STATUS (1 << 8) 357 358 #define DC_HPD1_INT_CONTROL 0x6020 359 #define DC_HPD2_INT_CONTROL 0x602c 360 #define DC_HPD3_INT_CONTROL 0x6038 361 #define DC_HPD4_INT_CONTROL 0x6044 362 #define DC_HPD5_INT_CONTROL 0x6050 363 #define DC_HPD6_INT_CONTROL 0x605c 364 # define DC_HPDx_INT_ACK (1 << 0) 365 # define DC_HPDx_INT_POLARITY (1 << 8) 366 # define DC_HPDx_INT_EN (1 << 16) 367 # define DC_HPDx_RX_INT_ACK (1 << 20) 368 # define DC_HPDx_RX_INT_EN (1 << 24) 369 370 #define DC_HPD1_CONTROL 0x6024 371 #define DC_HPD2_CONTROL 0x6030 372 #define DC_HPD3_CONTROL 0x603c 373 #define DC_HPD4_CONTROL 0x6048 374 #define DC_HPD5_CONTROL 0x6054 375 #define DC_HPD6_CONTROL 0x6060 376 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 377 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 378 # define DC_HPDx_EN (1 << 28) 379 380 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 381 #define CRTC_STATUS_FRAME_COUNT 0x6e98 382 383 #define GRBM_CNTL 0x8000 384 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 385 386 #define GRBM_STATUS2 0x8008 387 #define RLC_RQ_PENDING (1 << 0) 388 #define RLC_BUSY (1 << 8) 389 #define TC_BUSY (1 << 9) 390 391 #define GRBM_STATUS 0x8010 392 #define CMDFIFO_AVAIL_MASK 0x0000000F 393 #define RING2_RQ_PENDING (1 << 4) 394 #define SRBM_RQ_PENDING (1 << 5) 395 #define RING1_RQ_PENDING (1 << 6) 396 #define CF_RQ_PENDING (1 << 7) 397 #define PF_RQ_PENDING (1 << 8) 398 #define GDS_DMA_RQ_PENDING (1 << 9) 399 #define GRBM_EE_BUSY (1 << 10) 400 #define DB_CLEAN (1 << 12) 401 #define CB_CLEAN (1 << 13) 402 #define TA_BUSY (1 << 14) 403 #define GDS_BUSY (1 << 15) 404 #define VGT_BUSY (1 << 17) 405 #define IA_BUSY_NO_DMA (1 << 18) 406 #define IA_BUSY (1 << 19) 407 #define SX_BUSY (1 << 20) 408 #define SPI_BUSY (1 << 22) 409 #define BCI_BUSY (1 << 23) 410 #define SC_BUSY (1 << 24) 411 #define PA_BUSY (1 << 25) 412 #define DB_BUSY (1 << 26) 413 #define CP_COHERENCY_BUSY (1 << 28) 414 #define CP_BUSY (1 << 29) 415 #define CB_BUSY (1 << 30) 416 #define GUI_ACTIVE (1 << 31) 417 #define GRBM_STATUS_SE0 0x8014 418 #define GRBM_STATUS_SE1 0x8018 419 #define SE_DB_CLEAN (1 << 1) 420 #define SE_CB_CLEAN (1 << 2) 421 #define SE_BCI_BUSY (1 << 22) 422 #define SE_VGT_BUSY (1 << 23) 423 #define SE_PA_BUSY (1 << 24) 424 #define SE_TA_BUSY (1 << 25) 425 #define SE_SX_BUSY (1 << 26) 426 #define SE_SPI_BUSY (1 << 27) 427 #define SE_SC_BUSY (1 << 29) 428 #define SE_DB_BUSY (1 << 30) 429 #define SE_CB_BUSY (1 << 31) 430 431 #define GRBM_SOFT_RESET 0x8020 432 #define SOFT_RESET_CP (1 << 0) 433 #define SOFT_RESET_CB (1 << 1) 434 #define SOFT_RESET_RLC (1 << 2) 435 #define SOFT_RESET_DB (1 << 3) 436 #define SOFT_RESET_GDS (1 << 4) 437 #define SOFT_RESET_PA (1 << 5) 438 #define SOFT_RESET_SC (1 << 6) 439 #define SOFT_RESET_BCI (1 << 7) 440 #define SOFT_RESET_SPI (1 << 8) 441 #define SOFT_RESET_SX (1 << 10) 442 #define SOFT_RESET_TC (1 << 11) 443 #define SOFT_RESET_TA (1 << 12) 444 #define SOFT_RESET_VGT (1 << 14) 445 #define SOFT_RESET_IA (1 << 15) 446 447 #define GRBM_GFX_INDEX 0x802C 448 #define INSTANCE_INDEX(x) ((x) << 0) 449 #define SH_INDEX(x) ((x) << 8) 450 #define SE_INDEX(x) ((x) << 16) 451 #define SH_BROADCAST_WRITES (1 << 29) 452 #define INSTANCE_BROADCAST_WRITES (1 << 30) 453 #define SE_BROADCAST_WRITES (1 << 31) 454 455 #define GRBM_INT_CNTL 0x8060 456 # define RDERR_INT_ENABLE (1 << 0) 457 # define GUI_IDLE_INT_ENABLE (1 << 19) 458 459 #define CP_STRMOUT_CNTL 0x84FC 460 #define SCRATCH_REG0 0x8500 461 #define SCRATCH_REG1 0x8504 462 #define SCRATCH_REG2 0x8508 463 #define SCRATCH_REG3 0x850C 464 #define SCRATCH_REG4 0x8510 465 #define SCRATCH_REG5 0x8514 466 #define SCRATCH_REG6 0x8518 467 #define SCRATCH_REG7 0x851C 468 469 #define SCRATCH_UMSK 0x8540 470 #define SCRATCH_ADDR 0x8544 471 472 #define CP_SEM_WAIT_TIMER 0x85BC 473 474 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 475 476 #define CP_ME_CNTL 0x86D8 477 #define CP_CE_HALT (1 << 24) 478 #define CP_PFP_HALT (1 << 26) 479 #define CP_ME_HALT (1 << 28) 480 481 #define CP_COHER_CNTL2 0x85E8 482 483 #define CP_RB2_RPTR 0x86f8 484 #define CP_RB1_RPTR 0x86fc 485 #define CP_RB0_RPTR 0x8700 486 #define CP_RB_WPTR_DELAY 0x8704 487 488 #define CP_QUEUE_THRESHOLDS 0x8760 489 #define ROQ_IB1_START(x) ((x) << 0) 490 #define ROQ_IB2_START(x) ((x) << 8) 491 #define CP_MEQ_THRESHOLDS 0x8764 492 #define MEQ1_START(x) ((x) << 0) 493 #define MEQ2_START(x) ((x) << 8) 494 495 #define CP_PERFMON_CNTL 0x87FC 496 497 #define VGT_VTX_VECT_EJECT_REG 0x88B0 498 499 #define VGT_CACHE_INVALIDATION 0x88C4 500 #define CACHE_INVALIDATION(x) ((x) << 0) 501 #define VC_ONLY 0 502 #define TC_ONLY 1 503 #define VC_AND_TC 2 504 #define AUTO_INVLD_EN(x) ((x) << 6) 505 #define NO_AUTO 0 506 #define ES_AUTO 1 507 #define GS_AUTO 2 508 #define ES_AND_GS_AUTO 3 509 #define VGT_ESGS_RING_SIZE 0x88C8 510 #define VGT_GSVS_RING_SIZE 0x88CC 511 512 #define VGT_GS_VERTEX_REUSE 0x88D4 513 514 #define VGT_PRIMITIVE_TYPE 0x8958 515 #define VGT_INDEX_TYPE 0x895C 516 517 #define VGT_NUM_INDICES 0x8970 518 #define VGT_NUM_INSTANCES 0x8974 519 520 #define VGT_TF_RING_SIZE 0x8988 521 522 #define VGT_HS_OFFCHIP_PARAM 0x89B0 523 524 #define VGT_TF_MEMORY_BASE 0x89B8 525 526 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 527 #define INACTIVE_CUS_MASK 0xFFFF0000 528 #define INACTIVE_CUS_SHIFT 16 529 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 530 531 #define PA_CL_ENHANCE 0x8A14 532 #define CLIP_VTX_REORDER_ENA (1 << 0) 533 #define NUM_CLIP_SEQ(x) ((x) << 1) 534 535 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 536 537 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 538 539 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 540 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 541 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 542 543 #define PA_SC_FIFO_SIZE 0x8BCC 544 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 545 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 546 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 547 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 548 549 #define PA_SC_ENHANCE 0x8BF0 550 551 #define SQ_CONFIG 0x8C00 552 553 #define SQC_CACHES 0x8C08 554 555 #define SX_DEBUG_1 0x9060 556 557 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 558 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 559 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 560 #define SPI_PS_MAX_WAVE_ID 0x90EC 561 562 #define SPI_CONFIG_CNTL 0x9100 563 564 #define SPI_CONFIG_CNTL_1 0x913C 565 #define VTX_DONE_DELAY(x) ((x) << 0) 566 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 567 568 #define CGTS_TCC_DISABLE 0x9148 569 #define CGTS_USER_TCC_DISABLE 0x914C 570 #define TCC_DISABLE_MASK 0xFFFF0000 571 #define TCC_DISABLE_SHIFT 16 572 573 #define TA_CNTL_AUX 0x9508 574 575 #define CC_RB_BACKEND_DISABLE 0x98F4 576 #define BACKEND_DISABLE(x) ((x) << 16) 577 #define GB_ADDR_CONFIG 0x98F8 578 #define NUM_PIPES(x) ((x) << 0) 579 #define NUM_PIPES_MASK 0x00000007 580 #define NUM_PIPES_SHIFT 0 581 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 582 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 583 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 584 #define NUM_SHADER_ENGINES(x) ((x) << 12) 585 #define NUM_SHADER_ENGINES_MASK 0x00003000 586 #define NUM_SHADER_ENGINES_SHIFT 12 587 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 588 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 589 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 590 #define NUM_GPUS(x) ((x) << 20) 591 #define NUM_GPUS_MASK 0x00700000 592 #define NUM_GPUS_SHIFT 20 593 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 594 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 595 #define MULTI_GPU_TILE_SIZE_SHIFT 24 596 #define ROW_SIZE(x) ((x) << 28) 597 #define ROW_SIZE_MASK 0x30000000 598 #define ROW_SIZE_SHIFT 28 599 600 #define GB_TILE_MODE0 0x9910 601 # define MICRO_TILE_MODE(x) ((x) << 0) 602 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 603 # define ADDR_SURF_THIN_MICRO_TILING 1 604 # define ADDR_SURF_DEPTH_MICRO_TILING 2 605 # define ARRAY_MODE(x) ((x) << 2) 606 # define ARRAY_LINEAR_GENERAL 0 607 # define ARRAY_LINEAR_ALIGNED 1 608 # define ARRAY_1D_TILED_THIN1 2 609 # define ARRAY_2D_TILED_THIN1 4 610 # define PIPE_CONFIG(x) ((x) << 6) 611 # define ADDR_SURF_P2 0 612 # define ADDR_SURF_P4_8x16 4 613 # define ADDR_SURF_P4_16x16 5 614 # define ADDR_SURF_P4_16x32 6 615 # define ADDR_SURF_P4_32x32 7 616 # define ADDR_SURF_P8_16x16_8x16 8 617 # define ADDR_SURF_P8_16x32_8x16 9 618 # define ADDR_SURF_P8_32x32_8x16 10 619 # define ADDR_SURF_P8_16x32_16x16 11 620 # define ADDR_SURF_P8_32x32_16x16 12 621 # define ADDR_SURF_P8_32x32_16x32 13 622 # define ADDR_SURF_P8_32x64_32x32 14 623 # define TILE_SPLIT(x) ((x) << 11) 624 # define ADDR_SURF_TILE_SPLIT_64B 0 625 # define ADDR_SURF_TILE_SPLIT_128B 1 626 # define ADDR_SURF_TILE_SPLIT_256B 2 627 # define ADDR_SURF_TILE_SPLIT_512B 3 628 # define ADDR_SURF_TILE_SPLIT_1KB 4 629 # define ADDR_SURF_TILE_SPLIT_2KB 5 630 # define ADDR_SURF_TILE_SPLIT_4KB 6 631 # define BANK_WIDTH(x) ((x) << 14) 632 # define ADDR_SURF_BANK_WIDTH_1 0 633 # define ADDR_SURF_BANK_WIDTH_2 1 634 # define ADDR_SURF_BANK_WIDTH_4 2 635 # define ADDR_SURF_BANK_WIDTH_8 3 636 # define BANK_HEIGHT(x) ((x) << 16) 637 # define ADDR_SURF_BANK_HEIGHT_1 0 638 # define ADDR_SURF_BANK_HEIGHT_2 1 639 # define ADDR_SURF_BANK_HEIGHT_4 2 640 # define ADDR_SURF_BANK_HEIGHT_8 3 641 # define MACRO_TILE_ASPECT(x) ((x) << 18) 642 # define ADDR_SURF_MACRO_ASPECT_1 0 643 # define ADDR_SURF_MACRO_ASPECT_2 1 644 # define ADDR_SURF_MACRO_ASPECT_4 2 645 # define ADDR_SURF_MACRO_ASPECT_8 3 646 # define NUM_BANKS(x) ((x) << 20) 647 # define ADDR_SURF_2_BANK 0 648 # define ADDR_SURF_4_BANK 1 649 # define ADDR_SURF_8_BANK 2 650 # define ADDR_SURF_16_BANK 3 651 652 #define CB_PERFCOUNTER0_SELECT0 0x9a20 653 #define CB_PERFCOUNTER0_SELECT1 0x9a24 654 #define CB_PERFCOUNTER1_SELECT0 0x9a28 655 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 656 #define CB_PERFCOUNTER2_SELECT0 0x9a30 657 #define CB_PERFCOUNTER2_SELECT1 0x9a34 658 #define CB_PERFCOUNTER3_SELECT0 0x9a38 659 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 660 661 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 662 #define BACKEND_DISABLE_MASK 0x00FF0000 663 #define BACKEND_DISABLE_SHIFT 16 664 665 #define TCP_CHAN_STEER_LO 0xac0c 666 #define TCP_CHAN_STEER_HI 0xac10 667 668 #define CP_RB0_BASE 0xC100 669 #define CP_RB0_CNTL 0xC104 670 #define RB_BUFSZ(x) ((x) << 0) 671 #define RB_BLKSZ(x) ((x) << 8) 672 #define BUF_SWAP_32BIT (2 << 16) 673 #define RB_NO_UPDATE (1 << 27) 674 #define RB_RPTR_WR_ENA (1 << 31) 675 676 #define CP_RB0_RPTR_ADDR 0xC10C 677 #define CP_RB0_RPTR_ADDR_HI 0xC110 678 #define CP_RB0_WPTR 0xC114 679 680 #define CP_PFP_UCODE_ADDR 0xC150 681 #define CP_PFP_UCODE_DATA 0xC154 682 #define CP_ME_RAM_RADDR 0xC158 683 #define CP_ME_RAM_WADDR 0xC15C 684 #define CP_ME_RAM_DATA 0xC160 685 686 #define CP_CE_UCODE_ADDR 0xC168 687 #define CP_CE_UCODE_DATA 0xC16C 688 689 #define CP_RB1_BASE 0xC180 690 #define CP_RB1_CNTL 0xC184 691 #define CP_RB1_RPTR_ADDR 0xC188 692 #define CP_RB1_RPTR_ADDR_HI 0xC18C 693 #define CP_RB1_WPTR 0xC190 694 #define CP_RB2_BASE 0xC194 695 #define CP_RB2_CNTL 0xC198 696 #define CP_RB2_RPTR_ADDR 0xC19C 697 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 698 #define CP_RB2_WPTR 0xC1A4 699 #define CP_INT_CNTL_RING0 0xC1A8 700 #define CP_INT_CNTL_RING1 0xC1AC 701 #define CP_INT_CNTL_RING2 0xC1B0 702 # define CNTX_BUSY_INT_ENABLE (1 << 19) 703 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 704 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 705 # define TIME_STAMP_INT_ENABLE (1 << 26) 706 # define CP_RINGID2_INT_ENABLE (1 << 29) 707 # define CP_RINGID1_INT_ENABLE (1 << 30) 708 # define CP_RINGID0_INT_ENABLE (1 << 31) 709 #define CP_INT_STATUS_RING0 0xC1B4 710 #define CP_INT_STATUS_RING1 0xC1B8 711 #define CP_INT_STATUS_RING2 0xC1BC 712 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 713 # define TIME_STAMP_INT_STAT (1 << 26) 714 # define CP_RINGID2_INT_STAT (1 << 29) 715 # define CP_RINGID1_INT_STAT (1 << 30) 716 # define CP_RINGID0_INT_STAT (1 << 31) 717 718 #define CP_DEBUG 0xC1FC 719 720 #define RLC_CNTL 0xC300 721 # define RLC_ENABLE (1 << 0) 722 #define RLC_RL_BASE 0xC304 723 #define RLC_RL_SIZE 0xC308 724 #define RLC_LB_CNTL 0xC30C 725 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 726 #define RLC_LB_CNTR_MAX 0xC314 727 #define RLC_LB_CNTR_INIT 0xC318 728 729 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 730 731 #define RLC_UCODE_ADDR 0xC32C 732 #define RLC_UCODE_DATA 0xC330 733 734 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 735 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 736 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 737 #define RLC_MC_CNTL 0xC344 738 #define RLC_UCODE_CNTL 0xC348 739 740 #define PA_SC_RASTER_CONFIG 0x28350 741 # define RASTER_CONFIG_RB_MAP_0 0 742 # define RASTER_CONFIG_RB_MAP_1 1 743 # define RASTER_CONFIG_RB_MAP_2 2 744 # define RASTER_CONFIG_RB_MAP_3 3 745 746 #define VGT_EVENT_INITIATOR 0x28a90 747 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 748 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 749 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 750 # define CACHE_FLUSH_TS (4 << 0) 751 # define CACHE_FLUSH (6 << 0) 752 # define CS_PARTIAL_FLUSH (7 << 0) 753 # define VGT_STREAMOUT_RESET (10 << 0) 754 # define END_OF_PIPE_INCR_DE (11 << 0) 755 # define END_OF_PIPE_IB_END (12 << 0) 756 # define RST_PIX_CNT (13 << 0) 757 # define VS_PARTIAL_FLUSH (15 << 0) 758 # define PS_PARTIAL_FLUSH (16 << 0) 759 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 760 # define ZPASS_DONE (21 << 0) 761 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 762 # define PERFCOUNTER_START (23 << 0) 763 # define PERFCOUNTER_STOP (24 << 0) 764 # define PIPELINESTAT_START (25 << 0) 765 # define PIPELINESTAT_STOP (26 << 0) 766 # define PERFCOUNTER_SAMPLE (27 << 0) 767 # define SAMPLE_PIPELINESTAT (30 << 0) 768 # define SAMPLE_STREAMOUTSTATS (32 << 0) 769 # define RESET_VTX_CNT (33 << 0) 770 # define VGT_FLUSH (36 << 0) 771 # define BOTTOM_OF_PIPE_TS (40 << 0) 772 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 773 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 774 # define FLUSH_AND_INV_DB_META (44 << 0) 775 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 776 # define FLUSH_AND_INV_CB_META (46 << 0) 777 # define CS_DONE (47 << 0) 778 # define PS_DONE (48 << 0) 779 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 780 # define THREAD_TRACE_START (51 << 0) 781 # define THREAD_TRACE_STOP (52 << 0) 782 # define THREAD_TRACE_FLUSH (54 << 0) 783 # define THREAD_TRACE_FINISH (55 << 0) 784 785 /* 786 * PM4 787 */ 788 #define PACKET_TYPE0 0 789 #define PACKET_TYPE1 1 790 #define PACKET_TYPE2 2 791 #define PACKET_TYPE3 3 792 793 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 794 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 795 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 796 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 797 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 798 (((reg) >> 2) & 0xFFFF) | \ 799 ((n) & 0x3FFF) << 16) 800 #define CP_PACKET2 0x80000000 801 #define PACKET2_PAD_SHIFT 0 802 #define PACKET2_PAD_MASK (0x3fffffff << 0) 803 804 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 805 806 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 807 (((op) & 0xFF) << 8) | \ 808 ((n) & 0x3FFF) << 16) 809 810 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 811 812 /* Packet 3 types */ 813 #define PACKET3_NOP 0x10 814 #define PACKET3_SET_BASE 0x11 815 #define PACKET3_BASE_INDEX(x) ((x) << 0) 816 #define GDS_PARTITION_BASE 2 817 #define CE_PARTITION_BASE 3 818 #define PACKET3_CLEAR_STATE 0x12 819 #define PACKET3_INDEX_BUFFER_SIZE 0x13 820 #define PACKET3_DISPATCH_DIRECT 0x15 821 #define PACKET3_DISPATCH_INDIRECT 0x16 822 #define PACKET3_ALLOC_GDS 0x1B 823 #define PACKET3_WRITE_GDS_RAM 0x1C 824 #define PACKET3_ATOMIC_GDS 0x1D 825 #define PACKET3_ATOMIC 0x1E 826 #define PACKET3_OCCLUSION_QUERY 0x1F 827 #define PACKET3_SET_PREDICATION 0x20 828 #define PACKET3_REG_RMW 0x21 829 #define PACKET3_COND_EXEC 0x22 830 #define PACKET3_PRED_EXEC 0x23 831 #define PACKET3_DRAW_INDIRECT 0x24 832 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 833 #define PACKET3_INDEX_BASE 0x26 834 #define PACKET3_DRAW_INDEX_2 0x27 835 #define PACKET3_CONTEXT_CONTROL 0x28 836 #define PACKET3_INDEX_TYPE 0x2A 837 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 838 #define PACKET3_DRAW_INDEX_AUTO 0x2D 839 #define PACKET3_DRAW_INDEX_IMMD 0x2E 840 #define PACKET3_NUM_INSTANCES 0x2F 841 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 842 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 843 #define PACKET3_INDIRECT_BUFFER 0x32 844 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 845 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 846 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 847 #define PACKET3_WRITE_DATA 0x37 848 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 849 /* 0 - register 850 * 1 - memory (sync - via GRBM) 851 * 2 - tc/l2 852 * 3 - gds 853 * 4 - reserved 854 * 5 - memory (async - direct) 855 */ 856 #define WR_ONE_ADDR (1 << 16) 857 #define WR_CONFIRM (1 << 20) 858 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 859 /* 0 - me 860 * 1 - pfp 861 * 2 - ce 862 */ 863 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 864 #define PACKET3_MEM_SEMAPHORE 0x39 865 #define PACKET3_MPEG_INDEX 0x3A 866 #define PACKET3_COPY_DW 0x3B 867 #define PACKET3_WAIT_REG_MEM 0x3C 868 #define PACKET3_MEM_WRITE 0x3D 869 #define PACKET3_COPY_DATA 0x40 870 #define PACKET3_CP_DMA 0x41 871 /* 1. header 872 * 2. SRC_ADDR_LO or DATA [31:0] 873 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 874 * SRC_ADDR_HI [7:0] 875 * 4. DST_ADDR_LO [31:0] 876 * 5. DST_ADDR_HI [7:0] 877 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 878 */ 879 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 880 /* 0 - SRC_ADDR 881 * 1 - GDS 882 */ 883 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 884 /* 0 - ME 885 * 1 - PFP 886 */ 887 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 888 /* 0 - SRC_ADDR 889 * 1 - GDS 890 * 2 - DATA 891 */ 892 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 893 /* COMMAND */ 894 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 895 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 896 /* 0 - none 897 * 1 - 8 in 16 898 * 2 - 8 in 32 899 * 3 - 8 in 64 900 */ 901 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 902 /* 0 - none 903 * 1 - 8 in 16 904 * 2 - 8 in 32 905 * 3 - 8 in 64 906 */ 907 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 908 /* 0 - memory 909 * 1 - register 910 */ 911 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 912 /* 0 - memory 913 * 1 - register 914 */ 915 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 916 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 917 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 918 #define PACKET3_PFP_SYNC_ME 0x42 919 #define PACKET3_SURFACE_SYNC 0x43 920 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 921 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 922 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 923 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 924 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 925 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 926 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 927 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 928 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 929 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 930 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 931 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 932 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 933 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 934 # define PACKET3_TC_ACTION_ENA (1 << 23) 935 # define PACKET3_CB_ACTION_ENA (1 << 25) 936 # define PACKET3_DB_ACTION_ENA (1 << 26) 937 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 938 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 939 #define PACKET3_ME_INITIALIZE 0x44 940 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 941 #define PACKET3_COND_WRITE 0x45 942 #define PACKET3_EVENT_WRITE 0x46 943 #define EVENT_TYPE(x) ((x) << 0) 944 #define EVENT_INDEX(x) ((x) << 8) 945 /* 0 - any non-TS event 946 * 1 - ZPASS_DONE 947 * 2 - SAMPLE_PIPELINESTAT 948 * 3 - SAMPLE_STREAMOUTSTAT* 949 * 4 - *S_PARTIAL_FLUSH 950 * 5 - EOP events 951 * 6 - EOS events 952 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 953 */ 954 #define INV_L2 (1 << 20) 955 /* INV TC L2 cache when EVENT_INDEX = 7 */ 956 #define PACKET3_EVENT_WRITE_EOP 0x47 957 #define DATA_SEL(x) ((x) << 29) 958 /* 0 - discard 959 * 1 - send low 32bit data 960 * 2 - send 64bit data 961 * 3 - send 64bit counter value 962 */ 963 #define INT_SEL(x) ((x) << 24) 964 /* 0 - none 965 * 1 - interrupt only (DATA_SEL = 0) 966 * 2 - interrupt when data write is confirmed 967 */ 968 #define PACKET3_EVENT_WRITE_EOS 0x48 969 #define PACKET3_PREAMBLE_CNTL 0x4A 970 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 971 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 972 #define PACKET3_ONE_REG_WRITE 0x57 973 #define PACKET3_LOAD_CONFIG_REG 0x5F 974 #define PACKET3_LOAD_CONTEXT_REG 0x60 975 #define PACKET3_LOAD_SH_REG 0x61 976 #define PACKET3_SET_CONFIG_REG 0x68 977 #define PACKET3_SET_CONFIG_REG_START 0x00008000 978 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 979 #define PACKET3_SET_CONTEXT_REG 0x69 980 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 981 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 982 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 983 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 984 #define PACKET3_SET_SH_REG 0x76 985 #define PACKET3_SET_SH_REG_START 0x0000b000 986 #define PACKET3_SET_SH_REG_END 0x0000c000 987 #define PACKET3_SET_SH_REG_OFFSET 0x77 988 #define PACKET3_ME_WRITE 0x7A 989 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 990 #define PACKET3_SCRATCH_RAM_READ 0x7E 991 #define PACKET3_CE_WRITE 0x7F 992 #define PACKET3_LOAD_CONST_RAM 0x80 993 #define PACKET3_WRITE_CONST_RAM 0x81 994 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 995 #define PACKET3_DUMP_CONST_RAM 0x83 996 #define PACKET3_INCREMENT_CE_COUNTER 0x84 997 #define PACKET3_INCREMENT_DE_COUNTER 0x85 998 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 999 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1000 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1001 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1002 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1003 #define PACKET3_SWITCH_BUFFER 0x8B 1004 1005 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1006 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1007 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1008 1009 #define DMA_RB_CNTL 0xd000 1010 # define DMA_RB_ENABLE (1 << 0) 1011 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1012 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1013 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1014 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1015 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1016 #define DMA_RB_BASE 0xd004 1017 #define DMA_RB_RPTR 0xd008 1018 #define DMA_RB_WPTR 0xd00c 1019 1020 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1021 #define DMA_RB_RPTR_ADDR_LO 0xd020 1022 1023 #define DMA_IB_CNTL 0xd024 1024 # define DMA_IB_ENABLE (1 << 0) 1025 # define DMA_IB_SWAP_ENABLE (1 << 4) 1026 #define DMA_IB_RPTR 0xd028 1027 #define DMA_CNTL 0xd02c 1028 # define TRAP_ENABLE (1 << 0) 1029 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1030 # define SEM_WAIT_INT_ENABLE (1 << 2) 1031 # define DATA_SWAP_ENABLE (1 << 3) 1032 # define FENCE_SWAP_ENABLE (1 << 4) 1033 # define CTXEMPTY_INT_ENABLE (1 << 28) 1034 #define DMA_STATUS_REG 0xd034 1035 # define DMA_IDLE (1 << 0) 1036 #define DMA_TILING_CONFIG 0xd0b8 1037 1038 #define DMA_PACKET(cmd, b, t, s, n) ((((cmd) & 0xF) << 28) | \ 1039 (((b) & 0x1) << 26) | \ 1040 (((t) & 0x1) << 23) | \ 1041 (((s) & 0x1) << 22) | \ 1042 (((n) & 0xFFFFF) << 0)) 1043 1044 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1045 (((vmid) & 0xF) << 20) | \ 1046 (((n) & 0xFFFFF) << 0)) 1047 1048 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1049 (1 << 26) | \ 1050 (1 << 21) | \ 1051 (((n) & 0xFFFFF) << 0)) 1052 1053 /* async DMA Packet types */ 1054 #define DMA_PACKET_WRITE 0x2 1055 #define DMA_PACKET_COPY 0x3 1056 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1057 #define DMA_PACKET_SEMAPHORE 0x5 1058 #define DMA_PACKET_FENCE 0x6 1059 #define DMA_PACKET_TRAP 0x7 1060 #define DMA_PACKET_SRBM_WRITE 0x9 1061 #define DMA_PACKET_CONSTANT_FILL 0xd 1062 #define DMA_PACKET_NOP 0xf 1063 1064 #endif 1065