14cd92098Szrj /* 24cd92098Szrj * Copyright 2013 Advanced Micro Devices, Inc. 34cd92098Szrj * 44cd92098Szrj * Permission is hereby granted, free of charge, to any person obtaining a 54cd92098Szrj * copy of this software and associated documentation files (the "Software"), 64cd92098Szrj * to deal in the Software without restriction, including without limitation 74cd92098Szrj * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84cd92098Szrj * and/or sell copies of the Software, and to permit persons to whom the 94cd92098Szrj * Software is furnished to do so, subject to the following conditions: 104cd92098Szrj * 114cd92098Szrj * The above copyright notice and this permission notice shall be included in 124cd92098Szrj * all copies or substantial portions of the Software. 134cd92098Szrj * 144cd92098Szrj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154cd92098Szrj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164cd92098Szrj * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174cd92098Szrj * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184cd92098Szrj * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194cd92098Szrj * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204cd92098Szrj * OTHER DEALINGS IN THE SOFTWARE. 214cd92098Szrj * 224cd92098Szrj */ 234cd92098Szrj 244cd92098Szrj #ifndef SMU7_FUSION_H 254cd92098Szrj #define SMU7_FUSION_H 264cd92098Szrj 274cd92098Szrj #include "smu7.h" 284cd92098Szrj 294cd92098Szrj #pragma pack(push, 1) 304cd92098Szrj 314cd92098Szrj #define SMU7_DTE_ITERATIONS 5 324cd92098Szrj #define SMU7_DTE_SOURCES 5 334cd92098Szrj #define SMU7_DTE_SINKS 3 344cd92098Szrj #define SMU7_NUM_CPU_TES 2 354cd92098Szrj #define SMU7_NUM_GPU_TES 1 364cd92098Szrj #define SMU7_NUM_NON_TES 2 374cd92098Szrj 384cd92098Szrj // All 'soft registers' should be uint32_t. 394cd92098Szrj struct SMU7_SoftRegisters 404cd92098Szrj { 414cd92098Szrj uint32_t RefClockFrequency; 424cd92098Szrj uint32_t PmTimerP; 434cd92098Szrj uint32_t FeatureEnables; 444cd92098Szrj uint32_t HandshakeDisables; 454cd92098Szrj 464cd92098Szrj uint8_t DisplayPhy1Config; 474cd92098Szrj uint8_t DisplayPhy2Config; 484cd92098Szrj uint8_t DisplayPhy3Config; 494cd92098Szrj uint8_t DisplayPhy4Config; 504cd92098Szrj 514cd92098Szrj uint8_t DisplayPhy5Config; 524cd92098Szrj uint8_t DisplayPhy6Config; 534cd92098Szrj uint8_t DisplayPhy7Config; 544cd92098Szrj uint8_t DisplayPhy8Config; 554cd92098Szrj 564cd92098Szrj uint32_t AverageGraphicsA; 574cd92098Szrj uint32_t AverageMemoryA; 584cd92098Szrj uint32_t AverageGioA; 594cd92098Szrj 604cd92098Szrj uint8_t SClkDpmEnabledLevels; 614cd92098Szrj uint8_t MClkDpmEnabledLevels; 624cd92098Szrj uint8_t LClkDpmEnabledLevels; 634cd92098Szrj uint8_t PCIeDpmEnabledLevels; 644cd92098Szrj 654cd92098Szrj uint8_t UVDDpmEnabledLevels; 664cd92098Szrj uint8_t SAMUDpmEnabledLevels; 674cd92098Szrj uint8_t ACPDpmEnabledLevels; 684cd92098Szrj uint8_t VCEDpmEnabledLevels; 694cd92098Szrj 704cd92098Szrj uint32_t DRAM_LOG_ADDR_H; 714cd92098Szrj uint32_t DRAM_LOG_ADDR_L; 724cd92098Szrj uint32_t DRAM_LOG_PHY_ADDR_H; 734cd92098Szrj uint32_t DRAM_LOG_PHY_ADDR_L; 744cd92098Szrj uint32_t DRAM_LOG_BUFF_SIZE; 754cd92098Szrj uint32_t UlvEnterC; 764cd92098Szrj uint32_t UlvTime; 774cd92098Szrj uint32_t Reserved[3]; 784cd92098Szrj 794cd92098Szrj }; 804cd92098Szrj 814cd92098Szrj typedef struct SMU7_SoftRegisters SMU7_SoftRegisters; 824cd92098Szrj 834cd92098Szrj struct SMU7_Fusion_GraphicsLevel 844cd92098Szrj { 854cd92098Szrj uint32_t MinVddNb; 864cd92098Szrj 874cd92098Szrj uint32_t SclkFrequency; 884cd92098Szrj 894cd92098Szrj uint8_t Vid; 904cd92098Szrj uint8_t VidOffset; 914cd92098Szrj uint16_t AT; 924cd92098Szrj 934cd92098Szrj uint8_t PowerThrottle; 944cd92098Szrj uint8_t GnbSlow; 954cd92098Szrj uint8_t ForceNbPs1; 964cd92098Szrj uint8_t SclkDid; 974cd92098Szrj 984cd92098Szrj uint8_t DisplayWatermark; 994cd92098Szrj uint8_t EnabledForActivity; 1004cd92098Szrj uint8_t EnabledForThrottle; 1014cd92098Szrj uint8_t UpH; 1024cd92098Szrj 1034cd92098Szrj uint8_t DownH; 1044cd92098Szrj uint8_t VoltageDownH; 1054cd92098Szrj uint8_t DeepSleepDivId; 1064cd92098Szrj 1074cd92098Szrj uint8_t ClkBypassCntl; 1084cd92098Szrj 1094cd92098Szrj uint32_t reserved; 1104cd92098Szrj }; 1114cd92098Szrj 1124cd92098Szrj typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel; 1134cd92098Szrj 1144cd92098Szrj struct SMU7_Fusion_GIOLevel 1154cd92098Szrj { 1164cd92098Szrj uint8_t EnabledForActivity; 1174cd92098Szrj uint8_t LclkDid; 1184cd92098Szrj uint8_t Vid; 1194cd92098Szrj uint8_t VoltageDownH; 1204cd92098Szrj 1214cd92098Szrj uint32_t MinVddNb; 1224cd92098Szrj 1234cd92098Szrj uint16_t ResidencyCounter; 1244cd92098Szrj uint8_t UpH; 1254cd92098Szrj uint8_t DownH; 1264cd92098Szrj 1274cd92098Szrj uint32_t LclkFrequency; 1284cd92098Szrj 1294cd92098Szrj uint8_t ActivityLevel; 1304cd92098Szrj uint8_t EnabledForThrottle; 1314cd92098Szrj 1324cd92098Szrj uint8_t ClkBypassCntl; 1334cd92098Szrj 1344cd92098Szrj uint8_t padding; 1354cd92098Szrj }; 1364cd92098Szrj 1374cd92098Szrj typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel; 1384cd92098Szrj 1394cd92098Szrj // UVD VCLK/DCLK state (level) definition. 1404cd92098Szrj struct SMU7_Fusion_UvdLevel 1414cd92098Szrj { 1424cd92098Szrj uint32_t VclkFrequency; 1434cd92098Szrj uint32_t DclkFrequency; 1444cd92098Szrj uint16_t MinVddNb; 1454cd92098Szrj uint8_t VclkDivider; 1464cd92098Szrj uint8_t DclkDivider; 1474cd92098Szrj 1484cd92098Szrj uint8_t VClkBypassCntl; 1494cd92098Szrj uint8_t DClkBypassCntl; 1504cd92098Szrj 1514cd92098Szrj uint8_t padding[2]; 1524cd92098Szrj 1534cd92098Szrj }; 1544cd92098Szrj 1554cd92098Szrj typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel; 1564cd92098Szrj 1574cd92098Szrj // Clocks for other external blocks (VCE, ACP, SAMU). 1584cd92098Szrj struct SMU7_Fusion_ExtClkLevel 1594cd92098Szrj { 1604cd92098Szrj uint32_t Frequency; 1614cd92098Szrj uint16_t MinVoltage; 1624cd92098Szrj uint8_t Divider; 1634cd92098Szrj uint8_t ClkBypassCntl; 1644cd92098Szrj 1654cd92098Szrj uint32_t Reserved; 1664cd92098Szrj }; 1674cd92098Szrj typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel; 1684cd92098Szrj 1694cd92098Szrj struct SMU7_Fusion_ACPILevel 1704cd92098Szrj { 1714cd92098Szrj uint32_t Flags; 1724cd92098Szrj uint32_t MinVddNb; 1734cd92098Szrj uint32_t SclkFrequency; 1744cd92098Szrj uint8_t SclkDid; 1754cd92098Szrj uint8_t GnbSlow; 1764cd92098Szrj uint8_t ForceNbPs1; 1774cd92098Szrj uint8_t DisplayWatermark; 1784cd92098Szrj uint8_t DeepSleepDivId; 1794cd92098Szrj uint8_t padding[3]; 1804cd92098Szrj }; 1814cd92098Szrj 1824cd92098Szrj typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel; 1834cd92098Szrj 1844cd92098Szrj struct SMU7_Fusion_NbDpm 1854cd92098Szrj { 1864cd92098Szrj uint8_t DpmXNbPsHi; 1874cd92098Szrj uint8_t DpmXNbPsLo; 1884cd92098Szrj uint8_t Dpm0PgNbPsHi; 1894cd92098Szrj uint8_t Dpm0PgNbPsLo; 1904cd92098Szrj uint8_t EnablePsi1; 1914cd92098Szrj uint8_t SkipDPM0; 1924cd92098Szrj uint8_t SkipPG; 1934cd92098Szrj uint8_t Hysteresis; 1944cd92098Szrj uint8_t EnableDpmPstatePoll; 1954cd92098Szrj uint8_t padding[3]; 1964cd92098Szrj }; 1974cd92098Szrj 1984cd92098Szrj typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm; 1994cd92098Szrj 2004cd92098Szrj struct SMU7_Fusion_StateInfo 2014cd92098Szrj { 2024cd92098Szrj uint32_t SclkFrequency; 2034cd92098Szrj uint32_t LclkFrequency; 2044cd92098Szrj uint32_t VclkFrequency; 2054cd92098Szrj uint32_t DclkFrequency; 2064cd92098Szrj uint32_t SamclkFrequency; 2074cd92098Szrj uint32_t AclkFrequency; 2084cd92098Szrj uint32_t EclkFrequency; 2094cd92098Szrj uint8_t DisplayWatermark; 2104cd92098Szrj uint8_t McArbIndex; 2114cd92098Szrj int8_t SclkIndex; 2124cd92098Szrj int8_t MclkIndex; 2134cd92098Szrj }; 2144cd92098Szrj 2154cd92098Szrj typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo; 2164cd92098Szrj 2174cd92098Szrj struct SMU7_Fusion_DpmTable 2184cd92098Szrj { 2194cd92098Szrj uint32_t SystemFlags; 2204cd92098Szrj 2214cd92098Szrj SMU7_PIDController GraphicsPIDController; 2224cd92098Szrj SMU7_PIDController GioPIDController; 2234cd92098Szrj 2244cd92098Szrj uint8_t GraphicsDpmLevelCount; 2254cd92098Szrj uint8_t GIOLevelCount; 2264cd92098Szrj uint8_t UvdLevelCount; 2274cd92098Szrj uint8_t VceLevelCount; 2284cd92098Szrj 2294cd92098Szrj uint8_t AcpLevelCount; 2304cd92098Szrj uint8_t SamuLevelCount; 2314cd92098Szrj uint16_t FpsHighT; 2324cd92098Szrj 2334cd92098Szrj SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE]; 2344cd92098Szrj SMU7_Fusion_ACPILevel ACPILevel; 2354cd92098Szrj SMU7_Fusion_UvdLevel UvdLevel [SMU7_MAX_LEVELS_UVD]; 2364cd92098Szrj SMU7_Fusion_ExtClkLevel VceLevel [SMU7_MAX_LEVELS_VCE]; 2374cd92098Szrj SMU7_Fusion_ExtClkLevel AcpLevel [SMU7_MAX_LEVELS_ACP]; 2384cd92098Szrj SMU7_Fusion_ExtClkLevel SamuLevel [SMU7_MAX_LEVELS_SAMU]; 2394cd92098Szrj 2404cd92098Szrj uint8_t UvdBootLevel; 2414cd92098Szrj uint8_t VceBootLevel; 2424cd92098Szrj uint8_t AcpBootLevel; 2434cd92098Szrj uint8_t SamuBootLevel; 2444cd92098Szrj uint8_t UVDInterval; 2454cd92098Szrj uint8_t VCEInterval; 2464cd92098Szrj uint8_t ACPInterval; 2474cd92098Szrj uint8_t SAMUInterval; 2484cd92098Szrj 2494cd92098Szrj uint8_t GraphicsBootLevel; 2504cd92098Szrj uint8_t GraphicsInterval; 2514cd92098Szrj uint8_t GraphicsThermThrottleEnable; 2524cd92098Szrj uint8_t GraphicsVoltageChangeEnable; 2534cd92098Szrj 2544cd92098Szrj uint8_t GraphicsClkSlowEnable; 2554cd92098Szrj uint8_t GraphicsClkSlowDivider; 2564cd92098Szrj uint16_t FpsLowT; 2574cd92098Szrj 2584cd92098Szrj uint32_t DisplayCac; 2594cd92098Szrj uint32_t LowSclkInterruptT; 2604cd92098Szrj 2614cd92098Szrj uint32_t DRAM_LOG_ADDR_H; 2624cd92098Szrj uint32_t DRAM_LOG_ADDR_L; 2634cd92098Szrj uint32_t DRAM_LOG_PHY_ADDR_H; 2644cd92098Szrj uint32_t DRAM_LOG_PHY_ADDR_L; 2654cd92098Szrj uint32_t DRAM_LOG_BUFF_SIZE; 2664cd92098Szrj 2674cd92098Szrj }; 2684cd92098Szrj 2694cd92098Szrj struct SMU7_Fusion_GIODpmTable 2704cd92098Szrj { 2714cd92098Szrj 2724cd92098Szrj SMU7_Fusion_GIOLevel GIOLevel [SMU7_MAX_LEVELS_GIO]; 2734cd92098Szrj 2744cd92098Szrj SMU7_PIDController GioPIDController; 2754cd92098Szrj 2764cd92098Szrj uint32_t GIOLevelCount; 2774cd92098Szrj 2784cd92098Szrj uint8_t Enable; 2794cd92098Szrj uint8_t GIOVoltageChangeEnable; 2804cd92098Szrj uint8_t GIOBootLevel; 2814cd92098Szrj uint8_t padding; 2824cd92098Szrj uint8_t padding1[2]; 2834cd92098Szrj uint8_t TargetState; 2844cd92098Szrj uint8_t CurrenttState; 2854cd92098Szrj uint8_t ThrottleOnHtc; 2864cd92098Szrj uint8_t ThermThrottleStatus; 2874cd92098Szrj uint8_t ThermThrottleTempSelect; 2884cd92098Szrj uint8_t ThermThrottleEnable; 2894cd92098Szrj uint16_t TemperatureLimitHigh; 2904cd92098Szrj uint16_t TemperatureLimitLow; 2914cd92098Szrj 2924cd92098Szrj }; 2934cd92098Szrj 2944cd92098Szrj typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable; 2954cd92098Szrj typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable; 2964cd92098Szrj 2974cd92098Szrj #pragma pack(pop) 2984cd92098Szrj 2994cd92098Szrj #endif 300*a39b2473SFrançois Tigeot 301