1*57e252bfSMichael Neumann /* 2*57e252bfSMichael Neumann * Copyright 2012 Advanced Micro Devices, Inc. 3*57e252bfSMichael Neumann * 4*57e252bfSMichael Neumann * Permission is hereby granted, free of charge, to any person obtaining a 5*57e252bfSMichael Neumann * copy of this software and associated documentation files (the "Software"), 6*57e252bfSMichael Neumann * to deal in the Software without restriction, including without limitation 7*57e252bfSMichael Neumann * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*57e252bfSMichael Neumann * and/or sell copies of the Software, and to permit persons to whom the 9*57e252bfSMichael Neumann * Software is furnished to do so, subject to the following conditions: 10*57e252bfSMichael Neumann * 11*57e252bfSMichael Neumann * The above copyright notice and this permission notice shall be included in 12*57e252bfSMichael Neumann * all copies or substantial portions of the Software. 13*57e252bfSMichael Neumann * 14*57e252bfSMichael Neumann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*57e252bfSMichael Neumann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*57e252bfSMichael Neumann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*57e252bfSMichael Neumann * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*57e252bfSMichael Neumann * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*57e252bfSMichael Neumann * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*57e252bfSMichael Neumann * OTHER DEALINGS IN THE SOFTWARE. 21*57e252bfSMichael Neumann * 22*57e252bfSMichael Neumann * Authors: Alex Deucher 23*57e252bfSMichael Neumann */ 24*57e252bfSMichael Neumann #ifndef _TRINITYD_H_ 25*57e252bfSMichael Neumann #define _TRINITYD_H_ 26*57e252bfSMichael Neumann 27*57e252bfSMichael Neumann /* pm registers */ 28*57e252bfSMichael Neumann 29*57e252bfSMichael Neumann /* cg */ 30*57e252bfSMichael Neumann #define CG_CGTT_LOCAL_0 0x0 31*57e252bfSMichael Neumann #define CG_CGTT_LOCAL_1 0x1 32*57e252bfSMichael Neumann 33*57e252bfSMichael Neumann /* smc */ 34*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 35*57e252bfSMichael Neumann # define STATE_VALID(x) ((x) << 0) 36*57e252bfSMichael Neumann # define STATE_VALID_MASK (0xff << 0) 37*57e252bfSMichael Neumann # define STATE_VALID_SHIFT 0 38*57e252bfSMichael Neumann # define CLK_DIVIDER(x) ((x) << 8) 39*57e252bfSMichael Neumann # define CLK_DIVIDER_MASK (0xff << 8) 40*57e252bfSMichael Neumann # define CLK_DIVIDER_SHIFT 8 41*57e252bfSMichael Neumann # define VID(x) ((x) << 16) 42*57e252bfSMichael Neumann # define VID_MASK (0xff << 16) 43*57e252bfSMichael Neumann # define VID_SHIFT 16 44*57e252bfSMichael Neumann # define LVRT(x) ((x) << 24) 45*57e252bfSMichael Neumann # define LVRT_MASK (0xff << 24) 46*57e252bfSMichael Neumann # define LVRT_SHIFT 24 47*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 48*57e252bfSMichael Neumann # define DS_DIV(x) ((x) << 0) 49*57e252bfSMichael Neumann # define DS_DIV_MASK (0xff << 0) 50*57e252bfSMichael Neumann # define DS_DIV_SHIFT 0 51*57e252bfSMichael Neumann # define DS_SH_DIV(x) ((x) << 8) 52*57e252bfSMichael Neumann # define DS_SH_DIV_MASK (0xff << 8) 53*57e252bfSMichael Neumann # define DS_SH_DIV_SHIFT 8 54*57e252bfSMichael Neumann # define DISPLAY_WM(x) ((x) << 16) 55*57e252bfSMichael Neumann # define DISPLAY_WM_MASK (0xff << 16) 56*57e252bfSMichael Neumann # define DISPLAY_WM_SHIFT 16 57*57e252bfSMichael Neumann # define VCE_WM(x) ((x) << 24) 58*57e252bfSMichael Neumann # define VCE_WM_MASK (0xff << 24) 59*57e252bfSMichael Neumann # define VCE_WM_SHIFT 24 60*57e252bfSMichael Neumann 61*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c 62*57e252bfSMichael Neumann # define GNB_SLOW(x) ((x) << 0) 63*57e252bfSMichael Neumann # define GNB_SLOW_MASK (0xff << 0) 64*57e252bfSMichael Neumann # define GNB_SLOW_SHIFT 0 65*57e252bfSMichael Neumann # define FORCE_NBPS1(x) ((x) << 8) 66*57e252bfSMichael Neumann # define FORCE_NBPS1_MASK (0xff << 8) 67*57e252bfSMichael Neumann # define FORCE_NBPS1_SHIFT 8 68*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_0_AT 0x1f010 69*57e252bfSMichael Neumann # define AT(x) ((x) << 0) 70*57e252bfSMichael Neumann # define AT_MASK (0xff << 0) 71*57e252bfSMichael Neumann # define AT_SHIFT 0 72*57e252bfSMichael Neumann 73*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 74*57e252bfSMichael Neumann # define PD_SCLK_DIVIDER(x) ((x) << 16) 75*57e252bfSMichael Neumann # define PD_SCLK_DIVIDER_MASK (0xff << 16) 76*57e252bfSMichael Neumann # define PD_SCLK_DIVIDER_SHIFT 16 77*57e252bfSMichael Neumann 78*57e252bfSMichael Neumann #define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 79*57e252bfSMichael Neumann 80*57e252bfSMichael Neumann #define SMU_SCLK_DPM_CNTL 0x1f100 81*57e252bfSMichael Neumann # define SCLK_DPM_EN(x) ((x) << 0) 82*57e252bfSMichael Neumann # define SCLK_DPM_EN_MASK (0xff << 0) 83*57e252bfSMichael Neumann # define SCLK_DPM_EN_SHIFT 0 84*57e252bfSMichael Neumann # define SCLK_DPM_BOOT_STATE(x) ((x) << 16) 85*57e252bfSMichael Neumann # define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) 86*57e252bfSMichael Neumann # define SCLK_DPM_BOOT_STATE_SHIFT 16 87*57e252bfSMichael Neumann # define VOLTAGE_CHG_EN(x) ((x) << 24) 88*57e252bfSMichael Neumann # define VOLTAGE_CHG_EN_MASK (0xff << 24) 89*57e252bfSMichael Neumann # define VOLTAGE_CHG_EN_SHIFT 24 90*57e252bfSMichael Neumann 91*57e252bfSMichael Neumann #define SMU_SCLK_DPM_TT_CNTL 0x1f108 92*57e252bfSMichael Neumann # define SCLK_TT_EN(x) ((x) << 0) 93*57e252bfSMichael Neumann # define SCLK_TT_EN_MASK (0xff << 0) 94*57e252bfSMichael Neumann # define SCLK_TT_EN_SHIFT 0 95*57e252bfSMichael Neumann #define SMU_SCLK_DPM_TTT 0x1f10c 96*57e252bfSMichael Neumann # define LT(x) ((x) << 0) 97*57e252bfSMichael Neumann # define LT_MASK (0xffff << 0) 98*57e252bfSMichael Neumann # define LT_SHIFT 0 99*57e252bfSMichael Neumann # define HT(x) ((x) << 16) 100*57e252bfSMichael Neumann # define HT_MASK (0xffff << 16) 101*57e252bfSMichael Neumann # define HT_SHIFT 16 102*57e252bfSMichael Neumann 103*57e252bfSMichael Neumann #define SMU_UVD_DPM_STATES 0x1f1a0 104*57e252bfSMichael Neumann #define SMU_UVD_DPM_CNTL 0x1f1a4 105*57e252bfSMichael Neumann 106*57e252bfSMichael Neumann #define SMU_S_PG_CNTL 0x1f118 107*57e252bfSMichael Neumann # define DS_PG_EN(x) ((x) << 16) 108*57e252bfSMichael Neumann # define DS_PG_EN_MASK (0xff << 16) 109*57e252bfSMichael Neumann # define DS_PG_EN_SHIFT 16 110*57e252bfSMichael Neumann 111*57e252bfSMichael Neumann #define GFX_POWER_GATING_CNTL 0x1f38c 112*57e252bfSMichael Neumann # define PDS_DIV(x) ((x) << 0) 113*57e252bfSMichael Neumann # define PDS_DIV_MASK (0xff << 0) 114*57e252bfSMichael Neumann # define PDS_DIV_SHIFT 0 115*57e252bfSMichael Neumann # define SSSD(x) ((x) << 8) 116*57e252bfSMichael Neumann # define SSSD_MASK (0xff << 8) 117*57e252bfSMichael Neumann # define SSSD_SHIFT 8 118*57e252bfSMichael Neumann 119*57e252bfSMichael Neumann #define PM_CONFIG 0x1f428 120*57e252bfSMichael Neumann # define SVI_Mode (1 << 29) 121*57e252bfSMichael Neumann 122*57e252bfSMichael Neumann #define PM_I_CNTL_1 0x1f464 123*57e252bfSMichael Neumann # define SCLK_DPM(x) ((x) << 0) 124*57e252bfSMichael Neumann # define SCLK_DPM_MASK (0xff << 0) 125*57e252bfSMichael Neumann # define SCLK_DPM_SHIFT 0 126*57e252bfSMichael Neumann # define DS_PG_CNTL(x) ((x) << 16) 127*57e252bfSMichael Neumann # define DS_PG_CNTL_MASK (0xff << 16) 128*57e252bfSMichael Neumann # define DS_PG_CNTL_SHIFT 16 129*57e252bfSMichael Neumann #define PM_TP 0x1f468 130*57e252bfSMichael Neumann 131*57e252bfSMichael Neumann #define NB_PSTATE_CONFIG 0x1f5f8 132*57e252bfSMichael Neumann # define Dpm0PgNbPsLo(x) ((x) << 0) 133*57e252bfSMichael Neumann # define Dpm0PgNbPsLo_MASK (3 << 0) 134*57e252bfSMichael Neumann # define Dpm0PgNbPsLo_SHIFT 0 135*57e252bfSMichael Neumann # define Dpm0PgNbPsHi(x) ((x) << 2) 136*57e252bfSMichael Neumann # define Dpm0PgNbPsHi_MASK (3 << 2) 137*57e252bfSMichael Neumann # define Dpm0PgNbPsHi_SHIFT 2 138*57e252bfSMichael Neumann # define DpmXNbPsLo(x) ((x) << 4) 139*57e252bfSMichael Neumann # define DpmXNbPsLo_MASK (3 << 4) 140*57e252bfSMichael Neumann # define DpmXNbPsLo_SHIFT 4 141*57e252bfSMichael Neumann # define DpmXNbPsHi(x) ((x) << 6) 142*57e252bfSMichael Neumann # define DpmXNbPsHi_MASK (3 << 6) 143*57e252bfSMichael Neumann # define DpmXNbPsHi_SHIFT 6 144*57e252bfSMichael Neumann 145*57e252bfSMichael Neumann #define DC_CAC_VALUE 0x1f908 146*57e252bfSMichael Neumann 147*57e252bfSMichael Neumann #define GPU_CAC_AVRG_CNTL 0x1f920 148*57e252bfSMichael Neumann # define WINDOW_SIZE(x) ((x) << 0) 149*57e252bfSMichael Neumann # define WINDOW_SIZE_MASK (0xff << 0) 150*57e252bfSMichael Neumann # define WINDOW_SIZE_SHIFT 0 151*57e252bfSMichael Neumann 152*57e252bfSMichael Neumann #define CC_SMU_MISC_FUSES 0xe0001004 153*57e252bfSMichael Neumann # define MinSClkDid(x) ((x) << 2) 154*57e252bfSMichael Neumann # define MinSClkDid_MASK (0x7f << 2) 155*57e252bfSMichael Neumann # define MinSClkDid_SHIFT 2 156*57e252bfSMichael Neumann 157*57e252bfSMichael Neumann #define CC_SMU_TST_EFUSE1_MISC 0xe000101c 158*57e252bfSMichael Neumann # define RB_BACKEND_DISABLE(x) ((x) << 16) 159*57e252bfSMichael Neumann # define RB_BACKEND_DISABLE_MASK (3 << 16) 160*57e252bfSMichael Neumann # define RB_BACKEND_DISABLE_SHIFT 16 161*57e252bfSMichael Neumann 162*57e252bfSMichael Neumann #define SMU_SCRATCH_A 0xe0003024 163*57e252bfSMichael Neumann 164*57e252bfSMichael Neumann #define SMU_SCRATCH0 0xe0003040 165*57e252bfSMichael Neumann 166*57e252bfSMichael Neumann /* mmio */ 167*57e252bfSMichael Neumann #define SMC_INT_REQ 0x220 168*57e252bfSMichael Neumann 169*57e252bfSMichael Neumann #define SMC_MESSAGE_0 0x22c 170*57e252bfSMichael Neumann #define SMC_RESP_0 0x230 171*57e252bfSMichael Neumann 172*57e252bfSMichael Neumann #define GENERAL_PWRMGT 0x670 173*57e252bfSMichael Neumann # define GLOBAL_PWRMGT_EN (1 << 0) 174*57e252bfSMichael Neumann 175*57e252bfSMichael Neumann #define SCLK_PWRMGT_CNTL 0x678 176*57e252bfSMichael Neumann # define DYN_PWR_DOWN_EN (1 << 2) 177*57e252bfSMichael Neumann # define RESET_BUSY_CNT (1 << 4) 178*57e252bfSMichael Neumann # define RESET_SCLK_CNT (1 << 5) 179*57e252bfSMichael Neumann # define DYN_GFX_CLK_OFF_EN (1 << 7) 180*57e252bfSMichael Neumann # define GFX_CLK_FORCE_ON (1 << 8) 181*57e252bfSMichael Neumann # define DYNAMIC_PM_EN (1 << 21) 182*57e252bfSMichael Neumann 183*57e252bfSMichael Neumann #define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 184*57e252bfSMichael Neumann # define TARGET_STATE(x) ((x) << 0) 185*57e252bfSMichael Neumann # define TARGET_STATE_MASK (0xf << 0) 186*57e252bfSMichael Neumann # define TARGET_STATE_SHIFT 0 187*57e252bfSMichael Neumann # define CURRENT_STATE(x) ((x) << 4) 188*57e252bfSMichael Neumann # define CURRENT_STATE_MASK (0xf << 4) 189*57e252bfSMichael Neumann # define CURRENT_STATE_SHIFT 4 190*57e252bfSMichael Neumann 191*57e252bfSMichael Neumann #define CG_GIPOTS 0x6d8 192*57e252bfSMichael Neumann # define CG_GIPOT(x) ((x) << 16) 193*57e252bfSMichael Neumann # define CG_GIPOT_MASK (0xffff << 16) 194*57e252bfSMichael Neumann # define CG_GIPOT_SHIFT 16 195*57e252bfSMichael Neumann 196*57e252bfSMichael Neumann #define CG_PG_CTRL 0x6e0 197*57e252bfSMichael Neumann # define SP(x) ((x) << 0) 198*57e252bfSMichael Neumann # define SP_MASK (0xffff << 0) 199*57e252bfSMichael Neumann # define SP_SHIFT 0 200*57e252bfSMichael Neumann # define SU(x) ((x) << 16) 201*57e252bfSMichael Neumann # define SU_MASK (0xffff << 16) 202*57e252bfSMichael Neumann # define SU_SHIFT 16 203*57e252bfSMichael Neumann 204*57e252bfSMichael Neumann #define CG_MISC_REG 0x708 205*57e252bfSMichael Neumann 206*57e252bfSMichael Neumann #define CG_THERMAL_INT_CTRL 0x738 207*57e252bfSMichael Neumann # define DIG_THERM_INTH(x) ((x) << 0) 208*57e252bfSMichael Neumann # define DIG_THERM_INTH_MASK (0xff << 0) 209*57e252bfSMichael Neumann # define DIG_THERM_INTH_SHIFT 0 210*57e252bfSMichael Neumann # define DIG_THERM_INTL(x) ((x) << 8) 211*57e252bfSMichael Neumann # define DIG_THERM_INTL_MASK (0xff << 8) 212*57e252bfSMichael Neumann # define DIG_THERM_INTL_SHIFT 8 213*57e252bfSMichael Neumann # define THERM_INTH_MASK (1 << 24) 214*57e252bfSMichael Neumann # define THERM_INTL_MASK (1 << 25) 215*57e252bfSMichael Neumann 216*57e252bfSMichael Neumann #define CG_CG_VOLTAGE_CNTL 0x770 217*57e252bfSMichael Neumann # define EN (1 << 9) 218*57e252bfSMichael Neumann 219*57e252bfSMichael Neumann #define HW_REV 0x5564 220*57e252bfSMichael Neumann # define ATI_REV_ID_MASK (0xf << 28) 221*57e252bfSMichael Neumann # define ATI_REV_ID_SHIFT 28 222*57e252bfSMichael Neumann /* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ 223*57e252bfSMichael Neumann 224*57e252bfSMichael Neumann #define CGTS_SM_CTRL_REG 0x9150 225*57e252bfSMichael Neumann 226*57e252bfSMichael Neumann #define GB_ADDR_CONFIG 0x98f8 227*57e252bfSMichael Neumann 228*57e252bfSMichael Neumann #endif 229