1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "radeon.h" 28 #include "radeon_asic.h" 29 #include "rv770d.h" 30 31 /** 32 * uvd_v2_2_fence_emit - emit an fence & trap command 33 * 34 * @rdev: radeon_device pointer 35 * @fence: fence to emit 36 * 37 * Write a fence and a trap command to the ring. 38 */ 39 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 40 struct radeon_fence *fence) 41 { 42 struct radeon_ring *ring = &rdev->ring[fence->ring]; 43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 44 45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); 46 radeon_ring_write(ring, fence->seq); 47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 48 radeon_ring_write(ring, lower_32_bits(addr)); 49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 50 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 52 radeon_ring_write(ring, 0); 53 54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); 55 radeon_ring_write(ring, 0); 56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); 57 radeon_ring_write(ring, 0); 58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); 59 radeon_ring_write(ring, 2); 60 } 61 62 /** 63 * uvd_v2_2_resume - memory controller programming 64 * 65 * @rdev: radeon_device pointer 66 * 67 * Let the UVD memory controller know it's offsets 68 */ 69 int uvd_v2_2_resume(struct radeon_device *rdev) 70 { 71 uint64_t addr; 72 uint32_t chip_id, size; 73 int r; 74 75 /* RV770 uses V1.0 MC */ 76 if (rdev->family == CHIP_RV770) 77 return uvd_v1_0_resume(rdev); 78 79 r = radeon_uvd_resume(rdev); 80 if (r) 81 return r; 82 83 /* programm the VCPU memory controller bits 0-27 */ 84 addr = rdev->uvd.gpu_addr >> 3; 85 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3; 86 WREG32(UVD_VCPU_CACHE_OFFSET0, addr); 87 WREG32(UVD_VCPU_CACHE_SIZE0, size); 88 89 addr += size; 90 size = RADEON_UVD_STACK_SIZE >> 3; 91 WREG32(UVD_VCPU_CACHE_OFFSET1, addr); 92 WREG32(UVD_VCPU_CACHE_SIZE1, size); 93 94 addr += size; 95 size = RADEON_UVD_HEAP_SIZE >> 3; 96 WREG32(UVD_VCPU_CACHE_OFFSET2, addr); 97 WREG32(UVD_VCPU_CACHE_SIZE2, size); 98 99 /* bits 28-31 */ 100 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 101 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 102 103 /* bits 32-39 */ 104 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; 105 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 106 107 /* tell firmware which hardware it is running on */ 108 switch (rdev->family) { 109 default: 110 return -EINVAL; 111 case CHIP_RV710: 112 chip_id = 0x01000005; 113 break; 114 case CHIP_RV730: 115 chip_id = 0x01000006; 116 break; 117 case CHIP_RV740: 118 chip_id = 0x01000007; 119 break; 120 case CHIP_CYPRESS: 121 case CHIP_HEMLOCK: 122 chip_id = 0x01000008; 123 break; 124 case CHIP_JUNIPER: 125 chip_id = 0x01000009; 126 break; 127 case CHIP_REDWOOD: 128 chip_id = 0x0100000a; 129 break; 130 case CHIP_CEDAR: 131 chip_id = 0x0100000b; 132 break; 133 case CHIP_SUMO: 134 case CHIP_SUMO2: 135 chip_id = 0x0100000c; 136 break; 137 case CHIP_PALM: 138 chip_id = 0x0100000e; 139 break; 140 case CHIP_CAYMAN: 141 chip_id = 0x0100000f; 142 break; 143 case CHIP_BARTS: 144 chip_id = 0x01000010; 145 break; 146 case CHIP_TURKS: 147 chip_id = 0x01000011; 148 break; 149 case CHIP_CAICOS: 150 chip_id = 0x01000012; 151 break; 152 case CHIP_TAHITI: 153 chip_id = 0x01000014; 154 break; 155 case CHIP_VERDE: 156 chip_id = 0x01000015; 157 break; 158 case CHIP_PITCAIRN: 159 case CHIP_OLAND: 160 chip_id = 0x01000016; 161 break; 162 case CHIP_ARUBA: 163 chip_id = 0x01000017; 164 break; 165 } 166 WREG32(UVD_VCPU_CHIP_ID, chip_id); 167 168 return 0; 169 } 170