1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 * Authors: Christian König <christian.koenig@amd.com> 26 */ 27 28 #include <linux/firmware.h> 29 #include <drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "sid.h" 33 34 #define VCE_V1_0_FW_SIZE (256 * 1024) 35 #define VCE_V1_0_STACK_SIZE (64 * 1024) 36 #define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1)) 37 38 void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 39 40 struct vce_v1_0_fw_signature 41 { 42 int32_t off; 43 uint32_t len; 44 int32_t num; 45 struct { 46 uint32_t chip_id; 47 uint32_t keyselect; 48 uint32_t nonce[4]; 49 uint32_t sigval[4]; 50 } val[8]; 51 }; 52 53 /** 54 * vce_v1_0_get_rptr - get read pointer 55 * 56 * @rdev: radeon_device pointer 57 * @ring: radeon_ring pointer 58 * 59 * Returns the current hardware read pointer 60 */ 61 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 62 struct radeon_ring *ring) 63 { 64 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) 65 return RREG32(VCE_RB_RPTR); 66 else 67 return RREG32(VCE_RB_RPTR2); 68 } 69 70 /** 71 * vce_v1_0_get_wptr - get write pointer 72 * 73 * @rdev: radeon_device pointer 74 * @ring: radeon_ring pointer 75 * 76 * Returns the current hardware write pointer 77 */ 78 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 79 struct radeon_ring *ring) 80 { 81 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) 82 return RREG32(VCE_RB_WPTR); 83 else 84 return RREG32(VCE_RB_WPTR2); 85 } 86 87 /** 88 * vce_v1_0_set_wptr - set write pointer 89 * 90 * @rdev: radeon_device pointer 91 * @ring: radeon_ring pointer 92 * 93 * Commits the write pointer to the hardware 94 */ 95 void vce_v1_0_set_wptr(struct radeon_device *rdev, 96 struct radeon_ring *ring) 97 { 98 if (ring->idx == TN_RING_TYPE_VCE1_INDEX) 99 WREG32(VCE_RB_WPTR, ring->wptr); 100 else 101 WREG32(VCE_RB_WPTR2, ring->wptr); 102 } 103 104 void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable) 105 { 106 u32 tmp; 107 108 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) { 109 tmp = RREG32(VCE_CLOCK_GATING_A); 110 tmp |= CGC_DYN_CLOCK_MODE; 111 WREG32(VCE_CLOCK_GATING_A, tmp); 112 113 tmp = RREG32(VCE_UENC_CLOCK_GATING); 114 tmp &= ~0x1ff000; 115 tmp |= 0xff800000; 116 WREG32(VCE_UENC_CLOCK_GATING, tmp); 117 118 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); 119 tmp &= ~0x3ff; 120 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); 121 } else { 122 tmp = RREG32(VCE_CLOCK_GATING_A); 123 tmp &= ~CGC_DYN_CLOCK_MODE; 124 WREG32(VCE_CLOCK_GATING_A, tmp); 125 126 tmp = RREG32(VCE_UENC_CLOCK_GATING); 127 tmp |= 0x1ff000; 128 tmp &= ~0xff800000; 129 WREG32(VCE_UENC_CLOCK_GATING, tmp); 130 131 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); 132 tmp |= 0x3ff; 133 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); 134 } 135 } 136 137 static void vce_v1_0_init_cg(struct radeon_device *rdev) 138 { 139 u32 tmp; 140 141 tmp = RREG32(VCE_CLOCK_GATING_A); 142 tmp |= CGC_DYN_CLOCK_MODE; 143 WREG32(VCE_CLOCK_GATING_A, tmp); 144 145 tmp = RREG32(VCE_CLOCK_GATING_B); 146 tmp |= 0x1e; 147 tmp &= ~0xe100e1; 148 WREG32(VCE_CLOCK_GATING_B, tmp); 149 150 tmp = RREG32(VCE_UENC_CLOCK_GATING); 151 tmp &= ~0xff9ff000; 152 WREG32(VCE_UENC_CLOCK_GATING, tmp); 153 154 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); 155 tmp &= ~0x3ff; 156 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp); 157 } 158 159 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data) 160 { 161 const struct vce_v1_0_fw_signature *sign = (const struct vce_v1_0_fw_signature *)rdev->vce_fw->data; 162 uint32_t chip_id; 163 int i; 164 165 switch (rdev->family) { 166 case CHIP_TAHITI: 167 chip_id = 0x01000014; 168 break; 169 case CHIP_VERDE: 170 chip_id = 0x01000015; 171 break; 172 case CHIP_PITCAIRN: 173 case CHIP_OLAND: 174 chip_id = 0x01000016; 175 break; 176 case CHIP_ARUBA: 177 chip_id = 0x01000017; 178 break; 179 default: 180 return -EINVAL; 181 } 182 183 for (i = 0; i < le32_to_cpu(sign->num); ++i) { 184 if (le32_to_cpu(sign->val[i].chip_id) == chip_id) 185 break; 186 } 187 188 if (i == le32_to_cpu(sign->num)) 189 return -EINVAL; 190 191 data += (256 - 64) / 4; 192 data[0] = sign->val[i].nonce[0]; 193 data[1] = sign->val[i].nonce[1]; 194 data[2] = sign->val[i].nonce[2]; 195 data[3] = sign->val[i].nonce[3]; 196 data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64); 197 198 memset(&data[5], 0, 44); 199 memcpy(&data[16], &sign[1], rdev->vce_fw->datasize - sizeof(*sign)); 200 201 data += le32_to_cpu(data[4]) / 4; 202 data[0] = sign->val[i].sigval[0]; 203 data[1] = sign->val[i].sigval[1]; 204 data[2] = sign->val[i].sigval[2]; 205 data[3] = sign->val[i].sigval[3]; 206 207 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); 208 209 return 0; 210 } 211 212 unsigned vce_v1_0_bo_size(struct radeon_device *rdev) 213 { 214 WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->datasize); 215 return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE; 216 } 217 218 int vce_v1_0_resume(struct radeon_device *rdev) 219 { 220 uint64_t addr = rdev->vce.gpu_addr; 221 uint32_t size; 222 int i; 223 224 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); 225 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); 226 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); 227 WREG32(VCE_CLOCK_GATING_B, 0); 228 229 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); 230 231 WREG32(VCE_LMI_CTRL, 0x00398000); 232 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); 233 WREG32(VCE_LMI_SWAP_CNTL, 0); 234 WREG32(VCE_LMI_SWAP_CNTL1, 0); 235 WREG32(VCE_LMI_VM_CTRL, 0); 236 237 WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES); 238 239 addr += 256; 240 size = VCE_V1_0_FW_SIZE; 241 WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); 242 WREG32(VCE_VCPU_CACHE_SIZE0, size); 243 244 addr += size; 245 size = VCE_V1_0_STACK_SIZE; 246 WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); 247 WREG32(VCE_VCPU_CACHE_SIZE1, size); 248 249 addr += size; 250 size = VCE_V1_0_DATA_SIZE; 251 WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); 252 WREG32(VCE_VCPU_CACHE_SIZE2, size); 253 254 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); 255 256 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); 257 258 for (i = 0; i < 10; ++i) { 259 mdelay(10); 260 if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE) 261 break; 262 } 263 264 if (i == 10) 265 return -ETIMEDOUT; 266 267 if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS)) 268 return -EINVAL; 269 270 for (i = 0; i < 10; ++i) { 271 mdelay(10); 272 if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY)) 273 break; 274 } 275 276 if (i == 10) 277 return -ETIMEDOUT; 278 279 vce_v1_0_init_cg(rdev); 280 281 return 0; 282 } 283 284 /** 285 * vce_v1_0_start - start VCE block 286 * 287 * @rdev: radeon_device pointer 288 * 289 * Setup and start the VCE block 290 */ 291 int vce_v1_0_start(struct radeon_device *rdev) 292 { 293 struct radeon_ring *ring; 294 int i, j, r; 295 296 /* set BUSY flag */ 297 WREG32_P(VCE_STATUS, 1, ~1); 298 299 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 300 WREG32(VCE_RB_RPTR, ring->wptr); 301 WREG32(VCE_RB_WPTR, ring->wptr); 302 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); 303 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 304 WREG32(VCE_RB_SIZE, ring->ring_size / 4); 305 306 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 307 WREG32(VCE_RB_RPTR2, ring->wptr); 308 WREG32(VCE_RB_WPTR2, ring->wptr); 309 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); 310 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 311 WREG32(VCE_RB_SIZE2, ring->ring_size / 4); 312 313 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); 314 315 WREG32_P(VCE_SOFT_RESET, 316 VCE_ECPU_SOFT_RESET | 317 VCE_FME_SOFT_RESET, ~( 318 VCE_ECPU_SOFT_RESET | 319 VCE_FME_SOFT_RESET)); 320 321 mdelay(100); 322 323 WREG32_P(VCE_SOFT_RESET, 0, ~( 324 VCE_ECPU_SOFT_RESET | 325 VCE_FME_SOFT_RESET)); 326 327 for (i = 0; i < 10; ++i) { 328 uint32_t status; 329 for (j = 0; j < 100; ++j) { 330 status = RREG32(VCE_STATUS); 331 if (status & 2) 332 break; 333 mdelay(10); 334 } 335 r = 0; 336 if (status & 2) 337 break; 338 339 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n"); 340 WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET); 341 mdelay(10); 342 WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); 343 mdelay(10); 344 r = -1; 345 } 346 347 /* clear BUSY flag */ 348 WREG32_P(VCE_STATUS, 0, ~1); 349 350 if (r) { 351 DRM_ERROR("VCE not responding, giving up!!!\n"); 352 return r; 353 } 354 355 return 0; 356 } 357 358 int vce_v1_0_init(struct radeon_device *rdev) 359 { 360 struct radeon_ring *ring; 361 int r; 362 363 r = vce_v1_0_start(rdev); 364 if (r) 365 return r; 366 367 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 368 ring->ready = true; 369 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring); 370 if (r) { 371 ring->ready = false; 372 return r; 373 } 374 375 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 376 ring->ready = true; 377 r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring); 378 if (r) { 379 ring->ready = false; 380 return r; 381 } 382 383 DRM_INFO("VCE initialized successfully.\n"); 384 385 return 0; 386 } 387