1 /*- 2 * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * The following registers, bits and magic values are defined in Register 31 * Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and 32 * various versions of Fusion Controller Hubs (FCHs). FCHs integrated into 33 * CPUs are documented in BIOS and Kernel Development Guide documents for 34 * the corresponding processor families. 35 * 36 * At present there are three classes of supported chipsets: 37 * - SB600 and S7x0 southbridges where the SMBus controller device has 38 * a PCI Device ID of 0x43851002 and a revision less than 0x40 39 * - several types of southbridges and FCHs: 40 * o SB8x0, SB9x0 southbridges where the SMBus controller device has a PCI 41 * Device ID of 0x43851002 and a revision greater than or equal to 0x40 42 * o FCHs where the controller has an ID of 0x780b1022 and a revision less 43 * than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs 44 * integrated into processors, e.g. "Kabini") 45 * o FCHs where the controller has an ID of 0x790b1022 and a revision less 46 * than 0x49 47 * - several types of FCHs: 48 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 49 * and a revision greater than or equal to 0x41 (integrated into "Mullins" 50 * processors, code named "ML") 51 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater 52 * than or equal to 0x49 (integrated into "Carrizo" processors, code named 53 * "KERNCZ" or "CZ") 54 * 55 * The register definitions are compatible within the classes and may be 56 * incompatible accross them. 57 */ 58 59 /* 60 * IO registers for accessing the PMIO space. 61 * See SB7xx RRG 2.3.3.1.1, for instance. 62 */ 63 #define AMDSB_PMIO_INDEX 0xcd6 64 #define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 65 #define AMDSB_PMIO_WIDTH 2 66 67 /* 68 * SB7x0 and compatible registers in the PMIO space. 69 * See SB7xx RRG 2.3.3.2. 70 */ 71 #define AMDSB_PM_RESET_STATUS0 0x44 72 #define AMDSB_PM_RESET_STATUS1 0x45 73 #define AMDSB_WD_RST_STS 0x02 74 #define AMDSB_PM_WDT_CTRL 0x69 75 #define AMDSB_WDT_DISABLE 0x01 76 #define AMDSB_WDT_RES_MASK (0x02 | 0x04) 77 #define AMDSB_WDT_RES_32US 0x00 78 #define AMDSB_WDT_RES_10MS 0x02 79 #define AMDSB_WDT_RES_100MS 0x04 80 #define AMDSB_WDT_RES_1S 0x06 81 #define AMDSB_PM_WDT_BASE_LSB 0x6c 82 #define AMDSB_PM_WDT_BASE_MSB 0x6f 83 84 /* 85 * SB8x0 and compatible registers in the PMIO space. 86 * See SB8xx RRG 2.3.3, for instance. 87 */ 88 #define AMDSB8_PM_SMBUS_EN 0x2c 89 #define AMDSB8_SMBUS_EN 0x01 90 #define AMDSB8_SMBUS_ADDR_MASK 0xffe0u 91 #define AMDSB8_PM_WDT_EN 0x48 92 #define AMDSB8_WDT_DEC_EN 0x01 93 #define AMDSB8_WDT_DISABLE 0x02 94 #define AMDSB8_PM_WDT_CTRL 0x4c 95 #define AMDSB8_WDT_32KHZ 0x00 96 #define AMDSB8_WDT_1HZ 0x03 97 #define AMDSB8_WDT_RES_MASK 0x03 98 #define AMDSB8_PM_RESET_STATUS 0xc0 /* 32 bit wide */ 99 #define AMDSB8_WD_RST_STS 0x2000000 100 #define AMDSB8_PM_RESET_CTRL 0xc4 101 #define AMDSB8_RST_STS_DIS 0x04 102 103 /* 104 * Newer FCH registers in the PMIO space. 105 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 106 */ 107 #define AMDFCH41_PM_DECODE_EN0 0x00 108 #define AMDFCH41_SMBUS_EN 0x10 109 #define AMDFCH41_WDT_EN 0x80 110 #define AMDFCH41_PM_DECODE_EN1 0x01 111 #define AMDFCH41_PM_DECODE_EN3 0x03 112 #define AMDFCH41_WDT_RES_MASK 0x03 113 #define AMDFCH41_WDT_RES_32US 0x00 114 #define AMDFCH41_WDT_RES_10MS 0x01 115 #define AMDFCH41_WDT_RES_100MS 0x02 116 #define AMDFCH41_WDT_RES_1S 0x03 117 #define AMDFCH41_WDT_EN_MASK 0x0c 118 #define AMDFCH41_WDT_ENABLE 0x00 119 #define AMDFCH41_PM_ISA_CTRL 0x04 120 #define AMDFCH41_MMIO_EN 0x02 121 122 /* 123 * Fixed MMIO addresses for accessing Watchdog and SMBus registers. 124 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 125 */ 126 #define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u 127 #define AMDFCH41_MMIO_ADDR 0xfed80000u 128 #define AMDFCH41_MMIO_SMBUS_OFF 0x0a00 129 #define AMDFCH41_MMIO_WDT_OFF 0x0b00 130 131 /* 132 * PCI Device IDs and revisions. 133 * SB600 RRG 2.3.1.1, 134 * SB7xx RRG 2.3.1.1, 135 * SB8xx RRG 2.3.1, 136 * BKDG for Family 15h Models 60h-6Fh 3.26.6.1, 137 * BKDG for Family 15h Models 70h-7Fh 3.26.6.1, 138 * BKDG for Family 16h Models 00h-0Fh 3.26.7.1, 139 * BKDG for Family 16h Models 30h-3Fh 3.26.7.1. 140 * Also, see i2c-piix4 aka piix4_smbus Linux driver. 141 */ 142 #define AMDSB_SMBUS_DEVID 0x43851002 143 #define AMDSB8_SMBUS_REVID 0x40 144 #define AMDFCH_SMBUS_DEVID 0x780b1022 145 #define AMDFCH41_SMBUS_REVID 0x41 146 #define AMDCZ_SMBUS_DEVID 0x790b1022 147 #define AMDCZ49_SMBUS_REVID 0x49 148