1 /*- 2 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 29 * southbridges. 30 * Please see the following specifications for the descriptions of the 31 * registers and flags: 32 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 33 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 34 * - AMD SB700/710/750 Register Reference Guide (RRG) 35 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 36 * - AMD SB700/710/750 Register Programming Requirements (RPR) 37 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 38 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 39 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 40 * Please see the following for Watchdog Resource Table specification: 41 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 42 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 43 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 44 * specifications, but the table hasn't been spotted in the wild yet. 45 * 46 * $FreeBSD: src/sys/dev/amdsbwd/amdsbwd.c,v 1.3 2011/06/07 06:18:02 avg Exp $ 47 */ 48 49 #include <sys/param.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/systm.h> 53 #include <sys/sysctl.h> 54 #include <sys/bus.h> 55 #include <sys/rman.h> 56 #include <sys/resource.h> 57 #include <sys/wdog.h> 58 59 #include <bus/isa/isavar.h> 60 #include <bus/pci/pcivar.h> 61 62 /* SB7xx RRG 2.3.3.1.1. */ 63 #define AMDSB_PMIO_INDEX 0xcd6 64 #define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 65 #define AMDSB_PMIO_WIDTH 2 66 /* SB7xx RRG 2.3.3.2. */ 67 #define AMDSB_PM_RESET_STATUS0 0x44 68 #define AMDSB_PM_RESET_STATUS1 0x45 69 #define AMDSB_WD_RST_STS 0x02 70 /* SB7xx RRG 2.3.3.2, RPR 2.36. */ 71 #define AMDSB_PM_WDT_CTRL 0x69 72 #define AMDSB_WDT_DISABLE 0x01 73 #define AMDSB_WDT_RES_MASK (0x02 | 0x04) 74 #define AMDSB_WDT_RES_32US 0x00 75 #define AMDSB_WDT_RES_10MS 0x02 76 #define AMDSB_WDT_RES_100MS 0x04 77 #define AMDSB_WDT_RES_1S 0x06 78 #define AMDSB_PM_WDT_BASE_LSB 0x6c 79 #define AMDSB_PM_WDT_BASE_MSB 0x6f 80 /* SB8xx RRG 2.3.3. */ 81 #define AMDSB8_PM_WDT_EN 0x48 82 #define AMDSB8_WDT_DEC_EN 0x01 83 #define AMDSB8_WDT_DISABLE 0x02 84 #define AMDSB8_PM_WDT_CTRL 0x4c 85 #define AMDSB8_WDT_32KHZ 0x00 86 #define AMDSB8_WDT_1HZ 0x03 87 #define AMDSB8_WDT_RES_MASK 0x03 88 #define AMDSB8_PM_RESET_STATUS0 0xC0 89 #define AMDSB8_PM_RESET_STATUS1 0xC1 90 #define AMDSB8_WD_RST_STS 0x20 91 /* SB7xx RRG 2.3.4, WDRT. */ 92 #define AMDSB_WD_CTRL 0x00 93 #define AMDSB_WD_RUN 0x01 94 #define AMDSB_WD_FIRED 0x02 95 #define AMDSB_WD_SHUTDOWN 0x04 96 #define AMDSB_WD_DISABLE 0x08 97 #define AMDSB_WD_RESERVED 0x70 98 #define AMDSB_WD_RELOAD 0x80 99 #define AMDSB_WD_COUNT 0x04 100 #define AMDSB_WD_COUNT_MASK 0xffff 101 #define AMDSB_WDIO_REG_WIDTH 4 102 /* WDRT */ 103 #define MAXCOUNT_MIN_VALUE 511 104 /* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1. */ 105 #define AMDSB_SMBUS_DEVID 0x43851002 106 #define AMDSB8_SMBUS_REVID 0x40 107 108 #define amdsbwd_verbose_printf(dev, ...) \ 109 do { \ 110 if (bootverbose) \ 111 device_printf(dev, __VA_ARGS__);\ 112 } while (0) 113 114 struct amdsbwd_softc { 115 device_t dev; 116 struct resource *res_ctrl; 117 struct resource *res_count; 118 int rid_ctrl; 119 int rid_count; 120 int ms_per_tick; 121 int max_ticks; 122 int active; 123 unsigned int timeout; 124 }; 125 static struct amdsbwd_softc amdsbwd_sc; 126 127 static void amdsbwd_identify(driver_t *driver, device_t parent); 128 static int amdsbwd_probe(device_t dev); 129 static int amdsbwd_attach(device_t dev); 130 static int amdsbwd_detach(device_t dev); 131 132 static device_method_t amdsbwd_methods[] = { 133 DEVMETHOD(device_identify, amdsbwd_identify), 134 DEVMETHOD(device_probe, amdsbwd_probe), 135 DEVMETHOD(device_attach, amdsbwd_attach), 136 DEVMETHOD(device_detach, amdsbwd_detach), 137 #if 0 138 DEVMETHOD(device_shutdown, amdsbwd_detach), 139 #endif 140 DEVMETHOD_END 141 }; 142 143 static devclass_t amdsbwd_devclass; 144 static driver_t amdsbwd_driver = { 145 "amdsbwd", 146 amdsbwd_methods, 147 0 148 }; 149 150 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 151 MODULE_VERSION(amdsbwd, 1); 152 153 154 static uint8_t 155 pmio_read(struct resource *res, uint8_t reg) 156 { 157 bus_write_1(res, 0, reg); /* Index */ 158 return (bus_read_1(res, 1)); /* Data */ 159 } 160 161 static void 162 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 163 { 164 bus_write_1(res, 0, reg); /* Index */ 165 bus_write_1(res, 1, val); /* Data */ 166 } 167 168 static uint32_t 169 wdctrl_read(struct amdsbwd_softc *sc) 170 { 171 return (bus_read_4(sc->res_ctrl, 0)); 172 } 173 174 static void 175 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 176 { 177 bus_write_4(sc->res_ctrl, 0, val); 178 } 179 180 static __unused uint32_t 181 wdcount_read(struct amdsbwd_softc *sc) 182 { 183 return (bus_read_4(sc->res_count, 0)); 184 } 185 186 static void 187 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 188 { 189 bus_write_4(sc->res_count, 0, val); 190 } 191 192 static void 193 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 194 { 195 uint32_t val; 196 197 val = wdctrl_read(sc); 198 val |= AMDSB_WD_RUN; 199 wdctrl_write(sc, val); 200 sc->active = 1; 201 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 202 } 203 204 static void 205 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 206 { 207 uint32_t val; 208 209 val = wdctrl_read(sc); 210 val &= ~AMDSB_WD_RUN; 211 wdctrl_write(sc, val); 212 sc->active = 0; 213 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 214 } 215 216 static void 217 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 218 { 219 uint32_t val; 220 221 val = wdctrl_read(sc); 222 val |= AMDSB_WD_RELOAD; 223 wdctrl_write(sc, val); 224 } 225 226 static void 227 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 228 { 229 230 timeout &= AMDSB_WD_COUNT_MASK; 231 wdcount_write(sc, timeout); 232 sc->timeout = timeout; 233 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 234 } 235 236 static int 237 amdsb_watchdog(void *unused, int period) 238 { 239 unsigned int timeout; 240 struct amdsbwd_softc *sc; 241 242 sc = &amdsbwd_sc; 243 timeout = (period * 1000) / sc->ms_per_tick; 244 if (timeout > sc->max_ticks) 245 timeout = sc->max_ticks; 246 if (timeout != sc->timeout) { 247 amdsbwd_tmr_set(sc, timeout); 248 if (!sc->active) 249 amdsbwd_tmr_enable(sc); 250 } 251 amdsbwd_tmr_reload(sc); 252 253 return period; 254 } 255 256 static void 257 amdsbwd_identify(driver_t *driver, device_t parent) 258 { 259 device_t child; 260 device_t smb_dev; 261 262 if (resource_disabled("amdsbwd", 0)) 263 return; 264 if (device_find_child(parent, "amdsbwd", -1) != NULL) 265 return; 266 267 /* 268 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 269 * that should be present at bus 0, device 20, function 0. 270 */ 271 smb_dev = pci_find_bsf(0, 20, 0); 272 if (smb_dev == NULL) 273 return; 274 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID) 275 return; 276 277 child = BUS_ADD_CHILD(parent, parent, 0, "amdsbwd", 0); 278 if (child == NULL) 279 device_printf(parent, "add amdsbwd child failed\n"); 280 } 281 282 283 static void 284 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 285 { 286 uint32_t val; 287 int i; 288 289 /* Report cause of previous reset for user's convenience. */ 290 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 291 if (val != 0) 292 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 293 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 294 if (val != 0) 295 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 296 if ((val & AMDSB_WD_RST_STS) != 0) 297 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 298 299 /* Find base address of memory mapped WDT registers. */ 300 for (*addr = 0, i = 0; i < 4; i++) { 301 *addr <<= 8; 302 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 303 } 304 /* Set watchdog timer tick to 1s. */ 305 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 306 val &= ~AMDSB_WDT_RES_MASK; 307 val |= AMDSB_WDT_RES_10MS; 308 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 309 310 /* Enable watchdog device (in stopped state). */ 311 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 312 val &= ~AMDSB_WDT_DISABLE; 313 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 314 315 /* 316 * XXX TODO: Ensure that watchdog decode is enabled 317 * (register 0x41, bit 3). 318 */ 319 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 320 } 321 322 static void 323 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 324 { 325 uint32_t val; 326 int i; 327 328 /* Report cause of previous reset for user's convenience. */ 329 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 330 if (val != 0) 331 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 332 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 333 if (val != 0) 334 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 335 if ((val & AMDSB8_WD_RST_STS) != 0) 336 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 337 338 /* Find base address of memory mapped WDT registers. */ 339 for (*addr = 0, i = 0; i < 4; i++) { 340 *addr <<= 8; 341 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 342 } 343 *addr &= ~0x07u; 344 345 /* Set watchdog timer tick to 1s. */ 346 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 347 val &= ~AMDSB8_WDT_RES_MASK; 348 val |= AMDSB8_WDT_1HZ; 349 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 350 #ifdef AMDSBWD_DEBUG 351 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 352 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#02x\n", val); 353 #endif 354 355 /* 356 * Enable watchdog device (in stopped state) 357 * and decoding of its address. 358 */ 359 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 360 val &= ~AMDSB8_WDT_DISABLE; 361 val |= AMDSB8_WDT_DEC_EN; 362 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 363 #ifdef AMDSBWD_DEBUG 364 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 365 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#02x\n", val); 366 #endif 367 device_set_desc(dev, "AMD SB8xx Watchdog Timer"); 368 } 369 370 static int 371 amdsbwd_probe(device_t dev) 372 { 373 struct resource *res; 374 device_t smb_dev; 375 uint32_t addr; 376 int rid; 377 int rc; 378 379 /* Do not claim some ISA PnP device by accident. */ 380 if (isa_get_logicalid(dev) != 0) 381 return (ENXIO); 382 383 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 384 AMDSB_PMIO_WIDTH, -1); 385 if (rc != 0) { 386 device_printf(dev, "bus_set_resource for IO failed\n"); 387 return (ENXIO); 388 } 389 rid = 0; 390 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0ul, ~0ul, 391 AMDSB_PMIO_WIDTH, RF_ACTIVE | RF_SHAREABLE); 392 if (res == NULL) { 393 device_printf(dev, "bus_alloc_resource for IO failed\n"); 394 return (ENXIO); 395 } 396 397 smb_dev = pci_find_bsf(0, 20, 0); 398 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 399 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 400 amdsbwd_probe_sb7xx(dev, res, &addr); 401 else 402 amdsbwd_probe_sb8xx(dev, res, &addr); 403 404 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 405 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 406 407 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 408 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 409 AMDSB_WDIO_REG_WIDTH, -1); 410 if (rc != 0) { 411 device_printf(dev, "bus_set_resource for control failed\n"); 412 return (ENXIO); 413 } 414 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 415 AMDSB_WDIO_REG_WIDTH, -1); 416 if (rc != 0) { 417 device_printf(dev, "bus_set_resource for count failed\n"); 418 return (ENXIO); 419 } 420 421 return (0); 422 } 423 424 static int 425 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 426 { 427 device_t smb_dev; 428 429 sc->max_ticks = UINT16_MAX; 430 sc->rid_ctrl = 0; 431 sc->rid_count = 1; 432 433 smb_dev = pci_find_bsf(0, 20, 0); 434 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 435 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 436 sc->ms_per_tick = 10; 437 else 438 sc->ms_per_tick = 1000; 439 440 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 441 &sc->rid_ctrl, RF_ACTIVE); 442 if (sc->res_ctrl == NULL) { 443 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 444 return (ENXIO); 445 } 446 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 447 &sc->rid_count, RF_ACTIVE); 448 if (sc->res_count == NULL) { 449 device_printf(dev, "bus_alloc_resource for count failed\n"); 450 return (ENXIO); 451 } 452 return (0); 453 } 454 455 static struct watchdog amdsb_wdog = { 456 .name = "AMD southbridge", 457 .wdog_fn = amdsb_watchdog, 458 .arg = NULL, 459 .period_max = (UINT16_MAX*1000) / 10, 460 }; 461 462 static int 463 amdsbwd_attach(device_t dev) 464 { 465 struct amdsbwd_softc *sc; 466 int rc; 467 468 sc = &amdsbwd_sc; 469 sc->dev = dev; 470 471 rc = amdsbwd_attach_sb(dev, sc); 472 if (rc != 0) 473 goto fail; 474 475 #ifdef AMDSBWD_DEBUG 476 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 477 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 478 #endif 479 480 /* Setup initial state of Watchdog Control. */ 481 wdctrl_write(sc, AMDSB_WD_FIRED); 482 483 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 484 device_printf(dev, "watchdog hardware is disabled\n"); 485 goto fail; 486 } 487 488 wdog_register(&amdsb_wdog); 489 490 return (0); 491 492 fail: 493 amdsbwd_detach(dev); 494 return (ENXIO); 495 } 496 497 static int 498 amdsbwd_detach(device_t dev) 499 { 500 struct amdsbwd_softc *sc; 501 502 sc = &amdsbwd_sc; 503 wdog_unregister(&amdsb_wdog); 504 505 if (sc->active) 506 amdsbwd_tmr_disable(sc); 507 508 if (sc->res_ctrl != NULL) 509 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 510 sc->res_ctrl); 511 512 if (sc->res_count != NULL) 513 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 514 sc->res_count); 515 516 return (0); 517 } 518