1 /*- 2 * Copyright (c) 2006-2008 Stanislav Sedov <stas@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/dev/cpuctl/cpuctl.c 275960 2014-12-20 16:40:49Z kib $ 27 */ 28 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/conf.h> 33 #include <sys/fcntl.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/priv.h> 37 #include <sys/proc.h> 38 #include <sys/queue.h> 39 #include <sys/sched.h> 40 #include <sys/kernel.h> 41 #include <sys/sysctl.h> 42 #include <sys/uio.h> 43 #include <sys/cpuctl.h> 44 #include <sys/device.h> 45 #include <sys/thread2.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 static d_open_t cpuctl_open; 52 static d_ioctl_t cpuctl_ioctl; 53 54 #define CPUCTL_VERSION 1 55 56 #ifdef DEBUG 57 # define DPRINTF(format,...) kprintf(format, __VA_ARGS__); 58 #else 59 # define DPRINTF(format,...) 60 #endif 61 62 #define UCODE_SIZE_MAX (4 * 1024 * 1024) 63 64 static int cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd); 65 static void cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data); 66 static void cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data); 67 static int cpuctl_do_update(int cpu, cpuctl_update_args_t *data); 68 static int update_intel(int cpu, cpuctl_update_args_t *args); 69 static int update_amd(int cpu, cpuctl_update_args_t *args); 70 static int update_via(int cpu, cpuctl_update_args_t *args); 71 72 static cdev_t *cpuctl_devs; 73 static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer"); 74 static struct lock cpuctl_lock = LOCK_INITIALIZER("cpuctl", 0, 0); 75 76 static struct dev_ops cpuctl_cdevsw = { 77 .head = { .name = "cpuctl", .flags = D_MPSAFE }, 78 .d_open = cpuctl_open, 79 .d_ioctl = cpuctl_ioctl, 80 }; 81 82 int 83 cpuctl_ioctl(struct dev_ioctl_args *ap) 84 { 85 int ret; 86 int cpu = dev2unit(ap->a_head.a_dev); 87 u_long cmd = ap->a_cmd; 88 int flags = ap->a_fflag; 89 caddr_t data = ap->a_data; 90 91 if (cpu >= ncpus) { 92 DPRINTF("[cpuctl,%d]: bad cpu number %d\n", __LINE__, cpu); 93 return (ENXIO); 94 } 95 /* Require write flag for "write" requests. */ 96 if ((cmd == CPUCTL_WRMSR || cmd == CPUCTL_UPDATE || 97 cmd == CPUCTL_MSRSBIT || cmd == CPUCTL_MSRCBIT) && 98 ((flags & FWRITE) == 0)) 99 return (EPERM); 100 101 lockmgr(&cpuctl_lock, LK_EXCLUSIVE); 102 103 switch (cmd) { 104 case CPUCTL_RDMSR: 105 ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd); 106 break; 107 case CPUCTL_MSRSBIT: 108 case CPUCTL_MSRCBIT: 109 case CPUCTL_WRMSR: 110 ret = priv_check(curthread, PRIV_CPUCTL_WRMSR); 111 if (ret != 0) 112 goto fail; 113 ret = cpuctl_do_msr(cpu, (cpuctl_msr_args_t *)data, cmd); 114 break; 115 case CPUCTL_CPUID: 116 cpuctl_do_cpuid(cpu, (cpuctl_cpuid_args_t *)data); 117 ret = 0; 118 break; 119 case CPUCTL_UPDATE: 120 ret = priv_check(curthread, PRIV_CPUCTL_UPDATE); 121 if (ret != 0) 122 goto fail; 123 ret = cpuctl_do_update(cpu, (cpuctl_update_args_t *)data); 124 break; 125 case CPUCTL_CPUID_COUNT: 126 cpuctl_do_cpuid_count(cpu, (cpuctl_cpuid_count_args_t *)data); 127 ret = 0; 128 break; 129 default: 130 ret = EINVAL; 131 break; 132 } 133 fail: 134 lockmgr(&cpuctl_lock, LK_RELEASE); 135 136 return (ret); 137 } 138 139 /* 140 * Actually perform cpuid operation. 141 */ 142 static void 143 cpuctl_do_cpuid_count(int cpu, cpuctl_cpuid_count_args_t *data) 144 { 145 int oldcpu; 146 147 KASSERT(cpu >= 0 && cpu < ncpus, 148 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 149 150 /* Explicitly clear cpuid data to avoid returning stale info. */ 151 bzero(data->data, sizeof(data->data)); 152 DPRINTF("[cpuctl,%d]: retrieving cpuid lev %#0x type %#0x for %d cpu\n", 153 __LINE__, data->level, data->level_type, cpu); 154 oldcpu = mycpuid; 155 lwkt_migratecpu(cpu); 156 cpuid_count(data->level, data->level_type, data->data); 157 lwkt_migratecpu(oldcpu); 158 } 159 160 static void 161 cpuctl_do_cpuid(int cpu, cpuctl_cpuid_args_t *data) 162 { 163 cpuctl_cpuid_count_args_t cdata; 164 165 cdata.level = data->level; 166 /* Override the level type. */ 167 cdata.level_type = 0; 168 cpuctl_do_cpuid_count(cpu, &cdata); 169 bcopy(cdata.data, data->data, sizeof(data->data)); /* Ignore error */ 170 } 171 172 /* 173 * Actually perform MSR operations. 174 */ 175 static int 176 cpuctl_do_msr(int cpu, cpuctl_msr_args_t *data, u_long cmd) 177 { 178 uint64_t reg; 179 int oldcpu; 180 int ret; 181 182 KASSERT(cpu >= 0 && cpu < ncpus, 183 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 184 185 /* 186 * Explicitly clear cpuid data to avoid returning stale 187 * info 188 */ 189 DPRINTF("[cpuctl,%d]: operating on MSR %#0x for %d cpu\n", __LINE__, 190 data->msr, cpu); 191 oldcpu = mycpuid; 192 lwkt_migratecpu(cpu); 193 if (cmd == CPUCTL_RDMSR) { 194 data->data = 0; 195 ret = rdmsr_safe(data->msr, &data->data); 196 } else if (cmd == CPUCTL_WRMSR) { 197 ret = wrmsr_safe(data->msr, data->data); 198 } else if (cmd == CPUCTL_MSRSBIT) { 199 crit_enter(); 200 ret = rdmsr_safe(data->msr, ®); 201 if (ret == 0) 202 ret = wrmsr_safe(data->msr, reg | data->data); 203 crit_exit(); 204 } else if (cmd == CPUCTL_MSRCBIT) { 205 crit_enter(); 206 ret = rdmsr_safe(data->msr, ®); 207 if (ret == 0) 208 ret = wrmsr_safe(data->msr, reg & ~data->data); 209 crit_exit(); 210 } else 211 panic("[cpuctl,%d]: unknown operation requested: %lu", __LINE__, cmd); 212 lwkt_migratecpu(oldcpu); 213 return (ret); 214 } 215 216 /* 217 * Actually perform microcode update. 218 */ 219 extern void spectre_vm_setup(void *arg); 220 221 static int 222 cpuctl_do_update(int cpu, cpuctl_update_args_t *data) 223 { 224 cpuctl_cpuid_args_t args = { 225 .level = 0, 226 }; 227 char vendor[13]; 228 int ret; 229 230 KASSERT(cpu >= 0 && cpu < ncpus, 231 ("[cpuctl,%d]: bad cpu number %d", __LINE__, cpu)); 232 DPRINTF("[cpuctl,%d]: XXX %d", __LINE__, cpu); 233 234 cpuctl_do_cpuid(cpu, &args); 235 ((uint32_t *)vendor)[0] = args.data[1]; 236 ((uint32_t *)vendor)[1] = args.data[3]; 237 ((uint32_t *)vendor)[2] = args.data[2]; 238 vendor[12] = '\0'; 239 if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0) 240 ret = update_intel(cpu, data); 241 else if(strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0) 242 ret = update_amd(cpu, data); 243 else if(strncmp(vendor, CENTAUR_VENDOR_ID, sizeof(CENTAUR_VENDOR_ID)) == 0) 244 ret = update_via(cpu, data); 245 else 246 ret = ENXIO; 247 248 if (ret == 0) 249 spectre_vm_setup((void *)(intptr_t)1); 250 251 return (ret); 252 } 253 254 static int 255 update_intel(int cpu, cpuctl_update_args_t *args) 256 { 257 void *ptr; 258 uint64_t rev0, rev1; 259 uint32_t tmp[4]; 260 int oldcpu; 261 int ret; 262 263 if (args->size == 0 || args->data == NULL) { 264 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 265 return (EINVAL); 266 } 267 if (args->size > UCODE_SIZE_MAX) { 268 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 269 return (EINVAL); 270 } 271 272 /* 273 * 16 byte alignment required. Rely on the fact that 274 * malloc(9) always returns the pointer aligned at least on 275 * the size of the allocation. 276 */ 277 ptr = kmalloc(args->size + 16, M_CPUCTL, M_WAITOK); 278 if (copyin(args->data, ptr, args->size) != 0) { 279 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 280 __LINE__, args->data, ptr, args->size); 281 ret = EFAULT; 282 goto fail; 283 } 284 oldcpu = mycpuid; 285 lwkt_migratecpu(cpu); 286 crit_enter(); 287 rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */ 288 289 /* 290 * Perform update. 291 */ 292 wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr)); 293 wrmsr_safe(MSR_BIOS_SIGN, 0); 294 295 /* 296 * Serialize instruction flow. 297 */ 298 do_cpuid(0, tmp); 299 crit_exit(); 300 rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */ 301 lwkt_migratecpu(oldcpu); 302 kprintf("[cpu %d]: updated microcode from rev=0x%x to rev=0x%x\n", cpu, 303 (unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32)); 304 305 if (rev1 > rev0) 306 ret = 0; 307 else 308 ret = EEXIST; 309 fail: 310 kfree(ptr, M_CPUCTL); 311 return (ret); 312 } 313 314 static int 315 update_amd(int cpu, cpuctl_update_args_t *args) 316 { 317 void *ptr = NULL; 318 uint32_t tmp[4]; 319 int oldcpu; 320 int ret; 321 322 if (args->size == 0 || args->data == NULL) { 323 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 324 return (EINVAL); 325 } 326 if (args->size > UCODE_SIZE_MAX) { 327 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 328 return (EINVAL); 329 } 330 /* 331 * XXX Might not require contignous address space - needs check 332 */ 333 ptr = contigmalloc(args->size, M_CPUCTL, 0, 0, 0xffffffff, 16, 0); 334 if (ptr == NULL) { 335 DPRINTF("[cpuctl,%d]: cannot allocate %zd bytes of memory", 336 __LINE__, args->size); 337 return (ENOMEM); 338 } 339 if (copyin(args->data, ptr, args->size) != 0) { 340 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 341 __LINE__, args->data, ptr, args->size); 342 ret = EFAULT; 343 goto fail; 344 } 345 oldcpu = mycpuid; 346 lwkt_migratecpu(cpu); 347 crit_enter(); 348 349 /* 350 * Perform update. 351 */ 352 wrmsr_safe(MSR_K8_UCODE_UPDATE, (uintptr_t)ptr); 353 354 /* 355 * Serialize instruction flow. 356 */ 357 do_cpuid(0, tmp); 358 crit_exit(); 359 lwkt_migratecpu(oldcpu); 360 ret = 0; 361 fail: 362 if (ptr != NULL) 363 contigfree(ptr, args->size, M_CPUCTL); 364 return (ret); 365 } 366 367 static int 368 update_via(int cpu, cpuctl_update_args_t *args) 369 { 370 void *ptr; 371 uint64_t rev0, rev1, res; 372 uint32_t tmp[4]; 373 int oldcpu; 374 int ret; 375 376 if (args->size == 0 || args->data == NULL) { 377 DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__); 378 return (EINVAL); 379 } 380 if (args->size > UCODE_SIZE_MAX) { 381 DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__); 382 return (EINVAL); 383 } 384 385 /* 386 * 4 byte alignment required. 387 */ 388 ptr = kmalloc(args->size, M_CPUCTL, M_WAITOK); 389 if (copyin(args->data, ptr, args->size) != 0) { 390 DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed", 391 __LINE__, args->data, ptr, args->size); 392 ret = EFAULT; 393 goto fail; 394 } 395 oldcpu = mycpuid; 396 lwkt_migratecpu(cpu); 397 crit_enter(); 398 rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current microcode revision. */ 399 400 /* 401 * Perform update. 402 */ 403 wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr)); 404 do_cpuid(1, tmp); 405 406 /* 407 * Result are in low byte of MSR FCR5: 408 * 0x00: No update has been attempted since RESET. 409 * 0x01: The last attempted update was successful. 410 * 0x02: The last attempted update was unsuccessful due to a bad 411 * environment. No update was loaded and any preexisting 412 * patches are still active. 413 * 0x03: The last attempted update was not applicable to this processor. 414 * No update was loaded and any preexisting patches are still 415 * active. 416 * 0x04: The last attempted update was not successful due to an invalid 417 * update data block. No update was loaded and any preexisting 418 * patches are still active 419 */ 420 rdmsr_safe(0x1205, &res); 421 res &= 0xff; 422 crit_exit(); 423 rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */ 424 lwkt_migratecpu(oldcpu); 425 426 DPRINTF("[cpu,%d]: rev0=%x rev1=%x res=%x\n", __LINE__, 427 (unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32), (unsigned)res); 428 429 if (res != 0x01) 430 ret = EINVAL; 431 else 432 ret = 0; 433 fail: 434 kfree(ptr, M_CPUCTL); 435 return (ret); 436 } 437 438 int 439 cpuctl_open(struct dev_open_args *ap) 440 { 441 int ret = 0; 442 int cpu; 443 444 cpu = dev2unit(ap->a_head.a_dev); 445 if (cpu >= ncpus) { 446 DPRINTF("[cpuctl,%d]: incorrect cpu number %d\n", __LINE__, 447 cpu); 448 return (ENXIO); 449 } 450 if (ap->a_oflags & FWRITE) 451 ret = securelevel > 0 ? EPERM : 0; 452 return (ret); 453 } 454 455 static int 456 cpuctl_modevent(module_t mod __unused, int type, void *data __unused) 457 { 458 int cpu; 459 460 switch(type) { 461 case MOD_LOAD: 462 if ((cpu_feature & CPUID_MSR) == 0) { 463 if (bootverbose) 464 kprintf("cpuctl: not available.\n"); 465 return (ENODEV); 466 } 467 if (bootverbose) 468 kprintf("cpuctl: access to MSR registers/cpuid info.\n"); 469 cpuctl_devs = kmalloc(sizeof(*cpuctl_devs) * ncpus, M_CPUCTL, 470 M_WAITOK | M_ZERO); 471 for (cpu = 0; cpu < ncpus; cpu++) 472 cpuctl_devs[cpu] = make_dev(&cpuctl_cdevsw, cpu, 473 UID_ROOT, GID_KMEM, 0640, "cpuctl%d", cpu); 474 break; 475 case MOD_UNLOAD: 476 for (cpu = 0; cpu < ncpus; cpu++) { 477 if (cpuctl_devs[cpu] != NULL) 478 destroy_dev(cpuctl_devs[cpu]); 479 } 480 kfree(cpuctl_devs, M_CPUCTL); 481 break; 482 case MOD_SHUTDOWN: 483 break; 484 default: 485 return (EOPNOTSUPP); 486 } 487 return (0); 488 } 489 490 DEV_MODULE(cpuctl, cpuctl_modevent, NULL); 491 MODULE_VERSION(cpuctl, CPUCTL_VERSION); 492