xref: /dragonfly/sys/dev/misc/ecc/ecc_x3400_reg.h (revision 3170ffd7)
1 #ifndef _ECC_X3400_REG_H_
2 #define _ECC_X3400_REG_H_
3 
4 #ifndef _SYS_BITOPS_H_
5 #include <sys/bitops.h>
6 #endif
7 
8 #define PCIBUS_X3400UC			0xff
9 
10 #define PCISLOT_X3400UC_MC		3
11 #define PCIFUNC_X3400UC_MC		0
12 #define PCI_X3400UC_MC_VID_ID		0x8086
13 #define PCI_X3400UC_MC_DID_ID		0x2c98
14 #define PCI_X3400UC_MC_CTRL		0x48
15 #define PCI_X3400UC_MC_CTRL_ECCEN	__BIT(1)
16 #define PCI_X3400UC_MC_STS		0x4c
17 #define PCI_X3400UC_MC_STS_ECCEN	__BIT(4)
18 #define PCI_X3400UC_MC_MAX_DOD		0x64
19 #define PCI_X3400UC_MC_MAX_DOD_DIMMS	__BITS(0, 1)
20 
21 #define PCISLOT_X3400UC_MCT2		3
22 #define PCIFUNC_X3400UC_MCT2		2
23 #define PCI_X3400UC_MCT2_VID_ID		0x8086
24 #define PCI_X3400UC_MCT2_DID_ID		0x2c9a
25 #define PCI_X3400UC_MCT2_COR_ECC_CNT_0	0x80
26 #define PCI_X3400UC_MCT2_COR_ECC_CNT_1	0x84
27 #define PCI_X3400UC_MCT2_COR_ECC_CNT_2	0x88
28 #define PCI_X3400UC_MCT2_COR_ECC_CNT_3	0x8c
29 #define PCI_X3400UC_MCT2_COR_DIMM0	__BITS(0, 14)
30 #define PCI_X3400UC_MCT2_COR_DIMM0_OV	__BIT(15)
31 #define PCI_X3400UC_MCT2_COR_DIMM1	__BITS(16, 30)
32 #define PCI_X3400UC_MCT2_COR_DIMM1_OV	__BIT(31)
33 
34 #endif	/* !_ECC_X3400_REG_H_ */
35