1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/ichwd/ichwd.h,v 1.19 2012/01/05 16:27:32 jhb Exp $ 29 */ 30 31 #ifndef _ICHWD_H_ 32 #define _ICHWD_H_ 33 34 struct ichwd_device { 35 uint16_t device; 36 char *desc; 37 unsigned int version; 38 }; 39 40 struct ichwd_softc { 41 device_t device; 42 device_t ich; 43 int ich_version; 44 45 int active; 46 unsigned int timeout; 47 48 int smi_enabled; 49 int smi_rid; 50 struct resource *smi_res; 51 52 int tco_rid; 53 struct resource *tco_res; 54 55 int gcs_rid; 56 struct resource *gcs_res; 57 }; 58 59 #define VENDORID_INTEL 0x8086 60 #define DEVICEID_CPT0 0x1c40 61 #define DEVICEID_CPT1 0x1c41 62 #define DEVICEID_CPT2 0x1c42 63 #define DEVICEID_CPT3 0x1c43 64 #define DEVICEID_CPT4 0x1c44 65 #define DEVICEID_CPT5 0x1c45 66 #define DEVICEID_CPT6 0x1c46 67 #define DEVICEID_CPT7 0x1c47 68 #define DEVICEID_CPT8 0x1c48 69 #define DEVICEID_CPT9 0x1c49 70 #define DEVICEID_CPT10 0x1c4a 71 #define DEVICEID_CPT11 0x1c4b 72 #define DEVICEID_CPT12 0x1c4c 73 #define DEVICEID_CPT13 0x1c4d 74 #define DEVICEID_CPT14 0x1c4e 75 #define DEVICEID_CPT15 0x1c4f 76 #define DEVICEID_CPT16 0x1c50 77 #define DEVICEID_CPT17 0x1c51 78 #define DEVICEID_CPT18 0x1c52 79 #define DEVICEID_CPT19 0x1c53 80 #define DEVICEID_CPT20 0x1c54 81 #define DEVICEID_CPT21 0x1c55 82 #define DEVICEID_CPT22 0x1c56 83 #define DEVICEID_CPT23 0x1c57 84 #define DEVICEID_CPT24 0x1c58 85 #define DEVICEID_CPT25 0x1c59 86 #define DEVICEID_CPT26 0x1c5a 87 #define DEVICEID_CPT27 0x1c5b 88 #define DEVICEID_CPT28 0x1c5c 89 #define DEVICEID_CPT29 0x1c5d 90 #define DEVICEID_CPT30 0x1c5e 91 #define DEVICEID_CPT31 0x1c5f 92 #define DEVICEID_PATSBURG_LPC1 0x1d40 93 #define DEVICEID_PATSBURG_LPC2 0x1d41 94 #define DEVICEID_PPT0 0x1e40 95 #define DEVICEID_PPT1 0x1e41 96 #define DEVICEID_PPT2 0x1e42 97 #define DEVICEID_PPT3 0x1e43 98 #define DEVICEID_PPT4 0x1e44 99 #define DEVICEID_PPT5 0x1e45 100 #define DEVICEID_PPT6 0x1e46 101 #define DEVICEID_PPT7 0x1e47 102 #define DEVICEID_PPT8 0x1e48 103 #define DEVICEID_PPT9 0x1e49 104 #define DEVICEID_PPT10 0x1e4a 105 #define DEVICEID_PPT11 0x1e4b 106 #define DEVICEID_PPT12 0x1e4c 107 #define DEVICEID_PPT13 0x1e4d 108 #define DEVICEID_PPT14 0x1e4e 109 #define DEVICEID_PPT15 0x1e4f 110 #define DEVICEID_PPT16 0x1e50 111 #define DEVICEID_PPT17 0x1e51 112 #define DEVICEID_PPT18 0x1e52 113 #define DEVICEID_PPT19 0x1e53 114 #define DEVICEID_PPT20 0x1e54 115 #define DEVICEID_PPT21 0x1e55 116 #define DEVICEID_PPT22 0x1e56 117 #define DEVICEID_PPT23 0x1e57 118 #define DEVICEID_PPT24 0x1e58 119 #define DEVICEID_PPT25 0x1e59 120 #define DEVICEID_PPT26 0x1e5a 121 #define DEVICEID_PPT27 0x1e5b 122 #define DEVICEID_PPT28 0x1e5c 123 #define DEVICEID_PPT29 0x1e5d 124 #define DEVICEID_PPT30 0x1e5e 125 #define DEVICEID_PPT31 0x1e5f 126 #define DEVICEID_DH89XXCC_LPC 0x2310 127 #define DEVICEID_82801AA 0x2410 128 #define DEVICEID_82801AB 0x2420 129 #define DEVICEID_82801BA 0x2440 130 #define DEVICEID_82801BAM 0x244c 131 #define DEVICEID_82801CA 0x2480 132 #define DEVICEID_82801CAM 0x248c 133 #define DEVICEID_82801DB 0x24c0 134 #define DEVICEID_82801DBM 0x24cc 135 #define DEVICEID_82801E 0x2450 136 #define DEVICEID_82801EB 0x24dc 137 #define DEVICEID_82801EBR 0x24d0 138 #define DEVICEID_6300ESB 0x25a1 139 #define DEVICEID_82801FBR 0x2640 140 #define DEVICEID_ICH6M 0x2641 141 #define DEVICEID_ICH6W 0x2642 142 #define DEVICEID_63XXESB 0x2670 143 #define DEVICEID_ICH7 0x27b8 144 #define DEVICEID_ICH7DH 0x27b0 145 #define DEVICEID_ICH7M 0x27b9 146 #define DEVICEID_NM10 0x27bc 147 #define DEVICEID_ICH7MDH 0x27bd 148 #define DEVICEID_ICH8 0x2810 149 #define DEVICEID_ICH8DH 0x2812 150 #define DEVICEID_ICH8DO 0x2814 151 #define DEVICEID_ICH8M 0x2815 152 #define DEVICEID_ICH8ME 0x2811 153 #define DEVICEID_ICH9 0x2918 154 #define DEVICEID_ICH9DH 0x2912 155 #define DEVICEID_ICH9DO 0x2914 156 #define DEVICEID_ICH9M 0x2919 157 #define DEVICEID_ICH9ME 0x2917 158 #define DEVICEID_ICH9R 0x2916 159 #define DEVICEID_ICH10 0x3a18 160 #define DEVICEID_ICH10D 0x3a1a 161 #define DEVICEID_ICH10DO 0x3a14 162 #define DEVICEID_ICH10R 0x3a16 163 #define DEVICEID_PCH 0x3b00 164 #define DEVICEID_PCHM 0x3b01 165 #define DEVICEID_P55 0x3b02 166 #define DEVICEID_PM55 0x3b03 167 #define DEVICEID_H55 0x3b06 168 #define DEVICEID_QM57 0x3b07 169 #define DEVICEID_H57 0x3b08 170 #define DEVICEID_HM55 0x3b09 171 #define DEVICEID_Q57 0x3b0a 172 #define DEVICEID_HM57 0x3b0b 173 #define DEVICEID_PCHMSFF 0x3b0d 174 #define DEVICEID_QS57 0x3b0f 175 #define DEVICEID_3400 0x3b12 176 #define DEVICEID_3420 0x3b14 177 #define DEVICEID_3450 0x3b16 178 179 /* ICH LPC Interface Bridge Registers (ICH5 and older) */ 180 #define ICH_GEN_STA 0xd4 181 #define ICH_GEN_STA_NO_REBOOT 0x02 182 #define ICH_PMBASE 0x40 /* ACPI base address register */ 183 #define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 184 185 /* ICH Chipset Configuration Registers (ICH6 and newer) */ 186 #define ICH_RCBA 0xf0 187 #define ICH_GCS_OFFSET 0x3410 188 #define ICH_GCS_SIZE 0x4 189 #define ICH_GCS_NO_REBOOT 0x20 190 191 /* register names and locations (relative to PMBASE) */ 192 #define SMI_BASE 0x30 /* base address for SMI registers */ 193 #define SMI_LEN 0x08 194 #define SMI_EN 0x00 /* SMI Control and Enable Register */ 195 #define SMI_STS 0x04 /* SMI Status Register */ 196 #define TCO_BASE 0x60 /* base address for TCO registers */ 197 #define TCO_LEN 0x20 198 #define TCO_RLD 0x00 /* TCO Reload and Current Value */ 199 #define TCO_TMR1 0x01 /* TCO Timer Initial Value 200 (ICH5 and older, 8 bits) */ 201 #define TCO_TMR2 0x12 /* TCO Timer Initial Value 202 (ICH6 and newer, 16 bits) */ 203 #define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 204 #define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 205 #define TCO1_STS 0x04 /* TCO Status 1 */ 206 #define TCO2_STS 0x06 /* TCO Status 2 */ 207 #define TCO1_CNT 0x08 /* TCO Control 1 */ 208 #define TCO2_CNT 0x08 /* TCO Control 2 */ 209 #define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 210 #define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 211 212 /* bit definitions for SMI_EN and SMI_STS */ 213 #define SMI_TCO_EN 0x2000 214 #define SMI_TCO_STS 0x2000 215 #define SMI_GBL_EN 0x0001 216 217 /* timer value mask for TCO_RLD and TCO_TMR */ 218 #define TCO_TIMER_MASK 0x1f 219 220 /* status bits for TCO1_STS */ 221 #define TCO_NEWCENTURY 0x80 /* set for RTC year roll over (99 to 00) */ 222 #define TCO_TIMEOUT 0x08 /* timed out */ 223 #define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 224 #define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 225 226 /* status bits for TCO2_STS */ 227 #define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 228 #define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 229 230 /* control bits for TCO1_CNT */ 231 #define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 232 #define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 233 #define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 234 #define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 235 236 /* 237 * Masks for the TCO timer value field in TCO_RLD. 238 * If the datasheets are to be believed, the minimum value actually varies 239 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 240 * I suspect this is a bug in the ICH5 datasheet and that the minimum is 241 * uniformly 2, but I'd rather err on the side of caution. 242 */ 243 #define TCO_RLD_TMR_MIN 0x0004 244 #define TCO_RLD1_TMR_MAX 0x003f 245 #define TCO_RLD2_TMR_MAX 0x03ff 246 247 /* approximate length in milliseconds of one WDT tick (about 0.6 sec) */ 248 #define ICHWD_TICK 600 249 250 #endif 251