1*86d7f5d3SJohn Marino /*- 2*86d7f5d3SJohn Marino * Copyright (c) 2001 Alcove - Nicolas Souchu 3*86d7f5d3SJohn Marino * All rights reserved. 4*86d7f5d3SJohn Marino * 5*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 6*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 7*86d7f5d3SJohn Marino * are met: 8*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 9*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer. 10*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 11*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 12*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 13*86d7f5d3SJohn Marino * 14*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18*86d7f5d3SJohn Marino * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19*86d7f5d3SJohn Marino * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20*86d7f5d3SJohn Marino * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21*86d7f5d3SJohn Marino * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22*86d7f5d3SJohn Marino * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23*86d7f5d3SJohn Marino * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24*86d7f5d3SJohn Marino * SUCH DAMAGE. 25*86d7f5d3SJohn Marino * 26*86d7f5d3SJohn Marino * $FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp $ 27*86d7f5d3SJohn Marino * $DragonFly: src/sys/dev/misc/ppc/ppcreg.h,v 1.2 2003/06/17 04:28:40 dillon Exp $ 28*86d7f5d3SJohn Marino * 29*86d7f5d3SJohn Marino */ 30*86d7f5d3SJohn Marino #ifndef __PPCREG_H 31*86d7f5d3SJohn Marino #define __PPCREG_H 32*86d7f5d3SJohn Marino 33*86d7f5d3SJohn Marino /* 34*86d7f5d3SJohn Marino * Parallel Port Chipset type. 35*86d7f5d3SJohn Marino */ 36*86d7f5d3SJohn Marino #define SMC_LIKE 0 37*86d7f5d3SJohn Marino #define SMC_37C665GT 1 38*86d7f5d3SJohn Marino #define SMC_37C666GT 2 39*86d7f5d3SJohn Marino #define NS_PC87332 3 40*86d7f5d3SJohn Marino #define NS_PC87306 4 41*86d7f5d3SJohn Marino #define INTEL_820191AA 5 /* XXX not implemented */ 42*86d7f5d3SJohn Marino #define GENERIC 6 43*86d7f5d3SJohn Marino #define WINB_W83877F 7 44*86d7f5d3SJohn Marino #define WINB_W83877AF 8 45*86d7f5d3SJohn Marino #define WINB_UNKNOWN 9 46*86d7f5d3SJohn Marino #define NS_PC87334 10 47*86d7f5d3SJohn Marino #define SMC_37C935 11 48*86d7f5d3SJohn Marino #define NS_PC87303 12 49*86d7f5d3SJohn Marino 50*86d7f5d3SJohn Marino /* 51*86d7f5d3SJohn Marino * Parallel Port Chipset Type. SMC versus GENERIC (others) 52*86d7f5d3SJohn Marino */ 53*86d7f5d3SJohn Marino #define PPC_TYPE_SMCLIKE 0 54*86d7f5d3SJohn Marino #define PPC_TYPE_GENERIC 1 55*86d7f5d3SJohn Marino 56*86d7f5d3SJohn Marino /* 57*86d7f5d3SJohn Marino * Generic structure to hold parallel port chipset info. 58*86d7f5d3SJohn Marino */ 59*86d7f5d3SJohn Marino struct ppc_data { 60*86d7f5d3SJohn Marino 61*86d7f5d3SJohn Marino int ppc_unit; 62*86d7f5d3SJohn Marino int ppc_model; /* chipset model if detected */ 63*86d7f5d3SJohn Marino int ppc_type; /* generic or smclike chipset type */ 64*86d7f5d3SJohn Marino 65*86d7f5d3SJohn Marino int ppc_mode; /* chipset current mode */ 66*86d7f5d3SJohn Marino int ppc_avm; /* chipset available modes */ 67*86d7f5d3SJohn Marino int ppc_dtm; /* chipset detected modes */ 68*86d7f5d3SJohn Marino 69*86d7f5d3SJohn Marino #define PPC_IRQ_NONE 0x0 70*86d7f5d3SJohn Marino #define PPC_IRQ_nACK 0x1 71*86d7f5d3SJohn Marino #define PPC_IRQ_DMA 0x2 72*86d7f5d3SJohn Marino #define PPC_IRQ_FIFO 0x4 73*86d7f5d3SJohn Marino #define PPC_IRQ_nFAULT 0x8 74*86d7f5d3SJohn Marino int ppc_irqstat; /* remind irq settings */ 75*86d7f5d3SJohn Marino 76*86d7f5d3SJohn Marino #define PPC_DMA_INIT 0x01 77*86d7f5d3SJohn Marino #define PPC_DMA_STARTED 0x02 78*86d7f5d3SJohn Marino #define PPC_DMA_COMPLETE 0x03 79*86d7f5d3SJohn Marino #define PPC_DMA_INTERRUPTED 0x04 80*86d7f5d3SJohn Marino #define PPC_DMA_ERROR 0x05 81*86d7f5d3SJohn Marino int ppc_dmastat; /* dma state */ 82*86d7f5d3SJohn Marino int ppc_dmachan; /* dma channel */ 83*86d7f5d3SJohn Marino int ppc_dmaflags; /* dma transfer flags */ 84*86d7f5d3SJohn Marino caddr_t ppc_dmaddr; /* buffer address */ 85*86d7f5d3SJohn Marino u_int ppc_dmacnt; /* count of bytes sent with dma */ 86*86d7f5d3SJohn Marino 87*86d7f5d3SJohn Marino #define PPC_PWORD_MASK 0x30 88*86d7f5d3SJohn Marino #define PPC_PWORD_16 0x00 89*86d7f5d3SJohn Marino #define PPC_PWORD_8 0x10 90*86d7f5d3SJohn Marino #define PPC_PWORD_32 0x20 91*86d7f5d3SJohn Marino char ppc_pword; /* PWord size */ 92*86d7f5d3SJohn Marino short ppc_fifo; /* FIFO threshold */ 93*86d7f5d3SJohn Marino 94*86d7f5d3SJohn Marino short ppc_wthr; /* writeIntrThresold */ 95*86d7f5d3SJohn Marino short ppc_rthr; /* readIntrThresold */ 96*86d7f5d3SJohn Marino 97*86d7f5d3SJohn Marino char *ppc_ptr; /* microseq current pointer */ 98*86d7f5d3SJohn Marino int ppc_accum; /* microseq accumulator */ 99*86d7f5d3SJohn Marino int ppc_base; /* parallel port base address */ 100*86d7f5d3SJohn Marino int ppc_epp; /* EPP mode (1.7 or 1.9) */ 101*86d7f5d3SJohn Marino int ppc_irq; 102*86d7f5d3SJohn Marino 103*86d7f5d3SJohn Marino unsigned char ppc_flags; 104*86d7f5d3SJohn Marino 105*86d7f5d3SJohn Marino device_t ppbus; /* parallel port chipset corresponding ppbus */ 106*86d7f5d3SJohn Marino 107*86d7f5d3SJohn Marino int rid_irq, rid_drq, rid_ioport; 108*86d7f5d3SJohn Marino struct resource *res_irq, *res_drq, *res_ioport; 109*86d7f5d3SJohn Marino 110*86d7f5d3SJohn Marino bus_space_handle_t bsh; 111*86d7f5d3SJohn Marino bus_space_tag_t bst; 112*86d7f5d3SJohn Marino 113*86d7f5d3SJohn Marino void *intr_cookie; 114*86d7f5d3SJohn Marino 115*86d7f5d3SJohn Marino int ppc_registered; /* 1 if ppcintr() is the registered interrupt */ 116*86d7f5d3SJohn Marino }; 117*86d7f5d3SJohn Marino 118*86d7f5d3SJohn Marino /* 119*86d7f5d3SJohn Marino * Parallel Port Chipset registers. 120*86d7f5d3SJohn Marino */ 121*86d7f5d3SJohn Marino #define PPC_SPP_DTR 0 /* SPP data register */ 122*86d7f5d3SJohn Marino #define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 123*86d7f5d3SJohn Marino #define PPC_SPP_STR 1 /* SPP status register */ 124*86d7f5d3SJohn Marino #define PPC_SPP_CTR 2 /* SPP control register */ 125*86d7f5d3SJohn Marino #define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */ 126*86d7f5d3SJohn Marino #define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 127*86d7f5d3SJohn Marino #define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 128*86d7f5d3SJohn Marino #define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 129*86d7f5d3SJohn Marino #define PPC_ECP_CNFGB 0x401 /* Configuration register B */ 130*86d7f5d3SJohn Marino #define PPC_ECP_ECR 0x402 /* ECP extended control register */ 131*86d7f5d3SJohn Marino 132*86d7f5d3SJohn Marino #define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 133*86d7f5d3SJohn Marino #define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 134*86d7f5d3SJohn Marino #define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 135*86d7f5d3SJohn Marino #define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 136*86d7f5d3SJohn Marino #define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 137*86d7f5d3SJohn Marino #define PPC_ECR_STD 0x0 138*86d7f5d3SJohn Marino #define PPC_ECR_PS2 0x20 139*86d7f5d3SJohn Marino #define PPC_ECR_FIFO 0x40 140*86d7f5d3SJohn Marino #define PPC_ECR_ECP 0x60 141*86d7f5d3SJohn Marino #define PPC_ECR_EPP 0x80 142*86d7f5d3SJohn Marino 143*86d7f5d3SJohn Marino #define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 144*86d7f5d3SJohn Marino #define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 145*86d7f5d3SJohn Marino 146*86d7f5d3SJohn Marino #define r_dtr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_DTR)) 147*86d7f5d3SJohn Marino #define r_str(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_STR)) 148*86d7f5d3SJohn Marino #define r_ctr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_SPP_CTR)) 149*86d7f5d3SJohn Marino 150*86d7f5d3SJohn Marino #define r_epp_A(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_EPP_ADDR)) 151*86d7f5d3SJohn Marino #define r_epp_D(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_EPP_DATA)) 152*86d7f5d3SJohn Marino #define r_cnfgA(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_CNFGA)) 153*86d7f5d3SJohn Marino #define r_cnfgB(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_CNFGB)) 154*86d7f5d3SJohn Marino #define r_ecr(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_ECR)) 155*86d7f5d3SJohn Marino #define r_fifo(ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, PPC_ECP_D_FIFO)) 156*86d7f5d3SJohn Marino 157*86d7f5d3SJohn Marino #define w_dtr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_DTR, byte)) 158*86d7f5d3SJohn Marino #define w_str(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_STR, byte)) 159*86d7f5d3SJohn Marino #define w_ctr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_SPP_CTR, byte)) 160*86d7f5d3SJohn Marino 161*86d7f5d3SJohn Marino #define w_epp_A(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_EPP_ADDR, byte)) 162*86d7f5d3SJohn Marino #define w_epp_D(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_EPP_DATA, byte)) 163*86d7f5d3SJohn Marino #define w_ecr(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_ECP_ECR, byte)) 164*86d7f5d3SJohn Marino #define w_fifo(ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, PPC_ECP_D_FIFO, byte)) 165*86d7f5d3SJohn Marino 166*86d7f5d3SJohn Marino /* 167*86d7f5d3SJohn Marino * Register defines for the PC873xx parts 168*86d7f5d3SJohn Marino */ 169*86d7f5d3SJohn Marino 170*86d7f5d3SJohn Marino #define PC873_FER 0x00 171*86d7f5d3SJohn Marino #define PC873_PPENABLE (1<<0) 172*86d7f5d3SJohn Marino #define PC873_FAR 0x01 173*86d7f5d3SJohn Marino #define PC873_PTR 0x02 174*86d7f5d3SJohn Marino #define PC873_CFGLOCK (1<<6) 175*86d7f5d3SJohn Marino #define PC873_EPPRDIR (1<<7) 176*86d7f5d3SJohn Marino #define PC873_EXTENDED (1<<7) 177*86d7f5d3SJohn Marino #define PC873_LPTBIRQ7 (1<<3) 178*86d7f5d3SJohn Marino #define PC873_FCR 0x03 179*86d7f5d3SJohn Marino #define PC873_ZWS (1<<5) 180*86d7f5d3SJohn Marino #define PC873_ZWSPWDN (1<<6) 181*86d7f5d3SJohn Marino #define PC873_PCR 0x04 182*86d7f5d3SJohn Marino #define PC873_EPPEN (1<<0) 183*86d7f5d3SJohn Marino #define PC873_EPP19 (1<<1) 184*86d7f5d3SJohn Marino #define PC873_ECPEN (1<<2) 185*86d7f5d3SJohn Marino #define PC873_ECPCLK (1<<3) 186*86d7f5d3SJohn Marino #define PC873_PMC 0x06 187*86d7f5d3SJohn Marino #define PC873_TUP 0x07 188*86d7f5d3SJohn Marino #define PC873_SID 0x08 189*86d7f5d3SJohn Marino #define PC873_PNP0 0x1b 190*86d7f5d3SJohn Marino #define PC873_PNP1 0x1c 191*86d7f5d3SJohn Marino #define PC873_LPTBA 0x19 192*86d7f5d3SJohn Marino 193*86d7f5d3SJohn Marino /* 194*86d7f5d3SJohn Marino * Register defines for the SMC FDC37C66xGT parts 195*86d7f5d3SJohn Marino */ 196*86d7f5d3SJohn Marino 197*86d7f5d3SJohn Marino /* Init codes */ 198*86d7f5d3SJohn Marino #define SMC665_iCODE 0x55 199*86d7f5d3SJohn Marino #define SMC666_iCODE 0x44 200*86d7f5d3SJohn Marino 201*86d7f5d3SJohn Marino /* Base configuration ports */ 202*86d7f5d3SJohn Marino #define SMC66x_CSR 0x3F0 203*86d7f5d3SJohn Marino #define SMC666_CSR 0x370 /* hard-configured value for 666 */ 204*86d7f5d3SJohn Marino 205*86d7f5d3SJohn Marino /* Bits */ 206*86d7f5d3SJohn Marino #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 207*86d7f5d3SJohn Marino #define SMC_CR1_MODE (1<<3) /* bit 3 */ 208*86d7f5d3SJohn Marino #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 209*86d7f5d3SJohn Marino #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 210*86d7f5d3SJohn Marino 211*86d7f5d3SJohn Marino /* Extended modes */ 212*86d7f5d3SJohn Marino #define SMC_SPP 0x0 /* SPP */ 213*86d7f5d3SJohn Marino #define SMC_EPPSPP 0x1 /* EPP and SPP */ 214*86d7f5d3SJohn Marino #define SMC_ECP 0x2 /* ECP */ 215*86d7f5d3SJohn Marino #define SMC_ECPEPP 0x3 /* ECP and EPP */ 216*86d7f5d3SJohn Marino 217*86d7f5d3SJohn Marino /* 218*86d7f5d3SJohn Marino * Register defines for the SMC FDC37C935 parts 219*86d7f5d3SJohn Marino */ 220*86d7f5d3SJohn Marino 221*86d7f5d3SJohn Marino /* Configuration ports */ 222*86d7f5d3SJohn Marino #define SMC935_CFG 0x370 223*86d7f5d3SJohn Marino #define SMC935_IND 0x370 224*86d7f5d3SJohn Marino #define SMC935_DAT 0x371 225*86d7f5d3SJohn Marino 226*86d7f5d3SJohn Marino /* Registers */ 227*86d7f5d3SJohn Marino #define SMC935_LOGDEV 0x7 228*86d7f5d3SJohn Marino #define SMC935_ID 0x20 229*86d7f5d3SJohn Marino #define SMC935_PORTHI 0x60 230*86d7f5d3SJohn Marino #define SMC935_PORTLO 0x61 231*86d7f5d3SJohn Marino #define SMC935_PPMODE 0xf0 232*86d7f5d3SJohn Marino 233*86d7f5d3SJohn Marino /* Parallel port modes */ 234*86d7f5d3SJohn Marino #define SMC935_SPP 0x38 + 0 235*86d7f5d3SJohn Marino #define SMC935_EPP19SPP 0x38 + 1 236*86d7f5d3SJohn Marino #define SMC935_ECP 0x38 + 2 237*86d7f5d3SJohn Marino #define SMC935_ECPEPP19 0x38 + 3 238*86d7f5d3SJohn Marino #define SMC935_CENT 0x38 + 4 239*86d7f5d3SJohn Marino #define SMC935_EPP17SPP 0x38 + 5 240*86d7f5d3SJohn Marino #define SMC935_UNUSED 0x38 + 6 241*86d7f5d3SJohn Marino #define SMC935_ECPEPP17 0x38 + 7 242*86d7f5d3SJohn Marino 243*86d7f5d3SJohn Marino /* 244*86d7f5d3SJohn Marino * Register defines for the Winbond W83877F parts 245*86d7f5d3SJohn Marino */ 246*86d7f5d3SJohn Marino 247*86d7f5d3SJohn Marino #define WINB_W83877F_ID 0xa 248*86d7f5d3SJohn Marino #define WINB_W83877AF_ID 0xb 249*86d7f5d3SJohn Marino 250*86d7f5d3SJohn Marino /* Configuration bits */ 251*86d7f5d3SJohn Marino #define WINB_HEFERE (1<<5) /* CROC bit 5 */ 252*86d7f5d3SJohn Marino #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 253*86d7f5d3SJohn Marino 254*86d7f5d3SJohn Marino #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 255*86d7f5d3SJohn Marino #define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 256*86d7f5d3SJohn Marino 257*86d7f5d3SJohn Marino #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 258*86d7f5d3SJohn Marino #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 259*86d7f5d3SJohn Marino #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 260*86d7f5d3SJohn Marino 261*86d7f5d3SJohn Marino /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 262*86d7f5d3SJohn Marino #define WINB_W83757 0x0 263*86d7f5d3SJohn Marino #define WINB_EXTFDC 0x4 264*86d7f5d3SJohn Marino #define WINB_EXTADP 0x8 265*86d7f5d3SJohn Marino #define WINB_EXT2FDD 0xc 266*86d7f5d3SJohn Marino #define WINB_JOYSTICK 0x80 267*86d7f5d3SJohn Marino 268*86d7f5d3SJohn Marino #define WINB_PARALLEL 0x80 269*86d7f5d3SJohn Marino #define WINB_EPP_SPP 0x4 270*86d7f5d3SJohn Marino #define WINB_ECP 0x8 271*86d7f5d3SJohn Marino #define WINB_ECP_EPP 0xc 272*86d7f5d3SJohn Marino 273*86d7f5d3SJohn Marino #endif 274