1 /*- 2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter. 26 * 27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon. 28 * 29 * $FreeBSD: src/sys/dev/ae/if_ae.c,v 1.1.2.3.2.1 2009/04/15 03:14:26 kensmith Exp $ 30 */ 31 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/interrupt.h> 37 #include <sys/malloc.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/serialize.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/bpf.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/ifq_var.h> 52 #include <net/vlan/if_vlan_var.h> 53 #include <net/vlan/if_vlan_ether.h> 54 55 #include <bus/pci/pcireg.h> 56 #include <bus/pci/pcivar.h> 57 #include <bus/pci/pcidevs.h> 58 59 #include <dev/netif/mii_layer/miivar.h> 60 61 #include <dev/netif/ae/if_aereg.h> 62 #include <dev/netif/ae/if_aevar.h> 63 64 /* "device miibus" required. See GENERIC if you get errors here. */ 65 #include "miibus_if.h" 66 67 /* 68 * Devices supported by this driver. 69 */ 70 static const struct ae_dev { 71 uint16_t ae_vendorid; 72 uint16_t ae_deviceid; 73 const char *ae_name; 74 } ae_devs[] = { 75 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2, 76 "Attansic Technology Corp, L2 Fast Ethernet" }, 77 /* Required last entry */ 78 { 0, 0, NULL } 79 }; 80 81 82 static int ae_probe(device_t); 83 static int ae_attach(device_t); 84 static int ae_detach(device_t); 85 static int ae_shutdown(device_t); 86 static int ae_suspend(device_t); 87 static int ae_resume(device_t); 88 static int ae_miibus_readreg(device_t, int, int); 89 static int ae_miibus_writereg(device_t, int, int, int); 90 static void ae_miibus_statchg(device_t); 91 92 static int ae_mediachange(struct ifnet *); 93 static void ae_mediastatus(struct ifnet *, struct ifmediareq *); 94 static void ae_init(void *); 95 static void ae_start(struct ifnet *); 96 static int ae_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 97 static void ae_watchdog(struct ifnet *); 98 static void ae_stop(struct ae_softc *); 99 static void ae_tick(void *); 100 101 static void ae_intr(void *); 102 static void ae_tx_intr(struct ae_softc *); 103 static void ae_rx_intr(struct ae_softc *); 104 static int ae_rxeof(struct ae_softc *, struct ae_rxd *); 105 106 static int ae_encap(struct ae_softc *, struct mbuf **); 107 static void ae_sysctl_node(struct ae_softc *); 108 static void ae_phy_reset(struct ae_softc *); 109 static int ae_reset(struct ae_softc *); 110 static void ae_pcie_init(struct ae_softc *); 111 static void ae_get_eaddr(struct ae_softc *); 112 static void ae_dma_free(struct ae_softc *); 113 static int ae_dma_alloc(struct ae_softc *); 114 static void ae_mac_config(struct ae_softc *); 115 static void ae_stop_rxmac(struct ae_softc *); 116 static void ae_stop_txmac(struct ae_softc *); 117 static void ae_rxfilter(struct ae_softc *); 118 static void ae_rxvlan(struct ae_softc *); 119 static void ae_update_stats_rx(uint16_t, struct ae_stats *); 120 static void ae_update_stats_tx(uint16_t, struct ae_stats *); 121 static void ae_powersave_disable(struct ae_softc *); 122 static void ae_powersave_enable(struct ae_softc *); 123 124 static device_method_t ae_methods[] = { 125 /* Device interface. */ 126 DEVMETHOD(device_probe, ae_probe), 127 DEVMETHOD(device_attach, ae_attach), 128 DEVMETHOD(device_detach, ae_detach), 129 DEVMETHOD(device_shutdown, ae_shutdown), 130 DEVMETHOD(device_suspend, ae_suspend), 131 DEVMETHOD(device_resume, ae_resume), 132 133 /* Bus interface. */ 134 DEVMETHOD(bus_print_child, bus_generic_print_child), 135 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 136 137 /* MII interface. */ 138 DEVMETHOD(miibus_readreg, ae_miibus_readreg), 139 DEVMETHOD(miibus_writereg, ae_miibus_writereg), 140 DEVMETHOD(miibus_statchg, ae_miibus_statchg), 141 { NULL, NULL } 142 }; 143 144 static driver_t ae_driver = { 145 "ae", 146 ae_methods, 147 sizeof(struct ae_softc) 148 }; 149 150 static devclass_t ae_devclass; 151 DECLARE_DUMMY_MODULE(if_ae); 152 MODULE_DEPEND(if_ae, miibus, 1, 1, 1); 153 DRIVER_MODULE(if_ae, pci, ae_driver, ae_devclass, 0, 0); 154 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0); 155 156 /* Register access macros. */ 157 #define AE_WRITE_4(_sc, reg, val) \ 158 bus_space_write_4((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val)) 159 #define AE_WRITE_2(_sc, reg, val) \ 160 bus_space_write_2((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val)) 161 #define AE_WRITE_1(_sc, reg, val) \ 162 bus_space_write_1((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg), (val)) 163 #define AE_READ_4(_sc, reg) \ 164 bus_space_read_4((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg)) 165 #define AE_READ_2(_sc, reg) \ 166 bus_space_read_2((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg)) 167 #define AE_READ_1(_sc, reg) \ 168 bus_space_read_1((_sc)->ae_mem_bt, (_sc)->ae_mem_bh, (reg)) 169 170 #define AE_PHY_READ(sc, reg) \ 171 ae_miibus_readreg(sc->ae_dev, 0, reg) 172 #define AE_PHY_WRITE(sc, reg, val) \ 173 ae_miibus_writereg(sc->ae_dev, 0, reg, val) 174 #define AE_CHECK_EADDR_VALID(eaddr) \ 175 ((eaddr[0] == 0 && eaddr[1] == 0) || \ 176 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff)) 177 #define AE_RXD_VLAN(vtag) \ 178 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9)) 179 #define AE_TXD_VLAN(vtag) \ 180 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08)) 181 182 /* 183 * ae statistics. 184 */ 185 #define STATS_ENTRY(node, desc, field) \ 186 { node, desc, offsetof(struct ae_stats, field) } 187 struct { 188 const char *node; 189 const char *desc; 190 intptr_t offset; 191 } ae_stats_tx[] = { 192 STATS_ENTRY("bcast", "broadcast frames", tx_bcast), 193 STATS_ENTRY("mcast", "multicast frames", tx_mcast), 194 STATS_ENTRY("pause", "PAUSE frames", tx_pause), 195 STATS_ENTRY("control", "control frames", tx_ctrl), 196 STATS_ENTRY("defers", "deferrals occuried", tx_defer), 197 STATS_ENTRY("exc_defers", "excessive deferrals occuried", tx_excdefer), 198 STATS_ENTRY("singlecols", "single collisions occuried", tx_singlecol), 199 STATS_ENTRY("multicols", "multiple collisions occuried", tx_multicol), 200 STATS_ENTRY("latecols", "late collisions occuried", tx_latecol), 201 STATS_ENTRY("aborts", "transmit aborts due collisions", tx_abortcol), 202 STATS_ENTRY("underruns", "Tx FIFO underruns", tx_underrun) 203 }, ae_stats_rx[] = { 204 STATS_ENTRY("bcast", "broadcast frames", rx_bcast), 205 STATS_ENTRY("mcast", "multicast frames", rx_mcast), 206 STATS_ENTRY("pause", "PAUSE frames", rx_pause), 207 STATS_ENTRY("control", "control frames", rx_ctrl), 208 STATS_ENTRY("crc_errors", "frames with CRC errors", rx_crcerr), 209 STATS_ENTRY("code_errors", "frames with invalid opcode", rx_codeerr), 210 STATS_ENTRY("runt", "runt frames", rx_runt), 211 STATS_ENTRY("frag", "fragmented frames", rx_frag), 212 STATS_ENTRY("align_errors", "frames with alignment errors", rx_align), 213 STATS_ENTRY("truncated", "frames truncated due to Rx FIFO inderrun", 214 rx_trunc) 215 }; 216 #define AE_STATS_RX_LEN (sizeof(ae_stats_rx) / sizeof(*ae_stats_rx)) 217 #define AE_STATS_TX_LEN (sizeof(ae_stats_tx) / sizeof(*ae_stats_tx)) 218 219 static void 220 ae_stop(struct ae_softc *sc) 221 { 222 struct ifnet *ifp = &sc->arpcom.ac_if; 223 int i; 224 225 ASSERT_SERIALIZED(ifp->if_serializer); 226 227 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 228 ifp->if_timer = 0; 229 230 sc->ae_flags &= ~AE_FLAG_LINK; 231 callout_stop(&sc->ae_tick_ch); 232 233 /* 234 * Clear and disable interrupts. 235 */ 236 AE_WRITE_4(sc, AE_IMR_REG, 0); 237 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 238 239 /* 240 * Stop Rx/Tx MACs. 241 */ 242 ae_stop_txmac(sc); 243 ae_stop_rxmac(sc); 244 245 /* 246 * Stop DMA engines. 247 */ 248 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN); 249 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN); 250 251 /* 252 * Wait for everything to enter idle state. 253 */ 254 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 255 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 256 break; 257 DELAY(100); 258 } 259 if (i == AE_IDLE_TIMEOUT) 260 if_printf(ifp, "could not enter idle state in stop.\n"); 261 } 262 263 static void 264 ae_stop_rxmac(struct ae_softc *sc) 265 { 266 uint32_t val; 267 int i; 268 269 /* 270 * Stop Rx MAC engine. 271 */ 272 val = AE_READ_4(sc, AE_MAC_REG); 273 if ((val & AE_MAC_RX_EN) != 0) { 274 val &= ~AE_MAC_RX_EN; 275 AE_WRITE_4(sc, AE_MAC_REG, val); 276 } 277 278 /* 279 * Stop Rx DMA engine. 280 */ 281 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN) 282 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0); 283 284 /* 285 * Wait for IDLE state. 286 */ 287 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 288 val = AE_READ_4(sc, AE_IDLE_REG); 289 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0) 290 break; 291 DELAY(100); 292 } 293 if (i == AE_IDLE_TIMEOUT) { 294 if_printf(&sc->arpcom.ac_if, 295 "timed out while stopping Rx MAC.\n"); 296 } 297 } 298 299 static void 300 ae_stop_txmac(struct ae_softc *sc) 301 { 302 uint32_t val; 303 int i; 304 305 /* 306 * Stop Tx MAC engine. 307 */ 308 val = AE_READ_4(sc, AE_MAC_REG); 309 if ((val & AE_MAC_TX_EN) != 0) { 310 val &= ~AE_MAC_TX_EN; 311 AE_WRITE_4(sc, AE_MAC_REG, val); 312 } 313 314 /* 315 * Stop Tx DMA engine. 316 */ 317 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN) 318 AE_WRITE_1(sc, AE_DMAREAD_REG, 0); 319 320 /* 321 * Wait for IDLE state. 322 */ 323 for (i = 0; i < AE_IDLE_TIMEOUT; i--) { 324 val = AE_READ_4(sc, AE_IDLE_REG); 325 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0) 326 break; 327 DELAY(100); 328 } 329 if (i == AE_IDLE_TIMEOUT) { 330 if_printf(&sc->arpcom.ac_if, 331 "timed out while stopping Tx MAC.\n"); 332 } 333 } 334 335 /* 336 * Callback from MII layer when media changes. 337 */ 338 static void 339 ae_miibus_statchg(device_t dev) 340 { 341 struct ae_softc *sc = device_get_softc(dev); 342 struct ifnet *ifp = &sc->arpcom.ac_if; 343 struct mii_data *mii; 344 uint32_t val; 345 346 ASSERT_SERIALIZED(ifp->if_serializer); 347 348 if ((ifp->if_flags & IFF_RUNNING) == 0) 349 return; 350 351 mii = device_get_softc(sc->ae_miibus); 352 sc->ae_flags &= ~AE_FLAG_LINK; 353 if ((mii->mii_media_status & IFM_AVALID) != 0) { 354 switch (IFM_SUBTYPE(mii->mii_media_active)) { 355 case IFM_10_T: 356 case IFM_100_TX: 357 sc->ae_flags |= AE_FLAG_LINK; 358 break; 359 default: 360 break; 361 } 362 } 363 364 /* Stop Rx/Tx MACs. */ 365 ae_stop_rxmac(sc); 366 ae_stop_txmac(sc); 367 368 /* Program MACs with resolved speed/duplex/flow-control. */ 369 if ((sc->ae_flags & AE_FLAG_LINK) != 0) { 370 ae_mac_config(sc); 371 372 /* 373 * Restart DMA engines. 374 */ 375 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 376 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 377 378 /* 379 * Enable Rx and Tx MACs. 380 */ 381 val = AE_READ_4(sc, AE_MAC_REG); 382 val |= AE_MAC_TX_EN | AE_MAC_RX_EN; 383 AE_WRITE_4(sc, AE_MAC_REG, val); 384 } 385 } 386 387 static void 388 ae_sysctl_node(struct ae_softc *sc) 389 { 390 struct sysctl_ctx_list *ctx; 391 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx; 392 struct ae_stats *ae_stats; 393 unsigned int i; 394 395 ae_stats = &sc->stats; 396 sysctl_ctx_init(&sc->ae_sysctl_ctx); 397 sc->ae_sysctl_tree = SYSCTL_ADD_NODE(&sc->ae_sysctl_ctx, 398 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 399 device_get_nameunit(sc->ae_dev), 400 CTLFLAG_RD, 0, ""); 401 if (sc->ae_sysctl_tree == NULL) { 402 device_printf(sc->ae_dev, "can't add sysctl node\n"); 403 return; 404 } 405 ctx = &sc->ae_sysctl_ctx; 406 root = sc->ae_sysctl_tree; 407 408 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats", 409 CTLFLAG_RD, NULL, "ae statistics"); 410 if (stats == NULL) { 411 device_printf(sc->ae_dev, "can't add stats sysctl node\n"); 412 return; 413 } 414 415 /* 416 * Receiver statistcics. 417 */ 418 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx", 419 CTLFLAG_RD, NULL, "Rx MAC statistics"); 420 if (stats_rx != NULL) { 421 for (i = 0; i < AE_STATS_RX_LEN; i++) { 422 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_rx), 423 OID_AUTO, ae_stats_rx[i].node, CTLFLAG_RD, 424 (char *)ae_stats + ae_stats_rx[i].offset, 0, 425 ae_stats_rx[i].desc); 426 } 427 } 428 429 /* 430 * Transmitter statistcics. 431 */ 432 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx", 433 CTLFLAG_RD, NULL, "Tx MAC statistics"); 434 if (stats_tx != NULL) { 435 for (i = 0; i < AE_STATS_TX_LEN; i++) { 436 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(stats_tx), 437 OID_AUTO, ae_stats_tx[i].node, CTLFLAG_RD, 438 (char *)ae_stats + ae_stats_tx[i].offset, 0, 439 ae_stats_tx[i].desc); 440 } 441 } 442 } 443 444 static int 445 ae_miibus_readreg(device_t dev, int phy, int reg) 446 { 447 struct ae_softc *sc = device_get_softc(dev); 448 uint32_t val; 449 int i; 450 451 /* 452 * Locking is done in upper layers. 453 */ 454 if (phy != sc->ae_phyaddr) 455 return (0); 456 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 457 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE | 458 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK); 459 AE_WRITE_4(sc, AE_MDIO_REG, val); 460 461 /* 462 * Wait for operation to complete. 463 */ 464 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 465 DELAY(2); 466 val = AE_READ_4(sc, AE_MDIO_REG); 467 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 468 break; 469 } 470 if (i == AE_MDIO_TIMEOUT) { 471 device_printf(sc->ae_dev, "phy read timeout: %d.\n", reg); 472 return (0); 473 } 474 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 475 } 476 477 static int 478 ae_miibus_writereg(device_t dev, int phy, int reg, int val) 479 { 480 struct ae_softc *sc = device_get_softc(dev); 481 uint32_t aereg; 482 int i; 483 484 /* 485 * Locking is done in upper layers. 486 */ 487 if (phy != sc->ae_phyaddr) 488 return (0); 489 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) | 490 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE | 491 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) | 492 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK); 493 AE_WRITE_4(sc, AE_MDIO_REG, aereg); 494 495 /* 496 * Wait for operation to complete. 497 */ 498 for (i = 0; i < AE_MDIO_TIMEOUT; i++) { 499 DELAY(2); 500 aereg = AE_READ_4(sc, AE_MDIO_REG); 501 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0) 502 break; 503 } 504 if (i == AE_MDIO_TIMEOUT) 505 device_printf(sc->ae_dev, "phy write timeout: %d.\n", reg); 506 return (0); 507 } 508 509 static int 510 ae_probe(device_t dev) 511 { 512 uint16_t vendor, devid; 513 const struct ae_dev *sp; 514 515 vendor = pci_get_vendor(dev); 516 devid = pci_get_device(dev); 517 for (sp = ae_devs; sp->ae_name != NULL; sp++) { 518 if (vendor == sp->ae_vendorid && 519 devid == sp->ae_deviceid) { 520 device_set_desc(dev, sp->ae_name); 521 return (0); 522 } 523 } 524 return (ENXIO); 525 } 526 527 static int 528 ae_dma_alloc(struct ae_softc *sc) 529 { 530 bus_addr_t busaddr; 531 int error; 532 533 /* 534 * Create parent DMA tag. 535 */ 536 error = bus_dma_tag_create(NULL, 1, 0, 537 BUS_SPACE_MAXADDR_32BIT, 538 BUS_SPACE_MAXADDR, 539 NULL, NULL, 540 BUS_SPACE_MAXSIZE_32BIT, 541 0, 542 BUS_SPACE_MAXSIZE_32BIT, 543 0, &sc->dma_parent_tag); 544 if (error) { 545 device_printf(sc->ae_dev, "could not creare parent DMA tag.\n"); 546 return (error); 547 } 548 549 /* 550 * Create DMA stuffs for TxD. 551 */ 552 sc->txd_base = bus_dmamem_coherent_any(sc->dma_parent_tag, 4, 553 AE_TXD_BUFSIZE_DEFAULT, BUS_DMA_WAITOK | BUS_DMA_ZERO, 554 &sc->dma_txd_tag, &sc->dma_txd_map, 555 &sc->dma_txd_busaddr); 556 if (sc->txd_base == NULL) { 557 device_printf(sc->ae_dev, "could not creare TxD DMA stuffs.\n"); 558 return ENOMEM; 559 } 560 561 /* 562 * Create DMA stuffs for TxS. 563 */ 564 sc->txs_base = bus_dmamem_coherent_any(sc->dma_parent_tag, 4, 565 AE_TXS_COUNT_DEFAULT * 4, BUS_DMA_WAITOK | BUS_DMA_ZERO, 566 &sc->dma_txs_tag, &sc->dma_txs_map, 567 &sc->dma_txs_busaddr); 568 if (sc->txs_base == NULL) { 569 device_printf(sc->ae_dev, "could not creare TxS DMA stuffs.\n"); 570 return ENOMEM; 571 } 572 573 /* 574 * Create DMA stuffs for RxD. 575 */ 576 sc->rxd_base_dma = bus_dmamem_coherent_any(sc->dma_parent_tag, 128, 577 AE_RXD_COUNT_DEFAULT * 1536 + 120, 578 BUS_DMA_WAITOK | BUS_DMA_ZERO, 579 &sc->dma_rxd_tag, &sc->dma_rxd_map, 580 &busaddr); 581 if (sc->rxd_base_dma == NULL) { 582 device_printf(sc->ae_dev, "could not creare RxD DMA stuffs.\n"); 583 return ENOMEM; 584 } 585 sc->dma_rxd_busaddr = busaddr + 120; 586 sc->rxd_base = (struct ae_rxd *)(sc->rxd_base_dma + 120); 587 588 return (0); 589 } 590 591 static void 592 ae_mac_config(struct ae_softc *sc) 593 { 594 struct mii_data *mii; 595 uint32_t val; 596 597 mii = device_get_softc(sc->ae_miibus); 598 val = AE_READ_4(sc, AE_MAC_REG); 599 val &= ~AE_MAC_FULL_DUPLEX; 600 /* XXX disable AE_MAC_TX_FLOW_EN? */ 601 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 602 val |= AE_MAC_FULL_DUPLEX; 603 AE_WRITE_4(sc, AE_MAC_REG, val); 604 } 605 606 static int 607 ae_rxeof(struct ae_softc *sc, struct ae_rxd *rxd) 608 { 609 struct ifnet *ifp = &sc->arpcom.ac_if; 610 struct mbuf *m; 611 unsigned int size; 612 uint16_t flags; 613 614 flags = le16toh(rxd->flags); 615 #ifdef AE_DEBUG 616 if_printf(ifp, "Rx interrupt occuried.\n"); 617 #endif 618 size = le16toh(rxd->len) - ETHER_CRC_LEN; 619 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - 620 sizeof(struct ether_vlan_header))) { 621 if_printf(ifp, "Runt frame received."); 622 return (EIO); 623 } 624 625 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL); 626 if (m == NULL) 627 return (ENOBUFS); 628 629 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 630 (flags & AE_RXD_HAS_VLAN)) { 631 m->m_pkthdr.ether_vlantag = AE_RXD_VLAN(le16toh(rxd->vlan)); 632 m->m_flags |= M_VLANTAG; 633 } 634 ifp->if_input(ifp, m); 635 636 return (0); 637 } 638 639 static void 640 ae_rx_intr(struct ae_softc *sc) 641 { 642 struct ifnet *ifp = &sc->arpcom.ac_if; 643 struct ae_rxd *rxd; 644 uint16_t flags; 645 int error; 646 647 /* 648 * Syncronize DMA buffers. 649 */ 650 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map, 651 BUS_DMASYNC_POSTREAD); 652 for (;;) { 653 rxd = (struct ae_rxd *)(sc->rxd_base + sc->rxd_cur); 654 655 flags = le16toh(rxd->flags); 656 if ((flags & AE_RXD_UPDATE) == 0) 657 break; 658 rxd->flags = htole16(flags & ~AE_RXD_UPDATE); 659 660 /* Update stats. */ 661 ae_update_stats_rx(flags, &sc->stats); 662 663 /* 664 * Update position index. 665 */ 666 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT; 667 if ((flags & AE_RXD_SUCCESS) == 0) { 668 ifp->if_ierrors++; 669 continue; 670 } 671 672 error = ae_rxeof(sc, rxd); 673 if (error) 674 ifp->if_ierrors++; 675 else 676 ifp->if_ipackets++; 677 } 678 679 /* Update Rx index. */ 680 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 681 } 682 683 static void 684 ae_tx_intr(struct ae_softc *sc) 685 { 686 struct ifnet *ifp = &sc->arpcom.ac_if; 687 struct ae_txd *txd; 688 struct ae_txs *txs; 689 uint16_t flags; 690 691 /* 692 * Syncronize DMA buffers. 693 */ 694 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_POSTREAD); 695 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, BUS_DMASYNC_POSTREAD); 696 697 for (;;) { 698 txs = sc->txs_base + sc->txs_ack; 699 700 flags = le16toh(txs->flags); 701 if ((flags & AE_TXS_UPDATE) == 0) 702 break; 703 txs->flags = htole16(flags & ~AE_TXS_UPDATE); 704 705 /* Update stats. */ 706 ae_update_stats_tx(flags, &sc->stats); 707 708 /* 709 * Update TxS position. 710 */ 711 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT; 712 sc->ae_flags |= AE_FLAG_TXAVAIL; 713 txd = (struct ae_txd *)(sc->txd_base + sc->txd_ack); 714 if (txs->len != txd->len) { 715 device_printf(sc->ae_dev, "Size mismatch: " 716 "TxS:%d TxD:%d\n", 717 le16toh(txs->len), le16toh(txd->len)); 718 } 719 720 /* 721 * Move txd ack and align on 4-byte boundary. 722 */ 723 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) + 4 + 3) & ~3) % 724 AE_TXD_BUFSIZE_DEFAULT; 725 if ((flags & AE_TXS_SUCCESS) != 0) 726 ifp->if_opackets++; 727 else 728 ifp->if_oerrors++; 729 sc->tx_inproc--; 730 } 731 732 if (sc->tx_inproc < 0) { 733 /* XXX assert? */ 734 if_printf(ifp, "Received stray Tx interrupt(s).\n"); 735 sc->tx_inproc = 0; 736 } 737 if (sc->tx_inproc == 0) 738 ifp->if_timer = 0; /* Unarm watchdog. */ 739 if (sc->ae_flags & AE_FLAG_TXAVAIL) { 740 ifp->if_flags &= ~IFF_OACTIVE; 741 if (!ifq_is_empty(&ifp->if_snd)) 742 #ifdef foo 743 ae_intr(sc); 744 #else 745 if_devstart(ifp); 746 #endif 747 } 748 749 /* 750 * Syncronize DMA buffers. 751 */ 752 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREWRITE); 753 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, BUS_DMASYNC_PREWRITE); 754 } 755 756 static void 757 ae_intr(void *xsc) 758 { 759 struct ae_softc *sc = xsc; 760 struct ifnet *ifp = &sc->arpcom.ac_if; 761 uint32_t val; 762 763 ASSERT_SERIALIZED(ifp->if_serializer); 764 765 val = AE_READ_4(sc, AE_ISR_REG); 766 if (val == 0 || (val & AE_IMR_DEFAULT) == 0) 767 return; 768 769 #ifdef foo 770 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE); 771 #endif 772 773 /* Read interrupt status. */ 774 val = AE_READ_4(sc, AE_ISR_REG); 775 776 /* Clear interrupts and disable them. */ 777 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE); 778 779 if (ifp->if_flags & IFF_RUNNING) { 780 if (val & (AE_ISR_DMAR_TIMEOUT | 781 AE_ISR_DMAW_TIMEOUT | 782 AE_ISR_PHY_LINKDOWN)) { 783 ae_init(sc); 784 } 785 if (val & AE_ISR_TX_EVENT) 786 ae_tx_intr(sc); 787 if (val & AE_ISR_RX_EVENT) 788 ae_rx_intr(sc); 789 } 790 791 /* Re-enable interrupts. */ 792 AE_WRITE_4(sc, AE_ISR_REG, 0); 793 } 794 795 static void 796 ae_init(void *xsc) 797 { 798 struct ae_softc *sc = xsc; 799 struct ifnet *ifp = &sc->arpcom.ac_if; 800 struct mii_data *mii; 801 uint8_t eaddr[ETHER_ADDR_LEN]; 802 uint32_t val; 803 bus_addr_t addr; 804 805 ASSERT_SERIALIZED(ifp->if_serializer); 806 807 mii = device_get_softc(sc->ae_miibus); 808 ae_stop(sc); 809 ae_reset(sc); 810 ae_pcie_init(sc); 811 ae_powersave_disable(sc); 812 813 /* 814 * Clear and disable interrupts. 815 */ 816 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff); 817 818 /* 819 * Set the MAC address. 820 */ 821 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 822 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]; 823 AE_WRITE_4(sc, AE_EADDR0_REG, val); 824 val = eaddr[0] << 8 | eaddr[1]; 825 AE_WRITE_4(sc, AE_EADDR1_REG, val); 826 827 /* 828 * Set ring buffers base addresses. 829 */ 830 addr = sc->dma_rxd_busaddr; 831 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr)); 832 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 833 addr = sc->dma_txd_busaddr; 834 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr)); 835 addr = sc->dma_txs_busaddr; 836 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr)); 837 838 /* 839 * Configure ring buffers sizes. 840 */ 841 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT); 842 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4); 843 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT); 844 845 /* 846 * Configure interframe gap parameters. 847 */ 848 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) & 849 AE_IFG_TXIPG_MASK) | 850 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) & 851 AE_IFG_RXIPG_MASK) | 852 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) & 853 AE_IFG_IPGR1_MASK) | 854 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) & 855 AE_IFG_IPGR2_MASK); 856 AE_WRITE_4(sc, AE_IFG_REG, val); 857 858 /* 859 * Configure half-duplex operation. 860 */ 861 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) & 862 AE_HDPX_LCOL_MASK) | 863 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) & 864 AE_HDPX_RETRY_MASK) | 865 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) & 866 AE_HDPX_ABEBT_MASK) | 867 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) & 868 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN; 869 AE_WRITE_4(sc, AE_HDPX_REG, val); 870 871 /* 872 * Configure interrupt moderate timer. 873 */ 874 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT); 875 val = AE_READ_4(sc, AE_MASTER_REG); 876 val |= AE_MASTER_IMT_EN; 877 AE_WRITE_4(sc, AE_MASTER_REG, val); 878 879 /* 880 * Configure interrupt clearing timer. 881 */ 882 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT); 883 884 /* 885 * Configure MTU. 886 */ 887 val = ifp->if_mtu + ETHER_HDR_LEN + sizeof(struct ether_vlan_header) + 888 ETHER_CRC_LEN; 889 AE_WRITE_2(sc, AE_MTU_REG, val); 890 891 /* 892 * Configure cut-through threshold. 893 */ 894 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT); 895 896 /* 897 * Configure flow control. 898 */ 899 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7); 900 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) > 901 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) : 902 (AE_RXD_COUNT_DEFAULT / 12)); 903 904 /* 905 * Init mailboxes. 906 */ 907 sc->txd_cur = sc->rxd_cur = 0; 908 sc->txs_ack = sc->txd_ack = 0; 909 sc->rxd_cur = 0; 910 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur); 911 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur); 912 sc->tx_inproc = 0; 913 sc->ae_flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */ 914 915 /* 916 * Enable DMA. 917 */ 918 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN); 919 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN); 920 921 /* 922 * Check if everything is OK. 923 */ 924 val = AE_READ_4(sc, AE_ISR_REG); 925 if ((val & AE_ISR_PHY_LINKDOWN) != 0) { 926 device_printf(sc->ae_dev, "Initialization failed.\n"); 927 return; 928 } 929 930 /* 931 * Clear interrupt status. 932 */ 933 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff); 934 AE_WRITE_4(sc, AE_ISR_REG, 0x0); 935 936 /* 937 * Enable interrupts. 938 */ 939 val = AE_READ_4(sc, AE_MASTER_REG); 940 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT); 941 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT); 942 943 /* 944 * Disable WOL. 945 */ 946 AE_WRITE_4(sc, AE_WOL_REG, 0); 947 948 /* 949 * Configure MAC. 950 */ 951 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | 952 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY | 953 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN | 954 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) | 955 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) & 956 AE_MAC_PREAMBLE_MASK); 957 AE_WRITE_4(sc, AE_MAC_REG, val); 958 959 /* 960 * Configure Rx MAC. 961 */ 962 ae_rxfilter(sc); 963 ae_rxvlan(sc); 964 965 /* 966 * Enable Tx/Rx. 967 */ 968 val = AE_READ_4(sc, AE_MAC_REG); 969 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN); 970 971 sc->ae_flags &= ~AE_FLAG_LINK; 972 mii_mediachg(mii); /* Switch to the current media. */ 973 974 callout_reset(&sc->ae_tick_ch, hz, ae_tick, sc); 975 ifp->if_flags |= IFF_RUNNING; 976 ifp->if_flags &= ~IFF_OACTIVE; 977 } 978 979 static void 980 ae_watchdog(struct ifnet *ifp) 981 { 982 struct ae_softc *sc = ifp->if_softc; 983 984 ASSERT_SERIALIZED(ifp->if_serializer); 985 986 if ((sc->ae_flags & AE_FLAG_LINK) == 0) 987 if_printf(ifp, "watchdog timeout (missed link).\n"); 988 else 989 if_printf(ifp, "watchdog timeout - resetting.\n"); 990 ifp->if_oerrors++; 991 992 ae_init(sc); 993 if (!ifq_is_empty(&ifp->if_snd)) 994 if_devstart(ifp); 995 } 996 997 static void 998 ae_tick(void *xsc) 999 { 1000 struct ae_softc *sc = xsc; 1001 struct ifnet *ifp = &sc->arpcom.ac_if; 1002 struct mii_data *mii = device_get_softc(sc->ae_miibus); 1003 1004 lwkt_serialize_enter(ifp->if_serializer); 1005 mii_tick(mii); 1006 callout_reset(&sc->ae_tick_ch, hz, ae_tick, sc); 1007 lwkt_serialize_exit(ifp->if_serializer); 1008 } 1009 1010 static void 1011 ae_rxvlan(struct ae_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->arpcom.ac_if; 1014 uint32_t val; 1015 1016 val = AE_READ_4(sc, AE_MAC_REG); 1017 val &= ~AE_MAC_RMVLAN_EN; 1018 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1019 val |= AE_MAC_RMVLAN_EN; 1020 AE_WRITE_4(sc, AE_MAC_REG, val); 1021 } 1022 1023 static void 1024 ae_rxfilter(struct ae_softc *sc) 1025 { 1026 struct ifnet *ifp = &sc->arpcom.ac_if; 1027 struct ifmultiaddr *ifma; 1028 uint32_t crc; 1029 uint32_t mchash[2]; 1030 uint32_t rxcfg; 1031 1032 rxcfg = AE_READ_4(sc, AE_MAC_REG); 1033 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN); 1034 rxcfg |= AE_MAC_BCAST_EN; 1035 if (ifp->if_flags & IFF_PROMISC) 1036 rxcfg |= AE_MAC_PROMISC_EN; 1037 if (ifp->if_flags & IFF_ALLMULTI) 1038 rxcfg |= AE_MAC_MCAST_EN; 1039 1040 /* 1041 * Wipe old settings. 1042 */ 1043 AE_WRITE_4(sc, AE_REG_MHT0, 0); 1044 AE_WRITE_4(sc, AE_REG_MHT1, 0); 1045 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1046 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff); 1047 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff); 1048 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 1049 return; 1050 } 1051 1052 /* 1053 * Load multicast tables. 1054 */ 1055 bzero(mchash, sizeof(mchash)); 1056 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1057 if (ifma->ifma_addr->sa_family != AF_LINK) 1058 continue; 1059 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1060 ifma->ifma_addr), ETHER_ADDR_LEN); 1061 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 1062 } 1063 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]); 1064 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]); 1065 AE_WRITE_4(sc, AE_MAC_REG, rxcfg); 1066 } 1067 1068 static unsigned int 1069 ae_tx_avail_size(struct ae_softc *sc) 1070 { 1071 unsigned int avail; 1072 1073 if (sc->txd_cur >= sc->txd_ack) 1074 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack); 1075 else 1076 avail = sc->txd_ack - sc->txd_cur; 1077 return (avail - 4); /* 4-byte header. */ 1078 } 1079 1080 static int 1081 ae_encap(struct ae_softc *sc, struct mbuf **m_head) 1082 { 1083 struct mbuf *m0; 1084 struct ae_txd *hdr; 1085 unsigned int to_end; 1086 uint16_t len; 1087 1088 M_ASSERTPKTHDR((*m_head)); 1089 m0 = *m_head; 1090 len = m0->m_pkthdr.len; 1091 if ((sc->ae_flags & AE_FLAG_TXAVAIL) == 0 || 1092 ae_tx_avail_size(sc) < len) { 1093 #ifdef AE_DEBUG 1094 if_printf(sc->ifp, "No free Tx available.\n"); 1095 #endif 1096 return ENOBUFS; 1097 } 1098 1099 hdr = (struct ae_txd *)(sc->txd_base + sc->txd_cur); 1100 bzero(hdr, sizeof(*hdr)); 1101 1102 /* Header size. */ 1103 sc->txd_cur = (sc->txd_cur + 4) % AE_TXD_BUFSIZE_DEFAULT; 1104 1105 /* Space available to the end of the ring */ 1106 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur; 1107 1108 if (to_end >= len) { 1109 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur)); 1110 } else { 1111 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base + 1112 sc->txd_cur)); 1113 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base); 1114 } 1115 1116 /* 1117 * Set TxD flags and parameters. 1118 */ 1119 if ((m0->m_flags & M_VLANTAG) != 0) { 1120 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vlantag)); 1121 hdr->len = htole16(len | AE_TXD_INSERT_VTAG); 1122 } else { 1123 hdr->len = htole16(len); 1124 } 1125 1126 /* 1127 * Set current TxD position and round up to a 4-byte boundary. 1128 */ 1129 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT; 1130 if (sc->txd_cur == sc->txd_ack) 1131 sc->ae_flags &= ~AE_FLAG_TXAVAIL; 1132 #ifdef AE_DEBUG 1133 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur); 1134 #endif 1135 1136 /* 1137 * Update TxS position and check if there are empty TxS available. 1138 */ 1139 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE); 1140 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT; 1141 if (sc->txs_cur == sc->txs_ack) 1142 sc->ae_flags &= ~AE_FLAG_TXAVAIL; 1143 1144 /* 1145 * Synchronize DMA memory. 1146 */ 1147 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREWRITE); 1148 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map, BUS_DMASYNC_PREWRITE); 1149 1150 return (0); 1151 } 1152 1153 static void 1154 ae_start(struct ifnet *ifp) 1155 { 1156 struct ae_softc *sc = ifp->if_softc; 1157 int error, trans; 1158 1159 ASSERT_SERIALIZED(ifp->if_serializer); 1160 1161 #ifdef AE_DEBUG 1162 if_printf(ifp, "Start called.\n"); 1163 #endif 1164 if ((sc->ae_flags & AE_FLAG_LINK) == 0) { 1165 ifq_purge(&ifp->if_snd); 1166 return; 1167 } 1168 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1169 return; 1170 1171 trans = 0; 1172 while (!ifq_is_empty(&ifp->if_snd)) { 1173 struct mbuf *m0; 1174 1175 m0 = ifq_dequeue(&ifp->if_snd, NULL); 1176 if (m0 == NULL) 1177 break; /* Nothing to do. */ 1178 1179 error = ae_encap(sc, &m0); 1180 if (error != 0) { 1181 if (m0 != NULL) { 1182 ifq_prepend(&ifp->if_snd, m0); 1183 ifp->if_flags |= IFF_OACTIVE; 1184 #ifdef AE_DEBUG 1185 if_printf(ifp, "Setting OACTIVE.\n"); 1186 #endif 1187 } 1188 break; 1189 } 1190 trans = 1; 1191 sc->tx_inproc++; 1192 1193 /* Bounce a copy of the frame to BPF. */ 1194 ETHER_BPF_MTAP(ifp, m0); 1195 m_freem(m0); 1196 } 1197 if (trans) { /* Something was dequeued. */ 1198 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4); 1199 ifp->if_timer = AE_TX_TIMEOUT; /* Load watchdog. */ 1200 #ifdef AE_DEBUG 1201 if_printf(ifp, "%d packets dequeued.\n", count); 1202 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur); 1203 #endif 1204 } 1205 } 1206 1207 static int 1208 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1209 { 1210 struct ae_softc *sc = ifp->if_softc; 1211 struct ifreq *ifr; 1212 struct mii_data *mii; 1213 int error = 0, mask; 1214 1215 ASSERT_SERIALIZED(ifp->if_serializer); 1216 1217 ifr = (struct ifreq *)data; 1218 switch (cmd) { 1219 case SIOCSIFFLAGS: 1220 if (ifp->if_flags & IFF_UP) { 1221 if (ifp->if_flags & IFF_RUNNING) { 1222 if (((ifp->if_flags ^ sc->ae_if_flags) 1223 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1224 ae_rxfilter(sc); 1225 } else { 1226 ae_init(sc); 1227 } 1228 } else { 1229 if (ifp->if_flags & IFF_RUNNING) 1230 ae_stop(sc); 1231 } 1232 sc->ae_if_flags = ifp->if_flags; 1233 break; 1234 1235 case SIOCADDMULTI: 1236 case SIOCDELMULTI: 1237 if (ifp->if_flags & IFF_RUNNING) 1238 ae_rxfilter(sc); 1239 break; 1240 1241 case SIOCSIFMEDIA: 1242 case SIOCGIFMEDIA: 1243 mii = device_get_softc(sc->ae_miibus); 1244 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1245 break; 1246 1247 case SIOCSIFCAP: 1248 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1249 if (mask & IFCAP_VLAN_HWTAGGING) { 1250 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1251 ae_rxvlan(sc); 1252 } 1253 break; 1254 1255 default: 1256 error = ether_ioctl(ifp, cmd, data); 1257 break; 1258 } 1259 return (error); 1260 } 1261 1262 static int 1263 ae_attach(device_t dev) 1264 { 1265 struct ae_softc *sc = device_get_softc(dev); 1266 struct ifnet *ifp = &sc->arpcom.ac_if; 1267 int error = 0; 1268 1269 sc->ae_dev = dev; 1270 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1271 callout_init(&sc->ae_tick_ch); 1272 1273 /* Enable bus mastering */ 1274 pci_enable_busmaster(dev); 1275 1276 /* 1277 * Allocate memory mapped IO 1278 */ 1279 sc->ae_mem_rid = PCIR_BAR(0); 1280 sc->ae_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1281 &sc->ae_mem_rid, RF_ACTIVE); 1282 if (sc->ae_mem_res == NULL) { 1283 device_printf(dev, "can't allocate IO memory\n"); 1284 return ENXIO; 1285 } 1286 sc->ae_mem_bt = rman_get_bustag(sc->ae_mem_res); 1287 sc->ae_mem_bh = rman_get_bushandle(sc->ae_mem_res); 1288 1289 /* 1290 * Allocate IRQ 1291 */ 1292 sc->ae_irq_rid = 0; 1293 sc->ae_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1294 &sc->ae_irq_rid, 1295 RF_SHAREABLE | RF_ACTIVE); 1296 if (sc->ae_irq_res == NULL) { 1297 device_printf(dev, "can't allocate irq\n"); 1298 error = ENXIO; 1299 goto fail; 1300 } 1301 1302 /* Set PHY address. */ 1303 sc->ae_phyaddr = AE_PHYADDR_DEFAULT; 1304 1305 /* Create sysctl tree */ 1306 ae_sysctl_node(sc); 1307 1308 /* Reset PHY. */ 1309 ae_phy_reset(sc); 1310 1311 /* 1312 * Reset the ethernet controller. 1313 */ 1314 ae_reset(sc); 1315 ae_pcie_init(sc); 1316 1317 /* 1318 * Get PCI and chip id/revision. 1319 */ 1320 sc->ae_rev = pci_get_revid(dev); 1321 sc->ae_chip_rev = 1322 (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) & 1323 AE_MASTER_REVNUM_MASK; 1324 if (bootverbose) { 1325 device_printf(dev, "PCI device revision : 0x%04x\n", sc->ae_rev); 1326 device_printf(dev, "Chip id/revision : 0x%04x\n", 1327 sc->ae_chip_rev); 1328 } 1329 1330 /* 1331 * XXX 1332 * Unintialized hardware returns an invalid chip id/revision 1333 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 1334 * unplugged cable results in putting hardware into automatic 1335 * power down mode which in turn returns invalld chip revision. 1336 */ 1337 if (sc->ae_chip_rev == 0xFFFF) { 1338 device_printf(dev,"invalid chip revision : 0x%04x -- " 1339 "not initialized?\n", sc->ae_chip_rev); 1340 error = ENXIO; 1341 goto fail; 1342 } 1343 #if 0 1344 /* Get DMA parameters from PCIe device control register. */ 1345 pcie_ptr = pci_get_pciecap_ptr(dev); 1346 if (pcie_ptr) { 1347 uint16_t devctl; 1348 sc->ae_flags |= AE_FLAG_PCIE; 1349 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 1350 /* Max read request size. */ 1351 sc->ae_dma_rd_burst = ((devctl >> 12) & 0x07) << 1352 DMA_CFG_RD_BURST_SHIFT; 1353 /* Max payload size. */ 1354 sc->ae_dma_wr_burst = ((devctl >> 5) & 0x07) << 1355 DMA_CFG_WR_BURST_SHIFT; 1356 if (bootverbose) { 1357 device_printf(dev, "Read request size : %d bytes.\n", 1358 128 << ((devctl >> 12) & 0x07)); 1359 device_printf(dev, "TLP payload size : %d bytes.\n", 1360 128 << ((devctl >> 5) & 0x07)); 1361 } 1362 } else { 1363 sc->ae_dma_rd_burst = DMA_CFG_RD_BURST_128; 1364 sc->ae_dma_wr_burst = DMA_CFG_WR_BURST_128; 1365 } 1366 #endif 1367 1368 /* Create DMA stuffs */ 1369 error = ae_dma_alloc(sc); 1370 if (error) 1371 goto fail; 1372 1373 /* Load station address. */ 1374 ae_get_eaddr(sc); 1375 1376 ifp->if_softc = sc; 1377 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1378 ifp->if_ioctl = ae_ioctl; 1379 ifp->if_start = ae_start; 1380 ifp->if_init = ae_init; 1381 ifp->if_watchdog = ae_watchdog; 1382 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN - 1); 1383 ifq_set_ready(&ifp->if_snd); 1384 ifp->if_capabilities = IFCAP_VLAN_MTU | 1385 IFCAP_VLAN_HWTAGGING; 1386 ifp->if_hwassist = 0; 1387 ifp->if_capenable = ifp->if_capabilities; 1388 1389 /* Set up MII bus. */ 1390 error = mii_phy_probe(dev, &sc->ae_miibus, 1391 ae_mediachange, ae_mediastatus); 1392 if (error) { 1393 device_printf(dev, "no PHY found!\n"); 1394 goto fail; 1395 } 1396 ether_ifattach(ifp, sc->ae_eaddr, NULL); 1397 1398 /* Tell the upper layer(s) we support long frames. */ 1399 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1400 1401 error = bus_setup_intr(dev, sc->ae_irq_res, INTR_MPSAFE, ae_intr, sc, 1402 &sc->ae_irq_handle, ifp->if_serializer); 1403 if (error) { 1404 device_printf(dev, "could not set up interrupt handler.\n"); 1405 ether_ifdetach(ifp); 1406 goto fail; 1407 } 1408 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->ae_irq_res)); 1409 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 1410 return 0; 1411 fail: 1412 ae_detach(dev); 1413 return (error); 1414 } 1415 1416 static int 1417 ae_detach(device_t dev) 1418 { 1419 struct ae_softc *sc = device_get_softc(dev); 1420 1421 if (device_is_attached(dev)) { 1422 struct ifnet *ifp = &sc->arpcom.ac_if; 1423 1424 lwkt_serialize_enter(ifp->if_serializer); 1425 sc->ae_flags |= AE_FLAG_DETACH; 1426 ae_stop(sc); 1427 bus_teardown_intr(dev, sc->ae_irq_res, sc->ae_irq_handle); 1428 lwkt_serialize_exit(ifp->if_serializer); 1429 1430 ether_ifdetach(ifp); 1431 } 1432 1433 if (sc->ae_miibus != NULL) 1434 device_delete_child(dev, sc->ae_miibus); 1435 bus_generic_detach(dev); 1436 1437 if (sc->ae_irq_res != NULL) { 1438 bus_release_resource(dev, SYS_RES_IRQ, sc->ae_irq_rid, 1439 sc->ae_irq_res); 1440 } 1441 if (sc->ae_mem_res != NULL) { 1442 bus_release_resource(dev, SYS_RES_MEMORY, sc->ae_mem_rid, 1443 sc->ae_mem_res); 1444 } 1445 1446 if (sc->ae_sysctl_tree != NULL) 1447 sysctl_ctx_free(&sc->ae_sysctl_ctx); 1448 1449 ae_dma_free(sc); 1450 1451 return (0); 1452 } 1453 1454 static void 1455 ae_dma_free(struct ae_softc *sc) 1456 { 1457 if (sc->dma_txd_tag != NULL) { 1458 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map); 1459 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base, 1460 sc->dma_txd_map); 1461 bus_dma_tag_destroy(sc->dma_txd_tag); 1462 } 1463 if (sc->dma_txs_tag != NULL) { 1464 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map); 1465 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base, 1466 sc->dma_txs_map); 1467 bus_dma_tag_destroy(sc->dma_txs_tag); 1468 } 1469 if (sc->dma_rxd_tag != NULL) { 1470 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map); 1471 bus_dmamem_free(sc->dma_rxd_tag, 1472 sc->rxd_base_dma, sc->dma_rxd_map); 1473 bus_dma_tag_destroy(sc->dma_rxd_tag); 1474 } 1475 if (sc->dma_parent_tag != NULL) 1476 bus_dma_tag_destroy(sc->dma_parent_tag); 1477 } 1478 1479 static void 1480 ae_pcie_init(struct ae_softc *sc) 1481 { 1482 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, 1483 AE_PCIE_LTSSM_TESTMODE_DEFAULT); 1484 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, 1485 AE_PCIE_DLL_TX_CTRL_DEFAULT); 1486 } 1487 1488 static void 1489 ae_phy_reset(struct ae_softc *sc) 1490 { 1491 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE); 1492 DELAY(1000); /* XXX: pause(9) ? */ 1493 } 1494 1495 static int 1496 ae_reset(struct ae_softc *sc) 1497 { 1498 int i; 1499 1500 /* 1501 * Issue a soft reset. 1502 */ 1503 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET); 1504 bus_space_barrier(sc->ae_mem_bt, sc->ae_mem_bh, AE_MASTER_REG, 4, 1505 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1506 1507 /* 1508 * Wait for reset to complete. 1509 */ 1510 for (i = 0; i < AE_RESET_TIMEOUT; i++) { 1511 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0) 1512 break; 1513 DELAY(10); 1514 } 1515 if (i == AE_RESET_TIMEOUT) { 1516 device_printf(sc->ae_dev, "reset timeout.\n"); 1517 return (ENXIO); 1518 } 1519 1520 /* 1521 * Wait for everything to enter idle state. 1522 */ 1523 for (i = 0; i < AE_IDLE_TIMEOUT; i++) { 1524 if (AE_READ_4(sc, AE_IDLE_REG) == 0) 1525 break; 1526 DELAY(100); 1527 } 1528 if (i == AE_IDLE_TIMEOUT) { 1529 device_printf(sc->ae_dev, "could not enter idle state.\n"); 1530 return (ENXIO); 1531 } 1532 return (0); 1533 } 1534 1535 static int 1536 ae_check_eeprom_present(struct ae_softc *sc, int *vpdc) 1537 { 1538 int error; 1539 uint32_t val; 1540 1541 /* 1542 * Not sure why, but Linux does this. 1543 */ 1544 val = AE_READ_4(sc, AE_SPICTL_REG); 1545 if ((val & AE_SPICTL_VPD_EN) != 0) { 1546 val &= ~AE_SPICTL_VPD_EN; 1547 AE_WRITE_4(sc, AE_SPICTL_REG, val); 1548 } 1549 error = pci_find_extcap(sc->ae_dev, PCIY_VPD, vpdc); 1550 return (error); 1551 } 1552 1553 static int 1554 ae_vpd_read_word(struct ae_softc *sc, int reg, uint32_t *word) 1555 { 1556 uint32_t val; 1557 int i; 1558 1559 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */ 1560 1561 /* 1562 * VPD registers start at offset 0x100. Read them. 1563 */ 1564 val = 0x100 + reg * 4; 1565 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) & 1566 AE_VPD_CAP_ADDR_MASK); 1567 for (i = 0; i < AE_VPD_TIMEOUT; i++) { 1568 DELAY(2000); 1569 val = AE_READ_4(sc, AE_VPD_CAP_REG); 1570 if ((val & AE_VPD_CAP_DONE) != 0) 1571 break; 1572 } 1573 if (i == AE_VPD_TIMEOUT) { 1574 device_printf(sc->ae_dev, "timeout reading VPD register %d.\n", 1575 reg); 1576 return (ETIMEDOUT); 1577 } 1578 *word = AE_READ_4(sc, AE_VPD_DATA_REG); 1579 return (0); 1580 } 1581 1582 static int 1583 ae_get_vpd_eaddr(struct ae_softc *sc, uint32_t *eaddr) 1584 { 1585 uint32_t word, reg, val; 1586 int error; 1587 int found; 1588 int vpdc; 1589 int i; 1590 1591 /* 1592 * Check for EEPROM. 1593 */ 1594 error = ae_check_eeprom_present(sc, &vpdc); 1595 if (error != 0) 1596 return (error); 1597 1598 /* 1599 * Read the VPD configuration space. 1600 * Each register is prefixed with signature, 1601 * so we can check if it is valid. 1602 */ 1603 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) { 1604 error = ae_vpd_read_word(sc, i, &word); 1605 if (error != 0) 1606 break; 1607 1608 /* 1609 * Check signature. 1610 */ 1611 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG) 1612 break; 1613 reg = word >> AE_VPD_REG_SHIFT; 1614 i++; /* Move to the next word. */ 1615 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG) 1616 continue; 1617 1618 error = ae_vpd_read_word(sc, i, &val); 1619 if (error != 0) 1620 break; 1621 if (reg == AE_EADDR0_REG) 1622 eaddr[0] = val; 1623 else 1624 eaddr[1] = val; 1625 found++; 1626 } 1627 if (found < 2) 1628 return (ENOENT); 1629 1630 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1631 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1632 if (bootverbose) 1633 device_printf(sc->ae_dev, 1634 "VPD ethernet address registers are invalid.\n"); 1635 return (EINVAL); 1636 } 1637 return (0); 1638 } 1639 1640 static int 1641 ae_get_reg_eaddr(struct ae_softc *sc, uint32_t *eaddr) 1642 { 1643 /* 1644 * BIOS is supposed to set this. 1645 */ 1646 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG); 1647 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG); 1648 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */ 1649 if (AE_CHECK_EADDR_VALID(eaddr) != 0) { 1650 if (bootverbose) 1651 device_printf(sc->ae_dev, 1652 "Ethetnet address registers are invalid.\n"); 1653 return (EINVAL); 1654 } 1655 return (0); 1656 } 1657 1658 static void 1659 ae_get_eaddr(struct ae_softc *sc) 1660 { 1661 uint32_t eaddr[2] = {0, 0}; 1662 int error; 1663 1664 /* 1665 *Check for EEPROM. 1666 */ 1667 error = ae_get_vpd_eaddr(sc, eaddr); 1668 if (error) 1669 error = ae_get_reg_eaddr(sc, eaddr); 1670 if (error) { 1671 if (bootverbose) 1672 device_printf(sc->ae_dev, 1673 "Generating random ethernet address.\n"); 1674 eaddr[0] = karc4random(); 1675 /* 1676 * Set OUI to ASUSTek COMPUTER INC. 1677 */ 1678 sc->ae_eaddr[0] = 0x02; /* U/L bit set. */ 1679 sc->ae_eaddr[1] = 0x1f; 1680 sc->ae_eaddr[2] = 0xc6; 1681 sc->ae_eaddr[3] = (eaddr[0] >> 16) & 0xff; 1682 sc->ae_eaddr[4] = (eaddr[0] >> 8) & 0xff; 1683 sc->ae_eaddr[5] = (eaddr[0] >> 0) & 0xff; 1684 } else { 1685 sc->ae_eaddr[0] = (eaddr[1] >> 8) & 0xff; 1686 sc->ae_eaddr[1] = (eaddr[1] >> 0) & 0xff; 1687 sc->ae_eaddr[2] = (eaddr[0] >> 24) & 0xff; 1688 sc->ae_eaddr[3] = (eaddr[0] >> 16) & 0xff; 1689 sc->ae_eaddr[4] = (eaddr[0] >> 8) & 0xff; 1690 sc->ae_eaddr[5] = (eaddr[0] >> 0) & 0xff; 1691 } 1692 } 1693 1694 static int 1695 ae_mediachange(struct ifnet *ifp) 1696 { 1697 struct ae_softc *sc = ifp->if_softc; 1698 struct mii_data *mii = device_get_softc(sc->ae_miibus); 1699 int error; 1700 1701 ASSERT_SERIALIZED(ifp->if_serializer); 1702 if (mii->mii_instance != 0) { 1703 struct mii_softc *miisc; 1704 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1705 mii_phy_reset(miisc); 1706 } 1707 error = mii_mediachg(mii); 1708 return (error); 1709 } 1710 1711 static void 1712 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1713 { 1714 struct ae_softc *sc = ifp->if_softc; 1715 struct mii_data *mii = device_get_softc(sc->ae_miibus); 1716 1717 ASSERT_SERIALIZED(ifp->if_serializer); 1718 mii_pollstat(mii); 1719 ifmr->ifm_status = mii->mii_media_status; 1720 ifmr->ifm_active = mii->mii_media_active; 1721 } 1722 1723 static void 1724 ae_update_stats_tx(uint16_t flags, struct ae_stats *stats) 1725 { 1726 if ((flags & AE_TXS_BCAST) != 0) 1727 stats->tx_bcast++; 1728 if ((flags & AE_TXS_MCAST) != 0) 1729 stats->tx_mcast++; 1730 if ((flags & AE_TXS_PAUSE) != 0) 1731 stats->tx_pause++; 1732 if ((flags & AE_TXS_CTRL) != 0) 1733 stats->tx_ctrl++; 1734 if ((flags & AE_TXS_DEFER) != 0) 1735 stats->tx_defer++; 1736 if ((flags & AE_TXS_EXCDEFER) != 0) 1737 stats->tx_excdefer++; 1738 if ((flags & AE_TXS_SINGLECOL) != 0) 1739 stats->tx_singlecol++; 1740 if ((flags & AE_TXS_MULTICOL) != 0) 1741 stats->tx_multicol++; 1742 if ((flags & AE_TXS_LATECOL) != 0) 1743 stats->tx_latecol++; 1744 if ((flags & AE_TXS_ABORTCOL) != 0) 1745 stats->tx_abortcol++; 1746 if ((flags & AE_TXS_UNDERRUN) != 0) 1747 stats->tx_underrun++; 1748 } 1749 1750 static void 1751 ae_update_stats_rx(uint16_t flags, struct ae_stats *stats) 1752 { 1753 if ((flags & AE_RXD_BCAST) != 0) 1754 stats->rx_bcast++; 1755 if ((flags & AE_RXD_MCAST) != 0) 1756 stats->rx_mcast++; 1757 if ((flags & AE_RXD_PAUSE) != 0) 1758 stats->rx_pause++; 1759 if ((flags & AE_RXD_CTRL) != 0) 1760 stats->rx_ctrl++; 1761 if ((flags & AE_RXD_CRCERR) != 0) 1762 stats->rx_crcerr++; 1763 if ((flags & AE_RXD_CODEERR) != 0) 1764 stats->rx_codeerr++; 1765 if ((flags & AE_RXD_RUNT) != 0) 1766 stats->rx_runt++; 1767 if ((flags & AE_RXD_FRAG) != 0) 1768 stats->rx_frag++; 1769 if ((flags & AE_RXD_TRUNC) != 0) 1770 stats->rx_trunc++; 1771 if ((flags & AE_RXD_ALIGN) != 0) 1772 stats->rx_align++; 1773 } 1774 1775 static int 1776 ae_resume(device_t dev) 1777 { 1778 struct ae_softc *sc = device_get_softc(dev); 1779 struct ifnet *ifp = &sc->arpcom.ac_if; 1780 1781 lwkt_serialize_enter(ifp->if_serializer); 1782 #if 0 1783 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */ 1784 #endif 1785 ae_phy_reset(sc); 1786 if ((ifp->if_flags & IFF_UP) != 0) 1787 ae_init(sc); 1788 lwkt_serialize_exit(ifp->if_serializer); 1789 return (0); 1790 } 1791 1792 static int 1793 ae_suspend(device_t dev) 1794 { 1795 struct ae_softc *sc = device_get_softc(dev); 1796 struct ifnet *ifp = &sc->arpcom.ac_if; 1797 1798 lwkt_serialize_enter(ifp->if_serializer); 1799 ae_stop(sc); 1800 #if 0 1801 /* we don't use ae_pm_init because we don't want WOL */ 1802 ae_pm_init(sc); 1803 #endif 1804 lwkt_serialize_exit(ifp->if_serializer); 1805 return (0); 1806 } 1807 1808 static int 1809 ae_shutdown(device_t dev) 1810 { 1811 struct ae_softc *sc = device_get_softc(dev); 1812 struct ifnet *ifp = &sc->arpcom.ac_if; 1813 1814 ae_suspend(dev); 1815 1816 lwkt_serialize_enter(ifp->if_serializer); 1817 ae_powersave_enable(sc); 1818 lwkt_serialize_exit(ifp->if_serializer); 1819 1820 return (0); 1821 } 1822 1823 static void 1824 ae_powersave_disable(struct ae_softc *sc) 1825 { 1826 uint32_t val; 1827 1828 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1829 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1830 if (val & AE_PHY_DBG_POWERSAVE) { 1831 val &= ~AE_PHY_DBG_POWERSAVE; 1832 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val); 1833 DELAY(1000); 1834 } 1835 } 1836 1837 static void 1838 ae_powersave_enable(struct ae_softc *sc) 1839 { 1840 uint32_t val; 1841 1842 /* 1843 * XXX magic numbers. 1844 */ 1845 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0); 1846 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA); 1847 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000); 1848 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2); 1849 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000); 1850 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3); 1851 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0); 1852 } 1853