1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/age/if_age.c,v 1.6 2008/11/07 07:02:28 yongari Exp $ 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/interrupt.h> 37 #include <sys/malloc.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/serialize.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/bpf.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/ifq_var.h> 52 #include <net/vlan/if_vlan_var.h> 53 #include <net/vlan/if_vlan_ether.h> 54 55 #include <dev/netif/mii_layer/miivar.h> 56 #include <dev/netif/mii_layer/jmphyreg.h> 57 58 #include <bus/pci/pcireg.h> 59 #include <bus/pci/pcivar.h> 60 #include <bus/pci/pcidevs.h> 61 62 #include <dev/netif/age/if_agereg.h> 63 #include <dev/netif/age/if_agevar.h> 64 65 /* "device miibus" required. See GENERIC if you get errors here. */ 66 #include "miibus_if.h" 67 68 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 69 70 struct age_dmamap_ctx { 71 int nsegs; 72 bus_dma_segment_t *segs; 73 }; 74 75 static int age_probe(device_t); 76 static int age_attach(device_t); 77 static int age_detach(device_t); 78 static int age_shutdown(device_t); 79 static int age_suspend(device_t); 80 static int age_resume(device_t); 81 82 static int age_miibus_readreg(device_t, int, int); 83 static int age_miibus_writereg(device_t, int, int, int); 84 static void age_miibus_statchg(device_t); 85 86 static void age_init(void *); 87 static int age_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 88 static void age_start(struct ifnet *); 89 static void age_watchdog(struct ifnet *); 90 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 91 static int age_mediachange(struct ifnet *); 92 93 static void age_intr(void *); 94 static void age_txintr(struct age_softc *, int); 95 static void age_rxintr(struct age_softc *, int); 96 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 97 98 static int age_dma_alloc(struct age_softc *); 99 static void age_dma_free(struct age_softc *); 100 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 101 static void age_dmamap_buf_cb(void *, bus_dma_segment_t *, int, 102 bus_size_t, int); 103 static int age_check_boundary(struct age_softc *); 104 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 105 static int age_encap(struct age_softc *, struct mbuf **); 106 static void age_init_tx_ring(struct age_softc *); 107 static int age_init_rx_ring(struct age_softc *); 108 static void age_init_rr_ring(struct age_softc *); 109 static void age_init_cmb_block(struct age_softc *); 110 static void age_init_smb_block(struct age_softc *); 111 112 static void age_tick(void *); 113 static void age_stop(struct age_softc *); 114 static void age_reset(struct age_softc *); 115 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, 116 uint32_t *); 117 static void age_get_macaddr(struct age_softc *); 118 static void age_phy_reset(struct age_softc *); 119 static void age_mac_config(struct age_softc *); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *); 124 static void age_rxfilter(struct age_softc *); 125 #ifdef wol_notyet 126 static void age_setwol(struct age_softc *); 127 #endif 128 129 static void age_sysctl_node(struct age_softc *); 130 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 131 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 132 133 /* 134 * Devices supported by this driver. 135 */ 136 static struct age_dev { 137 uint16_t age_vendorid; 138 uint16_t age_deviceid; 139 const char *age_name; 140 } age_devs[] = { 141 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 142 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 143 }; 144 145 static device_method_t age_methods[] = { 146 /* Device interface. */ 147 DEVMETHOD(device_probe, age_probe), 148 DEVMETHOD(device_attach, age_attach), 149 DEVMETHOD(device_detach, age_detach), 150 DEVMETHOD(device_shutdown, age_shutdown), 151 DEVMETHOD(device_suspend, age_suspend), 152 DEVMETHOD(device_resume, age_resume), 153 154 /* Bus interface. */ 155 DEVMETHOD(bus_print_child, bus_generic_print_child), 156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 157 158 /* MII interface. */ 159 DEVMETHOD(miibus_readreg, age_miibus_readreg), 160 DEVMETHOD(miibus_writereg, age_miibus_writereg), 161 DEVMETHOD(miibus_statchg, age_miibus_statchg), 162 163 { NULL, NULL } 164 }; 165 166 static driver_t age_driver = { 167 "age", 168 age_methods, 169 sizeof(struct age_softc) 170 }; 171 172 static devclass_t age_devclass; 173 174 DECLARE_DUMMY_MODULE(if_age); 175 MODULE_DEPEND(if_age, miibus, 1, 1, 1); 176 DRIVER_MODULE(if_age, pci, age_driver, age_devclass, 0, 0); 177 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 178 179 /* 180 * Read a PHY register on the MII of the L1. 181 */ 182 static int 183 age_miibus_readreg(device_t dev, int phy, int reg) 184 { 185 struct age_softc *sc; 186 uint32_t v; 187 int i; 188 189 sc = device_get_softc(dev); 190 if (phy != sc->age_phyaddr) 191 return (0); 192 193 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 194 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 195 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 196 DELAY(1); 197 v = CSR_READ_4(sc, AGE_MDIO); 198 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 199 break; 200 } 201 202 if (i == 0) { 203 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 204 return (0); 205 } 206 207 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 208 } 209 210 /* 211 * Write a PHY register on the MII of the L1. 212 */ 213 static int 214 age_miibus_writereg(device_t dev, int phy, int reg, int val) 215 { 216 struct age_softc *sc; 217 uint32_t v; 218 int i; 219 220 sc = device_get_softc(dev); 221 if (phy != sc->age_phyaddr) 222 return (0); 223 224 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 225 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 226 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 227 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 228 DELAY(1); 229 v = CSR_READ_4(sc, AGE_MDIO); 230 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 231 break; 232 } 233 234 if (i == 0) 235 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 236 237 return (0); 238 } 239 240 /* 241 * Callback from MII layer when media changes. 242 */ 243 static void 244 age_miibus_statchg(device_t dev) 245 { 246 struct age_softc *sc = device_get_softc(dev); 247 struct ifnet *ifp = &sc->arpcom.ac_if; 248 struct mii_data *mii; 249 250 ASSERT_SERIALIZED(ifp->if_serializer); 251 252 if ((ifp->if_flags & IFF_RUNNING) == 0) 253 return; 254 255 mii = device_get_softc(sc->age_miibus); 256 257 sc->age_flags &= ~AGE_FLAG_LINK; 258 if ((mii->mii_media_status & IFM_AVALID) != 0) { 259 switch (IFM_SUBTYPE(mii->mii_media_active)) { 260 case IFM_10_T: 261 case IFM_100_TX: 262 case IFM_1000_T: 263 sc->age_flags |= AGE_FLAG_LINK; 264 break; 265 default: 266 break; 267 } 268 } 269 270 /* Stop Rx/Tx MACs. */ 271 age_stop_rxmac(sc); 272 age_stop_txmac(sc); 273 274 /* Program MACs with resolved speed/duplex/flow-control. */ 275 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 276 uint32_t reg; 277 278 age_mac_config(sc); 279 280 reg = CSR_READ_4(sc, AGE_MAC_CFG); 281 /* Restart DMA engine and Tx/Rx MAC. */ 282 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 283 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 284 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 285 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 286 } 287 } 288 289 /* 290 * Get the current interface media status. 291 */ 292 static void 293 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 294 { 295 struct age_softc *sc = ifp->if_softc; 296 struct mii_data *mii = device_get_softc(sc->age_miibus); 297 298 ASSERT_SERIALIZED(ifp->if_serializer); 299 300 mii_pollstat(mii); 301 ifmr->ifm_status = mii->mii_media_status; 302 ifmr->ifm_active = mii->mii_media_active; 303 } 304 305 /* 306 * Set hardware to newly-selected media. 307 */ 308 static int 309 age_mediachange(struct ifnet *ifp) 310 { 311 struct age_softc *sc = ifp->if_softc; 312 struct mii_data *mii = device_get_softc(sc->age_miibus); 313 int error; 314 315 ASSERT_SERIALIZED(ifp->if_serializer); 316 317 if (mii->mii_instance != 0) { 318 struct mii_softc *miisc; 319 320 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 321 mii_phy_reset(miisc); 322 } 323 error = mii_mediachg(mii); 324 325 return (error); 326 } 327 328 static int 329 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 330 uint32_t *word) 331 { 332 int i; 333 334 pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2); 335 for (i = AGE_TIMEOUT; i > 0; i--) { 336 DELAY(10); 337 if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) & 338 0x8000) == 0x8000) 339 break; 340 } 341 if (i == 0) { 342 device_printf(sc->age_dev, "VPD read timeout!\n"); 343 *word = 0; 344 return (ETIMEDOUT); 345 } 346 347 *word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4); 348 return (0); 349 } 350 351 static int 352 age_probe(device_t dev) 353 { 354 struct age_dev *sp; 355 int i; 356 uint16_t vendor, devid; 357 358 vendor = pci_get_vendor(dev); 359 devid = pci_get_device(dev); 360 sp = age_devs; 361 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 362 i++, sp++) { 363 if (vendor == sp->age_vendorid && 364 devid == sp->age_deviceid) { 365 device_set_desc(dev, sp->age_name); 366 return (0); 367 } 368 } 369 return (ENXIO); 370 } 371 372 static void 373 age_get_macaddr(struct age_softc *sc) 374 { 375 uint32_t ea[2], off, reg, word; 376 int vpd_error, match, vpdc; 377 378 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 379 if ((reg & SPI_VPD_ENB) != 0) { 380 /* Get VPD stored in TWSI EEPROM. */ 381 reg &= ~SPI_VPD_ENB; 382 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 383 } 384 385 ea[0] = ea[1] = 0; 386 vpdc = pci_get_vpdcap_ptr(sc->age_dev); 387 if (vpdc) { 388 vpd_error = 0; 389 390 /* 391 * PCI VPD capability exists, but it seems that it's 392 * not in the standard form as stated in PCI VPD 393 * specification such that driver could not use 394 * pci_get_vpd_readonly(9) with keyword 'NA'. 395 * Search VPD data starting at address 0x0100. The data 396 * should be used as initializers to set AGE_PAR0, 397 * AGE_PAR1 register including other PCI configuration 398 * registers. 399 */ 400 word = 0; 401 match = 0; 402 reg = 0; 403 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 404 off += sizeof(uint32_t)) { 405 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 406 if (vpd_error != 0) 407 break; 408 if (match != 0) { 409 switch (reg) { 410 case AGE_PAR0: 411 ea[0] = word; 412 break; 413 case AGE_PAR1: 414 ea[1] = word; 415 break; 416 default: 417 break; 418 } 419 match = 0; 420 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 421 match = 1; 422 reg = word >> 16; 423 } else 424 break; 425 } 426 if (off >= AGE_VPD_REG_CONF_END) 427 vpd_error = ENOENT; 428 if (vpd_error == 0) { 429 /* 430 * Don't blindly trust ethernet address obtained 431 * from VPD. Check whether ethernet address is 432 * valid one. Otherwise fall-back to reading 433 * PAR register. 434 */ 435 ea[1] &= 0xFFFF; 436 if ((ea[0] == 0 && ea[1] == 0) || 437 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 438 if (bootverbose) 439 device_printf(sc->age_dev, 440 "invalid ethernet address " 441 "returned from VPD.\n"); 442 vpd_error = EINVAL; 443 } 444 } 445 if (vpd_error != 0 && (bootverbose)) 446 device_printf(sc->age_dev, "VPD access failure!\n"); 447 } else { 448 vpd_error = ENOENT; 449 if (bootverbose) 450 device_printf(sc->age_dev, 451 "PCI VPD capability not found!\n"); 452 } 453 454 /* 455 * It seems that L1 also provides a way to extract ethernet 456 * address via SPI flash interface. Because SPI flash memory 457 * device of different vendors vary in their instruction 458 * codes for read ID instruction, it's very hard to get 459 * instructions codes without detailed information for the 460 * flash memory device used on ethernet controller. To simplify 461 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 462 * address which is supposed to be set by hardware during 463 * power on reset. 464 */ 465 if (vpd_error != 0) { 466 /* 467 * VPD is mapped to SPI flash memory or BIOS set it. 468 */ 469 ea[0] = CSR_READ_4(sc, AGE_PAR0); 470 ea[1] = CSR_READ_4(sc, AGE_PAR1); 471 } 472 473 ea[1] &= 0xFFFF; 474 if ((ea[0] == 0 && ea[1] == 0) || 475 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 476 device_printf(sc->age_dev, 477 "generating fake ethernet address.\n"); 478 ea[0] = karc4random(); 479 /* Set OUI to ASUSTek COMPUTER INC. */ 480 sc->age_eaddr[0] = 0x00; 481 sc->age_eaddr[1] = 0x1B; 482 sc->age_eaddr[2] = 0xFC; 483 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 484 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 485 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 486 } else { 487 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 488 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 489 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 490 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 491 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 492 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 493 } 494 } 495 496 static void 497 age_phy_reset(struct age_softc *sc) 498 { 499 /* Reset PHY. */ 500 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 501 DELAY(1000); 502 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 503 DELAY(1000); 504 } 505 506 static int 507 age_attach(device_t dev) 508 { 509 struct age_softc *sc = device_get_softc(dev); 510 struct ifnet *ifp = &sc->arpcom.ac_if; 511 uint8_t pcie_ptr; 512 int error; 513 514 error = 0; 515 sc->age_dev = dev; 516 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 517 518 callout_init(&sc->age_tick_ch); 519 520 #ifndef BURN_BRIDGES 521 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 522 uint32_t irq, mem; 523 524 irq = pci_read_config(dev, PCIR_INTLINE, 4); 525 mem = pci_read_config(dev, AGE_PCIR_BAR, 4); 526 527 device_printf(dev, "chip is in D%d power mode " 528 "-- setting to D0\n", pci_get_powerstate(dev)); 529 530 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 531 532 pci_write_config(dev, PCIR_INTLINE, irq, 4); 533 pci_write_config(dev, AGE_PCIR_BAR, mem, 4); 534 } 535 #endif /* !BURN_BRIDGE */ 536 537 /* Enable bus mastering */ 538 pci_enable_busmaster(dev); 539 540 /* 541 * Allocate memory mapped IO 542 */ 543 sc->age_mem_rid = AGE_PCIR_BAR; 544 sc->age_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 545 &sc->age_mem_rid, RF_ACTIVE); 546 if (sc->age_mem_res == NULL) { 547 device_printf(dev, "can't allocate IO memory\n"); 548 return ENXIO; 549 } 550 sc->age_mem_bt = rman_get_bustag(sc->age_mem_res); 551 sc->age_mem_bh = rman_get_bushandle(sc->age_mem_res); 552 553 /* 554 * Allocate IRQ 555 */ 556 sc->age_irq_rid = 0; 557 sc->age_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 558 &sc->age_irq_rid, 559 RF_SHAREABLE | RF_ACTIVE); 560 if (sc->age_irq_res == NULL) { 561 device_printf(dev, "can't allocate irq\n"); 562 error = ENXIO; 563 goto fail; 564 } 565 566 /* Set PHY address. */ 567 sc->age_phyaddr = AGE_PHY_ADDR; 568 569 /* Reset PHY. */ 570 age_phy_reset(sc); 571 572 /* Reset the ethernet controller. */ 573 age_reset(sc); 574 575 /* Get PCI and chip id/revision. */ 576 sc->age_rev = pci_get_revid(dev); 577 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 578 MASTER_CHIP_REV_SHIFT; 579 if (bootverbose) { 580 device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev); 581 device_printf(dev, "Chip id/revision : 0x%04x\n", 582 sc->age_chip_rev); 583 } 584 585 /* 586 * XXX 587 * Unintialized hardware returns an invalid chip id/revision 588 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 589 * unplugged cable results in putting hardware into automatic 590 * power down mode which in turn returns invalld chip revision. 591 */ 592 if (sc->age_chip_rev == 0xFFFF) { 593 device_printf(dev,"invalid chip revision : 0x%04x -- " 594 "not initialized?\n", sc->age_chip_rev); 595 error = ENXIO; 596 goto fail; 597 } 598 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 599 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 600 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 601 602 /* Get DMA parameters from PCIe device control register. */ 603 pcie_ptr = pci_get_pciecap_ptr(dev); 604 if (pcie_ptr) { 605 uint16_t devctl; 606 607 sc->age_flags |= AGE_FLAG_PCIE; 608 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 609 /* Max read request size. */ 610 sc->age_dma_rd_burst = ((devctl >> 12) & 0x07) << 611 DMA_CFG_RD_BURST_SHIFT; 612 /* Max payload size. */ 613 sc->age_dma_wr_burst = ((devctl >> 5) & 0x07) << 614 DMA_CFG_WR_BURST_SHIFT; 615 if (bootverbose) { 616 device_printf(dev, "Read request size : %d bytes.\n", 617 128 << ((devctl >> 12) & 0x07)); 618 device_printf(dev, "TLP payload size : %d bytes.\n", 619 128 << ((devctl >> 5) & 0x07)); 620 } 621 } else { 622 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 623 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 624 } 625 626 /* Create device sysctl node. */ 627 age_sysctl_node(sc); 628 629 if ((error = age_dma_alloc(sc) != 0)) 630 goto fail; 631 632 /* Load station address. */ 633 age_get_macaddr(sc); 634 635 ifp->if_softc = sc; 636 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 637 ifp->if_ioctl = age_ioctl; 638 ifp->if_start = age_start; 639 ifp->if_init = age_init; 640 ifp->if_watchdog = age_watchdog; 641 ifq_set_maxlen(&ifp->if_snd, AGE_TX_RING_CNT - 1); 642 ifq_set_ready(&ifp->if_snd); 643 644 ifp->if_capabilities = IFCAP_HWCSUM | 645 IFCAP_VLAN_MTU | 646 IFCAP_VLAN_HWTAGGING; 647 ifp->if_hwassist = AGE_CSUM_FEATURES; 648 ifp->if_capenable = ifp->if_capabilities; 649 650 /* Set up MII bus. */ 651 if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 652 age_mediastatus)) != 0) { 653 device_printf(dev, "no PHY found!\n"); 654 goto fail; 655 } 656 657 ether_ifattach(ifp, sc->age_eaddr, NULL); 658 659 /* Tell the upper layer(s) we support long frames. */ 660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 661 662 error = bus_setup_intr(dev, sc->age_irq_res, INTR_MPSAFE, age_intr, sc, 663 &sc->age_irq_handle, ifp->if_serializer); 664 if (error) { 665 device_printf(dev, "could not set up interrupt handler.\n"); 666 ether_ifdetach(ifp); 667 goto fail; 668 } 669 670 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->age_irq_res)); 671 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 672 return 0; 673 fail: 674 age_detach(dev); 675 return (error); 676 } 677 678 static int 679 age_detach(device_t dev) 680 { 681 struct age_softc *sc = device_get_softc(dev); 682 683 if (device_is_attached(dev)) { 684 struct ifnet *ifp = &sc->arpcom.ac_if; 685 686 lwkt_serialize_enter(ifp->if_serializer); 687 sc->age_flags |= AGE_FLAG_DETACH; 688 age_stop(sc); 689 bus_teardown_intr(dev, sc->age_irq_res, sc->age_irq_handle); 690 lwkt_serialize_exit(ifp->if_serializer); 691 692 ether_ifdetach(ifp); 693 } 694 695 if (sc->age_sysctl_tree != NULL) 696 sysctl_ctx_free(&sc->age_sysctl_ctx); 697 698 if (sc->age_miibus != NULL) 699 device_delete_child(dev, sc->age_miibus); 700 bus_generic_detach(dev); 701 702 if (sc->age_irq_res != NULL) { 703 bus_release_resource(dev, SYS_RES_IRQ, sc->age_irq_rid, 704 sc->age_irq_res); 705 } 706 if (sc->age_mem_res != NULL) { 707 bus_release_resource(dev, SYS_RES_MEMORY, sc->age_mem_rid, 708 sc->age_mem_res); 709 } 710 711 age_dma_free(sc); 712 713 return (0); 714 } 715 716 static void 717 age_sysctl_node(struct age_softc *sc) 718 { 719 int error; 720 721 sysctl_ctx_init(&sc->age_sysctl_ctx); 722 sc->age_sysctl_tree = SYSCTL_ADD_NODE(&sc->age_sysctl_ctx, 723 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 724 device_get_nameunit(sc->age_dev), 725 CTLFLAG_RD, 0, ""); 726 if (sc->age_sysctl_tree == NULL) { 727 device_printf(sc->age_dev, "can't add sysctl node\n"); 728 return; 729 } 730 731 SYSCTL_ADD_PROC(&sc->age_sysctl_ctx, 732 SYSCTL_CHILDREN(sc->age_sysctl_tree), OID_AUTO, 733 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 734 "I", "Statistics"); 735 736 SYSCTL_ADD_PROC(&sc->age_sysctl_ctx, 737 SYSCTL_CHILDREN(sc->age_sysctl_tree), OID_AUTO, 738 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 739 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 740 741 /* Pull in device tunables. */ 742 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 743 error = resource_int_value(device_get_name(sc->age_dev), 744 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 745 if (error == 0) { 746 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 747 sc->age_int_mod > AGE_IM_TIMER_MAX) { 748 device_printf(sc->age_dev, 749 "int_mod value out of range; using default: %d\n", 750 AGE_IM_TIMER_DEFAULT); 751 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 752 } 753 } 754 } 755 756 struct age_dmamap_arg { 757 bus_addr_t age_busaddr; 758 }; 759 760 static void 761 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 762 { 763 struct age_dmamap_arg *ctx; 764 765 if (error != 0) 766 return; 767 768 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 769 770 ctx = (struct age_dmamap_arg *)arg; 771 ctx->age_busaddr = segs[0].ds_addr; 772 } 773 774 /* 775 * Attansic L1 controller have single register to specify high 776 * address part of DMA blocks. So all descriptor structures and 777 * DMA memory blocks should have the same high address of given 778 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 779 */ 780 static int 781 age_check_boundary(struct age_softc *sc) 782 { 783 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 784 bus_addr_t cmb_block_end, smb_block_end; 785 786 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 787 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 788 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 789 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 790 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 791 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 792 793 if ((AGE_ADDR_HI(tx_ring_end) != 794 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 795 (AGE_ADDR_HI(rx_ring_end) != 796 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 797 (AGE_ADDR_HI(rr_ring_end) != 798 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 799 (AGE_ADDR_HI(cmb_block_end) != 800 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 801 (AGE_ADDR_HI(smb_block_end) != 802 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 803 return (EFBIG); 804 805 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 806 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 807 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 808 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 809 return (EFBIG); 810 811 return (0); 812 } 813 814 static int 815 age_dma_alloc(struct age_softc *sc) 816 { 817 struct age_txdesc *txd; 818 struct age_rxdesc *rxd; 819 bus_addr_t lowaddr; 820 struct age_dmamap_arg ctx; 821 int error, i; 822 823 lowaddr = BUS_SPACE_MAXADDR; 824 again: 825 /* Create parent ring/DMA block tag. */ 826 error = bus_dma_tag_create( 827 NULL, /* parent */ 828 1, 0, /* alignment, boundary */ 829 lowaddr, /* lowaddr */ 830 BUS_SPACE_MAXADDR, /* highaddr */ 831 NULL, NULL, /* filter, filterarg */ 832 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 833 0, /* nsegments */ 834 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 835 0, /* flags */ 836 &sc->age_cdata.age_parent_tag); 837 if (error != 0) { 838 device_printf(sc->age_dev, 839 "could not create parent DMA tag.\n"); 840 goto fail; 841 } 842 843 /* Create tag for Tx ring. */ 844 error = bus_dma_tag_create( 845 sc->age_cdata.age_parent_tag, /* parent */ 846 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 847 BUS_SPACE_MAXADDR, /* lowaddr */ 848 BUS_SPACE_MAXADDR, /* highaddr */ 849 NULL, NULL, /* filter, filterarg */ 850 AGE_TX_RING_SZ, /* maxsize */ 851 1, /* nsegments */ 852 AGE_TX_RING_SZ, /* maxsegsize */ 853 0, /* flags */ 854 &sc->age_cdata.age_tx_ring_tag); 855 if (error != 0) { 856 device_printf(sc->age_dev, 857 "could not create Tx ring DMA tag.\n"); 858 goto fail; 859 } 860 861 /* Create tag for Rx ring. */ 862 error = bus_dma_tag_create( 863 sc->age_cdata.age_parent_tag, /* parent */ 864 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 865 BUS_SPACE_MAXADDR, /* lowaddr */ 866 BUS_SPACE_MAXADDR, /* highaddr */ 867 NULL, NULL, /* filter, filterarg */ 868 AGE_RX_RING_SZ, /* maxsize */ 869 1, /* nsegments */ 870 AGE_RX_RING_SZ, /* maxsegsize */ 871 0, /* flags */ 872 &sc->age_cdata.age_rx_ring_tag); 873 if (error != 0) { 874 device_printf(sc->age_dev, 875 "could not create Rx ring DMA tag.\n"); 876 goto fail; 877 } 878 879 /* Create tag for Rx return ring. */ 880 error = bus_dma_tag_create( 881 sc->age_cdata.age_parent_tag, /* parent */ 882 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 883 BUS_SPACE_MAXADDR, /* lowaddr */ 884 BUS_SPACE_MAXADDR, /* highaddr */ 885 NULL, NULL, /* filter, filterarg */ 886 AGE_RR_RING_SZ, /* maxsize */ 887 1, /* nsegments */ 888 AGE_RR_RING_SZ, /* maxsegsize */ 889 0, /* flags */ 890 &sc->age_cdata.age_rr_ring_tag); 891 if (error != 0) { 892 device_printf(sc->age_dev, 893 "could not create Rx return ring DMA tag.\n"); 894 goto fail; 895 } 896 897 /* Create tag for coalesing message block. */ 898 error = bus_dma_tag_create( 899 sc->age_cdata.age_parent_tag, /* parent */ 900 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 901 BUS_SPACE_MAXADDR, /* lowaddr */ 902 BUS_SPACE_MAXADDR, /* highaddr */ 903 NULL, NULL, /* filter, filterarg */ 904 AGE_CMB_BLOCK_SZ, /* maxsize */ 905 1, /* nsegments */ 906 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 907 0, /* flags */ 908 &sc->age_cdata.age_cmb_block_tag); 909 if (error != 0) { 910 device_printf(sc->age_dev, 911 "could not create CMB DMA tag.\n"); 912 goto fail; 913 } 914 915 /* Create tag for statistics message block. */ 916 error = bus_dma_tag_create( 917 sc->age_cdata.age_parent_tag, /* parent */ 918 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 919 BUS_SPACE_MAXADDR, /* lowaddr */ 920 BUS_SPACE_MAXADDR, /* highaddr */ 921 NULL, NULL, /* filter, filterarg */ 922 AGE_SMB_BLOCK_SZ, /* maxsize */ 923 1, /* nsegments */ 924 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 925 0, /* flags */ 926 &sc->age_cdata.age_smb_block_tag); 927 if (error != 0) { 928 device_printf(sc->age_dev, 929 "could not create SMB DMA tag.\n"); 930 goto fail; 931 } 932 933 /* Allocate DMA'able memory and load the DMA map. */ 934 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 935 (void **)&sc->age_rdata.age_tx_ring, 936 BUS_DMA_WAITOK | BUS_DMA_ZERO, 937 &sc->age_cdata.age_tx_ring_map); 938 if (error != 0) { 939 device_printf(sc->age_dev, 940 "could not allocate DMA'able memory for Tx ring.\n"); 941 goto fail; 942 } 943 ctx.age_busaddr = 0; 944 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 945 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 946 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 947 if (error != 0 || ctx.age_busaddr == 0) { 948 device_printf(sc->age_dev, 949 "could not load DMA'able memory for Tx ring.\n"); 950 goto fail; 951 } 952 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 953 /* Rx ring */ 954 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 955 (void **)&sc->age_rdata.age_rx_ring, 956 BUS_DMA_WAITOK | BUS_DMA_ZERO, 957 &sc->age_cdata.age_rx_ring_map); 958 if (error != 0) { 959 device_printf(sc->age_dev, 960 "could not allocate DMA'able memory for Rx ring.\n"); 961 goto fail; 962 } 963 ctx.age_busaddr = 0; 964 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 965 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 966 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 967 if (error != 0 || ctx.age_busaddr == 0) { 968 device_printf(sc->age_dev, 969 "could not load DMA'able memory for Rx ring.\n"); 970 goto fail; 971 } 972 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 973 /* Rx return ring */ 974 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 975 (void **)&sc->age_rdata.age_rr_ring, 976 BUS_DMA_WAITOK | BUS_DMA_ZERO, 977 &sc->age_cdata.age_rr_ring_map); 978 if (error != 0) { 979 device_printf(sc->age_dev, 980 "could not allocate DMA'able memory for Rx return ring.\n"); 981 goto fail; 982 } 983 ctx.age_busaddr = 0; 984 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 985 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 986 AGE_RR_RING_SZ, age_dmamap_cb, &ctx, 0); 987 if (error != 0 || ctx.age_busaddr == 0) { 988 device_printf(sc->age_dev, 989 "could not load DMA'able memory for Rx return ring.\n"); 990 goto fail; 991 } 992 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 993 /* CMB block */ 994 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 995 (void **)&sc->age_rdata.age_cmb_block, 996 BUS_DMA_WAITOK | BUS_DMA_ZERO, 997 &sc->age_cdata.age_cmb_block_map); 998 if (error != 0) { 999 device_printf(sc->age_dev, 1000 "could not allocate DMA'able memory for CMB block.\n"); 1001 goto fail; 1002 } 1003 ctx.age_busaddr = 0; 1004 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1005 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1006 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1007 if (error != 0 || ctx.age_busaddr == 0) { 1008 device_printf(sc->age_dev, 1009 "could not load DMA'able memory for CMB block.\n"); 1010 goto fail; 1011 } 1012 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1013 /* SMB block */ 1014 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1015 (void **)&sc->age_rdata.age_smb_block, 1016 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1017 &sc->age_cdata.age_smb_block_map); 1018 if (error != 0) { 1019 device_printf(sc->age_dev, 1020 "could not allocate DMA'able memory for SMB block.\n"); 1021 goto fail; 1022 } 1023 ctx.age_busaddr = 0; 1024 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1025 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1026 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1027 if (error != 0 || ctx.age_busaddr == 0) { 1028 device_printf(sc->age_dev, 1029 "could not load DMA'able memory for SMB block.\n"); 1030 goto fail; 1031 } 1032 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1033 1034 /* 1035 * All ring buffer and DMA blocks should have the same 1036 * high address part of 64bit DMA address space. 1037 */ 1038 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1039 (error = age_check_boundary(sc)) != 0) { 1040 device_printf(sc->age_dev, "4GB boundary crossed, " 1041 "switching to 32bit DMA addressing mode.\n"); 1042 age_dma_free(sc); 1043 /* Limit DMA address space to 32bit and try again. */ 1044 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1045 goto again; 1046 } 1047 1048 /* 1049 * Create Tx/Rx buffer parent tag. 1050 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1051 * so it needs separate parent DMA tag. 1052 */ 1053 error = bus_dma_tag_create( 1054 NULL, /* parent */ 1055 1, 0, /* alignment, boundary */ 1056 BUS_SPACE_MAXADDR, /* lowaddr */ 1057 BUS_SPACE_MAXADDR, /* highaddr */ 1058 NULL, NULL, /* filter, filterarg */ 1059 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1060 0, /* nsegments */ 1061 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1062 0, /* flags */ 1063 &sc->age_cdata.age_buffer_tag); 1064 if (error != 0) { 1065 device_printf(sc->age_dev, 1066 "could not create parent buffer DMA tag.\n"); 1067 goto fail; 1068 } 1069 1070 /* Create tag for Tx buffers. */ 1071 error = bus_dma_tag_create( 1072 sc->age_cdata.age_buffer_tag, /* parent */ 1073 1, 0, /* alignment, boundary */ 1074 BUS_SPACE_MAXADDR, /* lowaddr */ 1075 BUS_SPACE_MAXADDR, /* highaddr */ 1076 NULL, NULL, /* filter, filterarg */ 1077 AGE_TSO_MAXSIZE, /* maxsize */ 1078 AGE_MAXTXSEGS, /* nsegments */ 1079 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1080 0, /* flags */ 1081 &sc->age_cdata.age_tx_tag); 1082 if (error != 0) { 1083 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1084 goto fail; 1085 } 1086 1087 /* Create tag for Rx buffers. */ 1088 error = bus_dma_tag_create( 1089 sc->age_cdata.age_buffer_tag, /* parent */ 1090 1, 0, /* alignment, boundary */ 1091 BUS_SPACE_MAXADDR, /* lowaddr */ 1092 BUS_SPACE_MAXADDR, /* highaddr */ 1093 NULL, NULL, /* filter, filterarg */ 1094 MCLBYTES, /* maxsize */ 1095 1, /* nsegments */ 1096 MCLBYTES, /* maxsegsize */ 1097 0, /* flags */ 1098 &sc->age_cdata.age_rx_tag); 1099 if (error != 0) { 1100 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1101 goto fail; 1102 } 1103 1104 /* Create DMA maps for Tx buffers. */ 1105 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1106 txd = &sc->age_cdata.age_txdesc[i]; 1107 txd->tx_m = NULL; 1108 txd->tx_dmamap = NULL; 1109 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1110 &txd->tx_dmamap); 1111 if (error != 0) { 1112 device_printf(sc->age_dev, 1113 "could not create Tx dmamap.\n"); 1114 goto fail; 1115 } 1116 } 1117 /* Create DMA maps for Rx buffers. */ 1118 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1119 &sc->age_cdata.age_rx_sparemap)) != 0) { 1120 device_printf(sc->age_dev, 1121 "could not create spare Rx dmamap.\n"); 1122 goto fail; 1123 } 1124 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1125 rxd = &sc->age_cdata.age_rxdesc[i]; 1126 rxd->rx_m = NULL; 1127 rxd->rx_dmamap = NULL; 1128 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1129 &rxd->rx_dmamap); 1130 if (error != 0) { 1131 device_printf(sc->age_dev, 1132 "could not create Rx dmamap.\n"); 1133 goto fail; 1134 } 1135 } 1136 fail: 1137 return (error); 1138 } 1139 1140 static void 1141 age_dma_free(struct age_softc *sc) 1142 { 1143 struct age_txdesc *txd; 1144 struct age_rxdesc *rxd; 1145 int i; 1146 1147 /* Tx buffers */ 1148 if (sc->age_cdata.age_tx_tag != NULL) { 1149 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1150 txd = &sc->age_cdata.age_txdesc[i]; 1151 if (txd->tx_dmamap != NULL) { 1152 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1153 txd->tx_dmamap); 1154 txd->tx_dmamap = NULL; 1155 } 1156 } 1157 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1158 sc->age_cdata.age_tx_tag = NULL; 1159 } 1160 /* Rx buffers */ 1161 if (sc->age_cdata.age_rx_tag != NULL) { 1162 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1163 rxd = &sc->age_cdata.age_rxdesc[i]; 1164 if (rxd->rx_dmamap != NULL) { 1165 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1166 rxd->rx_dmamap); 1167 rxd->rx_dmamap = NULL; 1168 } 1169 } 1170 if (sc->age_cdata.age_rx_sparemap != NULL) { 1171 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1172 sc->age_cdata.age_rx_sparemap); 1173 sc->age_cdata.age_rx_sparemap = NULL; 1174 } 1175 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1176 sc->age_cdata.age_rx_tag = NULL; 1177 } 1178 /* Tx ring. */ 1179 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1180 if (sc->age_cdata.age_tx_ring_map != NULL) 1181 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1182 sc->age_cdata.age_tx_ring_map); 1183 if (sc->age_cdata.age_tx_ring_map != NULL && 1184 sc->age_rdata.age_tx_ring != NULL) 1185 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1186 sc->age_rdata.age_tx_ring, 1187 sc->age_cdata.age_tx_ring_map); 1188 sc->age_rdata.age_tx_ring = NULL; 1189 sc->age_cdata.age_tx_ring_map = NULL; 1190 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1191 sc->age_cdata.age_tx_ring_tag = NULL; 1192 } 1193 /* Rx ring. */ 1194 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1195 if (sc->age_cdata.age_rx_ring_map != NULL) 1196 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1197 sc->age_cdata.age_rx_ring_map); 1198 if (sc->age_cdata.age_rx_ring_map != NULL && 1199 sc->age_rdata.age_rx_ring != NULL) 1200 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1201 sc->age_rdata.age_rx_ring, 1202 sc->age_cdata.age_rx_ring_map); 1203 sc->age_rdata.age_rx_ring = NULL; 1204 sc->age_cdata.age_rx_ring_map = NULL; 1205 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1206 sc->age_cdata.age_rx_ring_tag = NULL; 1207 } 1208 /* Rx return ring. */ 1209 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1210 if (sc->age_cdata.age_rr_ring_map != NULL) 1211 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1212 sc->age_cdata.age_rr_ring_map); 1213 if (sc->age_cdata.age_rr_ring_map != NULL && 1214 sc->age_rdata.age_rr_ring != NULL) 1215 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1216 sc->age_rdata.age_rr_ring, 1217 sc->age_cdata.age_rr_ring_map); 1218 sc->age_rdata.age_rr_ring = NULL; 1219 sc->age_cdata.age_rr_ring_map = NULL; 1220 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1221 sc->age_cdata.age_rr_ring_tag = NULL; 1222 } 1223 /* CMB block */ 1224 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1225 if (sc->age_cdata.age_cmb_block_map != NULL) 1226 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1227 sc->age_cdata.age_cmb_block_map); 1228 if (sc->age_cdata.age_cmb_block_map != NULL && 1229 sc->age_rdata.age_cmb_block != NULL) 1230 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1231 sc->age_rdata.age_cmb_block, 1232 sc->age_cdata.age_cmb_block_map); 1233 sc->age_rdata.age_cmb_block = NULL; 1234 sc->age_cdata.age_cmb_block_map = NULL; 1235 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1236 sc->age_cdata.age_cmb_block_tag = NULL; 1237 } 1238 /* SMB block */ 1239 if (sc->age_cdata.age_smb_block_tag != NULL) { 1240 if (sc->age_cdata.age_smb_block_map != NULL) 1241 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1242 sc->age_cdata.age_smb_block_map); 1243 if (sc->age_cdata.age_smb_block_map != NULL && 1244 sc->age_rdata.age_smb_block != NULL) 1245 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1246 sc->age_rdata.age_smb_block, 1247 sc->age_cdata.age_smb_block_map); 1248 sc->age_rdata.age_smb_block = NULL; 1249 sc->age_cdata.age_smb_block_map = NULL; 1250 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1251 sc->age_cdata.age_smb_block_tag = NULL; 1252 } 1253 1254 if (sc->age_cdata.age_buffer_tag != NULL) { 1255 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1256 sc->age_cdata.age_buffer_tag = NULL; 1257 } 1258 if (sc->age_cdata.age_parent_tag != NULL) { 1259 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1260 sc->age_cdata.age_parent_tag = NULL; 1261 } 1262 } 1263 1264 /* 1265 * Make sure the interface is stopped at reboot time. 1266 */ 1267 static int 1268 age_shutdown(device_t dev) 1269 { 1270 return age_suspend(dev); 1271 } 1272 1273 #ifdef wol_notyet 1274 1275 static void 1276 age_setwol(struct age_softc *sc) 1277 { 1278 struct ifnet *ifp; 1279 struct mii_data *mii; 1280 uint32_t reg, pmcs; 1281 uint16_t pmstat; 1282 int aneg, i, pmc; 1283 1284 AGE_LOCK_ASSERT(sc); 1285 1286 if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) == 0) { 1287 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1288 /* 1289 * No PME capability, PHY power down. 1290 * XXX 1291 * Due to an unknown reason powering down PHY resulted 1292 * in unexpected results such as inaccessbility of 1293 * hardware of freshly rebooted system. Disable 1294 * powering down PHY until I got more information for 1295 * Attansic/Atheros PHY hardwares. 1296 */ 1297 #ifdef notyet 1298 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1299 MII_BMCR, BMCR_PDOWN); 1300 #endif 1301 return; 1302 } 1303 1304 ifp = sc->age_ifp; 1305 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1306 /* 1307 * Note, this driver resets the link speed to 10/100Mbps with 1308 * auto-negotiation but we don't know whether that operation 1309 * would succeed or not as it have no control after powering 1310 * off. If the renegotiation fail WOL may not work. Running 1311 * at 1Gbps will draw more power than 375mA at 3.3V which is 1312 * specified in PCI specification and that would result in 1313 * complete shutdowning power to ethernet controller. 1314 * 1315 * TODO 1316 * Save current negotiated media speed/duplex/flow-control 1317 * to softc and restore the same link again after resuming. 1318 * PHY handling such as power down/resetting to 100Mbps 1319 * may be better handled in suspend method in phy driver. 1320 */ 1321 mii = device_get_softc(sc->age_miibus); 1322 mii_pollstat(mii); 1323 aneg = 0; 1324 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1325 switch IFM_SUBTYPE(mii->mii_media_active) { 1326 case IFM_10_T: 1327 case IFM_100_TX: 1328 goto got_link; 1329 case IFM_1000_T: 1330 aneg++; 1331 default: 1332 break; 1333 } 1334 } 1335 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1336 MII_100T2CR, 0); 1337 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1338 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1339 ANAR_10 | ANAR_CSMA); 1340 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1341 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1342 DELAY(1000); 1343 if (aneg != 0) { 1344 /* Poll link state until age(4) get a 10/100 link. */ 1345 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1346 mii_pollstat(mii); 1347 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1348 switch (IFM_SUBTYPE( 1349 mii->mii_media_active)) { 1350 case IFM_10_T: 1351 case IFM_100_TX: 1352 age_mac_config(sc); 1353 goto got_link; 1354 default: 1355 break; 1356 } 1357 } 1358 AGE_UNLOCK(sc); 1359 pause("agelnk", hz); 1360 AGE_LOCK(sc); 1361 } 1362 if (i == MII_ANEGTICKS_GIGE) 1363 device_printf(sc->age_dev, 1364 "establishing link failed, " 1365 "WOL may not work!"); 1366 } 1367 /* 1368 * No link, force MAC to have 100Mbps, full-duplex link. 1369 * This is the last resort and may/may not work. 1370 */ 1371 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1372 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1373 age_mac_config(sc); 1374 } 1375 1376 got_link: 1377 pmcs = 0; 1378 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1379 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1380 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1381 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1382 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1383 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1384 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1385 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1386 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1387 reg |= MAC_CFG_RX_ENB; 1388 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1389 } 1390 1391 /* Request PME. */ 1392 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1393 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1394 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1395 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1396 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1397 #ifdef notyet 1398 /* See above for powering down PHY issues. */ 1399 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1400 /* No WOL, PHY power down. */ 1401 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1402 MII_BMCR, BMCR_PDOWN); 1403 } 1404 #endif 1405 } 1406 1407 #endif /* wol_notyet */ 1408 1409 static int 1410 age_suspend(device_t dev) 1411 { 1412 struct age_softc *sc = device_get_softc(dev); 1413 struct ifnet *ifp = &sc->arpcom.ac_if; 1414 1415 lwkt_serialize_enter(ifp->if_serializer); 1416 age_stop(sc); 1417 #ifdef wol_notyet 1418 age_setwol(sc); 1419 #endif 1420 lwkt_serialize_exit(ifp->if_serializer); 1421 1422 return (0); 1423 } 1424 1425 static int 1426 age_resume(device_t dev) 1427 { 1428 struct age_softc *sc = device_get_softc(dev); 1429 struct ifnet *ifp = &sc->arpcom.ac_if; 1430 uint16_t cmd; 1431 1432 lwkt_serialize_enter(ifp->if_serializer); 1433 1434 /* 1435 * Clear INTx emulation disable for hardwares that 1436 * is set in resume event. From Linux. 1437 */ 1438 cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); 1439 if ((cmd & 0x0400) != 0) { 1440 cmd &= ~0x0400; 1441 pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); 1442 } 1443 if ((ifp->if_flags & IFF_UP) != 0) 1444 age_init(sc); 1445 1446 lwkt_serialize_exit(ifp->if_serializer); 1447 1448 return (0); 1449 } 1450 1451 static int 1452 age_encap(struct age_softc *sc, struct mbuf **m_head) 1453 { 1454 struct age_txdesc *txd, *txd_last; 1455 struct tx_desc *desc; 1456 struct mbuf *m; 1457 struct age_dmamap_ctx ctx; 1458 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1459 bus_dmamap_t map; 1460 uint32_t cflags, poff, vtag; 1461 int error, i, nsegs, prod, si; 1462 1463 M_ASSERTPKTHDR((*m_head)); 1464 1465 m = *m_head; 1466 cflags = vtag = 0; 1467 poff = 0; 1468 1469 si = prod = sc->age_cdata.age_tx_prod; 1470 txd = &sc->age_cdata.age_txdesc[prod]; 1471 txd_last = txd; 1472 map = txd->tx_dmamap; 1473 1474 ctx.nsegs = AGE_MAXTXSEGS; 1475 ctx.segs = txsegs; 1476 error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map, 1477 *m_head, age_dmamap_buf_cb, &ctx, 1478 BUS_DMA_NOWAIT); 1479 if (!error && ctx.nsegs == 0) { 1480 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1481 error = EFBIG; 1482 } 1483 if (error == EFBIG) { 1484 m = m_defrag(*m_head, MB_DONTWAIT); 1485 if (m == NULL) { 1486 m_freem(*m_head); 1487 *m_head = NULL; 1488 return (ENOBUFS); 1489 } 1490 *m_head = m; 1491 1492 ctx.nsegs = AGE_MAXTXSEGS; 1493 ctx.segs = txsegs; 1494 error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map, 1495 *m_head, age_dmamap_buf_cb, &ctx, 1496 BUS_DMA_NOWAIT); 1497 if (error || ctx.nsegs == 0) { 1498 if (!error) { 1499 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 1500 map); 1501 error = EFBIG; 1502 } 1503 m_freem(*m_head); 1504 *m_head = NULL; 1505 return (error); 1506 } 1507 } else if (error != 0) { 1508 return (error); 1509 } 1510 nsegs = ctx.nsegs; 1511 1512 if (nsegs == 0) { 1513 m_freem(*m_head); 1514 *m_head = NULL; 1515 return (EIO); 1516 } 1517 1518 /* Check descriptor overrun. */ 1519 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1520 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1521 return (ENOBUFS); 1522 } 1523 1524 m = *m_head; 1525 /* Configure Tx IP/TCP/UDP checksum offload. */ 1526 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1527 cflags |= AGE_TD_CSUM; 1528 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1529 cflags |= AGE_TD_TCPCSUM; 1530 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1531 cflags |= AGE_TD_UDPCSUM; 1532 /* Set checksum start offset. */ 1533 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1534 /* Set checksum insertion position of TCP/UDP. */ 1535 cflags |= ((poff + m->m_pkthdr.csum_data) << 1536 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1537 } 1538 1539 /* Configure VLAN hardware tag insertion. */ 1540 if ((m->m_flags & M_VLANTAG) != 0) { 1541 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag); 1542 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1543 cflags |= AGE_TD_INSERT_VLAN_TAG; 1544 } 1545 1546 desc = NULL; 1547 for (i = 0; i < nsegs; i++) { 1548 desc = &sc->age_rdata.age_tx_ring[prod]; 1549 desc->addr = htole64(txsegs[i].ds_addr); 1550 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1551 desc->flags = htole32(cflags); 1552 sc->age_cdata.age_tx_cnt++; 1553 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1554 } 1555 /* Update producer index. */ 1556 sc->age_cdata.age_tx_prod = prod; 1557 1558 /* Set EOP on the last descriptor. */ 1559 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1560 desc = &sc->age_rdata.age_tx_ring[prod]; 1561 desc->flags |= htole32(AGE_TD_EOP); 1562 1563 /* Swap dmamap of the first and the last. */ 1564 txd = &sc->age_cdata.age_txdesc[prod]; 1565 map = txd_last->tx_dmamap; 1566 txd_last->tx_dmamap = txd->tx_dmamap; 1567 txd->tx_dmamap = map; 1568 txd->tx_m = m; 1569 1570 /* Sync descriptors. */ 1571 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1572 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1573 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 1574 1575 return (0); 1576 } 1577 1578 static void 1579 age_start(struct ifnet *ifp) 1580 { 1581 struct age_softc *sc = ifp->if_softc; 1582 struct mbuf *m_head; 1583 int enq; 1584 1585 ASSERT_SERIALIZED(ifp->if_serializer); 1586 1587 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1588 ifq_purge(&ifp->if_snd); 1589 return; 1590 } 1591 1592 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1593 return; 1594 1595 enq = 0; 1596 while (!ifq_is_empty(&ifp->if_snd)) { 1597 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1598 if (m_head == NULL) 1599 break; 1600 1601 /* 1602 * Pack the data into the transmit ring. If we 1603 * don't have room, set the OACTIVE flag and wait 1604 * for the NIC to drain the ring. 1605 */ 1606 if (age_encap(sc, &m_head)) { 1607 if (m_head == NULL) 1608 break; 1609 ifq_prepend(&ifp->if_snd, m_head); 1610 ifp->if_flags |= IFF_OACTIVE; 1611 break; 1612 } 1613 enq = 1; 1614 1615 /* 1616 * If there's a BPF listener, bounce a copy of this frame 1617 * to him. 1618 */ 1619 ETHER_BPF_MTAP(ifp, m_head); 1620 } 1621 1622 if (enq) { 1623 /* Update mbox. */ 1624 AGE_COMMIT_MBOX(sc); 1625 /* Set a timeout in case the chip goes out to lunch. */ 1626 ifp->if_timer = AGE_TX_TIMEOUT; 1627 } 1628 } 1629 1630 static void 1631 age_watchdog(struct ifnet *ifp) 1632 { 1633 struct age_softc *sc = ifp->if_softc; 1634 1635 ASSERT_SERIALIZED(ifp->if_serializer); 1636 1637 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1638 if_printf(ifp, "watchdog timeout (missed link)\n"); 1639 ifp->if_oerrors++; 1640 age_init(sc); 1641 return; 1642 } 1643 1644 if (sc->age_cdata.age_tx_cnt == 0) { 1645 if_printf(ifp, 1646 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1647 if (!ifq_is_empty(&ifp->if_snd)) 1648 if_devstart(ifp); 1649 return; 1650 } 1651 1652 if_printf(ifp, "watchdog timeout\n"); 1653 ifp->if_oerrors++; 1654 age_init(sc); 1655 if (!ifq_is_empty(&ifp->if_snd)) 1656 if_devstart(ifp); 1657 } 1658 1659 static int 1660 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1661 { 1662 struct age_softc *sc = ifp->if_softc; 1663 struct ifreq *ifr; 1664 struct mii_data *mii; 1665 uint32_t reg; 1666 int error, mask; 1667 1668 ASSERT_SERIALIZED(ifp->if_serializer); 1669 1670 ifr = (struct ifreq *)data; 1671 error = 0; 1672 switch (cmd) { 1673 case SIOCSIFMTU: 1674 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) { 1675 error = EINVAL; 1676 } else if (ifp->if_mtu != ifr->ifr_mtu) { 1677 ifp->if_mtu = ifr->ifr_mtu; 1678 if ((ifp->if_flags & IFF_RUNNING) != 0) 1679 age_init(sc); 1680 } 1681 break; 1682 1683 case SIOCSIFFLAGS: 1684 if ((ifp->if_flags & IFF_UP) != 0) { 1685 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1686 if (((ifp->if_flags ^ sc->age_if_flags) 1687 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1688 age_rxfilter(sc); 1689 } else { 1690 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1691 age_init(sc); 1692 } 1693 } else { 1694 if ((ifp->if_flags & IFF_RUNNING) != 0) 1695 age_stop(sc); 1696 } 1697 sc->age_if_flags = ifp->if_flags; 1698 break; 1699 1700 case SIOCADDMULTI: 1701 case SIOCDELMULTI: 1702 if ((ifp->if_flags & IFF_RUNNING) != 0) 1703 age_rxfilter(sc); 1704 break; 1705 1706 case SIOCSIFMEDIA: 1707 case SIOCGIFMEDIA: 1708 mii = device_get_softc(sc->age_miibus); 1709 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1710 break; 1711 1712 case SIOCSIFCAP: 1713 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1714 1715 if ((mask & IFCAP_TXCSUM) != 0 && 1716 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1717 ifp->if_capenable ^= IFCAP_TXCSUM; 1718 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1719 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1720 else 1721 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1722 } 1723 1724 if ((mask & IFCAP_RXCSUM) != 0 && 1725 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1726 ifp->if_capenable ^= IFCAP_RXCSUM; 1727 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1728 reg &= ~MAC_CFG_RXCSUM_ENB; 1729 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1730 reg |= MAC_CFG_RXCSUM_ENB; 1731 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1732 } 1733 1734 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1735 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1736 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1737 age_rxvlan(sc); 1738 } 1739 break; 1740 1741 default: 1742 error = ether_ioctl(ifp, cmd, data); 1743 break; 1744 } 1745 return (error); 1746 } 1747 1748 static void 1749 age_mac_config(struct age_softc *sc) 1750 { 1751 struct mii_data *mii = device_get_softc(sc->age_miibus); 1752 uint32_t reg; 1753 1754 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1755 reg &= ~MAC_CFG_FULL_DUPLEX; 1756 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1757 reg &= ~MAC_CFG_SPEED_MASK; 1758 1759 /* Reprogram MAC with resolved speed/duplex. */ 1760 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1761 case IFM_10_T: 1762 case IFM_100_TX: 1763 reg |= MAC_CFG_SPEED_10_100; 1764 break; 1765 case IFM_1000_T: 1766 reg |= MAC_CFG_SPEED_1000; 1767 break; 1768 } 1769 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1770 reg |= MAC_CFG_FULL_DUPLEX; 1771 #ifdef notyet 1772 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1773 reg |= MAC_CFG_TX_FC; 1774 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1775 reg |= MAC_CFG_RX_FC; 1776 #endif 1777 } 1778 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1779 } 1780 1781 static void 1782 age_stats_update(struct age_softc *sc) 1783 { 1784 struct ifnet *ifp = &sc->arpcom.ac_if; 1785 struct age_stats *stat; 1786 struct smb *smb; 1787 1788 stat = &sc->age_stat; 1789 1790 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 1791 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_POSTREAD); 1792 1793 smb = sc->age_rdata.age_smb_block; 1794 if (smb->updated == 0) 1795 return; 1796 1797 /* Rx stats. */ 1798 stat->rx_frames += smb->rx_frames; 1799 stat->rx_bcast_frames += smb->rx_bcast_frames; 1800 stat->rx_mcast_frames += smb->rx_mcast_frames; 1801 stat->rx_pause_frames += smb->rx_pause_frames; 1802 stat->rx_control_frames += smb->rx_control_frames; 1803 stat->rx_crcerrs += smb->rx_crcerrs; 1804 stat->rx_lenerrs += smb->rx_lenerrs; 1805 stat->rx_bytes += smb->rx_bytes; 1806 stat->rx_runts += smb->rx_runts; 1807 stat->rx_fragments += smb->rx_fragments; 1808 stat->rx_pkts_64 += smb->rx_pkts_64; 1809 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1810 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1811 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1812 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1813 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1814 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1815 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1816 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1817 stat->rx_desc_oflows += smb->rx_desc_oflows; 1818 stat->rx_alignerrs += smb->rx_alignerrs; 1819 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1820 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1821 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1822 1823 /* Tx stats. */ 1824 stat->tx_frames += smb->tx_frames; 1825 stat->tx_bcast_frames += smb->tx_bcast_frames; 1826 stat->tx_mcast_frames += smb->tx_mcast_frames; 1827 stat->tx_pause_frames += smb->tx_pause_frames; 1828 stat->tx_excess_defer += smb->tx_excess_defer; 1829 stat->tx_control_frames += smb->tx_control_frames; 1830 stat->tx_deferred += smb->tx_deferred; 1831 stat->tx_bytes += smb->tx_bytes; 1832 stat->tx_pkts_64 += smb->tx_pkts_64; 1833 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1834 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1835 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1836 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1837 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1838 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1839 stat->tx_single_colls += smb->tx_single_colls; 1840 stat->tx_multi_colls += smb->tx_multi_colls; 1841 stat->tx_late_colls += smb->tx_late_colls; 1842 stat->tx_excess_colls += smb->tx_excess_colls; 1843 stat->tx_underrun += smb->tx_underrun; 1844 stat->tx_desc_underrun += smb->tx_desc_underrun; 1845 stat->tx_lenerrs += smb->tx_lenerrs; 1846 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1847 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1848 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1849 1850 /* Update counters in ifnet. */ 1851 ifp->if_opackets += smb->tx_frames; 1852 1853 ifp->if_collisions += smb->tx_single_colls + 1854 smb->tx_multi_colls + smb->tx_late_colls + 1855 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT; 1856 1857 ifp->if_oerrors += smb->tx_excess_colls + 1858 smb->tx_late_colls + smb->tx_underrun + 1859 smb->tx_pkts_truncated; 1860 1861 ifp->if_ipackets += smb->rx_frames; 1862 1863 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1864 smb->rx_runts + smb->rx_pkts_truncated + 1865 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1866 smb->rx_alignerrs; 1867 1868 /* Update done, clear. */ 1869 smb->updated = 0; 1870 1871 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 1872 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE); 1873 } 1874 1875 static void 1876 age_intr(void *xsc) 1877 { 1878 struct age_softc *sc = xsc; 1879 struct ifnet *ifp = &sc->arpcom.ac_if; 1880 struct cmb *cmb; 1881 uint32_t status; 1882 1883 ASSERT_SERIALIZED(ifp->if_serializer); 1884 1885 status = CSR_READ_4(sc, AGE_INTR_STATUS); 1886 if (status == 0 || (status & AGE_INTRS) == 0) 1887 return; 1888 1889 /* Disable and acknowledge interrupts. */ 1890 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 1891 1892 cmb = sc->age_rdata.age_cmb_block; 1893 1894 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1895 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD); 1896 status = le32toh(cmb->intr_status); 1897 if ((status & AGE_INTRS) == 0) 1898 goto done; 1899 again: 1900 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 1901 TPD_CONS_SHIFT; 1902 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 1903 RRD_PROD_SHIFT; 1904 1905 /* Let hardware know CMB was served. */ 1906 cmb->intr_status = 0; 1907 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1908 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE); 1909 1910 #if 0 1911 kprintf("INTR: 0x%08x\n", status); 1912 status &= ~INTR_DIS_DMA; 1913 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 1914 #endif 1915 1916 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1917 if ((status & INTR_CMB_RX) != 0) 1918 age_rxintr(sc, sc->age_rr_prod); 1919 1920 if ((status & INTR_CMB_TX) != 0) 1921 age_txintr(sc, sc->age_tpd_cons); 1922 1923 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 1924 if ((status & INTR_DMA_RD_TO_RST) != 0) 1925 device_printf(sc->age_dev, 1926 "DMA read error! -- resetting\n"); 1927 if ((status & INTR_DMA_WR_TO_RST) != 0) 1928 device_printf(sc->age_dev, 1929 "DMA write error! -- resetting\n"); 1930 age_init(sc); 1931 /* XXX return? */ 1932 } 1933 1934 if (!ifq_is_empty(&ifp->if_snd)) 1935 if_devstart(ifp); 1936 1937 if ((status & INTR_SMB) != 0) 1938 age_stats_update(sc); 1939 } 1940 1941 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 1942 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1943 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD); 1944 status = le32toh(cmb->intr_status); 1945 if ((status & AGE_INTRS) != 0) 1946 goto again; 1947 done: 1948 /* Re-enable interrupts. */ 1949 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1950 } 1951 1952 static void 1953 age_txintr(struct age_softc *sc, int tpd_cons) 1954 { 1955 struct ifnet *ifp = &sc->arpcom.ac_if; 1956 struct age_txdesc *txd; 1957 int cons, prog; 1958 1959 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1960 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_POSTREAD); 1961 1962 /* 1963 * Go through our Tx list and free mbufs for those 1964 * frames which have been transmitted. 1965 */ 1966 cons = sc->age_cdata.age_tx_cons; 1967 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1968 if (sc->age_cdata.age_tx_cnt <= 0) 1969 break; 1970 prog++; 1971 ifp->if_flags &= ~IFF_OACTIVE; 1972 sc->age_cdata.age_tx_cnt--; 1973 txd = &sc->age_cdata.age_txdesc[cons]; 1974 /* 1975 * Clear Tx descriptors, it's not required but would 1976 * help debugging in case of Tx issues. 1977 */ 1978 txd->tx_desc->addr = 0; 1979 txd->tx_desc->len = 0; 1980 txd->tx_desc->flags = 0; 1981 1982 if (txd->tx_m == NULL) 1983 continue; 1984 /* Reclaim transmitted mbufs. */ 1985 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 1986 m_freem(txd->tx_m); 1987 txd->tx_m = NULL; 1988 } 1989 1990 if (prog > 0) { 1991 sc->age_cdata.age_tx_cons = cons; 1992 1993 /* 1994 * Unarm watchdog timer only when there are no pending 1995 * Tx descriptors in queue. 1996 */ 1997 if (sc->age_cdata.age_tx_cnt == 0) 1998 ifp->if_timer = 0; 1999 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2000 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 2001 } 2002 } 2003 2004 /* Receive a frame. */ 2005 static void 2006 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2007 { 2008 struct ifnet *ifp = &sc->arpcom.ac_if; 2009 struct age_rxdesc *rxd; 2010 struct rx_desc *desc; 2011 struct mbuf *mp, *m; 2012 uint32_t status, index, vtag; 2013 int count, nsegs, pktlen; 2014 int rx_cons; 2015 2016 status = le32toh(rxrd->flags); 2017 index = le32toh(rxrd->index); 2018 rx_cons = AGE_RX_CONS(index); 2019 nsegs = AGE_RX_NSEGS(index); 2020 2021 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2022 if ((status & AGE_RRD_ERROR) != 0 && 2023 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2024 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2025 /* 2026 * We want to pass the following frames to upper 2027 * layer regardless of error status of Rx return 2028 * ring. 2029 * 2030 * o IP/TCP/UDP checksum is bad. 2031 * o frame length and protocol specific length 2032 * does not match. 2033 */ 2034 sc->age_cdata.age_rx_cons += nsegs; 2035 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2036 return; 2037 } 2038 2039 pktlen = 0; 2040 for (count = 0; count < nsegs; count++, 2041 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2042 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2043 mp = rxd->rx_m; 2044 desc = rxd->rx_desc; 2045 /* Add a new receive buffer to the ring. */ 2046 if (age_newbuf(sc, rxd, 0) != 0) { 2047 ifp->if_iqdrops++; 2048 /* Reuse Rx buffers. */ 2049 if (sc->age_cdata.age_rxhead != NULL) { 2050 m_freem(sc->age_cdata.age_rxhead); 2051 AGE_RXCHAIN_RESET(sc); 2052 } 2053 break; 2054 } 2055 2056 /* The length of the first mbuf is computed last. */ 2057 if (count != 0) { 2058 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2059 pktlen += mp->m_len; 2060 } 2061 2062 /* Chain received mbufs. */ 2063 if (sc->age_cdata.age_rxhead == NULL) { 2064 sc->age_cdata.age_rxhead = mp; 2065 sc->age_cdata.age_rxtail = mp; 2066 } else { 2067 mp->m_flags &= ~M_PKTHDR; 2068 sc->age_cdata.age_rxprev_tail = 2069 sc->age_cdata.age_rxtail; 2070 sc->age_cdata.age_rxtail->m_next = mp; 2071 sc->age_cdata.age_rxtail = mp; 2072 } 2073 2074 if (count == nsegs - 1) { 2075 /* 2076 * It seems that L1 controller has no way 2077 * to tell hardware to strip CRC bytes. 2078 */ 2079 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2080 if (nsegs > 1) { 2081 /* Remove the CRC bytes in chained mbufs. */ 2082 pktlen -= ETHER_CRC_LEN; 2083 if (mp->m_len <= ETHER_CRC_LEN) { 2084 sc->age_cdata.age_rxtail = 2085 sc->age_cdata.age_rxprev_tail; 2086 sc->age_cdata.age_rxtail->m_len -= 2087 (ETHER_CRC_LEN - mp->m_len); 2088 sc->age_cdata.age_rxtail->m_next = NULL; 2089 m_freem(mp); 2090 } else { 2091 mp->m_len -= ETHER_CRC_LEN; 2092 } 2093 } 2094 2095 m = sc->age_cdata.age_rxhead; 2096 m->m_flags |= M_PKTHDR; 2097 m->m_pkthdr.rcvif = ifp; 2098 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2099 /* Set the first mbuf length. */ 2100 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2101 2102 /* 2103 * Set checksum information. 2104 * It seems that L1 controller can compute partial 2105 * checksum. The partial checksum value can be used 2106 * to accelerate checksum computation for fragmented 2107 * TCP/UDP packets. Upper network stack already 2108 * takes advantage of the partial checksum value in 2109 * IP reassembly stage. But I'm not sure the 2110 * correctness of the partial hardware checksum 2111 * assistance due to lack of data sheet. If it is 2112 * proven to work on L1 I'll enable it. 2113 */ 2114 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2115 (status & AGE_RRD_IPV4) != 0) { 2116 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2117 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2118 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2119 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2120 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2121 m->m_pkthdr.csum_flags |= 2122 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2123 m->m_pkthdr.csum_data = 0xffff; 2124 } 2125 /* 2126 * Don't mark bad checksum for TCP/UDP frames 2127 * as fragmented frames may always have set 2128 * bad checksummed bit of descriptor status. 2129 */ 2130 } 2131 2132 /* Check for VLAN tagged frames. */ 2133 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2134 (status & AGE_RRD_VLAN) != 0) { 2135 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2136 m->m_pkthdr.ether_vlantag = 2137 AGE_RX_VLAN_TAG(vtag); 2138 m->m_flags |= M_VLANTAG; 2139 } 2140 2141 /* Pass it on. */ 2142 ifp->if_input(ifp, m); 2143 2144 /* Reset mbuf chains. */ 2145 AGE_RXCHAIN_RESET(sc); 2146 } 2147 } 2148 2149 if (count != nsegs) { 2150 sc->age_cdata.age_rx_cons += nsegs; 2151 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2152 } else { 2153 sc->age_cdata.age_rx_cons = rx_cons; 2154 } 2155 } 2156 2157 static void 2158 age_rxintr(struct age_softc *sc, int rr_prod) 2159 { 2160 struct rx_rdesc *rxrd; 2161 int rr_cons, nsegs, pktlen, prog; 2162 2163 rr_cons = sc->age_cdata.age_rr_cons; 2164 if (rr_cons == rr_prod) 2165 return; 2166 2167 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2168 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_POSTREAD); 2169 2170 for (prog = 0; rr_cons != rr_prod; prog++) { 2171 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2172 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2173 if (nsegs == 0) 2174 break; 2175 2176 /* 2177 * Check number of segments against received bytes. 2178 * Non-matching value would indicate that hardware 2179 * is still trying to update Rx return descriptors. 2180 * I'm not sure whether this check is really needed. 2181 */ 2182 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2183 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2184 (MCLBYTES - ETHER_ALIGN))) 2185 break; 2186 2187 /* Received a frame. */ 2188 age_rxeof(sc, rxrd); 2189 2190 /* Clear return ring. */ 2191 rxrd->index = 0; 2192 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2193 } 2194 2195 if (prog > 0) { 2196 /* Update the consumer index. */ 2197 sc->age_cdata.age_rr_cons = rr_cons; 2198 2199 /* Sync descriptors. */ 2200 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2201 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE); 2202 2203 /* Notify hardware availability of new Rx buffers. */ 2204 AGE_COMMIT_MBOX(sc); 2205 } 2206 } 2207 2208 static void 2209 age_tick(void *xsc) 2210 { 2211 struct age_softc *sc = xsc; 2212 struct ifnet *ifp = &sc->arpcom.ac_if; 2213 struct mii_data *mii = device_get_softc(sc->age_miibus); 2214 2215 lwkt_serialize_enter(ifp->if_serializer); 2216 2217 mii_tick(mii); 2218 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2219 2220 lwkt_serialize_exit(ifp->if_serializer); 2221 } 2222 2223 static void 2224 age_reset(struct age_softc *sc) 2225 { 2226 uint32_t reg; 2227 int i; 2228 2229 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2230 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2231 DELAY(1); 2232 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 2233 break; 2234 } 2235 if (i == 0) 2236 device_printf(sc->age_dev, "master reset timeout!\n"); 2237 2238 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2239 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2240 break; 2241 DELAY(10); 2242 } 2243 if (i == 0) 2244 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2245 2246 /* Initialize PCIe module. From Linux. */ 2247 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2248 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2249 } 2250 2251 static void 2252 age_init(void *xsc) 2253 { 2254 struct age_softc *sc = xsc; 2255 struct ifnet *ifp = &sc->arpcom.ac_if; 2256 struct mii_data *mii; 2257 uint8_t eaddr[ETHER_ADDR_LEN]; 2258 bus_addr_t paddr; 2259 uint32_t reg, fsize; 2260 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2261 int error; 2262 2263 ASSERT_SERIALIZED(ifp->if_serializer); 2264 2265 mii = device_get_softc(sc->age_miibus); 2266 2267 /* 2268 * Cancel any pending I/O. 2269 */ 2270 age_stop(sc); 2271 2272 /* 2273 * Reset the chip to a known state. 2274 */ 2275 age_reset(sc); 2276 2277 /* Initialize descriptors. */ 2278 error = age_init_rx_ring(sc); 2279 if (error != 0) { 2280 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2281 age_stop(sc); 2282 return; 2283 } 2284 age_init_rr_ring(sc); 2285 age_init_tx_ring(sc); 2286 age_init_cmb_block(sc); 2287 age_init_smb_block(sc); 2288 2289 /* Reprogram the station address. */ 2290 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2291 CSR_WRITE_4(sc, AGE_PAR0, 2292 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2293 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2294 2295 /* Set descriptor base addresses. */ 2296 paddr = sc->age_rdata.age_tx_ring_paddr; 2297 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2298 paddr = sc->age_rdata.age_rx_ring_paddr; 2299 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2300 paddr = sc->age_rdata.age_rr_ring_paddr; 2301 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2302 paddr = sc->age_rdata.age_tx_ring_paddr; 2303 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2304 paddr = sc->age_rdata.age_cmb_block_paddr; 2305 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2306 paddr = sc->age_rdata.age_smb_block_paddr; 2307 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2308 2309 /* Set Rx/Rx return descriptor counter. */ 2310 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2311 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2312 DESC_RRD_CNT_MASK) | 2313 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2314 2315 /* Set Tx descriptor counter. */ 2316 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2317 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2318 2319 /* Tell hardware that we're ready to load descriptors. */ 2320 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2321 2322 /* 2323 * Initialize mailbox register. 2324 * Updated producer/consumer index information is exchanged 2325 * through this mailbox register. However Tx producer and 2326 * Rx return consumer/Rx producer are all shared such that 2327 * it's hard to separate code path between Tx and Rx without 2328 * locking. If L1 hardware have a separate mail box register 2329 * for Tx and Rx consumer/producer management we could have 2330 * indepent Tx/Rx handler which in turn Rx handler could have 2331 * been run without any locking. 2332 */ 2333 AGE_COMMIT_MBOX(sc); 2334 2335 /* Configure IPG/IFG parameters. */ 2336 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2337 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2338 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2339 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2340 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2341 2342 /* Set parameters for half-duplex media. */ 2343 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2344 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2345 HDPX_CFG_LCOL_MASK) | 2346 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2347 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2348 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2349 HDPX_CFG_ABEBT_MASK) | 2350 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2351 HDPX_CFG_JAMIPG_MASK)); 2352 2353 /* Configure interrupt moderation timer. */ 2354 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2355 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2356 reg &= ~MASTER_MTIMER_ENB; 2357 if (AGE_USECS(sc->age_int_mod) == 0) 2358 reg &= ~MASTER_ITIMER_ENB; 2359 else 2360 reg |= MASTER_ITIMER_ENB; 2361 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2362 if (bootverbose) 2363 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2364 sc->age_int_mod); 2365 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2366 2367 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2368 if (ifp->if_mtu < ETHERMTU) 2369 sc->age_max_frame_size = ETHERMTU; 2370 else 2371 sc->age_max_frame_size = ifp->if_mtu; 2372 sc->age_max_frame_size += ETHER_HDR_LEN + 2373 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2374 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2375 2376 /* Configure jumbo frame. */ 2377 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2378 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2379 (((fsize / sizeof(uint64_t)) << 2380 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2381 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2382 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2383 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2384 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2385 2386 /* Configure flow-control parameters. From Linux. */ 2387 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2388 /* 2389 * Magic workaround for old-L1. 2390 * Don't know which hw revision requires this magic. 2391 */ 2392 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2393 /* 2394 * Another magic workaround for flow-control mode 2395 * change. From Linux. 2396 */ 2397 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2398 } 2399 /* 2400 * TODO 2401 * Should understand pause parameter relationships between FIFO 2402 * size and number of Rx descriptors and Rx return descriptors. 2403 * 2404 * Magic parameters came from Linux. 2405 */ 2406 switch (sc->age_chip_rev) { 2407 case 0x8001: 2408 case 0x9001: 2409 case 0x9002: 2410 case 0x9003: 2411 rxf_hi = AGE_RX_RING_CNT / 16; 2412 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2413 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2414 rrd_lo = AGE_RR_RING_CNT / 16; 2415 break; 2416 default: 2417 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2418 rxf_lo = reg / 16; 2419 if (rxf_lo < 192) 2420 rxf_lo = 192; 2421 rxf_hi = (reg * 7) / 8; 2422 if (rxf_hi < rxf_lo) 2423 rxf_hi = rxf_lo + 16; 2424 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2425 rrd_lo = reg / 8; 2426 rrd_hi = (reg * 7) / 8; 2427 if (rrd_lo < 2) 2428 rrd_lo = 2; 2429 if (rrd_hi < rrd_lo) 2430 rrd_hi = rrd_lo + 3; 2431 break; 2432 } 2433 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2434 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2435 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2436 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2437 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2438 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2439 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2440 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2441 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2442 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2443 2444 /* Configure RxQ. */ 2445 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2446 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2447 RXQ_CFG_RD_BURST_MASK) | 2448 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2449 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2450 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2451 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2452 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2453 2454 /* Configure TxQ. */ 2455 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2456 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2457 TXQ_CFG_TPD_BURST_MASK) | 2458 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2459 TXQ_CFG_TX_FIFO_BURST_MASK) | 2460 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2461 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2462 TXQ_CFG_ENB); 2463 2464 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2465 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2466 TX_JUMBO_TPD_TH_MASK) | 2467 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2468 TX_JUMBO_TPD_IPG_MASK)); 2469 2470 /* Configure DMA parameters. */ 2471 CSR_WRITE_4(sc, AGE_DMA_CFG, 2472 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2473 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2474 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2475 2476 /* Configure CMB DMA write threshold. */ 2477 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2478 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2479 CMB_WR_THRESH_RRD_MASK) | 2480 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2481 CMB_WR_THRESH_TPD_MASK)); 2482 2483 /* Set CMB/SMB timer and enable them. */ 2484 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2485 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2486 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2487 2488 /* Request SMB updates for every seconds. */ 2489 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2490 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2491 2492 /* 2493 * Disable all WOL bits as WOL can interfere normal Rx 2494 * operation. 2495 */ 2496 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2497 2498 /* 2499 * Configure Tx/Rx MACs. 2500 * - Auto-padding for short frames. 2501 * - Enable CRC generation. 2502 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2503 * of MAC is followed after link establishment. 2504 */ 2505 CSR_WRITE_4(sc, AGE_MAC_CFG, 2506 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2507 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2508 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2509 MAC_CFG_PREAMBLE_MASK)); 2510 2511 /* Set up the receive filter. */ 2512 age_rxfilter(sc); 2513 age_rxvlan(sc); 2514 2515 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2516 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2517 reg |= MAC_CFG_RXCSUM_ENB; 2518 2519 /* Ack all pending interrupts and clear it. */ 2520 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2521 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2522 2523 /* Finally enable Tx/Rx MAC. */ 2524 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2525 2526 sc->age_flags &= ~AGE_FLAG_LINK; 2527 /* Switch to the current media. */ 2528 mii_mediachg(mii); 2529 2530 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2531 2532 ifp->if_flags |= IFF_RUNNING; 2533 ifp->if_flags &= ~IFF_OACTIVE; 2534 } 2535 2536 static void 2537 age_stop(struct age_softc *sc) 2538 { 2539 struct ifnet *ifp = &sc->arpcom.ac_if; 2540 struct age_txdesc *txd; 2541 struct age_rxdesc *rxd; 2542 uint32_t reg; 2543 int i; 2544 2545 ASSERT_SERIALIZED(ifp->if_serializer); 2546 2547 /* 2548 * Mark the interface down and cancel the watchdog timer. 2549 */ 2550 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2551 ifp->if_timer = 0; 2552 2553 sc->age_flags &= ~AGE_FLAG_LINK; 2554 callout_stop(&sc->age_tick_ch); 2555 2556 /* 2557 * Disable interrupts. 2558 */ 2559 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2560 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2561 2562 /* Stop CMB/SMB updates. */ 2563 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2564 2565 /* Stop Rx/Tx MAC. */ 2566 age_stop_rxmac(sc); 2567 age_stop_txmac(sc); 2568 2569 /* Stop DMA. */ 2570 CSR_WRITE_4(sc, AGE_DMA_CFG, 2571 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2572 2573 /* Stop TxQ/RxQ. */ 2574 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2575 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2576 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2577 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2578 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2579 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2580 break; 2581 DELAY(10); 2582 } 2583 if (i == 0) 2584 device_printf(sc->age_dev, 2585 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2586 2587 /* Reclaim Rx buffers that have been processed. */ 2588 if (sc->age_cdata.age_rxhead != NULL) 2589 m_freem(sc->age_cdata.age_rxhead); 2590 AGE_RXCHAIN_RESET(sc); 2591 2592 /* 2593 * Free RX and TX mbufs still in the queues. 2594 */ 2595 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2596 rxd = &sc->age_cdata.age_rxdesc[i]; 2597 if (rxd->rx_m != NULL) { 2598 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2599 rxd->rx_dmamap); 2600 m_freem(rxd->rx_m); 2601 rxd->rx_m = NULL; 2602 } 2603 } 2604 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2605 txd = &sc->age_cdata.age_txdesc[i]; 2606 if (txd->tx_m != NULL) { 2607 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2608 txd->tx_dmamap); 2609 m_freem(txd->tx_m); 2610 txd->tx_m = NULL; 2611 } 2612 } 2613 } 2614 2615 static void 2616 age_stop_txmac(struct age_softc *sc) 2617 { 2618 uint32_t reg; 2619 int i; 2620 2621 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2622 if ((reg & MAC_CFG_TX_ENB) != 0) { 2623 reg &= ~MAC_CFG_TX_ENB; 2624 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2625 } 2626 /* Stop Tx DMA engine. */ 2627 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2628 if ((reg & DMA_CFG_RD_ENB) != 0) { 2629 reg &= ~DMA_CFG_RD_ENB; 2630 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2631 } 2632 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2633 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2634 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2635 break; 2636 DELAY(10); 2637 } 2638 if (i == 0) 2639 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2640 } 2641 2642 static void 2643 age_stop_rxmac(struct age_softc *sc) 2644 { 2645 uint32_t reg; 2646 int i; 2647 2648 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2649 if ((reg & MAC_CFG_RX_ENB) != 0) { 2650 reg &= ~MAC_CFG_RX_ENB; 2651 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2652 } 2653 /* Stop Rx DMA engine. */ 2654 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2655 if ((reg & DMA_CFG_WR_ENB) != 0) { 2656 reg &= ~DMA_CFG_WR_ENB; 2657 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2658 } 2659 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2660 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2661 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2662 break; 2663 DELAY(10); 2664 } 2665 if (i == 0) 2666 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2667 } 2668 2669 static void 2670 age_init_tx_ring(struct age_softc *sc) 2671 { 2672 struct age_ring_data *rd; 2673 struct age_txdesc *txd; 2674 int i; 2675 2676 sc->age_cdata.age_tx_prod = 0; 2677 sc->age_cdata.age_tx_cons = 0; 2678 sc->age_cdata.age_tx_cnt = 0; 2679 2680 rd = &sc->age_rdata; 2681 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2682 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2683 txd = &sc->age_cdata.age_txdesc[i]; 2684 txd->tx_desc = &rd->age_tx_ring[i]; 2685 txd->tx_m = NULL; 2686 } 2687 2688 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2689 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 2690 } 2691 2692 static int 2693 age_init_rx_ring(struct age_softc *sc) 2694 { 2695 struct age_ring_data *rd; 2696 struct age_rxdesc *rxd; 2697 int i; 2698 2699 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2700 rd = &sc->age_rdata; 2701 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2702 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2703 rxd = &sc->age_cdata.age_rxdesc[i]; 2704 rxd->rx_m = NULL; 2705 rxd->rx_desc = &rd->age_rx_ring[i]; 2706 if (age_newbuf(sc, rxd, 1) != 0) 2707 return (ENOBUFS); 2708 } 2709 2710 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2711 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2712 2713 return (0); 2714 } 2715 2716 static void 2717 age_init_rr_ring(struct age_softc *sc) 2718 { 2719 struct age_ring_data *rd; 2720 2721 sc->age_cdata.age_rr_cons = 0; 2722 AGE_RXCHAIN_RESET(sc); 2723 2724 rd = &sc->age_rdata; 2725 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2726 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2727 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE); 2728 } 2729 2730 static void 2731 age_init_cmb_block(struct age_softc *sc) 2732 { 2733 struct age_ring_data *rd; 2734 2735 rd = &sc->age_rdata; 2736 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2737 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2738 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE); 2739 } 2740 2741 static void 2742 age_init_smb_block(struct age_softc *sc) 2743 { 2744 struct age_ring_data *rd; 2745 2746 rd = &sc->age_rdata; 2747 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2748 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2749 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE); 2750 } 2751 2752 static int 2753 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2754 { 2755 struct rx_desc *desc; 2756 struct mbuf *m; 2757 struct age_dmamap_ctx ctx; 2758 bus_dma_segment_t segs[1]; 2759 bus_dmamap_t map; 2760 int error; 2761 2762 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); 2763 if (m == NULL) 2764 return (ENOBUFS); 2765 2766 m->m_len = m->m_pkthdr.len = MCLBYTES; 2767 m_adj(m, ETHER_ALIGN); 2768 2769 ctx.nsegs = 1; 2770 ctx.segs = segs; 2771 error = bus_dmamap_load_mbuf(sc->age_cdata.age_rx_tag, 2772 sc->age_cdata.age_rx_sparemap, 2773 m, age_dmamap_buf_cb, &ctx, 2774 BUS_DMA_NOWAIT); 2775 if (error || ctx.nsegs == 0) { 2776 if (!error) { 2777 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2778 sc->age_cdata.age_rx_sparemap); 2779 error = EFBIG; 2780 if_printf(&sc->arpcom.ac_if, "too many segments?!\n"); 2781 } 2782 m_freem(m); 2783 2784 if (init) 2785 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 2786 return (error); 2787 } 2788 KASSERT(ctx.nsegs == 1, 2789 ("%s: %d segments returned!", __func__, ctx.nsegs)); 2790 2791 if (rxd->rx_m != NULL) { 2792 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 2793 BUS_DMASYNC_POSTREAD); 2794 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 2795 } 2796 map = rxd->rx_dmamap; 2797 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2798 sc->age_cdata.age_rx_sparemap = map; 2799 rxd->rx_m = m; 2800 2801 desc = rxd->rx_desc; 2802 desc->addr = htole64(segs[0].ds_addr); 2803 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 2804 AGE_RD_LEN_SHIFT); 2805 return (0); 2806 } 2807 2808 static void 2809 age_rxvlan(struct age_softc *sc) 2810 { 2811 struct ifnet *ifp = &sc->arpcom.ac_if; 2812 uint32_t reg; 2813 2814 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2815 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2816 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2817 reg |= MAC_CFG_VLAN_TAG_STRIP; 2818 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2819 } 2820 2821 static void 2822 age_rxfilter(struct age_softc *sc) 2823 { 2824 struct ifnet *ifp = &sc->arpcom.ac_if; 2825 struct ifmultiaddr *ifma; 2826 uint32_t crc; 2827 uint32_t mchash[2]; 2828 uint32_t rxcfg; 2829 2830 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2831 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2832 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2833 rxcfg |= MAC_CFG_BCAST; 2834 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2835 if ((ifp->if_flags & IFF_PROMISC) != 0) 2836 rxcfg |= MAC_CFG_PROMISC; 2837 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2838 rxcfg |= MAC_CFG_ALLMULTI; 2839 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2840 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2841 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2842 return; 2843 } 2844 2845 /* Program new filter. */ 2846 bzero(mchash, sizeof(mchash)); 2847 2848 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2849 if (ifma->ifma_addr->sa_family != AF_LINK) 2850 continue; 2851 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2852 ifma->ifma_addr), ETHER_ADDR_LEN); 2853 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2854 } 2855 2856 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2857 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2858 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2859 } 2860 2861 static int 2862 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 2863 { 2864 struct age_softc *sc; 2865 struct age_stats *stats; 2866 int error, result; 2867 2868 result = -1; 2869 error = sysctl_handle_int(oidp, &result, 0, req); 2870 2871 if (error != 0 || req->newptr == NULL) 2872 return (error); 2873 2874 if (result != 1) 2875 return (error); 2876 2877 sc = (struct age_softc *)arg1; 2878 stats = &sc->age_stat; 2879 kprintf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 2880 kprintf("Transmit good frames : %ju\n", 2881 (uintmax_t)stats->tx_frames); 2882 kprintf("Transmit good broadcast frames : %ju\n", 2883 (uintmax_t)stats->tx_bcast_frames); 2884 kprintf("Transmit good multicast frames : %ju\n", 2885 (uintmax_t)stats->tx_mcast_frames); 2886 kprintf("Transmit pause control frames : %u\n", 2887 stats->tx_pause_frames); 2888 kprintf("Transmit control frames : %u\n", 2889 stats->tx_control_frames); 2890 kprintf("Transmit frames with excessive deferrals : %u\n", 2891 stats->tx_excess_defer); 2892 kprintf("Transmit deferrals : %u\n", 2893 stats->tx_deferred); 2894 kprintf("Transmit good octets : %ju\n", 2895 (uintmax_t)stats->tx_bytes); 2896 kprintf("Transmit good broadcast octets : %ju\n", 2897 (uintmax_t)stats->tx_bcast_bytes); 2898 kprintf("Transmit good multicast octets : %ju\n", 2899 (uintmax_t)stats->tx_mcast_bytes); 2900 kprintf("Transmit frames 64 bytes : %ju\n", 2901 (uintmax_t)stats->tx_pkts_64); 2902 kprintf("Transmit frames 65 to 127 bytes : %ju\n", 2903 (uintmax_t)stats->tx_pkts_65_127); 2904 kprintf("Transmit frames 128 to 255 bytes : %ju\n", 2905 (uintmax_t)stats->tx_pkts_128_255); 2906 kprintf("Transmit frames 256 to 511 bytes : %ju\n", 2907 (uintmax_t)stats->tx_pkts_256_511); 2908 kprintf("Transmit frames 512 to 1024 bytes : %ju\n", 2909 (uintmax_t)stats->tx_pkts_512_1023); 2910 kprintf("Transmit frames 1024 to 1518 bytes : %ju\n", 2911 (uintmax_t)stats->tx_pkts_1024_1518); 2912 kprintf("Transmit frames 1519 to MTU bytes : %ju\n", 2913 (uintmax_t)stats->tx_pkts_1519_max); 2914 kprintf("Transmit single collisions : %u\n", 2915 stats->tx_single_colls); 2916 kprintf("Transmit multiple collisions : %u\n", 2917 stats->tx_multi_colls); 2918 kprintf("Transmit late collisions : %u\n", 2919 stats->tx_late_colls); 2920 kprintf("Transmit abort due to excessive collisions : %u\n", 2921 stats->tx_excess_colls); 2922 kprintf("Transmit underruns due to FIFO underruns : %u\n", 2923 stats->tx_underrun); 2924 kprintf("Transmit descriptor write-back errors : %u\n", 2925 stats->tx_desc_underrun); 2926 kprintf("Transmit frames with length mismatched frame size : %u\n", 2927 stats->tx_lenerrs); 2928 kprintf("Transmit frames with truncated due to MTU size : %u\n", 2929 stats->tx_lenerrs); 2930 2931 kprintf("Receive good frames : %ju\n", 2932 (uintmax_t)stats->rx_frames); 2933 kprintf("Receive good broadcast frames : %ju\n", 2934 (uintmax_t)stats->rx_bcast_frames); 2935 kprintf("Receive good multicast frames : %ju\n", 2936 (uintmax_t)stats->rx_mcast_frames); 2937 kprintf("Receive pause control frames : %u\n", 2938 stats->rx_pause_frames); 2939 kprintf("Receive control frames : %u\n", 2940 stats->rx_control_frames); 2941 kprintf("Receive CRC errors : %u\n", 2942 stats->rx_crcerrs); 2943 kprintf("Receive frames with length errors : %u\n", 2944 stats->rx_lenerrs); 2945 kprintf("Receive good octets : %ju\n", 2946 (uintmax_t)stats->rx_bytes); 2947 kprintf("Receive good broadcast octets : %ju\n", 2948 (uintmax_t)stats->rx_bcast_bytes); 2949 kprintf("Receive good multicast octets : %ju\n", 2950 (uintmax_t)stats->rx_mcast_bytes); 2951 kprintf("Receive frames too short : %u\n", 2952 stats->rx_runts); 2953 kprintf("Receive fragmented frames : %ju\n", 2954 (uintmax_t)stats->rx_fragments); 2955 kprintf("Receive frames 64 bytes : %ju\n", 2956 (uintmax_t)stats->rx_pkts_64); 2957 kprintf("Receive frames 65 to 127 bytes : %ju\n", 2958 (uintmax_t)stats->rx_pkts_65_127); 2959 kprintf("Receive frames 128 to 255 bytes : %ju\n", 2960 (uintmax_t)stats->rx_pkts_128_255); 2961 kprintf("Receive frames 256 to 511 bytes : %ju\n", 2962 (uintmax_t)stats->rx_pkts_256_511); 2963 kprintf("Receive frames 512 to 1024 bytes : %ju\n", 2964 (uintmax_t)stats->rx_pkts_512_1023); 2965 kprintf("Receive frames 1024 to 1518 bytes : %ju\n", 2966 (uintmax_t)stats->rx_pkts_1024_1518); 2967 kprintf("Receive frames 1519 to MTU bytes : %ju\n", 2968 (uintmax_t)stats->rx_pkts_1519_max); 2969 kprintf("Receive frames too long : %ju\n", 2970 (uint64_t)stats->rx_pkts_truncated); 2971 kprintf("Receive frames with FIFO overflow : %u\n", 2972 stats->rx_fifo_oflows); 2973 kprintf("Receive frames with return descriptor overflow : %u\n", 2974 stats->rx_desc_oflows); 2975 kprintf("Receive frames with alignment errors : %u\n", 2976 stats->rx_alignerrs); 2977 kprintf("Receive frames dropped due to address filtering : %ju\n", 2978 (uint64_t)stats->rx_pkts_filtered); 2979 2980 return (error); 2981 } 2982 2983 static int 2984 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 2985 { 2986 2987 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 2988 AGE_IM_TIMER_MAX)); 2989 } 2990 2991 static void 2992 age_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs, 2993 bus_size_t mapsz __unused, int error) 2994 { 2995 struct age_dmamap_ctx *ctx = xctx; 2996 int i; 2997 2998 if (error) 2999 return; 3000 3001 if (nsegs > ctx->nsegs) { 3002 ctx->nsegs = 0; 3003 return; 3004 } 3005 3006 ctx->nsegs = nsegs; 3007 for (i = 0; i < nsegs; ++i) 3008 ctx->segs[i] = segs[i]; 3009 } 3010