1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/age/if_age.c,v 1.6 2008/11/07 07:02:28 yongari Exp $ 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/interrupt.h> 37 #include <sys/malloc.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/serialize.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/bpf.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/ifq_var.h> 52 #include <net/vlan/if_vlan_var.h> 53 #include <net/vlan/if_vlan_ether.h> 54 55 #include <dev/netif/mii_layer/miivar.h> 56 #include <dev/netif/mii_layer/jmphyreg.h> 57 58 #include <bus/pci/pcireg.h> 59 #include <bus/pci/pcivar.h> 60 #include "pcidevs.h" 61 62 #include <dev/netif/age/if_agereg.h> 63 #include <dev/netif/age/if_agevar.h> 64 65 /* "device miibus" required. See GENERIC if you get errors here. */ 66 #include "miibus_if.h" 67 68 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 69 70 struct age_dmamap_ctx { 71 int nsegs; 72 bus_dma_segment_t *segs; 73 }; 74 75 static int age_probe(device_t); 76 static int age_attach(device_t); 77 static int age_detach(device_t); 78 static int age_shutdown(device_t); 79 static int age_suspend(device_t); 80 static int age_resume(device_t); 81 82 static int age_miibus_readreg(device_t, int, int); 83 static int age_miibus_writereg(device_t, int, int, int); 84 static void age_miibus_statchg(device_t); 85 86 static void age_init(void *); 87 static int age_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 88 static void age_start(struct ifnet *, struct ifaltq_subque *); 89 static void age_watchdog(struct ifnet *); 90 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 91 static int age_mediachange(struct ifnet *); 92 93 static void age_intr(void *); 94 static void age_txintr(struct age_softc *, int); 95 static void age_rxintr(struct age_softc *, int); 96 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 97 98 static int age_dma_alloc(struct age_softc *); 99 static void age_dma_free(struct age_softc *); 100 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 101 static void age_dmamap_buf_cb(void *, bus_dma_segment_t *, int, 102 bus_size_t, int); 103 static int age_check_boundary(struct age_softc *); 104 static int age_newbuf(struct age_softc *, struct age_rxdesc *, int); 105 static int age_encap(struct age_softc *, struct mbuf **); 106 static void age_init_tx_ring(struct age_softc *); 107 static int age_init_rx_ring(struct age_softc *); 108 static void age_init_rr_ring(struct age_softc *); 109 static void age_init_cmb_block(struct age_softc *); 110 static void age_init_smb_block(struct age_softc *); 111 112 static void age_tick(void *); 113 static void age_stop(struct age_softc *); 114 static void age_reset(struct age_softc *); 115 static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t, 116 uint32_t *); 117 static void age_get_macaddr(struct age_softc *); 118 static void age_phy_reset(struct age_softc *); 119 static void age_mac_config(struct age_softc *); 120 static void age_stats_update(struct age_softc *); 121 static void age_stop_txmac(struct age_softc *); 122 static void age_stop_rxmac(struct age_softc *); 123 static void age_rxvlan(struct age_softc *); 124 static void age_rxfilter(struct age_softc *); 125 #ifdef wol_notyet 126 static void age_setwol(struct age_softc *); 127 #endif 128 129 static void age_sysctl_node(struct age_softc *); 130 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 131 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 132 133 /* 134 * Devices supported by this driver. 135 */ 136 static struct age_dev { 137 uint16_t age_vendorid; 138 uint16_t age_deviceid; 139 const char *age_name; 140 } age_devs[] = { 141 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 142 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 143 }; 144 145 static device_method_t age_methods[] = { 146 /* Device interface. */ 147 DEVMETHOD(device_probe, age_probe), 148 DEVMETHOD(device_attach, age_attach), 149 DEVMETHOD(device_detach, age_detach), 150 DEVMETHOD(device_shutdown, age_shutdown), 151 DEVMETHOD(device_suspend, age_suspend), 152 DEVMETHOD(device_resume, age_resume), 153 154 /* Bus interface. */ 155 DEVMETHOD(bus_print_child, bus_generic_print_child), 156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 157 158 /* MII interface. */ 159 DEVMETHOD(miibus_readreg, age_miibus_readreg), 160 DEVMETHOD(miibus_writereg, age_miibus_writereg), 161 DEVMETHOD(miibus_statchg, age_miibus_statchg), 162 163 { NULL, NULL } 164 }; 165 166 static driver_t age_driver = { 167 "age", 168 age_methods, 169 sizeof(struct age_softc) 170 }; 171 172 static devclass_t age_devclass; 173 174 DECLARE_DUMMY_MODULE(if_age); 175 MODULE_DEPEND(if_age, miibus, 1, 1, 1); 176 DRIVER_MODULE(if_age, pci, age_driver, age_devclass, NULL, NULL); 177 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, NULL, NULL); 178 179 /* 180 * Read a PHY register on the MII of the L1. 181 */ 182 static int 183 age_miibus_readreg(device_t dev, int phy, int reg) 184 { 185 struct age_softc *sc; 186 uint32_t v; 187 int i; 188 189 sc = device_get_softc(dev); 190 if (phy != sc->age_phyaddr) 191 return (0); 192 193 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 194 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 195 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 196 DELAY(1); 197 v = CSR_READ_4(sc, AGE_MDIO); 198 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 199 break; 200 } 201 202 if (i == 0) { 203 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 204 return (0); 205 } 206 207 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 208 } 209 210 /* 211 * Write a PHY register on the MII of the L1. 212 */ 213 static int 214 age_miibus_writereg(device_t dev, int phy, int reg, int val) 215 { 216 struct age_softc *sc; 217 uint32_t v; 218 int i; 219 220 sc = device_get_softc(dev); 221 if (phy != sc->age_phyaddr) 222 return (0); 223 224 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 225 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 226 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 227 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 228 DELAY(1); 229 v = CSR_READ_4(sc, AGE_MDIO); 230 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 231 break; 232 } 233 234 if (i == 0) 235 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 236 237 return (0); 238 } 239 240 /* 241 * Callback from MII layer when media changes. 242 */ 243 static void 244 age_miibus_statchg(device_t dev) 245 { 246 struct age_softc *sc = device_get_softc(dev); 247 struct ifnet *ifp = &sc->arpcom.ac_if; 248 struct mii_data *mii; 249 250 ASSERT_SERIALIZED(ifp->if_serializer); 251 252 if ((ifp->if_flags & IFF_RUNNING) == 0) 253 return; 254 255 mii = device_get_softc(sc->age_miibus); 256 257 sc->age_flags &= ~AGE_FLAG_LINK; 258 if ((mii->mii_media_status & IFM_AVALID) != 0) { 259 switch (IFM_SUBTYPE(mii->mii_media_active)) { 260 case IFM_10_T: 261 case IFM_100_TX: 262 case IFM_1000_T: 263 sc->age_flags |= AGE_FLAG_LINK; 264 break; 265 default: 266 break; 267 } 268 } 269 270 /* Stop Rx/Tx MACs. */ 271 age_stop_rxmac(sc); 272 age_stop_txmac(sc); 273 274 /* Program MACs with resolved speed/duplex/flow-control. */ 275 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 276 uint32_t reg; 277 278 age_mac_config(sc); 279 280 reg = CSR_READ_4(sc, AGE_MAC_CFG); 281 /* Restart DMA engine and Tx/Rx MAC. */ 282 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 283 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 284 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 285 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 286 } 287 } 288 289 /* 290 * Get the current interface media status. 291 */ 292 static void 293 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 294 { 295 struct age_softc *sc = ifp->if_softc; 296 struct mii_data *mii = device_get_softc(sc->age_miibus); 297 298 ASSERT_SERIALIZED(ifp->if_serializer); 299 300 mii_pollstat(mii); 301 ifmr->ifm_status = mii->mii_media_status; 302 ifmr->ifm_active = mii->mii_media_active; 303 } 304 305 /* 306 * Set hardware to newly-selected media. 307 */ 308 static int 309 age_mediachange(struct ifnet *ifp) 310 { 311 struct age_softc *sc = ifp->if_softc; 312 struct mii_data *mii = device_get_softc(sc->age_miibus); 313 int error; 314 315 ASSERT_SERIALIZED(ifp->if_serializer); 316 317 if (mii->mii_instance != 0) { 318 struct mii_softc *miisc; 319 320 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 321 mii_phy_reset(miisc); 322 } 323 error = mii_mediachg(mii); 324 325 return (error); 326 } 327 328 static int 329 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset, 330 uint32_t *word) 331 { 332 int i; 333 334 pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2); 335 for (i = AGE_TIMEOUT; i > 0; i--) { 336 DELAY(10); 337 if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) & 338 0x8000) == 0x8000) 339 break; 340 } 341 if (i == 0) { 342 device_printf(sc->age_dev, "VPD read timeout!\n"); 343 *word = 0; 344 return (ETIMEDOUT); 345 } 346 347 *word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4); 348 return (0); 349 } 350 351 static int 352 age_probe(device_t dev) 353 { 354 struct age_dev *sp; 355 int i; 356 uint16_t vendor, devid; 357 358 vendor = pci_get_vendor(dev); 359 devid = pci_get_device(dev); 360 sp = age_devs; 361 for (i = 0; i < NELEM(age_devs); i++, sp++) { 362 if (vendor == sp->age_vendorid && 363 devid == sp->age_deviceid) { 364 device_set_desc(dev, sp->age_name); 365 return (0); 366 } 367 } 368 return (ENXIO); 369 } 370 371 static void 372 age_get_macaddr(struct age_softc *sc) 373 { 374 uint32_t ea[2], off, reg, word; 375 int vpd_error, match, vpdc; 376 377 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 378 if ((reg & SPI_VPD_ENB) != 0) { 379 /* Get VPD stored in TWSI EEPROM. */ 380 reg &= ~SPI_VPD_ENB; 381 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 382 } 383 384 ea[0] = ea[1] = 0; 385 vpdc = pci_get_vpdcap_ptr(sc->age_dev); 386 if (vpdc) { 387 vpd_error = 0; 388 389 /* 390 * PCI VPD capability exists, but it seems that it's 391 * not in the standard form as stated in PCI VPD 392 * specification such that driver could not use 393 * pci_get_vpd_readonly(9) with keyword 'NA'. 394 * Search VPD data starting at address 0x0100. The data 395 * should be used as initializers to set AGE_PAR0, 396 * AGE_PAR1 register including other PCI configuration 397 * registers. 398 */ 399 word = 0; 400 match = 0; 401 reg = 0; 402 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END; 403 off += sizeof(uint32_t)) { 404 vpd_error = age_read_vpd_word(sc, vpdc, off, &word); 405 if (vpd_error != 0) 406 break; 407 if (match != 0) { 408 switch (reg) { 409 case AGE_PAR0: 410 ea[0] = word; 411 break; 412 case AGE_PAR1: 413 ea[1] = word; 414 break; 415 default: 416 break; 417 } 418 match = 0; 419 } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) { 420 match = 1; 421 reg = word >> 16; 422 } else 423 break; 424 } 425 if (off >= AGE_VPD_REG_CONF_END) 426 vpd_error = ENOENT; 427 if (vpd_error == 0) { 428 /* 429 * Don't blindly trust ethernet address obtained 430 * from VPD. Check whether ethernet address is 431 * valid one. Otherwise fall-back to reading 432 * PAR register. 433 */ 434 ea[1] &= 0xFFFF; 435 if ((ea[0] == 0 && ea[1] == 0) || 436 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 437 if (bootverbose) 438 device_printf(sc->age_dev, 439 "invalid ethernet address " 440 "returned from VPD.\n"); 441 vpd_error = EINVAL; 442 } 443 } 444 if (vpd_error != 0 && (bootverbose)) 445 device_printf(sc->age_dev, "VPD access failure!\n"); 446 } else { 447 vpd_error = ENOENT; 448 if (bootverbose) 449 device_printf(sc->age_dev, 450 "PCI VPD capability not found!\n"); 451 } 452 453 /* 454 * It seems that L1 also provides a way to extract ethernet 455 * address via SPI flash interface. Because SPI flash memory 456 * device of different vendors vary in their instruction 457 * codes for read ID instruction, it's very hard to get 458 * instructions codes without detailed information for the 459 * flash memory device used on ethernet controller. To simplify 460 * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet 461 * address which is supposed to be set by hardware during 462 * power on reset. 463 */ 464 if (vpd_error != 0) { 465 /* 466 * VPD is mapped to SPI flash memory or BIOS set it. 467 */ 468 ea[0] = CSR_READ_4(sc, AGE_PAR0); 469 ea[1] = CSR_READ_4(sc, AGE_PAR1); 470 } 471 472 ea[1] &= 0xFFFF; 473 if ((ea[0] == 0 && ea[1] == 0) || 474 (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) { 475 device_printf(sc->age_dev, 476 "generating fake ethernet address.\n"); 477 ea[0] = karc4random(); 478 /* Set OUI to ASUSTek COMPUTER INC. */ 479 sc->age_eaddr[0] = 0x00; 480 sc->age_eaddr[1] = 0x1B; 481 sc->age_eaddr[2] = 0xFC; 482 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 483 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 484 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 485 } else { 486 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 487 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 488 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 489 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 490 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 491 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 492 } 493 } 494 495 static void 496 age_phy_reset(struct age_softc *sc) 497 { 498 /* Reset PHY. */ 499 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 500 DELAY(1000); 501 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 502 DELAY(1000); 503 } 504 505 static int 506 age_attach(device_t dev) 507 { 508 struct age_softc *sc = device_get_softc(dev); 509 struct ifnet *ifp = &sc->arpcom.ac_if; 510 uint8_t pcie_ptr; 511 int error; 512 513 error = 0; 514 sc->age_dev = dev; 515 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 516 517 callout_init(&sc->age_tick_ch); 518 519 #ifndef BURN_BRIDGES 520 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 521 uint32_t irq, mem; 522 523 irq = pci_read_config(dev, PCIR_INTLINE, 4); 524 mem = pci_read_config(dev, AGE_PCIR_BAR, 4); 525 526 device_printf(dev, "chip is in D%d power mode " 527 "-- setting to D0\n", pci_get_powerstate(dev)); 528 529 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 530 531 pci_write_config(dev, PCIR_INTLINE, irq, 4); 532 pci_write_config(dev, AGE_PCIR_BAR, mem, 4); 533 } 534 #endif /* !BURN_BRIDGE */ 535 536 /* Enable bus mastering */ 537 pci_enable_busmaster(dev); 538 539 /* 540 * Allocate memory mapped IO 541 */ 542 sc->age_mem_rid = AGE_PCIR_BAR; 543 sc->age_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 544 &sc->age_mem_rid, RF_ACTIVE); 545 if (sc->age_mem_res == NULL) { 546 device_printf(dev, "can't allocate IO memory\n"); 547 return ENXIO; 548 } 549 sc->age_mem_bt = rman_get_bustag(sc->age_mem_res); 550 sc->age_mem_bh = rman_get_bushandle(sc->age_mem_res); 551 552 /* 553 * Allocate IRQ 554 */ 555 sc->age_irq_rid = 0; 556 sc->age_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 557 &sc->age_irq_rid, 558 RF_SHAREABLE | RF_ACTIVE); 559 if (sc->age_irq_res == NULL) { 560 device_printf(dev, "can't allocate irq\n"); 561 error = ENXIO; 562 goto fail; 563 } 564 565 /* Set PHY address. */ 566 sc->age_phyaddr = AGE_PHY_ADDR; 567 568 /* Reset PHY. */ 569 age_phy_reset(sc); 570 571 /* Reset the ethernet controller. */ 572 age_reset(sc); 573 574 /* Get PCI and chip id/revision. */ 575 sc->age_rev = pci_get_revid(dev); 576 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 577 MASTER_CHIP_REV_SHIFT; 578 if (bootverbose) { 579 device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev); 580 device_printf(dev, "Chip id/revision : 0x%04x\n", 581 sc->age_chip_rev); 582 } 583 584 /* 585 * XXX 586 * Unintialized hardware returns an invalid chip id/revision 587 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 588 * unplugged cable results in putting hardware into automatic 589 * power down mode which in turn returns invalld chip revision. 590 */ 591 if (sc->age_chip_rev == 0xFFFF) { 592 device_printf(dev,"invalid chip revision : 0x%04x -- " 593 "not initialized?\n", sc->age_chip_rev); 594 error = ENXIO; 595 goto fail; 596 } 597 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 598 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 599 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 600 601 /* Get DMA parameters from PCIe device control register. */ 602 pcie_ptr = pci_get_pciecap_ptr(dev); 603 if (pcie_ptr) { 604 uint16_t devctl; 605 606 sc->age_flags |= AGE_FLAG_PCIE; 607 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 608 /* Max read request size. */ 609 sc->age_dma_rd_burst = ((devctl >> 12) & 0x07) << 610 DMA_CFG_RD_BURST_SHIFT; 611 /* Max payload size. */ 612 sc->age_dma_wr_burst = ((devctl >> 5) & 0x07) << 613 DMA_CFG_WR_BURST_SHIFT; 614 if (bootverbose) { 615 device_printf(dev, "Read request size : %d bytes.\n", 616 128 << ((devctl >> 12) & 0x07)); 617 device_printf(dev, "TLP payload size : %d bytes.\n", 618 128 << ((devctl >> 5) & 0x07)); 619 } 620 } else { 621 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 622 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 623 } 624 625 /* Create device sysctl node. */ 626 age_sysctl_node(sc); 627 628 if ((error = age_dma_alloc(sc)) != 0) 629 goto fail; 630 631 /* Load station address. */ 632 age_get_macaddr(sc); 633 634 ifp->if_softc = sc; 635 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 636 ifp->if_ioctl = age_ioctl; 637 ifp->if_start = age_start; 638 ifp->if_init = age_init; 639 ifp->if_watchdog = age_watchdog; 640 ifq_set_maxlen(&ifp->if_snd, AGE_TX_RING_CNT - 1); 641 ifq_set_ready(&ifp->if_snd); 642 643 ifp->if_capabilities = IFCAP_HWCSUM | 644 IFCAP_VLAN_MTU | 645 IFCAP_VLAN_HWTAGGING; 646 ifp->if_hwassist = AGE_CSUM_FEATURES; 647 ifp->if_capenable = ifp->if_capabilities; 648 649 /* Set up MII bus. */ 650 if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange, 651 age_mediastatus)) != 0) { 652 device_printf(dev, "no PHY found!\n"); 653 goto fail; 654 } 655 656 ether_ifattach(ifp, sc->age_eaddr, NULL); 657 658 /* Tell the upper layer(s) we support long frames. */ 659 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 660 661 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->age_irq_res)); 662 663 error = bus_setup_intr(dev, sc->age_irq_res, INTR_MPSAFE, age_intr, sc, 664 &sc->age_irq_handle, ifp->if_serializer); 665 if (error) { 666 device_printf(dev, "could not set up interrupt handler.\n"); 667 ether_ifdetach(ifp); 668 goto fail; 669 } 670 671 return 0; 672 fail: 673 age_detach(dev); 674 return (error); 675 } 676 677 static int 678 age_detach(device_t dev) 679 { 680 struct age_softc *sc = device_get_softc(dev); 681 682 if (device_is_attached(dev)) { 683 struct ifnet *ifp = &sc->arpcom.ac_if; 684 685 lwkt_serialize_enter(ifp->if_serializer); 686 sc->age_flags |= AGE_FLAG_DETACH; 687 age_stop(sc); 688 bus_teardown_intr(dev, sc->age_irq_res, sc->age_irq_handle); 689 lwkt_serialize_exit(ifp->if_serializer); 690 691 ether_ifdetach(ifp); 692 } 693 694 if (sc->age_miibus != NULL) 695 device_delete_child(dev, sc->age_miibus); 696 bus_generic_detach(dev); 697 698 if (sc->age_irq_res != NULL) { 699 bus_release_resource(dev, SYS_RES_IRQ, sc->age_irq_rid, 700 sc->age_irq_res); 701 } 702 if (sc->age_mem_res != NULL) { 703 bus_release_resource(dev, SYS_RES_MEMORY, sc->age_mem_rid, 704 sc->age_mem_res); 705 } 706 707 age_dma_free(sc); 708 709 return (0); 710 } 711 712 static void 713 age_sysctl_node(struct age_softc *sc) 714 { 715 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->age_dev); 716 struct sysctl_oid *tree = device_get_sysctl_tree(sc->age_dev); 717 int error; 718 719 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 720 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 721 "I", "Statistics"); 722 723 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 724 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 725 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 726 727 /* Pull in device tunables. */ 728 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 729 error = resource_int_value(device_get_name(sc->age_dev), 730 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 731 if (error == 0) { 732 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 733 sc->age_int_mod > AGE_IM_TIMER_MAX) { 734 device_printf(sc->age_dev, 735 "int_mod value out of range; using default: %d\n", 736 AGE_IM_TIMER_DEFAULT); 737 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 738 } 739 } 740 } 741 742 struct age_dmamap_arg { 743 bus_addr_t age_busaddr; 744 }; 745 746 static void 747 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 748 { 749 struct age_dmamap_arg *ctx; 750 751 if (error != 0) 752 return; 753 754 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 755 756 ctx = (struct age_dmamap_arg *)arg; 757 ctx->age_busaddr = segs[0].ds_addr; 758 } 759 760 /* 761 * Attansic L1 controller have single register to specify high 762 * address part of DMA blocks. So all descriptor structures and 763 * DMA memory blocks should have the same high address of given 764 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 765 */ 766 static int 767 age_check_boundary(struct age_softc *sc) 768 { 769 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 770 bus_addr_t cmb_block_end, smb_block_end; 771 772 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 773 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 774 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 775 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 776 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 777 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 778 779 if ((AGE_ADDR_HI(tx_ring_end) != 780 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 781 (AGE_ADDR_HI(rx_ring_end) != 782 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 783 (AGE_ADDR_HI(rr_ring_end) != 784 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 785 (AGE_ADDR_HI(cmb_block_end) != 786 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 787 (AGE_ADDR_HI(smb_block_end) != 788 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 789 return (EFBIG); 790 791 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 792 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 793 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 794 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 795 return (EFBIG); 796 797 return (0); 798 } 799 800 static int 801 age_dma_alloc(struct age_softc *sc) 802 { 803 struct age_txdesc *txd; 804 struct age_rxdesc *rxd; 805 bus_addr_t lowaddr; 806 struct age_dmamap_arg ctx; 807 int error, i; 808 809 lowaddr = BUS_SPACE_MAXADDR; 810 again: 811 /* Create parent ring/DMA block tag. */ 812 error = bus_dma_tag_create( 813 NULL, /* parent */ 814 1, 0, /* alignment, boundary */ 815 lowaddr, /* lowaddr */ 816 BUS_SPACE_MAXADDR, /* highaddr */ 817 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 818 0, /* nsegments */ 819 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 820 0, /* flags */ 821 &sc->age_cdata.age_parent_tag); 822 if (error != 0) { 823 device_printf(sc->age_dev, 824 "could not create parent DMA tag.\n"); 825 goto fail; 826 } 827 828 /* Create tag for Tx ring. */ 829 error = bus_dma_tag_create( 830 sc->age_cdata.age_parent_tag, /* parent */ 831 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 832 BUS_SPACE_MAXADDR, /* lowaddr */ 833 BUS_SPACE_MAXADDR, /* highaddr */ 834 AGE_TX_RING_SZ, /* maxsize */ 835 1, /* nsegments */ 836 AGE_TX_RING_SZ, /* maxsegsize */ 837 0, /* flags */ 838 &sc->age_cdata.age_tx_ring_tag); 839 if (error != 0) { 840 device_printf(sc->age_dev, 841 "could not create Tx ring DMA tag.\n"); 842 goto fail; 843 } 844 845 /* Create tag for Rx ring. */ 846 error = bus_dma_tag_create( 847 sc->age_cdata.age_parent_tag, /* parent */ 848 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 849 BUS_SPACE_MAXADDR, /* lowaddr */ 850 BUS_SPACE_MAXADDR, /* highaddr */ 851 AGE_RX_RING_SZ, /* maxsize */ 852 1, /* nsegments */ 853 AGE_RX_RING_SZ, /* maxsegsize */ 854 0, /* flags */ 855 &sc->age_cdata.age_rx_ring_tag); 856 if (error != 0) { 857 device_printf(sc->age_dev, 858 "could not create Rx ring DMA tag.\n"); 859 goto fail; 860 } 861 862 /* Create tag for Rx return ring. */ 863 error = bus_dma_tag_create( 864 sc->age_cdata.age_parent_tag, /* parent */ 865 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 866 BUS_SPACE_MAXADDR, /* lowaddr */ 867 BUS_SPACE_MAXADDR, /* highaddr */ 868 AGE_RR_RING_SZ, /* maxsize */ 869 1, /* nsegments */ 870 AGE_RR_RING_SZ, /* maxsegsize */ 871 0, /* flags */ 872 &sc->age_cdata.age_rr_ring_tag); 873 if (error != 0) { 874 device_printf(sc->age_dev, 875 "could not create Rx return ring DMA tag.\n"); 876 goto fail; 877 } 878 879 /* Create tag for coalesing message block. */ 880 error = bus_dma_tag_create( 881 sc->age_cdata.age_parent_tag, /* parent */ 882 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 883 BUS_SPACE_MAXADDR, /* lowaddr */ 884 BUS_SPACE_MAXADDR, /* highaddr */ 885 AGE_CMB_BLOCK_SZ, /* maxsize */ 886 1, /* nsegments */ 887 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 888 0, /* flags */ 889 &sc->age_cdata.age_cmb_block_tag); 890 if (error != 0) { 891 device_printf(sc->age_dev, 892 "could not create CMB DMA tag.\n"); 893 goto fail; 894 } 895 896 /* Create tag for statistics message block. */ 897 error = bus_dma_tag_create( 898 sc->age_cdata.age_parent_tag, /* parent */ 899 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 900 BUS_SPACE_MAXADDR, /* lowaddr */ 901 BUS_SPACE_MAXADDR, /* highaddr */ 902 AGE_SMB_BLOCK_SZ, /* maxsize */ 903 1, /* nsegments */ 904 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 905 0, /* flags */ 906 &sc->age_cdata.age_smb_block_tag); 907 if (error != 0) { 908 device_printf(sc->age_dev, 909 "could not create SMB DMA tag.\n"); 910 goto fail; 911 } 912 913 /* Allocate DMA'able memory and load the DMA map. */ 914 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 915 (void **)&sc->age_rdata.age_tx_ring, 916 BUS_DMA_WAITOK | BUS_DMA_ZERO, 917 &sc->age_cdata.age_tx_ring_map); 918 if (error != 0) { 919 device_printf(sc->age_dev, 920 "could not allocate DMA'able memory for Tx ring.\n"); 921 goto fail; 922 } 923 ctx.age_busaddr = 0; 924 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 925 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 926 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 927 if (error != 0 || ctx.age_busaddr == 0) { 928 device_printf(sc->age_dev, 929 "could not load DMA'able memory for Tx ring.\n"); 930 goto fail; 931 } 932 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 933 /* Rx ring */ 934 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 935 (void **)&sc->age_rdata.age_rx_ring, 936 BUS_DMA_WAITOK | BUS_DMA_ZERO, 937 &sc->age_cdata.age_rx_ring_map); 938 if (error != 0) { 939 device_printf(sc->age_dev, 940 "could not allocate DMA'able memory for Rx ring.\n"); 941 goto fail; 942 } 943 ctx.age_busaddr = 0; 944 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 945 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 946 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 947 if (error != 0 || ctx.age_busaddr == 0) { 948 device_printf(sc->age_dev, 949 "could not load DMA'able memory for Rx ring.\n"); 950 goto fail; 951 } 952 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 953 /* Rx return ring */ 954 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 955 (void **)&sc->age_rdata.age_rr_ring, 956 BUS_DMA_WAITOK | BUS_DMA_ZERO, 957 &sc->age_cdata.age_rr_ring_map); 958 if (error != 0) { 959 device_printf(sc->age_dev, 960 "could not allocate DMA'able memory for Rx return ring.\n"); 961 goto fail; 962 } 963 ctx.age_busaddr = 0; 964 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 965 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 966 AGE_RR_RING_SZ, age_dmamap_cb, &ctx, 0); 967 if (error != 0 || ctx.age_busaddr == 0) { 968 device_printf(sc->age_dev, 969 "could not load DMA'able memory for Rx return ring.\n"); 970 goto fail; 971 } 972 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 973 /* CMB block */ 974 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 975 (void **)&sc->age_rdata.age_cmb_block, 976 BUS_DMA_WAITOK | BUS_DMA_ZERO, 977 &sc->age_cdata.age_cmb_block_map); 978 if (error != 0) { 979 device_printf(sc->age_dev, 980 "could not allocate DMA'able memory for CMB block.\n"); 981 goto fail; 982 } 983 ctx.age_busaddr = 0; 984 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 985 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 986 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 987 if (error != 0 || ctx.age_busaddr == 0) { 988 device_printf(sc->age_dev, 989 "could not load DMA'able memory for CMB block.\n"); 990 goto fail; 991 } 992 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 993 /* SMB block */ 994 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 995 (void **)&sc->age_rdata.age_smb_block, 996 BUS_DMA_WAITOK | BUS_DMA_ZERO, 997 &sc->age_cdata.age_smb_block_map); 998 if (error != 0) { 999 device_printf(sc->age_dev, 1000 "could not allocate DMA'able memory for SMB block.\n"); 1001 goto fail; 1002 } 1003 ctx.age_busaddr = 0; 1004 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1005 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1006 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1007 if (error != 0 || ctx.age_busaddr == 0) { 1008 device_printf(sc->age_dev, 1009 "could not load DMA'able memory for SMB block.\n"); 1010 goto fail; 1011 } 1012 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1013 1014 /* 1015 * All ring buffer and DMA blocks should have the same 1016 * high address part of 64bit DMA address space. 1017 */ 1018 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1019 (error = age_check_boundary(sc)) != 0) { 1020 device_printf(sc->age_dev, "4GB boundary crossed, " 1021 "switching to 32bit DMA addressing mode.\n"); 1022 age_dma_free(sc); 1023 /* Limit DMA address space to 32bit and try again. */ 1024 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1025 goto again; 1026 } 1027 1028 /* 1029 * Create Tx/Rx buffer parent tag. 1030 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1031 * so it needs separate parent DMA tag. 1032 */ 1033 error = bus_dma_tag_create( 1034 NULL, /* parent */ 1035 1, 0, /* alignment, boundary */ 1036 BUS_SPACE_MAXADDR, /* lowaddr */ 1037 BUS_SPACE_MAXADDR, /* highaddr */ 1038 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1039 0, /* nsegments */ 1040 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1041 0, /* flags */ 1042 &sc->age_cdata.age_buffer_tag); 1043 if (error != 0) { 1044 device_printf(sc->age_dev, 1045 "could not create parent buffer DMA tag.\n"); 1046 goto fail; 1047 } 1048 1049 /* Create tag for Tx buffers. */ 1050 error = bus_dma_tag_create( 1051 sc->age_cdata.age_buffer_tag, /* parent */ 1052 1, 0, /* alignment, boundary */ 1053 BUS_SPACE_MAXADDR, /* lowaddr */ 1054 BUS_SPACE_MAXADDR, /* highaddr */ 1055 AGE_TSO_MAXSIZE, /* maxsize */ 1056 AGE_MAXTXSEGS, /* nsegments */ 1057 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1058 0, /* flags */ 1059 &sc->age_cdata.age_tx_tag); 1060 if (error != 0) { 1061 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1062 goto fail; 1063 } 1064 1065 /* Create tag for Rx buffers. */ 1066 error = bus_dma_tag_create( 1067 sc->age_cdata.age_buffer_tag, /* parent */ 1068 1, 0, /* alignment, boundary */ 1069 BUS_SPACE_MAXADDR, /* lowaddr */ 1070 BUS_SPACE_MAXADDR, /* highaddr */ 1071 MCLBYTES, /* maxsize */ 1072 1, /* nsegments */ 1073 MCLBYTES, /* maxsegsize */ 1074 0, /* flags */ 1075 &sc->age_cdata.age_rx_tag); 1076 if (error != 0) { 1077 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1078 goto fail; 1079 } 1080 1081 /* Create DMA maps for Tx buffers. */ 1082 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1083 txd = &sc->age_cdata.age_txdesc[i]; 1084 txd->tx_m = NULL; 1085 txd->tx_dmamap = NULL; 1086 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1087 &txd->tx_dmamap); 1088 if (error != 0) { 1089 device_printf(sc->age_dev, 1090 "could not create Tx dmamap.\n"); 1091 goto fail; 1092 } 1093 } 1094 /* Create DMA maps for Rx buffers. */ 1095 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1096 &sc->age_cdata.age_rx_sparemap)) != 0) { 1097 device_printf(sc->age_dev, 1098 "could not create spare Rx dmamap.\n"); 1099 goto fail; 1100 } 1101 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1102 rxd = &sc->age_cdata.age_rxdesc[i]; 1103 rxd->rx_m = NULL; 1104 rxd->rx_dmamap = NULL; 1105 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1106 &rxd->rx_dmamap); 1107 if (error != 0) { 1108 device_printf(sc->age_dev, 1109 "could not create Rx dmamap.\n"); 1110 goto fail; 1111 } 1112 } 1113 fail: 1114 return (error); 1115 } 1116 1117 static void 1118 age_dma_free(struct age_softc *sc) 1119 { 1120 struct age_txdesc *txd; 1121 struct age_rxdesc *rxd; 1122 int i; 1123 1124 /* Tx buffers */ 1125 if (sc->age_cdata.age_tx_tag != NULL) { 1126 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1127 txd = &sc->age_cdata.age_txdesc[i]; 1128 if (txd->tx_dmamap != NULL) { 1129 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1130 txd->tx_dmamap); 1131 txd->tx_dmamap = NULL; 1132 } 1133 } 1134 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1135 sc->age_cdata.age_tx_tag = NULL; 1136 } 1137 /* Rx buffers */ 1138 if (sc->age_cdata.age_rx_tag != NULL) { 1139 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1140 rxd = &sc->age_cdata.age_rxdesc[i]; 1141 if (rxd->rx_dmamap != NULL) { 1142 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1143 rxd->rx_dmamap); 1144 rxd->rx_dmamap = NULL; 1145 } 1146 } 1147 if (sc->age_cdata.age_rx_sparemap != NULL) { 1148 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1149 sc->age_cdata.age_rx_sparemap); 1150 sc->age_cdata.age_rx_sparemap = NULL; 1151 } 1152 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1153 sc->age_cdata.age_rx_tag = NULL; 1154 } 1155 /* Tx ring. */ 1156 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1157 if (sc->age_cdata.age_tx_ring_map != NULL) 1158 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1159 sc->age_cdata.age_tx_ring_map); 1160 if (sc->age_cdata.age_tx_ring_map != NULL && 1161 sc->age_rdata.age_tx_ring != NULL) 1162 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1163 sc->age_rdata.age_tx_ring, 1164 sc->age_cdata.age_tx_ring_map); 1165 sc->age_rdata.age_tx_ring = NULL; 1166 sc->age_cdata.age_tx_ring_map = NULL; 1167 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1168 sc->age_cdata.age_tx_ring_tag = NULL; 1169 } 1170 /* Rx ring. */ 1171 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1172 if (sc->age_cdata.age_rx_ring_map != NULL) 1173 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1174 sc->age_cdata.age_rx_ring_map); 1175 if (sc->age_cdata.age_rx_ring_map != NULL && 1176 sc->age_rdata.age_rx_ring != NULL) 1177 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1178 sc->age_rdata.age_rx_ring, 1179 sc->age_cdata.age_rx_ring_map); 1180 sc->age_rdata.age_rx_ring = NULL; 1181 sc->age_cdata.age_rx_ring_map = NULL; 1182 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1183 sc->age_cdata.age_rx_ring_tag = NULL; 1184 } 1185 /* Rx return ring. */ 1186 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1187 if (sc->age_cdata.age_rr_ring_map != NULL) 1188 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1189 sc->age_cdata.age_rr_ring_map); 1190 if (sc->age_cdata.age_rr_ring_map != NULL && 1191 sc->age_rdata.age_rr_ring != NULL) 1192 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1193 sc->age_rdata.age_rr_ring, 1194 sc->age_cdata.age_rr_ring_map); 1195 sc->age_rdata.age_rr_ring = NULL; 1196 sc->age_cdata.age_rr_ring_map = NULL; 1197 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1198 sc->age_cdata.age_rr_ring_tag = NULL; 1199 } 1200 /* CMB block */ 1201 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1202 if (sc->age_cdata.age_cmb_block_map != NULL) 1203 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1204 sc->age_cdata.age_cmb_block_map); 1205 if (sc->age_cdata.age_cmb_block_map != NULL && 1206 sc->age_rdata.age_cmb_block != NULL) 1207 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1208 sc->age_rdata.age_cmb_block, 1209 sc->age_cdata.age_cmb_block_map); 1210 sc->age_rdata.age_cmb_block = NULL; 1211 sc->age_cdata.age_cmb_block_map = NULL; 1212 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1213 sc->age_cdata.age_cmb_block_tag = NULL; 1214 } 1215 /* SMB block */ 1216 if (sc->age_cdata.age_smb_block_tag != NULL) { 1217 if (sc->age_cdata.age_smb_block_map != NULL) 1218 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1219 sc->age_cdata.age_smb_block_map); 1220 if (sc->age_cdata.age_smb_block_map != NULL && 1221 sc->age_rdata.age_smb_block != NULL) 1222 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1223 sc->age_rdata.age_smb_block, 1224 sc->age_cdata.age_smb_block_map); 1225 sc->age_rdata.age_smb_block = NULL; 1226 sc->age_cdata.age_smb_block_map = NULL; 1227 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1228 sc->age_cdata.age_smb_block_tag = NULL; 1229 } 1230 1231 if (sc->age_cdata.age_buffer_tag != NULL) { 1232 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1233 sc->age_cdata.age_buffer_tag = NULL; 1234 } 1235 if (sc->age_cdata.age_parent_tag != NULL) { 1236 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1237 sc->age_cdata.age_parent_tag = NULL; 1238 } 1239 } 1240 1241 /* 1242 * Make sure the interface is stopped at reboot time. 1243 */ 1244 static int 1245 age_shutdown(device_t dev) 1246 { 1247 return age_suspend(dev); 1248 } 1249 1250 #ifdef wol_notyet 1251 1252 static void 1253 age_setwol(struct age_softc *sc) 1254 { 1255 struct ifnet *ifp; 1256 struct mii_data *mii; 1257 uint32_t reg, pmcs; 1258 uint16_t pmstat; 1259 int aneg, i, pmc; 1260 1261 AGE_LOCK_ASSERT(sc); 1262 1263 if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) == 0) { 1264 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1265 /* 1266 * No PME capability, PHY power down. 1267 * XXX 1268 * Due to an unknown reason powering down PHY resulted 1269 * in unexpected results such as inaccessbility of 1270 * hardware of freshly rebooted system. Disable 1271 * powering down PHY until I got more information for 1272 * Attansic/Atheros PHY hardwares. 1273 */ 1274 #ifdef notyet 1275 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1276 MII_BMCR, BMCR_PDOWN); 1277 #endif 1278 return; 1279 } 1280 1281 ifp = sc->age_ifp; 1282 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1283 /* 1284 * Note, this driver resets the link speed to 10/100Mbps with 1285 * auto-negotiation but we don't know whether that operation 1286 * would succeed or not as it have no control after powering 1287 * off. If the renegotiation fail WOL may not work. Running 1288 * at 1Gbps will draw more power than 375mA at 3.3V which is 1289 * specified in PCI specification and that would result in 1290 * complete shutdowning power to ethernet controller. 1291 * 1292 * TODO 1293 * Save current negotiated media speed/duplex/flow-control 1294 * to softc and restore the same link again after resuming. 1295 * PHY handling such as power down/resetting to 100Mbps 1296 * may be better handled in suspend method in phy driver. 1297 */ 1298 mii = device_get_softc(sc->age_miibus); 1299 mii_pollstat(mii); 1300 aneg = 0; 1301 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1302 switch IFM_SUBTYPE(mii->mii_media_active) { 1303 case IFM_10_T: 1304 case IFM_100_TX: 1305 goto got_link; 1306 case IFM_1000_T: 1307 aneg++; 1308 default: 1309 break; 1310 } 1311 } 1312 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1313 MII_100T2CR, 0); 1314 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1315 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1316 ANAR_10 | ANAR_CSMA); 1317 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1318 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1319 DELAY(1000); 1320 if (aneg != 0) { 1321 /* Poll link state until age(4) get a 10/100 link. */ 1322 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1323 mii_pollstat(mii); 1324 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1325 switch (IFM_SUBTYPE( 1326 mii->mii_media_active)) { 1327 case IFM_10_T: 1328 case IFM_100_TX: 1329 age_mac_config(sc); 1330 goto got_link; 1331 default: 1332 break; 1333 } 1334 } 1335 AGE_UNLOCK(sc); 1336 pause("agelnk", hz); 1337 AGE_LOCK(sc); 1338 } 1339 if (i == MII_ANEGTICKS_GIGE) 1340 device_printf(sc->age_dev, 1341 "establishing link failed, " 1342 "WOL may not work!"); 1343 } 1344 /* 1345 * No link, force MAC to have 100Mbps, full-duplex link. 1346 * This is the last resort and may/may not work. 1347 */ 1348 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1349 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1350 age_mac_config(sc); 1351 } 1352 1353 got_link: 1354 pmcs = 0; 1355 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1356 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1357 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1358 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1359 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1360 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1361 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1362 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1363 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1364 reg |= MAC_CFG_RX_ENB; 1365 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1366 } 1367 1368 /* Request PME. */ 1369 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1370 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1371 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1372 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1373 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1374 #ifdef notyet 1375 /* See above for powering down PHY issues. */ 1376 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1377 /* No WOL, PHY power down. */ 1378 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1379 MII_BMCR, BMCR_PDOWN); 1380 } 1381 #endif 1382 } 1383 1384 #endif /* wol_notyet */ 1385 1386 static int 1387 age_suspend(device_t dev) 1388 { 1389 struct age_softc *sc = device_get_softc(dev); 1390 struct ifnet *ifp = &sc->arpcom.ac_if; 1391 1392 lwkt_serialize_enter(ifp->if_serializer); 1393 age_stop(sc); 1394 #ifdef wol_notyet 1395 age_setwol(sc); 1396 #endif 1397 lwkt_serialize_exit(ifp->if_serializer); 1398 1399 return (0); 1400 } 1401 1402 static int 1403 age_resume(device_t dev) 1404 { 1405 struct age_softc *sc = device_get_softc(dev); 1406 struct ifnet *ifp = &sc->arpcom.ac_if; 1407 uint16_t cmd; 1408 1409 lwkt_serialize_enter(ifp->if_serializer); 1410 1411 /* 1412 * Clear INTx emulation disable for hardwares that 1413 * is set in resume event. From Linux. 1414 */ 1415 cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2); 1416 if ((cmd & 0x0400) != 0) { 1417 cmd &= ~0x0400; 1418 pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2); 1419 } 1420 if ((ifp->if_flags & IFF_UP) != 0) 1421 age_init(sc); 1422 1423 lwkt_serialize_exit(ifp->if_serializer); 1424 1425 return (0); 1426 } 1427 1428 static int 1429 age_encap(struct age_softc *sc, struct mbuf **m_head) 1430 { 1431 struct age_txdesc *txd, *txd_last; 1432 struct tx_desc *desc; 1433 struct mbuf *m; 1434 struct age_dmamap_ctx ctx; 1435 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1436 bus_dmamap_t map; 1437 uint32_t cflags, poff, vtag; 1438 int error, i, nsegs, prod; 1439 1440 M_ASSERTPKTHDR((*m_head)); 1441 1442 m = *m_head; 1443 cflags = vtag = 0; 1444 poff = 0; 1445 1446 prod = sc->age_cdata.age_tx_prod; 1447 txd = &sc->age_cdata.age_txdesc[prod]; 1448 txd_last = txd; 1449 map = txd->tx_dmamap; 1450 1451 ctx.nsegs = AGE_MAXTXSEGS; 1452 ctx.segs = txsegs; 1453 error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map, 1454 *m_head, age_dmamap_buf_cb, &ctx, 1455 BUS_DMA_NOWAIT); 1456 if (!error && ctx.nsegs == 0) { 1457 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1458 error = EFBIG; 1459 } 1460 if (error == EFBIG) { 1461 m = m_defrag(*m_head, M_NOWAIT); 1462 if (m == NULL) { 1463 m_freem(*m_head); 1464 *m_head = NULL; 1465 return (ENOBUFS); 1466 } 1467 *m_head = m; 1468 1469 ctx.nsegs = AGE_MAXTXSEGS; 1470 ctx.segs = txsegs; 1471 error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map, 1472 *m_head, age_dmamap_buf_cb, &ctx, 1473 BUS_DMA_NOWAIT); 1474 if (error || ctx.nsegs == 0) { 1475 if (!error) { 1476 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 1477 map); 1478 error = EFBIG; 1479 } 1480 m_freem(*m_head); 1481 *m_head = NULL; 1482 return (error); 1483 } 1484 } else if (error != 0) { 1485 return (error); 1486 } 1487 nsegs = ctx.nsegs; 1488 1489 if (nsegs == 0) { 1490 m_freem(*m_head); 1491 *m_head = NULL; 1492 return (EIO); 1493 } 1494 1495 /* Check descriptor overrun. */ 1496 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1497 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1498 return (ENOBUFS); 1499 } 1500 1501 m = *m_head; 1502 /* Configure Tx IP/TCP/UDP checksum offload. */ 1503 if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1504 cflags |= AGE_TD_CSUM; 1505 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1506 cflags |= AGE_TD_TCPCSUM; 1507 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1508 cflags |= AGE_TD_UDPCSUM; 1509 /* Set checksum start offset. */ 1510 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1511 /* Set checksum insertion position of TCP/UDP. */ 1512 cflags |= ((poff + m->m_pkthdr.csum_data) << 1513 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1514 } 1515 1516 /* Configure VLAN hardware tag insertion. */ 1517 if ((m->m_flags & M_VLANTAG) != 0) { 1518 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag); 1519 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1520 cflags |= AGE_TD_INSERT_VLAN_TAG; 1521 } 1522 1523 desc = NULL; 1524 for (i = 0; i < nsegs; i++) { 1525 desc = &sc->age_rdata.age_tx_ring[prod]; 1526 desc->addr = htole64(txsegs[i].ds_addr); 1527 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1528 desc->flags = htole32(cflags); 1529 sc->age_cdata.age_tx_cnt++; 1530 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1531 } 1532 /* Update producer index. */ 1533 sc->age_cdata.age_tx_prod = prod; 1534 1535 /* Set EOP on the last descriptor. */ 1536 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1537 desc = &sc->age_rdata.age_tx_ring[prod]; 1538 desc->flags |= htole32(AGE_TD_EOP); 1539 1540 /* Swap dmamap of the first and the last. */ 1541 txd = &sc->age_cdata.age_txdesc[prod]; 1542 map = txd_last->tx_dmamap; 1543 txd_last->tx_dmamap = txd->tx_dmamap; 1544 txd->tx_dmamap = map; 1545 txd->tx_m = m; 1546 1547 /* Sync descriptors. */ 1548 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1549 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1550 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 1551 1552 return (0); 1553 } 1554 1555 static void 1556 age_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1557 { 1558 struct age_softc *sc = ifp->if_softc; 1559 struct mbuf *m_head; 1560 int enq; 1561 1562 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1563 ASSERT_SERIALIZED(ifp->if_serializer); 1564 1565 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1566 ifq_purge(&ifp->if_snd); 1567 return; 1568 } 1569 1570 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1571 return; 1572 1573 enq = 0; 1574 while (!ifq_is_empty(&ifp->if_snd)) { 1575 m_head = ifq_dequeue(&ifp->if_snd); 1576 if (m_head == NULL) 1577 break; 1578 1579 /* 1580 * Pack the data into the transmit ring. If we 1581 * don't have room, set the OACTIVE flag and wait 1582 * for the NIC to drain the ring. 1583 */ 1584 if (age_encap(sc, &m_head)) { 1585 if (m_head == NULL) 1586 break; 1587 ifq_prepend(&ifp->if_snd, m_head); 1588 ifq_set_oactive(&ifp->if_snd); 1589 break; 1590 } 1591 enq = 1; 1592 1593 /* 1594 * If there's a BPF listener, bounce a copy of this frame 1595 * to him. 1596 */ 1597 ETHER_BPF_MTAP(ifp, m_head); 1598 } 1599 1600 if (enq) { 1601 /* Update mbox. */ 1602 AGE_COMMIT_MBOX(sc); 1603 /* Set a timeout in case the chip goes out to lunch. */ 1604 ifp->if_timer = AGE_TX_TIMEOUT; 1605 } 1606 } 1607 1608 static void 1609 age_watchdog(struct ifnet *ifp) 1610 { 1611 struct age_softc *sc = ifp->if_softc; 1612 1613 ASSERT_SERIALIZED(ifp->if_serializer); 1614 1615 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1616 if_printf(ifp, "watchdog timeout (missed link)\n"); 1617 IFNET_STAT_INC(ifp, oerrors, 1); 1618 age_init(sc); 1619 return; 1620 } 1621 1622 if (sc->age_cdata.age_tx_cnt == 0) { 1623 if_printf(ifp, 1624 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1625 if (!ifq_is_empty(&ifp->if_snd)) 1626 if_devstart(ifp); 1627 return; 1628 } 1629 1630 if_printf(ifp, "watchdog timeout\n"); 1631 IFNET_STAT_INC(ifp, oerrors, 1); 1632 age_init(sc); 1633 if (!ifq_is_empty(&ifp->if_snd)) 1634 if_devstart(ifp); 1635 } 1636 1637 static int 1638 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1639 { 1640 struct age_softc *sc = ifp->if_softc; 1641 struct ifreq *ifr; 1642 struct mii_data *mii; 1643 uint32_t reg; 1644 int error, mask; 1645 1646 ASSERT_SERIALIZED(ifp->if_serializer); 1647 1648 ifr = (struct ifreq *)data; 1649 error = 0; 1650 switch (cmd) { 1651 case SIOCSIFMTU: 1652 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) { 1653 error = EINVAL; 1654 } else if (ifp->if_mtu != ifr->ifr_mtu) { 1655 ifp->if_mtu = ifr->ifr_mtu; 1656 if ((ifp->if_flags & IFF_RUNNING) != 0) 1657 age_init(sc); 1658 } 1659 break; 1660 1661 case SIOCSIFFLAGS: 1662 if ((ifp->if_flags & IFF_UP) != 0) { 1663 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1664 if (((ifp->if_flags ^ sc->age_if_flags) 1665 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1666 age_rxfilter(sc); 1667 } else { 1668 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1669 age_init(sc); 1670 } 1671 } else { 1672 if ((ifp->if_flags & IFF_RUNNING) != 0) 1673 age_stop(sc); 1674 } 1675 sc->age_if_flags = ifp->if_flags; 1676 break; 1677 1678 case SIOCADDMULTI: 1679 case SIOCDELMULTI: 1680 if ((ifp->if_flags & IFF_RUNNING) != 0) 1681 age_rxfilter(sc); 1682 break; 1683 1684 case SIOCSIFMEDIA: 1685 case SIOCGIFMEDIA: 1686 mii = device_get_softc(sc->age_miibus); 1687 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1688 break; 1689 1690 case SIOCSIFCAP: 1691 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1692 1693 if ((mask & IFCAP_TXCSUM) != 0 && 1694 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1695 ifp->if_capenable ^= IFCAP_TXCSUM; 1696 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1697 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1698 else 1699 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1700 } 1701 1702 if ((mask & IFCAP_RXCSUM) != 0 && 1703 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1704 ifp->if_capenable ^= IFCAP_RXCSUM; 1705 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1706 reg &= ~MAC_CFG_RXCSUM_ENB; 1707 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1708 reg |= MAC_CFG_RXCSUM_ENB; 1709 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1710 } 1711 1712 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1713 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1714 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1715 age_rxvlan(sc); 1716 } 1717 break; 1718 1719 default: 1720 error = ether_ioctl(ifp, cmd, data); 1721 break; 1722 } 1723 return (error); 1724 } 1725 1726 static void 1727 age_mac_config(struct age_softc *sc) 1728 { 1729 struct mii_data *mii = device_get_softc(sc->age_miibus); 1730 uint32_t reg; 1731 1732 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1733 reg &= ~MAC_CFG_FULL_DUPLEX; 1734 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1735 reg &= ~MAC_CFG_SPEED_MASK; 1736 1737 /* Reprogram MAC with resolved speed/duplex. */ 1738 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1739 case IFM_10_T: 1740 case IFM_100_TX: 1741 reg |= MAC_CFG_SPEED_10_100; 1742 break; 1743 case IFM_1000_T: 1744 reg |= MAC_CFG_SPEED_1000; 1745 break; 1746 } 1747 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1748 reg |= MAC_CFG_FULL_DUPLEX; 1749 #ifdef notyet 1750 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1751 reg |= MAC_CFG_TX_FC; 1752 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1753 reg |= MAC_CFG_RX_FC; 1754 #endif 1755 } 1756 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1757 } 1758 1759 static void 1760 age_stats_update(struct age_softc *sc) 1761 { 1762 struct ifnet *ifp = &sc->arpcom.ac_if; 1763 struct age_stats *stat; 1764 struct smb *smb; 1765 1766 stat = &sc->age_stat; 1767 1768 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 1769 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_POSTREAD); 1770 1771 smb = sc->age_rdata.age_smb_block; 1772 if (smb->updated == 0) 1773 return; 1774 1775 /* Rx stats. */ 1776 stat->rx_frames += smb->rx_frames; 1777 stat->rx_bcast_frames += smb->rx_bcast_frames; 1778 stat->rx_mcast_frames += smb->rx_mcast_frames; 1779 stat->rx_pause_frames += smb->rx_pause_frames; 1780 stat->rx_control_frames += smb->rx_control_frames; 1781 stat->rx_crcerrs += smb->rx_crcerrs; 1782 stat->rx_lenerrs += smb->rx_lenerrs; 1783 stat->rx_bytes += smb->rx_bytes; 1784 stat->rx_runts += smb->rx_runts; 1785 stat->rx_fragments += smb->rx_fragments; 1786 stat->rx_pkts_64 += smb->rx_pkts_64; 1787 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1788 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1789 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1790 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1791 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1792 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1793 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1794 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1795 stat->rx_desc_oflows += smb->rx_desc_oflows; 1796 stat->rx_alignerrs += smb->rx_alignerrs; 1797 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1798 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1799 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1800 1801 /* Tx stats. */ 1802 stat->tx_frames += smb->tx_frames; 1803 stat->tx_bcast_frames += smb->tx_bcast_frames; 1804 stat->tx_mcast_frames += smb->tx_mcast_frames; 1805 stat->tx_pause_frames += smb->tx_pause_frames; 1806 stat->tx_excess_defer += smb->tx_excess_defer; 1807 stat->tx_control_frames += smb->tx_control_frames; 1808 stat->tx_deferred += smb->tx_deferred; 1809 stat->tx_bytes += smb->tx_bytes; 1810 stat->tx_pkts_64 += smb->tx_pkts_64; 1811 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1812 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1813 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1814 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1815 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1816 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1817 stat->tx_single_colls += smb->tx_single_colls; 1818 stat->tx_multi_colls += smb->tx_multi_colls; 1819 stat->tx_late_colls += smb->tx_late_colls; 1820 stat->tx_excess_colls += smb->tx_excess_colls; 1821 stat->tx_underrun += smb->tx_underrun; 1822 stat->tx_desc_underrun += smb->tx_desc_underrun; 1823 stat->tx_lenerrs += smb->tx_lenerrs; 1824 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1825 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1826 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1827 1828 /* Update counters in ifnet. */ 1829 IFNET_STAT_INC(ifp, opackets, smb->tx_frames); 1830 1831 IFNET_STAT_INC(ifp, collisions, smb->tx_single_colls + 1832 smb->tx_multi_colls + smb->tx_late_colls + 1833 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 1834 1835 IFNET_STAT_INC(ifp, oerrors, smb->tx_excess_colls + 1836 smb->tx_late_colls + smb->tx_underrun + 1837 smb->tx_pkts_truncated); 1838 1839 IFNET_STAT_INC(ifp, ipackets, smb->rx_frames); 1840 1841 IFNET_STAT_INC(ifp, ierrors, smb->rx_crcerrs + smb->rx_lenerrs + 1842 smb->rx_runts + smb->rx_pkts_truncated + 1843 smb->rx_fifo_oflows + smb->rx_desc_oflows + 1844 smb->rx_alignerrs); 1845 1846 /* Update done, clear. */ 1847 smb->updated = 0; 1848 1849 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 1850 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE); 1851 } 1852 1853 static void 1854 age_intr(void *xsc) 1855 { 1856 struct age_softc *sc = xsc; 1857 struct ifnet *ifp = &sc->arpcom.ac_if; 1858 struct cmb *cmb; 1859 uint32_t status; 1860 1861 ASSERT_SERIALIZED(ifp->if_serializer); 1862 1863 status = CSR_READ_4(sc, AGE_INTR_STATUS); 1864 if (status == 0 || (status & AGE_INTRS) == 0) 1865 return; 1866 1867 /* Disable and acknowledge interrupts. */ 1868 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 1869 1870 cmb = sc->age_rdata.age_cmb_block; 1871 1872 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1873 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD); 1874 status = le32toh(cmb->intr_status); 1875 if ((status & AGE_INTRS) == 0) 1876 goto done; 1877 again: 1878 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 1879 TPD_CONS_SHIFT; 1880 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 1881 RRD_PROD_SHIFT; 1882 1883 /* Let hardware know CMB was served. */ 1884 cmb->intr_status = 0; 1885 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1886 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE); 1887 1888 #if 0 1889 kprintf("INTR: 0x%08x\n", status); 1890 status &= ~INTR_DIS_DMA; 1891 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 1892 #endif 1893 1894 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1895 if ((status & INTR_CMB_RX) != 0) 1896 age_rxintr(sc, sc->age_rr_prod); 1897 1898 if ((status & INTR_CMB_TX) != 0) 1899 age_txintr(sc, sc->age_tpd_cons); 1900 1901 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 1902 if ((status & INTR_DMA_RD_TO_RST) != 0) 1903 device_printf(sc->age_dev, 1904 "DMA read error! -- resetting\n"); 1905 if ((status & INTR_DMA_WR_TO_RST) != 0) 1906 device_printf(sc->age_dev, 1907 "DMA write error! -- resetting\n"); 1908 age_init(sc); 1909 /* XXX return? */ 1910 } 1911 1912 if (!ifq_is_empty(&ifp->if_snd)) 1913 if_devstart(ifp); 1914 1915 if ((status & INTR_SMB) != 0) 1916 age_stats_update(sc); 1917 } 1918 1919 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 1920 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 1921 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD); 1922 status = le32toh(cmb->intr_status); 1923 if ((status & AGE_INTRS) != 0) 1924 goto again; 1925 done: 1926 /* Re-enable interrupts. */ 1927 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 1928 } 1929 1930 static void 1931 age_txintr(struct age_softc *sc, int tpd_cons) 1932 { 1933 struct ifnet *ifp = &sc->arpcom.ac_if; 1934 struct age_txdesc *txd; 1935 int cons, prog; 1936 1937 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1938 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_POSTREAD); 1939 1940 /* 1941 * Go through our Tx list and free mbufs for those 1942 * frames which have been transmitted. 1943 */ 1944 cons = sc->age_cdata.age_tx_cons; 1945 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 1946 if (sc->age_cdata.age_tx_cnt <= 0) 1947 break; 1948 prog++; 1949 ifq_clr_oactive(&ifp->if_snd); 1950 sc->age_cdata.age_tx_cnt--; 1951 txd = &sc->age_cdata.age_txdesc[cons]; 1952 /* 1953 * Clear Tx descriptors, it's not required but would 1954 * help debugging in case of Tx issues. 1955 */ 1956 txd->tx_desc->addr = 0; 1957 txd->tx_desc->len = 0; 1958 txd->tx_desc->flags = 0; 1959 1960 if (txd->tx_m == NULL) 1961 continue; 1962 /* Reclaim transmitted mbufs. */ 1963 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 1964 m_freem(txd->tx_m); 1965 txd->tx_m = NULL; 1966 } 1967 1968 if (prog > 0) { 1969 sc->age_cdata.age_tx_cons = cons; 1970 1971 /* 1972 * Unarm watchdog timer only when there are no pending 1973 * Tx descriptors in queue. 1974 */ 1975 if (sc->age_cdata.age_tx_cnt == 0) 1976 ifp->if_timer = 0; 1977 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1978 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 1979 } 1980 } 1981 1982 /* Receive a frame. */ 1983 static void 1984 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 1985 { 1986 struct ifnet *ifp = &sc->arpcom.ac_if; 1987 struct age_rxdesc *rxd; 1988 struct rx_desc *desc; 1989 struct mbuf *mp, *m; 1990 uint32_t status, index, vtag; 1991 int count, nsegs, pktlen; 1992 int rx_cons; 1993 1994 status = le32toh(rxrd->flags); 1995 index = le32toh(rxrd->index); 1996 rx_cons = AGE_RX_CONS(index); 1997 nsegs = AGE_RX_NSEGS(index); 1998 1999 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2000 if ((status & AGE_RRD_ERROR) != 0 && 2001 (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2002 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) { 2003 /* 2004 * We want to pass the following frames to upper 2005 * layer regardless of error status of Rx return 2006 * ring. 2007 * 2008 * o IP/TCP/UDP checksum is bad. 2009 * o frame length and protocol specific length 2010 * does not match. 2011 */ 2012 sc->age_cdata.age_rx_cons += nsegs; 2013 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2014 return; 2015 } 2016 2017 pktlen = 0; 2018 for (count = 0; count < nsegs; count++, 2019 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2020 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2021 mp = rxd->rx_m; 2022 desc = rxd->rx_desc; 2023 /* Add a new receive buffer to the ring. */ 2024 if (age_newbuf(sc, rxd, 0) != 0) { 2025 IFNET_STAT_INC(ifp, iqdrops, 1); 2026 /* Reuse Rx buffers. */ 2027 if (sc->age_cdata.age_rxhead != NULL) { 2028 m_freem(sc->age_cdata.age_rxhead); 2029 AGE_RXCHAIN_RESET(sc); 2030 } 2031 break; 2032 } 2033 2034 /* The length of the first mbuf is computed last. */ 2035 if (count != 0) { 2036 mp->m_len = AGE_RX_BYTES(le32toh(desc->len)); 2037 pktlen += mp->m_len; 2038 } 2039 2040 /* Chain received mbufs. */ 2041 if (sc->age_cdata.age_rxhead == NULL) { 2042 sc->age_cdata.age_rxhead = mp; 2043 sc->age_cdata.age_rxtail = mp; 2044 } else { 2045 mp->m_flags &= ~M_PKTHDR; 2046 sc->age_cdata.age_rxprev_tail = 2047 sc->age_cdata.age_rxtail; 2048 sc->age_cdata.age_rxtail->m_next = mp; 2049 sc->age_cdata.age_rxtail = mp; 2050 } 2051 2052 if (count == nsegs - 1) { 2053 /* 2054 * It seems that L1 controller has no way 2055 * to tell hardware to strip CRC bytes. 2056 */ 2057 sc->age_cdata.age_rxlen -= ETHER_CRC_LEN; 2058 if (nsegs > 1) { 2059 /* Remove the CRC bytes in chained mbufs. */ 2060 pktlen -= ETHER_CRC_LEN; 2061 if (mp->m_len <= ETHER_CRC_LEN) { 2062 sc->age_cdata.age_rxtail = 2063 sc->age_cdata.age_rxprev_tail; 2064 sc->age_cdata.age_rxtail->m_len -= 2065 (ETHER_CRC_LEN - mp->m_len); 2066 sc->age_cdata.age_rxtail->m_next = NULL; 2067 m_freem(mp); 2068 } else { 2069 mp->m_len -= ETHER_CRC_LEN; 2070 } 2071 } 2072 2073 m = sc->age_cdata.age_rxhead; 2074 m->m_flags |= M_PKTHDR; 2075 m->m_pkthdr.rcvif = ifp; 2076 m->m_pkthdr.len = sc->age_cdata.age_rxlen; 2077 /* Set the first mbuf length. */ 2078 m->m_len = sc->age_cdata.age_rxlen - pktlen; 2079 2080 /* 2081 * Set checksum information. 2082 * It seems that L1 controller can compute partial 2083 * checksum. The partial checksum value can be used 2084 * to accelerate checksum computation for fragmented 2085 * TCP/UDP packets. Upper network stack already 2086 * takes advantage of the partial checksum value in 2087 * IP reassembly stage. But I'm not sure the 2088 * correctness of the partial hardware checksum 2089 * assistance due to lack of data sheet. If it is 2090 * proven to work on L1 I'll enable it. 2091 */ 2092 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2093 (status & AGE_RRD_IPV4) != 0) { 2094 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2095 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2096 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2097 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2098 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2099 m->m_pkthdr.csum_flags |= 2100 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2101 m->m_pkthdr.csum_data = 0xffff; 2102 } 2103 /* 2104 * Don't mark bad checksum for TCP/UDP frames 2105 * as fragmented frames may always have set 2106 * bad checksummed bit of descriptor status. 2107 */ 2108 } 2109 2110 /* Check for VLAN tagged frames. */ 2111 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2112 (status & AGE_RRD_VLAN) != 0) { 2113 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2114 m->m_pkthdr.ether_vlantag = 2115 AGE_RX_VLAN_TAG(vtag); 2116 m->m_flags |= M_VLANTAG; 2117 } 2118 2119 /* Pass it on. */ 2120 ifp->if_input(ifp, m, NULL, -1); 2121 2122 /* Reset mbuf chains. */ 2123 AGE_RXCHAIN_RESET(sc); 2124 } 2125 } 2126 2127 if (count != nsegs) { 2128 sc->age_cdata.age_rx_cons += nsegs; 2129 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2130 } else { 2131 sc->age_cdata.age_rx_cons = rx_cons; 2132 } 2133 } 2134 2135 static void 2136 age_rxintr(struct age_softc *sc, int rr_prod) 2137 { 2138 struct rx_rdesc *rxrd; 2139 int rr_cons, nsegs, pktlen, prog; 2140 2141 rr_cons = sc->age_cdata.age_rr_cons; 2142 if (rr_cons == rr_prod) 2143 return; 2144 2145 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2146 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_POSTREAD); 2147 2148 for (prog = 0; rr_cons != rr_prod; prog++) { 2149 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2150 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2151 if (nsegs == 0) 2152 break; 2153 2154 /* 2155 * Check number of segments against received bytes. 2156 * Non-matching value would indicate that hardware 2157 * is still trying to update Rx return descriptors. 2158 * I'm not sure whether this check is really needed. 2159 */ 2160 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2161 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) / 2162 (MCLBYTES - ETHER_ALIGN))) 2163 break; 2164 2165 /* Received a frame. */ 2166 age_rxeof(sc, rxrd); 2167 2168 /* Clear return ring. */ 2169 rxrd->index = 0; 2170 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2171 } 2172 2173 if (prog > 0) { 2174 /* Update the consumer index. */ 2175 sc->age_cdata.age_rr_cons = rr_cons; 2176 2177 /* Sync descriptors. */ 2178 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2179 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE); 2180 2181 /* Notify hardware availability of new Rx buffers. */ 2182 AGE_COMMIT_MBOX(sc); 2183 } 2184 } 2185 2186 static void 2187 age_tick(void *xsc) 2188 { 2189 struct age_softc *sc = xsc; 2190 struct ifnet *ifp = &sc->arpcom.ac_if; 2191 struct mii_data *mii = device_get_softc(sc->age_miibus); 2192 2193 lwkt_serialize_enter(ifp->if_serializer); 2194 2195 mii_tick(mii); 2196 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2197 2198 lwkt_serialize_exit(ifp->if_serializer); 2199 } 2200 2201 static void 2202 age_reset(struct age_softc *sc) 2203 { 2204 uint32_t reg; 2205 int i; 2206 2207 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2208 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2209 DELAY(1); 2210 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0) 2211 break; 2212 } 2213 if (i == 0) 2214 device_printf(sc->age_dev, "master reset timeout!\n"); 2215 2216 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2217 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2218 break; 2219 DELAY(10); 2220 } 2221 if (i == 0) 2222 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2223 2224 /* Initialize PCIe module. From Linux. */ 2225 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2226 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2227 } 2228 2229 static void 2230 age_init(void *xsc) 2231 { 2232 struct age_softc *sc = xsc; 2233 struct ifnet *ifp = &sc->arpcom.ac_if; 2234 struct mii_data *mii; 2235 uint8_t eaddr[ETHER_ADDR_LEN]; 2236 bus_addr_t paddr; 2237 uint32_t reg, fsize; 2238 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2239 int error; 2240 2241 ASSERT_SERIALIZED(ifp->if_serializer); 2242 2243 mii = device_get_softc(sc->age_miibus); 2244 2245 /* 2246 * Cancel any pending I/O. 2247 */ 2248 age_stop(sc); 2249 2250 /* 2251 * Reset the chip to a known state. 2252 */ 2253 age_reset(sc); 2254 2255 /* Initialize descriptors. */ 2256 error = age_init_rx_ring(sc); 2257 if (error != 0) { 2258 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2259 age_stop(sc); 2260 return; 2261 } 2262 age_init_rr_ring(sc); 2263 age_init_tx_ring(sc); 2264 age_init_cmb_block(sc); 2265 age_init_smb_block(sc); 2266 2267 /* Reprogram the station address. */ 2268 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2269 CSR_WRITE_4(sc, AGE_PAR0, 2270 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2271 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2272 2273 /* Set descriptor base addresses. */ 2274 paddr = sc->age_rdata.age_tx_ring_paddr; 2275 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2276 paddr = sc->age_rdata.age_rx_ring_paddr; 2277 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2278 paddr = sc->age_rdata.age_rr_ring_paddr; 2279 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2280 paddr = sc->age_rdata.age_tx_ring_paddr; 2281 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2282 paddr = sc->age_rdata.age_cmb_block_paddr; 2283 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2284 paddr = sc->age_rdata.age_smb_block_paddr; 2285 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2286 2287 /* Set Rx/Rx return descriptor counter. */ 2288 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2289 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2290 DESC_RRD_CNT_MASK) | 2291 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2292 2293 /* Set Tx descriptor counter. */ 2294 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2295 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2296 2297 /* Tell hardware that we're ready to load descriptors. */ 2298 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2299 2300 /* 2301 * Initialize mailbox register. 2302 * Updated producer/consumer index information is exchanged 2303 * through this mailbox register. However Tx producer and 2304 * Rx return consumer/Rx producer are all shared such that 2305 * it's hard to separate code path between Tx and Rx without 2306 * locking. If L1 hardware have a separate mail box register 2307 * for Tx and Rx consumer/producer management we could have 2308 * indepent Tx/Rx handler which in turn Rx handler could have 2309 * been run without any locking. 2310 */ 2311 AGE_COMMIT_MBOX(sc); 2312 2313 /* Configure IPG/IFG parameters. */ 2314 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2315 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2316 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2317 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2318 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2319 2320 /* Set parameters for half-duplex media. */ 2321 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2322 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2323 HDPX_CFG_LCOL_MASK) | 2324 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2325 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2326 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2327 HDPX_CFG_ABEBT_MASK) | 2328 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2329 HDPX_CFG_JAMIPG_MASK)); 2330 2331 /* Configure interrupt moderation timer. */ 2332 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2333 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2334 reg &= ~MASTER_MTIMER_ENB; 2335 if (AGE_USECS(sc->age_int_mod) == 0) 2336 reg &= ~MASTER_ITIMER_ENB; 2337 else 2338 reg |= MASTER_ITIMER_ENB; 2339 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2340 if (bootverbose) 2341 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2342 sc->age_int_mod); 2343 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2344 2345 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2346 if (ifp->if_mtu < ETHERMTU) 2347 sc->age_max_frame_size = ETHERMTU; 2348 else 2349 sc->age_max_frame_size = ifp->if_mtu; 2350 sc->age_max_frame_size += ETHER_HDR_LEN + 2351 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2352 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2353 2354 /* Configure jumbo frame. */ 2355 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2356 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2357 (((fsize / sizeof(uint64_t)) << 2358 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2359 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2360 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2361 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2362 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2363 2364 /* Configure flow-control parameters. From Linux. */ 2365 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2366 /* 2367 * Magic workaround for old-L1. 2368 * Don't know which hw revision requires this magic. 2369 */ 2370 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2371 /* 2372 * Another magic workaround for flow-control mode 2373 * change. From Linux. 2374 */ 2375 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2376 } 2377 /* 2378 * TODO 2379 * Should understand pause parameter relationships between FIFO 2380 * size and number of Rx descriptors and Rx return descriptors. 2381 * 2382 * Magic parameters came from Linux. 2383 */ 2384 switch (sc->age_chip_rev) { 2385 case 0x8001: 2386 case 0x9001: 2387 case 0x9002: 2388 case 0x9003: 2389 rxf_hi = AGE_RX_RING_CNT / 16; 2390 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2391 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2392 rrd_lo = AGE_RR_RING_CNT / 16; 2393 break; 2394 default: 2395 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2396 rxf_lo = reg / 16; 2397 if (rxf_lo < 192) 2398 rxf_lo = 192; 2399 rxf_hi = (reg * 7) / 8; 2400 if (rxf_hi < rxf_lo) 2401 rxf_hi = rxf_lo + 16; 2402 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2403 rrd_lo = reg / 8; 2404 rrd_hi = (reg * 7) / 8; 2405 if (rrd_lo < 2) 2406 rrd_lo = 2; 2407 if (rrd_hi < rrd_lo) 2408 rrd_hi = rrd_lo + 3; 2409 break; 2410 } 2411 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2412 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2413 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2414 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2415 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2416 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2417 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2418 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2419 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2420 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2421 2422 /* Configure RxQ. */ 2423 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2424 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2425 RXQ_CFG_RD_BURST_MASK) | 2426 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2427 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2428 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2429 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2430 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2431 2432 /* Configure TxQ. */ 2433 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2434 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2435 TXQ_CFG_TPD_BURST_MASK) | 2436 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2437 TXQ_CFG_TX_FIFO_BURST_MASK) | 2438 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2439 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2440 TXQ_CFG_ENB); 2441 2442 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2443 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2444 TX_JUMBO_TPD_TH_MASK) | 2445 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2446 TX_JUMBO_TPD_IPG_MASK)); 2447 2448 /* Configure DMA parameters. */ 2449 CSR_WRITE_4(sc, AGE_DMA_CFG, 2450 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2451 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2452 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2453 2454 /* Configure CMB DMA write threshold. */ 2455 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2456 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2457 CMB_WR_THRESH_RRD_MASK) | 2458 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2459 CMB_WR_THRESH_TPD_MASK)); 2460 2461 /* Set CMB/SMB timer and enable them. */ 2462 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2463 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2464 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2465 2466 /* Request SMB updates for every seconds. */ 2467 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2468 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2469 2470 /* 2471 * Disable all WOL bits as WOL can interfere normal Rx 2472 * operation. 2473 */ 2474 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2475 2476 /* 2477 * Configure Tx/Rx MACs. 2478 * - Auto-padding for short frames. 2479 * - Enable CRC generation. 2480 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2481 * of MAC is followed after link establishment. 2482 */ 2483 CSR_WRITE_4(sc, AGE_MAC_CFG, 2484 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2485 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2486 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2487 MAC_CFG_PREAMBLE_MASK)); 2488 2489 /* Set up the receive filter. */ 2490 age_rxfilter(sc); 2491 age_rxvlan(sc); 2492 2493 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2494 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2495 reg |= MAC_CFG_RXCSUM_ENB; 2496 2497 /* Ack all pending interrupts and clear it. */ 2498 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2499 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2500 2501 /* Finally enable Tx/Rx MAC. */ 2502 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2503 2504 sc->age_flags &= ~AGE_FLAG_LINK; 2505 /* Switch to the current media. */ 2506 mii_mediachg(mii); 2507 2508 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2509 2510 ifp->if_flags |= IFF_RUNNING; 2511 ifq_clr_oactive(&ifp->if_snd); 2512 } 2513 2514 static void 2515 age_stop(struct age_softc *sc) 2516 { 2517 struct ifnet *ifp = &sc->arpcom.ac_if; 2518 struct age_txdesc *txd; 2519 struct age_rxdesc *rxd; 2520 uint32_t reg; 2521 int i; 2522 2523 ASSERT_SERIALIZED(ifp->if_serializer); 2524 2525 /* 2526 * Mark the interface down and cancel the watchdog timer. 2527 */ 2528 ifp->if_flags &= ~IFF_RUNNING; 2529 ifq_clr_oactive(&ifp->if_snd); 2530 ifp->if_timer = 0; 2531 2532 sc->age_flags &= ~AGE_FLAG_LINK; 2533 callout_stop(&sc->age_tick_ch); 2534 2535 /* 2536 * Disable interrupts. 2537 */ 2538 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2539 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2540 2541 /* Stop CMB/SMB updates. */ 2542 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2543 2544 /* Stop Rx/Tx MAC. */ 2545 age_stop_rxmac(sc); 2546 age_stop_txmac(sc); 2547 2548 /* Stop DMA. */ 2549 CSR_WRITE_4(sc, AGE_DMA_CFG, 2550 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2551 2552 /* Stop TxQ/RxQ. */ 2553 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2554 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2555 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2556 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2557 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2558 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2559 break; 2560 DELAY(10); 2561 } 2562 if (i == 0) 2563 device_printf(sc->age_dev, 2564 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2565 2566 /* Reclaim Rx buffers that have been processed. */ 2567 if (sc->age_cdata.age_rxhead != NULL) 2568 m_freem(sc->age_cdata.age_rxhead); 2569 AGE_RXCHAIN_RESET(sc); 2570 2571 /* 2572 * Free RX and TX mbufs still in the queues. 2573 */ 2574 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2575 rxd = &sc->age_cdata.age_rxdesc[i]; 2576 if (rxd->rx_m != NULL) { 2577 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2578 rxd->rx_dmamap); 2579 m_freem(rxd->rx_m); 2580 rxd->rx_m = NULL; 2581 } 2582 } 2583 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2584 txd = &sc->age_cdata.age_txdesc[i]; 2585 if (txd->tx_m != NULL) { 2586 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2587 txd->tx_dmamap); 2588 m_freem(txd->tx_m); 2589 txd->tx_m = NULL; 2590 } 2591 } 2592 } 2593 2594 static void 2595 age_stop_txmac(struct age_softc *sc) 2596 { 2597 uint32_t reg; 2598 int i; 2599 2600 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2601 if ((reg & MAC_CFG_TX_ENB) != 0) { 2602 reg &= ~MAC_CFG_TX_ENB; 2603 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2604 } 2605 /* Stop Tx DMA engine. */ 2606 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2607 if ((reg & DMA_CFG_RD_ENB) != 0) { 2608 reg &= ~DMA_CFG_RD_ENB; 2609 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2610 } 2611 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2612 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2613 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2614 break; 2615 DELAY(10); 2616 } 2617 if (i == 0) 2618 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2619 } 2620 2621 static void 2622 age_stop_rxmac(struct age_softc *sc) 2623 { 2624 uint32_t reg; 2625 int i; 2626 2627 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2628 if ((reg & MAC_CFG_RX_ENB) != 0) { 2629 reg &= ~MAC_CFG_RX_ENB; 2630 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2631 } 2632 /* Stop Rx DMA engine. */ 2633 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2634 if ((reg & DMA_CFG_WR_ENB) != 0) { 2635 reg &= ~DMA_CFG_WR_ENB; 2636 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2637 } 2638 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2639 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2640 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2641 break; 2642 DELAY(10); 2643 } 2644 if (i == 0) 2645 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2646 } 2647 2648 static void 2649 age_init_tx_ring(struct age_softc *sc) 2650 { 2651 struct age_ring_data *rd; 2652 struct age_txdesc *txd; 2653 int i; 2654 2655 sc->age_cdata.age_tx_prod = 0; 2656 sc->age_cdata.age_tx_cons = 0; 2657 sc->age_cdata.age_tx_cnt = 0; 2658 2659 rd = &sc->age_rdata; 2660 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2661 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2662 txd = &sc->age_cdata.age_txdesc[i]; 2663 txd->tx_desc = &rd->age_tx_ring[i]; 2664 txd->tx_m = NULL; 2665 } 2666 2667 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2668 sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE); 2669 } 2670 2671 static int 2672 age_init_rx_ring(struct age_softc *sc) 2673 { 2674 struct age_ring_data *rd; 2675 struct age_rxdesc *rxd; 2676 int i; 2677 2678 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 2679 rd = &sc->age_rdata; 2680 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 2681 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2682 rxd = &sc->age_cdata.age_rxdesc[i]; 2683 rxd->rx_m = NULL; 2684 rxd->rx_desc = &rd->age_rx_ring[i]; 2685 if (age_newbuf(sc, rxd, 1) != 0) 2686 return (ENOBUFS); 2687 } 2688 2689 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2690 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2691 2692 return (0); 2693 } 2694 2695 static void 2696 age_init_rr_ring(struct age_softc *sc) 2697 { 2698 struct age_ring_data *rd; 2699 2700 sc->age_cdata.age_rr_cons = 0; 2701 AGE_RXCHAIN_RESET(sc); 2702 2703 rd = &sc->age_rdata; 2704 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 2705 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2706 sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE); 2707 } 2708 2709 static void 2710 age_init_cmb_block(struct age_softc *sc) 2711 { 2712 struct age_ring_data *rd; 2713 2714 rd = &sc->age_rdata; 2715 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 2716 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2717 sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE); 2718 } 2719 2720 static void 2721 age_init_smb_block(struct age_softc *sc) 2722 { 2723 struct age_ring_data *rd; 2724 2725 rd = &sc->age_rdata; 2726 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 2727 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2728 sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE); 2729 } 2730 2731 static int 2732 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init) 2733 { 2734 struct rx_desc *desc; 2735 struct mbuf *m; 2736 struct age_dmamap_ctx ctx; 2737 bus_dma_segment_t segs[1]; 2738 bus_dmamap_t map; 2739 int error; 2740 2741 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 2742 if (m == NULL) 2743 return (ENOBUFS); 2744 2745 m->m_len = m->m_pkthdr.len = MCLBYTES; 2746 m_adj(m, ETHER_ALIGN); 2747 2748 ctx.nsegs = 1; 2749 ctx.segs = segs; 2750 error = bus_dmamap_load_mbuf(sc->age_cdata.age_rx_tag, 2751 sc->age_cdata.age_rx_sparemap, 2752 m, age_dmamap_buf_cb, &ctx, 2753 BUS_DMA_NOWAIT); 2754 if (error || ctx.nsegs == 0) { 2755 if (!error) { 2756 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2757 sc->age_cdata.age_rx_sparemap); 2758 error = EFBIG; 2759 if_printf(&sc->arpcom.ac_if, "too many segments?!\n"); 2760 } 2761 m_freem(m); 2762 2763 if (init) 2764 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); 2765 return (error); 2766 } 2767 KASSERT(ctx.nsegs == 1, 2768 ("%s: %d segments returned!", __func__, ctx.nsegs)); 2769 2770 if (rxd->rx_m != NULL) { 2771 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 2772 BUS_DMASYNC_POSTREAD); 2773 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 2774 } 2775 map = rxd->rx_dmamap; 2776 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 2777 sc->age_cdata.age_rx_sparemap = map; 2778 rxd->rx_m = m; 2779 2780 desc = rxd->rx_desc; 2781 desc->addr = htole64(segs[0].ds_addr); 2782 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 2783 AGE_RD_LEN_SHIFT); 2784 return (0); 2785 } 2786 2787 static void 2788 age_rxvlan(struct age_softc *sc) 2789 { 2790 struct ifnet *ifp = &sc->arpcom.ac_if; 2791 uint32_t reg; 2792 2793 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2794 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2795 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2796 reg |= MAC_CFG_VLAN_TAG_STRIP; 2797 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2798 } 2799 2800 static void 2801 age_rxfilter(struct age_softc *sc) 2802 { 2803 struct ifnet *ifp = &sc->arpcom.ac_if; 2804 struct ifmultiaddr *ifma; 2805 uint32_t crc; 2806 uint32_t mchash[2]; 2807 uint32_t rxcfg; 2808 2809 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 2810 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2811 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2812 rxcfg |= MAC_CFG_BCAST; 2813 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2814 if ((ifp->if_flags & IFF_PROMISC) != 0) 2815 rxcfg |= MAC_CFG_PROMISC; 2816 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2817 rxcfg |= MAC_CFG_ALLMULTI; 2818 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 2819 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 2820 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2821 return; 2822 } 2823 2824 /* Program new filter. */ 2825 bzero(mchash, sizeof(mchash)); 2826 2827 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2828 if (ifma->ifma_addr->sa_family != AF_LINK) 2829 continue; 2830 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2831 ifma->ifma_addr), ETHER_ADDR_LEN); 2832 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2833 } 2834 2835 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 2836 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 2837 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 2838 } 2839 2840 static int 2841 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 2842 { 2843 struct age_softc *sc; 2844 struct age_stats *stats; 2845 int error, result; 2846 2847 result = -1; 2848 error = sysctl_handle_int(oidp, &result, 0, req); 2849 2850 if (error != 0 || req->newptr == NULL) 2851 return (error); 2852 2853 if (result != 1) 2854 return (error); 2855 2856 sc = (struct age_softc *)arg1; 2857 stats = &sc->age_stat; 2858 kprintf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 2859 kprintf("Transmit good frames : %ju\n", 2860 (uintmax_t)stats->tx_frames); 2861 kprintf("Transmit good broadcast frames : %ju\n", 2862 (uintmax_t)stats->tx_bcast_frames); 2863 kprintf("Transmit good multicast frames : %ju\n", 2864 (uintmax_t)stats->tx_mcast_frames); 2865 kprintf("Transmit pause control frames : %u\n", 2866 stats->tx_pause_frames); 2867 kprintf("Transmit control frames : %u\n", 2868 stats->tx_control_frames); 2869 kprintf("Transmit frames with excessive deferrals : %u\n", 2870 stats->tx_excess_defer); 2871 kprintf("Transmit deferrals : %u\n", 2872 stats->tx_deferred); 2873 kprintf("Transmit good octets : %ju\n", 2874 (uintmax_t)stats->tx_bytes); 2875 kprintf("Transmit good broadcast octets : %ju\n", 2876 (uintmax_t)stats->tx_bcast_bytes); 2877 kprintf("Transmit good multicast octets : %ju\n", 2878 (uintmax_t)stats->tx_mcast_bytes); 2879 kprintf("Transmit frames 64 bytes : %ju\n", 2880 (uintmax_t)stats->tx_pkts_64); 2881 kprintf("Transmit frames 65 to 127 bytes : %ju\n", 2882 (uintmax_t)stats->tx_pkts_65_127); 2883 kprintf("Transmit frames 128 to 255 bytes : %ju\n", 2884 (uintmax_t)stats->tx_pkts_128_255); 2885 kprintf("Transmit frames 256 to 511 bytes : %ju\n", 2886 (uintmax_t)stats->tx_pkts_256_511); 2887 kprintf("Transmit frames 512 to 1024 bytes : %ju\n", 2888 (uintmax_t)stats->tx_pkts_512_1023); 2889 kprintf("Transmit frames 1024 to 1518 bytes : %ju\n", 2890 (uintmax_t)stats->tx_pkts_1024_1518); 2891 kprintf("Transmit frames 1519 to MTU bytes : %ju\n", 2892 (uintmax_t)stats->tx_pkts_1519_max); 2893 kprintf("Transmit single collisions : %u\n", 2894 stats->tx_single_colls); 2895 kprintf("Transmit multiple collisions : %u\n", 2896 stats->tx_multi_colls); 2897 kprintf("Transmit late collisions : %u\n", 2898 stats->tx_late_colls); 2899 kprintf("Transmit abort due to excessive collisions : %u\n", 2900 stats->tx_excess_colls); 2901 kprintf("Transmit underruns due to FIFO underruns : %u\n", 2902 stats->tx_underrun); 2903 kprintf("Transmit descriptor write-back errors : %u\n", 2904 stats->tx_desc_underrun); 2905 kprintf("Transmit frames with length mismatched frame size : %u\n", 2906 stats->tx_lenerrs); 2907 kprintf("Transmit frames with truncated due to MTU size : %u\n", 2908 stats->tx_lenerrs); 2909 2910 kprintf("Receive good frames : %ju\n", 2911 (uintmax_t)stats->rx_frames); 2912 kprintf("Receive good broadcast frames : %ju\n", 2913 (uintmax_t)stats->rx_bcast_frames); 2914 kprintf("Receive good multicast frames : %ju\n", 2915 (uintmax_t)stats->rx_mcast_frames); 2916 kprintf("Receive pause control frames : %u\n", 2917 stats->rx_pause_frames); 2918 kprintf("Receive control frames : %u\n", 2919 stats->rx_control_frames); 2920 kprintf("Receive CRC errors : %u\n", 2921 stats->rx_crcerrs); 2922 kprintf("Receive frames with length errors : %u\n", 2923 stats->rx_lenerrs); 2924 kprintf("Receive good octets : %ju\n", 2925 (uintmax_t)stats->rx_bytes); 2926 kprintf("Receive good broadcast octets : %ju\n", 2927 (uintmax_t)stats->rx_bcast_bytes); 2928 kprintf("Receive good multicast octets : %ju\n", 2929 (uintmax_t)stats->rx_mcast_bytes); 2930 kprintf("Receive frames too short : %u\n", 2931 stats->rx_runts); 2932 kprintf("Receive fragmented frames : %ju\n", 2933 (uintmax_t)stats->rx_fragments); 2934 kprintf("Receive frames 64 bytes : %ju\n", 2935 (uintmax_t)stats->rx_pkts_64); 2936 kprintf("Receive frames 65 to 127 bytes : %ju\n", 2937 (uintmax_t)stats->rx_pkts_65_127); 2938 kprintf("Receive frames 128 to 255 bytes : %ju\n", 2939 (uintmax_t)stats->rx_pkts_128_255); 2940 kprintf("Receive frames 256 to 511 bytes : %ju\n", 2941 (uintmax_t)stats->rx_pkts_256_511); 2942 kprintf("Receive frames 512 to 1024 bytes : %ju\n", 2943 (uintmax_t)stats->rx_pkts_512_1023); 2944 kprintf("Receive frames 1024 to 1518 bytes : %ju\n", 2945 (uintmax_t)stats->rx_pkts_1024_1518); 2946 kprintf("Receive frames 1519 to MTU bytes : %ju\n", 2947 (uintmax_t)stats->rx_pkts_1519_max); 2948 kprintf("Receive frames too long : %ju\n", 2949 (uint64_t)stats->rx_pkts_truncated); 2950 kprintf("Receive frames with FIFO overflow : %u\n", 2951 stats->rx_fifo_oflows); 2952 kprintf("Receive frames with return descriptor overflow : %u\n", 2953 stats->rx_desc_oflows); 2954 kprintf("Receive frames with alignment errors : %u\n", 2955 stats->rx_alignerrs); 2956 kprintf("Receive frames dropped due to address filtering : %ju\n", 2957 (uint64_t)stats->rx_pkts_filtered); 2958 2959 return (error); 2960 } 2961 2962 static int 2963 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 2964 { 2965 2966 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 2967 AGE_IM_TIMER_MAX)); 2968 } 2969 2970 static void 2971 age_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs, 2972 bus_size_t mapsz __unused, int error) 2973 { 2974 struct age_dmamap_ctx *ctx = xctx; 2975 int i; 2976 2977 if (error) 2978 return; 2979 2980 if (nsegs > ctx->nsegs) { 2981 ctx->nsegs = 0; 2982 return; 2983 } 2984 2985 ctx->nsegs = nsegs; 2986 for (i = 0; i < nsegs; ++i) 2987 ctx->segs[i] = segs[i]; 2988 } 2989