1*86d7f5d3SJohn Marino /*- 2*86d7f5d3SJohn Marino * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3*86d7f5d3SJohn Marino * All rights reserved. 4*86d7f5d3SJohn Marino * 5*86d7f5d3SJohn Marino * Redistribution and use in source and binary forms, with or without 6*86d7f5d3SJohn Marino * modification, are permitted provided that the following conditions 7*86d7f5d3SJohn Marino * are met: 8*86d7f5d3SJohn Marino * 1. Redistributions of source code must retain the above copyright 9*86d7f5d3SJohn Marino * notice unmodified, this list of conditions, and the following 10*86d7f5d3SJohn Marino * disclaimer. 11*86d7f5d3SJohn Marino * 2. Redistributions in binary form must reproduce the above copyright 12*86d7f5d3SJohn Marino * notice, this list of conditions and the following disclaimer in the 13*86d7f5d3SJohn Marino * documentation and/or other materials provided with the distribution. 14*86d7f5d3SJohn Marino * 15*86d7f5d3SJohn Marino * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*86d7f5d3SJohn Marino * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*86d7f5d3SJohn Marino * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*86d7f5d3SJohn Marino * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*86d7f5d3SJohn Marino * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*86d7f5d3SJohn Marino * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*86d7f5d3SJohn Marino * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*86d7f5d3SJohn Marino * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*86d7f5d3SJohn Marino * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*86d7f5d3SJohn Marino * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*86d7f5d3SJohn Marino * SUCH DAMAGE. 26*86d7f5d3SJohn Marino * 27*86d7f5d3SJohn Marino * $FreeBSD: src/sys/dev/age/if_agereg.h,v 1.1 2008/05/19 01:39:59 yongari Exp $ 28*86d7f5d3SJohn Marino */ 29*86d7f5d3SJohn Marino 30*86d7f5d3SJohn Marino #ifndef _IF_AGEREG_H 31*86d7f5d3SJohn Marino #define _IF_AGEREG_H 32*86d7f5d3SJohn Marino 33*86d7f5d3SJohn Marino /* 34*86d7f5d3SJohn Marino * Attansic Technology Corp. PCI vendor ID 35*86d7f5d3SJohn Marino */ 36*86d7f5d3SJohn Marino #define VENDORID_ATTANSIC 0x1969 37*86d7f5d3SJohn Marino 38*86d7f5d3SJohn Marino #define AGE_PCIR_BAR PCIR_BAR(0) 39*86d7f5d3SJohn Marino 40*86d7f5d3SJohn Marino /* 41*86d7f5d3SJohn Marino * Attansic L1 device ID 42*86d7f5d3SJohn Marino */ 43*86d7f5d3SJohn Marino #define DEVICEID_ATTANSIC_L1 0x1048 44*86d7f5d3SJohn Marino 45*86d7f5d3SJohn Marino #define AGE_VPD_REG_CONF_START 0x0100 46*86d7f5d3SJohn Marino #define AGE_VPD_REG_CONF_END 0x01FF 47*86d7f5d3SJohn Marino #define AGE_VPD_REG_CONF_SIG 0x5A 48*86d7f5d3SJohn Marino 49*86d7f5d3SJohn Marino #define AGE_SPI_CTRL 0x200 50*86d7f5d3SJohn Marino #define SPI_STAT_NOT_READY 0x00000001 51*86d7f5d3SJohn Marino #define SPI_STAT_WR_ENB 0x00000002 52*86d7f5d3SJohn Marino #define SPI_STAT_WRP_ENB 0x00000080 53*86d7f5d3SJohn Marino #define SPI_INST_MASK 0x000000FF 54*86d7f5d3SJohn Marino #define SPI_START 0x00000100 55*86d7f5d3SJohn Marino #define SPI_INST_START 0x00000800 56*86d7f5d3SJohn Marino #define SPI_VPD_ENB 0x00002000 57*86d7f5d3SJohn Marino #define SPI_LOADER_START 0x00008000 58*86d7f5d3SJohn Marino #define SPI_CS_HI_MASK 0x00030000 59*86d7f5d3SJohn Marino #define SPI_CS_HOLD_MASK 0x000C0000 60*86d7f5d3SJohn Marino #define SPI_CLK_LO_MASK 0x00300000 61*86d7f5d3SJohn Marino #define SPI_CLK_HI_MASK 0x00C00000 62*86d7f5d3SJohn Marino #define SPI_CS_SETUP_MASK 0x03000000 63*86d7f5d3SJohn Marino #define SPI_EPROM_PG_MASK 0x0C000000 64*86d7f5d3SJohn Marino #define SPI_INST_SHIFT 8 65*86d7f5d3SJohn Marino #define SPI_CS_HI_SHIFT 16 66*86d7f5d3SJohn Marino #define SPI_CS_HOLD_SHIFT 18 67*86d7f5d3SJohn Marino #define SPI_CLK_LO_SHIFT 20 68*86d7f5d3SJohn Marino #define SPI_CLK_HI_SHIFT 22 69*86d7f5d3SJohn Marino #define SPI_CS_SETUP_SHIFT 24 70*86d7f5d3SJohn Marino #define SPI_EPROM_PG_SHIFT 26 71*86d7f5d3SJohn Marino #define SPI_WAIT_READY 0x10000000 72*86d7f5d3SJohn Marino 73*86d7f5d3SJohn Marino #define AGE_SPI_ADDR 0x204 /* 16bits */ 74*86d7f5d3SJohn Marino 75*86d7f5d3SJohn Marino #define AGE_SPI_DATA 0x208 76*86d7f5d3SJohn Marino 77*86d7f5d3SJohn Marino #define AGE_SPI_CONFIG 0x20C 78*86d7f5d3SJohn Marino 79*86d7f5d3SJohn Marino #define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */ 80*86d7f5d3SJohn Marino 81*86d7f5d3SJohn Marino #define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 82*86d7f5d3SJohn Marino 83*86d7f5d3SJohn Marino #define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 84*86d7f5d3SJohn Marino 85*86d7f5d3SJohn Marino #define AGE_SPI_OP_RDID 0x213 /* 8bits */ 86*86d7f5d3SJohn Marino 87*86d7f5d3SJohn Marino #define AGE_SPI_OP_WREN 0x214 /* 8bits */ 88*86d7f5d3SJohn Marino 89*86d7f5d3SJohn Marino #define AGE_SPI_OP_RDSR 0x215 /* 8bits */ 90*86d7f5d3SJohn Marino 91*86d7f5d3SJohn Marino #define AGE_SPI_OP_WRSR 0x216 /* 8bits */ 92*86d7f5d3SJohn Marino 93*86d7f5d3SJohn Marino #define AGE_SPI_OP_READ 0x217 /* 8bits */ 94*86d7f5d3SJohn Marino 95*86d7f5d3SJohn Marino #define AGE_TWSI_CTRL 0x218 96*86d7f5d3SJohn Marino 97*86d7f5d3SJohn Marino #define AGE_DEV_MISC_CTRL 0x21C 98*86d7f5d3SJohn Marino 99*86d7f5d3SJohn Marino #define AGE_MASTER_CFG 0x1400 100*86d7f5d3SJohn Marino #define MASTER_RESET 0x00000001 101*86d7f5d3SJohn Marino #define MASTER_MTIMER_ENB 0x00000002 102*86d7f5d3SJohn Marino #define MASTER_ITIMER_ENB 0x00000004 103*86d7f5d3SJohn Marino #define MASTER_MANUAL_INT_ENB 0x00000008 104*86d7f5d3SJohn Marino #define MASTER_CHIP_REV_MASK 0x00FF0000 105*86d7f5d3SJohn Marino #define MASTER_CHIP_ID_MASK 0xFF000000 106*86d7f5d3SJohn Marino #define MASTER_CHIP_REV_SHIFT 16 107*86d7f5d3SJohn Marino #define MASTER_CHIP_ID_SHIFT 24 108*86d7f5d3SJohn Marino 109*86d7f5d3SJohn Marino /* Number of ticks per usec for L1. */ 110*86d7f5d3SJohn Marino #define AGE_TICK_USECS 2 111*86d7f5d3SJohn Marino #define AGE_USECS(x) ((x) / AGE_TICK_USECS) 112*86d7f5d3SJohn Marino 113*86d7f5d3SJohn Marino #define AGE_MANUAL_TIMER 0x1404 114*86d7f5d3SJohn Marino 115*86d7f5d3SJohn Marino #define AGE_IM_TIMER 0x1408 /* 16bits */ 116*86d7f5d3SJohn Marino #define AGE_IM_TIMER_MIN 0 117*86d7f5d3SJohn Marino #define AGE_IM_TIMER_MAX 130000 /* 130ms */ 118*86d7f5d3SJohn Marino #define AGE_IM_TIMER_DEFAULT 100 119*86d7f5d3SJohn Marino 120*86d7f5d3SJohn Marino #define AGE_GPHY_CTRL 0x140C /* 16bits */ 121*86d7f5d3SJohn Marino #define GPHY_CTRL_RST 0x0000 122*86d7f5d3SJohn Marino #define GPHY_CTRL_CLR 0x0001 123*86d7f5d3SJohn Marino 124*86d7f5d3SJohn Marino #define AGE_INTR_CLR_TIMER 0x140E /* 16bits */ 125*86d7f5d3SJohn Marino 126*86d7f5d3SJohn Marino #define AGE_IDLE_STATUS 0x1410 127*86d7f5d3SJohn Marino #define IDLE_STATUS_RXMAC 0x00000001 128*86d7f5d3SJohn Marino #define IDLE_STATUS_TXMAC 0x00000002 129*86d7f5d3SJohn Marino #define IDLE_STATUS_RXQ 0x00000004 130*86d7f5d3SJohn Marino #define IDLE_STATUS_TXQ 0x00000008 131*86d7f5d3SJohn Marino #define IDLE_STATUS_DMARD 0x00000010 132*86d7f5d3SJohn Marino #define IDLE_STATUS_DMAWR 0x00000020 133*86d7f5d3SJohn Marino #define IDLE_STATUS_SMB 0x00000040 134*86d7f5d3SJohn Marino #define IDLE_STATUS_CMB 0x00000080 135*86d7f5d3SJohn Marino 136*86d7f5d3SJohn Marino #define AGE_MDIO 0x1414 137*86d7f5d3SJohn Marino #define MDIO_DATA_MASK 0x0000FFFF 138*86d7f5d3SJohn Marino #define MDIO_REG_ADDR_MASK 0x001F0000 139*86d7f5d3SJohn Marino #define MDIO_OP_READ 0x00200000 140*86d7f5d3SJohn Marino #define MDIO_OP_WRITE 0x00000000 141*86d7f5d3SJohn Marino #define MDIO_SUP_PREAMBLE 0x00400000 142*86d7f5d3SJohn Marino #define MDIO_OP_EXECUTE 0x00800000 143*86d7f5d3SJohn Marino #define MDIO_CLK_25_4 0x00000000 144*86d7f5d3SJohn Marino #define MDIO_CLK_25_6 0x02000000 145*86d7f5d3SJohn Marino #define MDIO_CLK_25_8 0x03000000 146*86d7f5d3SJohn Marino #define MDIO_CLK_25_10 0x04000000 147*86d7f5d3SJohn Marino #define MDIO_CLK_25_14 0x05000000 148*86d7f5d3SJohn Marino #define MDIO_CLK_25_20 0x06000000 149*86d7f5d3SJohn Marino #define MDIO_CLK_25_28 0x07000000 150*86d7f5d3SJohn Marino #define MDIO_OP_BUSY 0x08000000 151*86d7f5d3SJohn Marino #define MDIO_DATA_SHIFT 0 152*86d7f5d3SJohn Marino #define MDIO_REG_ADDR_SHIFT 16 153*86d7f5d3SJohn Marino 154*86d7f5d3SJohn Marino #define MDIO_REG_ADDR(x) \ 155*86d7f5d3SJohn Marino (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 156*86d7f5d3SJohn Marino /* Default PHY address. */ 157*86d7f5d3SJohn Marino #define AGE_PHY_ADDR 0 158*86d7f5d3SJohn Marino 159*86d7f5d3SJohn Marino #define AGE_PHY_STATUS 0x1418 160*86d7f5d3SJohn Marino 161*86d7f5d3SJohn Marino #define AGE_BIST0 0x141C 162*86d7f5d3SJohn Marino #define BIST0_ENB 0x00000001 163*86d7f5d3SJohn Marino #define BIST0_SRAM_FAIL 0x00000002 164*86d7f5d3SJohn Marino #define BIST0_FUSE_FLAG 0x00000004 165*86d7f5d3SJohn Marino 166*86d7f5d3SJohn Marino #define AGE_BIST1 0x1420 167*86d7f5d3SJohn Marino #define BIST1_ENB 0x00000001 168*86d7f5d3SJohn Marino #define BIST1_SRAM_FAIL 0x00000002 169*86d7f5d3SJohn Marino #define BIST1_FUSE_FLAG 0x00000004 170*86d7f5d3SJohn Marino 171*86d7f5d3SJohn Marino #define AGE_MAC_CFG 0x1480 172*86d7f5d3SJohn Marino #define MAC_CFG_TX_ENB 0x00000001 173*86d7f5d3SJohn Marino #define MAC_CFG_RX_ENB 0x00000002 174*86d7f5d3SJohn Marino #define MAC_CFG_TX_FC 0x00000004 175*86d7f5d3SJohn Marino #define MAC_CFG_RX_FC 0x00000008 176*86d7f5d3SJohn Marino #define MAC_CFG_LOOP 0x00000010 177*86d7f5d3SJohn Marino #define MAC_CFG_FULL_DUPLEX 0x00000020 178*86d7f5d3SJohn Marino #define MAC_CFG_TX_CRC_ENB 0x00000040 179*86d7f5d3SJohn Marino #define MAC_CFG_TX_AUTO_PAD 0x00000080 180*86d7f5d3SJohn Marino #define MAC_CFG_TX_LENCHK 0x00000100 181*86d7f5d3SJohn Marino #define MAC_CFG_RX_JUMBO_ENB 0x00000200 182*86d7f5d3SJohn Marino #define MAC_CFG_PREAMBLE_MASK 0x00003C00 183*86d7f5d3SJohn Marino #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 184*86d7f5d3SJohn Marino #define MAC_CFG_PROMISC 0x00008000 185*86d7f5d3SJohn Marino #define MAC_CFG_TX_PAUSE 0x00010000 186*86d7f5d3SJohn Marino #define MAC_CFG_SCNT 0x00020000 187*86d7f5d3SJohn Marino #define MAC_CFG_SYNC_RST_TX 0x00040000 188*86d7f5d3SJohn Marino #define MAC_CFG_SPEED_MASK 0x00300000 189*86d7f5d3SJohn Marino #define MAC_CFG_SPEED_10_100 0x00100000 190*86d7f5d3SJohn Marino #define MAC_CFG_SPEED_1000 0x00200000 191*86d7f5d3SJohn Marino #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 192*86d7f5d3SJohn Marino #define MAC_CFG_TX_JUMBO_ENB 0x00800000 193*86d7f5d3SJohn Marino #define MAC_CFG_RXCSUM_ENB 0x01000000 194*86d7f5d3SJohn Marino #define MAC_CFG_ALLMULTI 0x02000000 195*86d7f5d3SJohn Marino #define MAC_CFG_BCAST 0x04000000 196*86d7f5d3SJohn Marino #define MAC_CFG_DBG 0x08000000 197*86d7f5d3SJohn Marino #define MAC_CFG_PREAMBLE_SHIFT 10 198*86d7f5d3SJohn Marino #define MAC_CFG_PREAMBLE_DEFAULT 7 199*86d7f5d3SJohn Marino 200*86d7f5d3SJohn Marino #define AGE_IPG_IFG_CFG 0x1484 201*86d7f5d3SJohn Marino #define IPG_IFG_IPGT_MASK 0x0000007F 202*86d7f5d3SJohn Marino #define IPG_IFG_MIFG_MASK 0x0000FF00 203*86d7f5d3SJohn Marino #define IPG_IFG_IPG1_MASK 0x007F0000 204*86d7f5d3SJohn Marino #define IPG_IFG_IPG2_MASK 0x7F000000 205*86d7f5d3SJohn Marino #define IPG_IFG_IPGT_SHIFT 0 206*86d7f5d3SJohn Marino #define IPG_IFG_IPGT_DEFAULT 0x60 207*86d7f5d3SJohn Marino #define IPG_IFG_MIFG_SHIFT 8 208*86d7f5d3SJohn Marino #define IPG_IFG_MIFG_DEFAULT 0x50 209*86d7f5d3SJohn Marino #define IPG_IFG_IPG1_SHIFT 16 210*86d7f5d3SJohn Marino #define IPG_IFG_IPG1_DEFAULT 0x40 211*86d7f5d3SJohn Marino #define IPG_IFG_IPG2_SHIFT 24 212*86d7f5d3SJohn Marino #define IPG_IFG_IPG2_DEFAULT 0x60 213*86d7f5d3SJohn Marino 214*86d7f5d3SJohn Marino /* station address */ 215*86d7f5d3SJohn Marino #define AGE_PAR0 0x1488 216*86d7f5d3SJohn Marino #define AGE_PAR1 0x148C 217*86d7f5d3SJohn Marino 218*86d7f5d3SJohn Marino /* 64bit multicast hash register. */ 219*86d7f5d3SJohn Marino #define AGE_MAR0 0x1490 220*86d7f5d3SJohn Marino #define AGE_MAR1 0x1494 221*86d7f5d3SJohn Marino 222*86d7f5d3SJohn Marino /* half-duplex parameter configuration. */ 223*86d7f5d3SJohn Marino #define AGE_HDPX_CFG 0x1498 224*86d7f5d3SJohn Marino #define HDPX_CFG_LCOL_MASK 0x000003FF 225*86d7f5d3SJohn Marino #define HDPX_CFG_RETRY_MASK 0x0000F000 226*86d7f5d3SJohn Marino #define HDPX_CFG_EXC_DEF_EN 0x00010000 227*86d7f5d3SJohn Marino #define HDPX_CFG_NO_BACK_C 0x00020000 228*86d7f5d3SJohn Marino #define HDPX_CFG_NO_BACK_P 0x00040000 229*86d7f5d3SJohn Marino #define HDPX_CFG_ABEBE 0x00080000 230*86d7f5d3SJohn Marino #define HDPX_CFG_ABEBT_MASK 0x00F00000 231*86d7f5d3SJohn Marino #define HDPX_CFG_JAMIPG_MASK 0x0F000000 232*86d7f5d3SJohn Marino #define HDPX_CFG_LCOL_SHIFT 0 233*86d7f5d3SJohn Marino #define HDPX_CFG_LCOL_DEFAULT 0x37 234*86d7f5d3SJohn Marino #define HDPX_CFG_RETRY_SHIFT 12 235*86d7f5d3SJohn Marino #define HDPX_CFG_RETRY_DEFAULT 0x0F 236*86d7f5d3SJohn Marino #define HDPX_CFG_ABEBT_SHIFT 20 237*86d7f5d3SJohn Marino #define HDPX_CFG_ABEBT_DEFAULT 0x0A 238*86d7f5d3SJohn Marino #define HDPX_CFG_JAMIPG_SHIFT 24 239*86d7f5d3SJohn Marino #define HDPX_CFG_JAMIPG_DEFAULT 0x07 240*86d7f5d3SJohn Marino 241*86d7f5d3SJohn Marino #define AGE_FRAME_SIZE 0x149C 242*86d7f5d3SJohn Marino 243*86d7f5d3SJohn Marino #define AGE_WOL_CFG 0x14A0 244*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN 0x00000001 245*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN_ENB 0x00000002 246*86d7f5d3SJohn Marino #define WOL_CFG_MAGIC 0x00000004 247*86d7f5d3SJohn Marino #define WOL_CFG_MAGIC_ENB 0x00000008 248*86d7f5d3SJohn Marino #define WOL_CFG_LINK_CHG 0x00000010 249*86d7f5d3SJohn Marino #define WOL_CFG_LINK_CHG_ENB 0x00000020 250*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN_DET 0x00000100 251*86d7f5d3SJohn Marino #define WOL_CFG_MAGIC_DET 0x00000200 252*86d7f5d3SJohn Marino #define WOL_CFG_LINK_CHG_DET 0x00000400 253*86d7f5d3SJohn Marino #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 254*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN0 0x00010000 255*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN1 0x00020000 256*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN2 0x00040000 257*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN3 0x00080000 258*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN4 0x00100000 259*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN5 0x00200000 260*86d7f5d3SJohn Marino #define WOL_CFG_PATTERN6 0x00400000 261*86d7f5d3SJohn Marino 262*86d7f5d3SJohn Marino /* WOL pattern length. */ 263*86d7f5d3SJohn Marino #define AGE_PATTERN_CFG0 0x14A4 264*86d7f5d3SJohn Marino #define PATTERN_CFG_0_LEN_MASK 0x0000007F 265*86d7f5d3SJohn Marino #define PATTERN_CFG_1_LEN_MASK 0x00007F00 266*86d7f5d3SJohn Marino #define PATTERN_CFG_2_LEN_MASK 0x007F0000 267*86d7f5d3SJohn Marino #define PATTERN_CFG_3_LEN_MASK 0x7F000000 268*86d7f5d3SJohn Marino 269*86d7f5d3SJohn Marino #define AGE_PATTERN_CFG1 0x14A8 270*86d7f5d3SJohn Marino #define PATTERN_CFG_4_LEN_MASK 0x0000007F 271*86d7f5d3SJohn Marino #define PATTERN_CFG_5_LEN_MASK 0x00007F00 272*86d7f5d3SJohn Marino #define PATTERN_CFG_6_LEN_MASK 0x007F0000 273*86d7f5d3SJohn Marino 274*86d7f5d3SJohn Marino #define AGE_SRAM_RD_ADDR 0x1500 275*86d7f5d3SJohn Marino 276*86d7f5d3SJohn Marino #define AGE_SRAM_RD_LEN 0x1504 277*86d7f5d3SJohn Marino 278*86d7f5d3SJohn Marino #define AGE_SRAM_RRD_ADDR 0x1508 279*86d7f5d3SJohn Marino 280*86d7f5d3SJohn Marino #define AGE_SRAM_RRD_LEN 0x150C 281*86d7f5d3SJohn Marino 282*86d7f5d3SJohn Marino #define AGE_SRAM_TPD_ADDR 0x1510 283*86d7f5d3SJohn Marino 284*86d7f5d3SJohn Marino #define AGE_SRAM_TPD_LEN 0x1514 285*86d7f5d3SJohn Marino 286*86d7f5d3SJohn Marino #define AGE_SRAM_TRD_ADDR 0x1518 287*86d7f5d3SJohn Marino 288*86d7f5d3SJohn Marino #define AGE_SRAM_TRD_LEN 0x151C 289*86d7f5d3SJohn Marino 290*86d7f5d3SJohn Marino #define AGE_SRAM_RX_FIFO_ADDR 0x1520 291*86d7f5d3SJohn Marino 292*86d7f5d3SJohn Marino #define AGE_SRAM_RX_FIFO_LEN 0x1524 293*86d7f5d3SJohn Marino 294*86d7f5d3SJohn Marino #define AGE_SRAM_TX_FIFO_ADDR 0x1528 295*86d7f5d3SJohn Marino 296*86d7f5d3SJohn Marino #define AGE_SRAM_TX_FIFO_LEN 0x152C 297*86d7f5d3SJohn Marino 298*86d7f5d3SJohn Marino #define AGE_SRAM_TCPH_ADDR 0x1530 299*86d7f5d3SJohn Marino #define SRAM_TCPH_ADDR_MASK 0x00000FFF 300*86d7f5d3SJohn Marino #define SRAM_PATH_ADDR_MASK 0x0FFF0000 301*86d7f5d3SJohn Marino #define SRAM_TCPH_ADDR_SHIFT 0 302*86d7f5d3SJohn Marino #define SRAM_PATH_ADDR_SHIFT 16 303*86d7f5d3SJohn Marino 304*86d7f5d3SJohn Marino #define AGE_DMA_BLOCK 0x1534 305*86d7f5d3SJohn Marino #define DMA_BLOCK_LOAD 0x00000001 306*86d7f5d3SJohn Marino 307*86d7f5d3SJohn Marino /* 308*86d7f5d3SJohn Marino * All descriptors and CMB/SMB share the same high address. 309*86d7f5d3SJohn Marino */ 310*86d7f5d3SJohn Marino #define AGE_DESC_ADDR_HI 0x1540 311*86d7f5d3SJohn Marino 312*86d7f5d3SJohn Marino #define AGE_DESC_RD_ADDR_LO 0x1544 313*86d7f5d3SJohn Marino 314*86d7f5d3SJohn Marino #define AGE_DESC_RRD_ADDR_LO 0x1548 315*86d7f5d3SJohn Marino 316*86d7f5d3SJohn Marino #define AGE_DESC_TPD_ADDR_LO 0x154C 317*86d7f5d3SJohn Marino 318*86d7f5d3SJohn Marino #define AGE_DESC_CMB_ADDR_LO 0x1550 319*86d7f5d3SJohn Marino 320*86d7f5d3SJohn Marino #define AGE_DESC_SMB_ADDR_LO 0x1554 321*86d7f5d3SJohn Marino 322*86d7f5d3SJohn Marino #define AGE_DESC_RRD_RD_CNT 0x1558 323*86d7f5d3SJohn Marino #define DESC_RD_CNT_MASK 0x000007FF 324*86d7f5d3SJohn Marino #define DESC_RRD_CNT_MASK 0x07FF0000 325*86d7f5d3SJohn Marino #define DESC_RD_CNT_SHIFT 0 326*86d7f5d3SJohn Marino #define DESC_RRD_CNT_SHIFT 16 327*86d7f5d3SJohn Marino 328*86d7f5d3SJohn Marino #define AGE_DESC_TPD_CNT 0x155C 329*86d7f5d3SJohn Marino #define DESC_TPD_CNT_MASK 0x00003FF 330*86d7f5d3SJohn Marino #define DESC_TPD_CNT_SHIFT 0 331*86d7f5d3SJohn Marino 332*86d7f5d3SJohn Marino #define AGE_TXQ_CFG 0x1580 333*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_BURST_MASK 0x0000001F 334*86d7f5d3SJohn Marino #define TXQ_CFG_ENB 0x00000020 335*86d7f5d3SJohn Marino #define TXQ_CFG_ENHANCED_MODE 0x00000040 336*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 337*86d7f5d3SJohn Marino #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 338*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_BURST_SHIFT 0 339*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_BURST_DEFAULT 4 340*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 341*86d7f5d3SJohn Marino #define TXQ_CFG_TPD_FETCH_DEFAULT 16 342*86d7f5d3SJohn Marino #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 343*86d7f5d3SJohn Marino #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 344*86d7f5d3SJohn Marino 345*86d7f5d3SJohn Marino #define AGE_TX_JUMBO_TPD_TH_IPG 0x1584 346*86d7f5d3SJohn Marino #define TX_JUMBO_TPD_TH_MASK 0x000007FF 347*86d7f5d3SJohn Marino #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 348*86d7f5d3SJohn Marino #define TX_JUMBO_TPD_TH_SHIFT 0 349*86d7f5d3SJohn Marino #define TX_JUMBO_TPD_IPG_SHIFT 16 350*86d7f5d3SJohn Marino #define TX_JUMBO_TPD_IPG_DEFAULT 1 351*86d7f5d3SJohn Marino 352*86d7f5d3SJohn Marino #define AGE_RXQ_CFG 0x15A0 353*86d7f5d3SJohn Marino #define RXQ_CFG_RD_BURST_MASK 0x000000FF 354*86d7f5d3SJohn Marino #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 355*86d7f5d3SJohn Marino #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 356*86d7f5d3SJohn Marino #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 357*86d7f5d3SJohn Marino #define RXQ_CFG_ENB 0x80000000 358*86d7f5d3SJohn Marino #define RXQ_CFG_RD_BURST_SHIFT 0 359*86d7f5d3SJohn Marino #define RXQ_CFG_RD_BURST_DEFAULT 8 360*86d7f5d3SJohn Marino #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 361*86d7f5d3SJohn Marino #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 362*86d7f5d3SJohn Marino #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 363*86d7f5d3SJohn Marino #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 364*86d7f5d3SJohn Marino 365*86d7f5d3SJohn Marino #define AGE_RXQ_JUMBO_CFG 0x15A4 366*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 367*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 368*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 369*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 370*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_LKAH_SHIFT 11 371*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 372*86d7f5d3SJohn Marino #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 373*86d7f5d3SJohn Marino 374*86d7f5d3SJohn Marino #define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 375*86d7f5d3SJohn Marino #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 376*86d7f5d3SJohn Marino #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 377*86d7f5d3SJohn Marino #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 378*86d7f5d3SJohn Marino #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 379*86d7f5d3SJohn Marino 380*86d7f5d3SJohn Marino #define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC 381*86d7f5d3SJohn Marino #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 382*86d7f5d3SJohn Marino #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 383*86d7f5d3SJohn Marino #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 384*86d7f5d3SJohn Marino #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 385*86d7f5d3SJohn Marino 386*86d7f5d3SJohn Marino #define AGE_DMA_CFG 0x15C0 387*86d7f5d3SJohn Marino #define DMA_CFG_IN_ORDER 0x00000001 388*86d7f5d3SJohn Marino #define DMA_CFG_ENH_ORDER 0x00000002 389*86d7f5d3SJohn Marino #define DMA_CFG_OUT_ORDER 0x00000004 390*86d7f5d3SJohn Marino #define DMA_CFG_RCB_64 0x00000000 391*86d7f5d3SJohn Marino #define DMA_CFG_RCB_128 0x00000008 392*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_128 0x00000000 393*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_256 0x00000010 394*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_512 0x00000020 395*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_1024 0x00000030 396*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_2048 0x00000040 397*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_4096 0x00000050 398*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_128 0x00000000 399*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_256 0x00000080 400*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_512 0x00000100 401*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_1024 0x00000180 402*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_2048 0x00000200 403*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_4096 0x00000280 404*86d7f5d3SJohn Marino #define DMA_CFG_RD_ENB 0x00000400 405*86d7f5d3SJohn Marino #define DMA_CFG_WR_ENB 0x00000800 406*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_MASK 0x07 407*86d7f5d3SJohn Marino #define DMA_CFG_RD_BURST_SHIFT 4 408*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_MASK 0x07 409*86d7f5d3SJohn Marino #define DMA_CFG_WR_BURST_SHIFT 7 410*86d7f5d3SJohn Marino 411*86d7f5d3SJohn Marino #define AGE_CSMB_CTRL 0x15D0 412*86d7f5d3SJohn Marino #define CSMB_CTRL_CMB_KICK 0x00000001 413*86d7f5d3SJohn Marino #define CSMB_CTRL_SMB_KICK 0x00000002 414*86d7f5d3SJohn Marino #define CSMB_CTRL_CMB_ENB 0x00000004 415*86d7f5d3SJohn Marino #define CSMB_CTRL_SMB_ENB 0x00000008 416*86d7f5d3SJohn Marino 417*86d7f5d3SJohn Marino /* CMB DMA Write Threshold Register */ 418*86d7f5d3SJohn Marino #define AGE_CMB_WR_THRESH 0x15D4 419*86d7f5d3SJohn Marino #define CMB_WR_THRESH_RRD_MASK 0x000007FF 420*86d7f5d3SJohn Marino #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 421*86d7f5d3SJohn Marino #define CMB_WR_THRESH_RRD_SHIFT 0 422*86d7f5d3SJohn Marino #define CMB_WR_THRESH_RRD_DEFAULT 4 423*86d7f5d3SJohn Marino #define CMB_WR_THRESH_TPD_SHIFT 16 424*86d7f5d3SJohn Marino #define CMB_WR_THRESH_TPD_DEFAULT 4 425*86d7f5d3SJohn Marino 426*86d7f5d3SJohn Marino /* RX/TX count-down timer to trigger CMB-write. */ 427*86d7f5d3SJohn Marino #define AGE_CMB_WR_TIMER 0x15D8 428*86d7f5d3SJohn Marino #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 429*86d7f5d3SJohn Marino #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 430*86d7f5d3SJohn Marino #define CMB_WR_TIMER_RX_SHIFT 0 431*86d7f5d3SJohn Marino #define CMB_WR_TIMER_TX_SHIFT 16 432*86d7f5d3SJohn Marino 433*86d7f5d3SJohn Marino /* Number of packet received since last CMB write */ 434*86d7f5d3SJohn Marino #define AGE_CMB_RX_PKT_CNT 0x15DC 435*86d7f5d3SJohn Marino 436*86d7f5d3SJohn Marino /* Number of packet transmitted since last CMB write */ 437*86d7f5d3SJohn Marino #define AGE_CMB_TX_PKT_CNT 0x15E0 438*86d7f5d3SJohn Marino 439*86d7f5d3SJohn Marino /* SMB auto DMA timer register */ 440*86d7f5d3SJohn Marino #define AGE_SMB_TIMER 0x15E4 441*86d7f5d3SJohn Marino 442*86d7f5d3SJohn Marino #define AGE_MBOX 0x15F0 443*86d7f5d3SJohn Marino #define MBOX_RD_PROD_IDX_MASK 0x000007FF 444*86d7f5d3SJohn Marino #define MBOX_RRD_CONS_IDX_MASK 0x003FF800 445*86d7f5d3SJohn Marino #define MBOX_TD_PROD_IDX_MASK 0xFFC00000 446*86d7f5d3SJohn Marino #define MBOX_RD_PROD_IDX_SHIFT 0 447*86d7f5d3SJohn Marino #define MBOX_RRD_CONS_IDX_SHIFT 11 448*86d7f5d3SJohn Marino #define MBOX_TD_PROD_IDX_SHIFT 22 449*86d7f5d3SJohn Marino 450*86d7f5d3SJohn Marino #define AGE_INTR_STATUS 0x1600 451*86d7f5d3SJohn Marino #define INTR_SMB 0x00000001 452*86d7f5d3SJohn Marino #define INTR_MOD_TIMER 0x00000002 453*86d7f5d3SJohn Marino #define INTR_MANUAL_TIMER 0x00000004 454*86d7f5d3SJohn Marino #define INTR_RX_FIFO_OFLOW 0x00000008 455*86d7f5d3SJohn Marino #define INTR_RD_UNDERRUN 0x00000010 456*86d7f5d3SJohn Marino #define INTR_RRD_OFLOW 0x00000020 457*86d7f5d3SJohn Marino #define INTR_TX_FIFO_UNDERRUN 0x00000040 458*86d7f5d3SJohn Marino #define INTR_LINK_CHG 0x00000080 459*86d7f5d3SJohn Marino #define INTR_HOST_RD_UNDERRUN 0x00000100 460*86d7f5d3SJohn Marino #define INTR_HOST_RRD_OFLOW 0x00000200 461*86d7f5d3SJohn Marino #define INTR_DMA_RD_TO_RST 0x00000400 462*86d7f5d3SJohn Marino #define INTR_DMA_WR_TO_RST 0x00000800 463*86d7f5d3SJohn Marino #define INTR_GPHY 0x00001000 464*86d7f5d3SJohn Marino #define INTR_RX_PKT 0x00010000 465*86d7f5d3SJohn Marino #define INTR_TX_PKT 0x00020000 466*86d7f5d3SJohn Marino #define INTR_TX_DMA 0x00040000 467*86d7f5d3SJohn Marino #define INTR_RX_DMA 0x00080000 468*86d7f5d3SJohn Marino #define INTR_CMB_RX 0x00100000 469*86d7f5d3SJohn Marino #define INTR_CMB_TX 0x00200000 470*86d7f5d3SJohn Marino #define INTR_MAC_RX 0x00400000 471*86d7f5d3SJohn Marino #define INTR_MAC_TX 0x00800000 472*86d7f5d3SJohn Marino #define INTR_UNDERRUN 0x01000000 473*86d7f5d3SJohn Marino #define INTR_FRAME_ERROR 0x02000000 474*86d7f5d3SJohn Marino #define INTR_FRAME_OK 0x04000000 475*86d7f5d3SJohn Marino #define INTR_CSUM_ERROR 0x08000000 476*86d7f5d3SJohn Marino #define INTR_PHY_LINK_DOWN 0x10000000 477*86d7f5d3SJohn Marino #define INTR_DIS_SMB 0x20000000 478*86d7f5d3SJohn Marino #define INTR_DIS_DMA 0x40000000 479*86d7f5d3SJohn Marino #define INTR_DIS_INT 0x80000000 480*86d7f5d3SJohn Marino 481*86d7f5d3SJohn Marino /* Interrupt Mask Register */ 482*86d7f5d3SJohn Marino #define AGE_INTR_MASK 0x1604 483*86d7f5d3SJohn Marino 484*86d7f5d3SJohn Marino #define AGE_INTRS \ 485*86d7f5d3SJohn Marino (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 486*86d7f5d3SJohn Marino INTR_CMB_TX | INTR_CMB_RX) 487*86d7f5d3SJohn Marino 488*86d7f5d3SJohn Marino /* Statistics counters collected by the MAC. */ 489*86d7f5d3SJohn Marino struct smb { 490*86d7f5d3SJohn Marino /* Rx stats. */ 491*86d7f5d3SJohn Marino uint32_t rx_frames; 492*86d7f5d3SJohn Marino uint32_t rx_bcast_frames; 493*86d7f5d3SJohn Marino uint32_t rx_mcast_frames; 494*86d7f5d3SJohn Marino uint32_t rx_pause_frames; 495*86d7f5d3SJohn Marino uint32_t rx_control_frames; 496*86d7f5d3SJohn Marino uint32_t rx_crcerrs; 497*86d7f5d3SJohn Marino uint32_t rx_lenerrs; 498*86d7f5d3SJohn Marino uint32_t rx_bytes; 499*86d7f5d3SJohn Marino uint32_t rx_runts; 500*86d7f5d3SJohn Marino uint32_t rx_fragments; 501*86d7f5d3SJohn Marino uint32_t rx_pkts_64; 502*86d7f5d3SJohn Marino uint32_t rx_pkts_65_127; 503*86d7f5d3SJohn Marino uint32_t rx_pkts_128_255; 504*86d7f5d3SJohn Marino uint32_t rx_pkts_256_511; 505*86d7f5d3SJohn Marino uint32_t rx_pkts_512_1023; 506*86d7f5d3SJohn Marino uint32_t rx_pkts_1024_1518; 507*86d7f5d3SJohn Marino uint32_t rx_pkts_1519_max; 508*86d7f5d3SJohn Marino uint32_t rx_pkts_truncated; 509*86d7f5d3SJohn Marino uint32_t rx_fifo_oflows; 510*86d7f5d3SJohn Marino uint32_t rx_desc_oflows; 511*86d7f5d3SJohn Marino uint32_t rx_alignerrs; 512*86d7f5d3SJohn Marino uint32_t rx_bcast_bytes; 513*86d7f5d3SJohn Marino uint32_t rx_mcast_bytes; 514*86d7f5d3SJohn Marino uint32_t rx_pkts_filtered; 515*86d7f5d3SJohn Marino /* Tx stats. */ 516*86d7f5d3SJohn Marino uint32_t tx_frames; 517*86d7f5d3SJohn Marino uint32_t tx_bcast_frames; 518*86d7f5d3SJohn Marino uint32_t tx_mcast_frames; 519*86d7f5d3SJohn Marino uint32_t tx_pause_frames; 520*86d7f5d3SJohn Marino uint32_t tx_excess_defer; 521*86d7f5d3SJohn Marino uint32_t tx_control_frames; 522*86d7f5d3SJohn Marino uint32_t tx_deferred; 523*86d7f5d3SJohn Marino uint32_t tx_bytes; 524*86d7f5d3SJohn Marino uint32_t tx_pkts_64; 525*86d7f5d3SJohn Marino uint32_t tx_pkts_65_127; 526*86d7f5d3SJohn Marino uint32_t tx_pkts_128_255; 527*86d7f5d3SJohn Marino uint32_t tx_pkts_256_511; 528*86d7f5d3SJohn Marino uint32_t tx_pkts_512_1023; 529*86d7f5d3SJohn Marino uint32_t tx_pkts_1024_1518; 530*86d7f5d3SJohn Marino uint32_t tx_pkts_1519_max; 531*86d7f5d3SJohn Marino uint32_t tx_single_colls; 532*86d7f5d3SJohn Marino uint32_t tx_multi_colls; 533*86d7f5d3SJohn Marino uint32_t tx_late_colls; 534*86d7f5d3SJohn Marino uint32_t tx_excess_colls; 535*86d7f5d3SJohn Marino uint32_t tx_underrun; 536*86d7f5d3SJohn Marino uint32_t tx_desc_underrun; 537*86d7f5d3SJohn Marino uint32_t tx_lenerrs; 538*86d7f5d3SJohn Marino uint32_t tx_pkts_truncated; 539*86d7f5d3SJohn Marino uint32_t tx_bcast_bytes; 540*86d7f5d3SJohn Marino uint32_t tx_mcast_bytes; 541*86d7f5d3SJohn Marino uint32_t updated; 542*86d7f5d3SJohn Marino } __packed; 543*86d7f5d3SJohn Marino 544*86d7f5d3SJohn Marino /* Coalescing message block */ 545*86d7f5d3SJohn Marino struct cmb { 546*86d7f5d3SJohn Marino uint32_t intr_status; 547*86d7f5d3SJohn Marino uint32_t rprod_cons; 548*86d7f5d3SJohn Marino #define RRD_PROD_MASK 0x0000FFFF 549*86d7f5d3SJohn Marino #define RD_CONS_MASK 0xFFFF0000 550*86d7f5d3SJohn Marino #define RRD_PROD_SHIFT 0 551*86d7f5d3SJohn Marino #define RD_CONS_SHIFT 16 552*86d7f5d3SJohn Marino uint32_t tpd_cons; 553*86d7f5d3SJohn Marino #define CMB_UPDATED 0x00000001 554*86d7f5d3SJohn Marino #define TPD_CONS_MASK 0xFFFF0000 555*86d7f5d3SJohn Marino #define TPD_CONS_SHIFT 16 556*86d7f5d3SJohn Marino } __packed; 557*86d7f5d3SJohn Marino 558*86d7f5d3SJohn Marino /* Rx return descriptor */ 559*86d7f5d3SJohn Marino struct rx_rdesc { 560*86d7f5d3SJohn Marino uint32_t index; 561*86d7f5d3SJohn Marino #define AGE_RRD_NSEGS_MASK 0x000000FF 562*86d7f5d3SJohn Marino #define AGE_RRD_CONS_MASK 0xFFFF0000 563*86d7f5d3SJohn Marino #define AGE_RRD_NSEGS_SHIFT 0 564*86d7f5d3SJohn Marino #define AGE_RRD_CONS_SHIFT 16 565*86d7f5d3SJohn Marino uint32_t len; 566*86d7f5d3SJohn Marino #define AGE_RRD_CSUM_MASK 0x0000FFFF 567*86d7f5d3SJohn Marino #define AGE_RRD_LEN_MASK 0xFFFF0000 568*86d7f5d3SJohn Marino #define AGE_RRD_CSUM_SHIFT 0 569*86d7f5d3SJohn Marino #define AGE_RRD_LEN_SHIFT 16 570*86d7f5d3SJohn Marino uint32_t flags; 571*86d7f5d3SJohn Marino #define AGE_RRD_ETHERNET 0x00000080 572*86d7f5d3SJohn Marino #define AGE_RRD_VLAN 0x00000100 573*86d7f5d3SJohn Marino #define AGE_RRD_ERROR 0x00000200 574*86d7f5d3SJohn Marino #define AGE_RRD_IPV4 0x00000400 575*86d7f5d3SJohn Marino #define AGE_RRD_UDP 0x00000800 576*86d7f5d3SJohn Marino #define AGE_RRD_TCP 0x00001000 577*86d7f5d3SJohn Marino #define AGE_RRD_BCAST 0x00002000 578*86d7f5d3SJohn Marino #define AGE_RRD_MCAST 0x00004000 579*86d7f5d3SJohn Marino #define AGE_RRD_PAUSE 0x00008000 580*86d7f5d3SJohn Marino #define AGE_RRD_CRC 0x00010000 581*86d7f5d3SJohn Marino #define AGE_RRD_CODE 0x00020000 582*86d7f5d3SJohn Marino #define AGE_RRD_DRIBBLE 0x00040000 583*86d7f5d3SJohn Marino #define AGE_RRD_RUNT 0x00080000 584*86d7f5d3SJohn Marino #define AGE_RRD_OFLOW 0x00100000 585*86d7f5d3SJohn Marino #define AGE_RRD_TRUNC 0x00200000 586*86d7f5d3SJohn Marino #define AGE_RRD_IPCSUM_NOK 0x00400000 587*86d7f5d3SJohn Marino #define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000 588*86d7f5d3SJohn Marino #define AGE_RRD_LENGTH_NOK 0x01000000 589*86d7f5d3SJohn Marino #define AGE_RRD_DES_ADDR_FILTERED 0x02000000 590*86d7f5d3SJohn Marino uint32_t vtags; 591*86d7f5d3SJohn Marino #define AGE_RRD_VLAN_MASK 0xFFFF0000 592*86d7f5d3SJohn Marino #define AGE_RRD_VLAN_SHIFT 16 593*86d7f5d3SJohn Marino } __packed; 594*86d7f5d3SJohn Marino 595*86d7f5d3SJohn Marino #define AGE_RX_NSEGS(x) \ 596*86d7f5d3SJohn Marino (((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT) 597*86d7f5d3SJohn Marino #define AGE_RX_CONS(x) \ 598*86d7f5d3SJohn Marino (((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT) 599*86d7f5d3SJohn Marino #define AGE_RX_CSUM(x) \ 600*86d7f5d3SJohn Marino (((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT) 601*86d7f5d3SJohn Marino #define AGE_RX_BYTES(x) \ 602*86d7f5d3SJohn Marino (((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT) 603*86d7f5d3SJohn Marino #define AGE_RX_VLAN(x) \ 604*86d7f5d3SJohn Marino (((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT) 605*86d7f5d3SJohn Marino #define AGE_RX_VLAN_TAG(x) \ 606*86d7f5d3SJohn Marino (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 607*86d7f5d3SJohn Marino 608*86d7f5d3SJohn Marino /* Rx descriptor. */ 609*86d7f5d3SJohn Marino struct rx_desc { 610*86d7f5d3SJohn Marino uint64_t addr; 611*86d7f5d3SJohn Marino uint32_t len; 612*86d7f5d3SJohn Marino #define AGE_RD_LEN_MASK 0x0000FFFF 613*86d7f5d3SJohn Marino #define AGE_CONS_UPD_REQ_MASK 0xFFFF0000 614*86d7f5d3SJohn Marino #define AGE_RD_LEN_SHIFT 0 615*86d7f5d3SJohn Marino #define AGE_CONS_UPD_REQ_SHIFT 16 616*86d7f5d3SJohn Marino } __packed; 617*86d7f5d3SJohn Marino 618*86d7f5d3SJohn Marino /* Tx descriptor. */ 619*86d7f5d3SJohn Marino struct tx_desc { 620*86d7f5d3SJohn Marino uint64_t addr; 621*86d7f5d3SJohn Marino uint32_t len; 622*86d7f5d3SJohn Marino #define AGE_TD_VLAN_MASK 0xFFFF0000 623*86d7f5d3SJohn Marino #define AGE_TD_PKT_INT 0x00008000 624*86d7f5d3SJohn Marino #define AGE_TD_DMA_INT 0x00004000 625*86d7f5d3SJohn Marino #define AGE_TD_BUFLEN_MASK 0x00003FFF 626*86d7f5d3SJohn Marino #define AGE_TD_VLAN_SHIFT 16 627*86d7f5d3SJohn Marino #define AGE_TX_VLAN_TAG(x) \ 628*86d7f5d3SJohn Marino (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 629*86d7f5d3SJohn Marino #define AGE_TD_BUFLEN_SHIFT 0 630*86d7f5d3SJohn Marino #define AGE_TX_BYTES(x) \ 631*86d7f5d3SJohn Marino (((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK) 632*86d7f5d3SJohn Marino uint32_t flags; 633*86d7f5d3SJohn Marino #define AGE_TD_TSO_MSS 0xFFF80000 634*86d7f5d3SJohn Marino #define AGE_TD_TSO_HDR 0x00040000 635*86d7f5d3SJohn Marino #define AGE_TD_TSO_TCPHDR_LEN 0x0003C000 636*86d7f5d3SJohn Marino #define AGE_TD_IPHDR_LEN 0x00003C00 637*86d7f5d3SJohn Marino #define AGE_TD_LLC_SNAP 0x00000200 638*86d7f5d3SJohn Marino #define AGE_TD_VLAN_TAGGED 0x00000100 639*86d7f5d3SJohn Marino #define AGE_TD_UDPCSUM 0x00000080 640*86d7f5d3SJohn Marino #define AGE_TD_TCPCSUM 0x00000040 641*86d7f5d3SJohn Marino #define AGE_TD_IPCSUM 0x00000020 642*86d7f5d3SJohn Marino #define AGE_TD_TSO_IPV4 0x00000010 643*86d7f5d3SJohn Marino #define AGE_TD_TSO_IPV6 0x00000012 644*86d7f5d3SJohn Marino #define AGE_TD_CSUM 0x00000008 645*86d7f5d3SJohn Marino #define AGE_TD_INSERT_VLAN_TAG 0x00000004 646*86d7f5d3SJohn Marino #define AGE_TD_COALESCE 0x00000002 647*86d7f5d3SJohn Marino #define AGE_TD_EOP 0x00000001 648*86d7f5d3SJohn Marino 649*86d7f5d3SJohn Marino #define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000 650*86d7f5d3SJohn Marino #define AGE_TD_CSUM_XSUMOFFSET 0xFF000000 651*86d7f5d3SJohn Marino #define AGE_TD_CSUM_XSUMOFFSET_SHIFT 24 652*86d7f5d3SJohn Marino #define AGE_TD_CSUM_PLOADOFFSET_SHIFT 16 653*86d7f5d3SJohn Marino #define AGE_TD_TSO_MSS_SHIFT 19 654*86d7f5d3SJohn Marino #define AGE_TD_TSO_TCPHDR_LEN_SHIFT 14 655*86d7f5d3SJohn Marino #define AGE_TD_IPHDR_LEN_SHIFT 10 656*86d7f5d3SJohn Marino } __packed; 657*86d7f5d3SJohn Marino 658*86d7f5d3SJohn Marino #endif /* _IF_AGEREG_H */ 659