1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $ 28 */ 29 30 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/spinlock.h> 42 #include <sys/rman.h> 43 #include <sys/queue.h> 44 #include <sys/socket.h> 45 #include <sys/sockio.h> 46 #include <sys/sysctl.h> 47 #include <sys/taskqueue.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/ifq_var.h> 58 #include <net/vlan/if_vlan_var.h> 59 #include <net/vlan/if_vlan_ether.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/netif/mii_layer/mii.h> 67 #include <dev/netif/mii_layer/miivar.h> 68 69 #include <bus/pci/pcireg.h> 70 #include <bus/pci/pcivar.h> 71 72 #include <machine/atomic.h> 73 /* 74 XXX 75 #include <machine/bus.h> 76 #include <machine/in_cksum.h> 77 */ 78 79 #include "if_alcreg.h" 80 #include "if_alcvar.h" 81 82 /* "device miibus" required. See GENERIC if you get errors here. */ 83 #include "miibus_if.h" 84 #undef ALC_USE_CUSTOM_CSUM 85 86 #ifdef ALC_USE_CUSTOM_CSUM 87 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 88 #else 89 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 90 #endif 91 #ifndef IFCAP_VLAN_HWTSO 92 #define IFCAP_VLAN_HWTSO 0 93 #endif 94 95 MODULE_DEPEND(alc, pci, 1, 1, 1); 96 MODULE_DEPEND(alc, ether, 1, 1, 1); 97 MODULE_DEPEND(alc, miibus, 1, 1, 1); 98 99 /* Tunables. */ 100 static int msi_disable = 0; 101 static int msix_disable = 0; 102 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 103 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 104 105 /* 106 * Devices supported by this driver. 107 */ 108 109 static struct alc_ident alc_ident_table[] = { 110 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 111 "Atheros AR8131 PCIe Gigabit Ethernet" }, 112 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 113 "Atheros AR8132 PCIe Fast Ethernet" }, 114 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 115 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 116 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 117 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 118 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 119 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 120 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 121 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 122 { 0, 0, 0, NULL} 123 }; 124 125 static void alc_aspm(struct alc_softc *, int); 126 static int alc_attach(device_t); 127 static int alc_check_boundary(struct alc_softc *); 128 static int alc_detach(device_t); 129 static void alc_disable_l0s_l1(struct alc_softc *); 130 static int alc_dma_alloc(struct alc_softc *); 131 static void alc_dma_free(struct alc_softc *); 132 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 133 static int alc_encap(struct alc_softc *, struct mbuf **); 134 static struct alc_ident *alc_find_ident(device_t); 135 #ifndef __NO_STRICT_ALIGNMENT 136 static struct mbuf * 137 alc_fixup_rx(struct ifnet *, struct mbuf *); 138 #endif 139 static void alc_get_macaddr(struct alc_softc *); 140 static void alc_init(void *); 141 static void alc_init_cmb(struct alc_softc *); 142 static void alc_init_locked(struct alc_softc *); 143 static void alc_init_rr_ring(struct alc_softc *); 144 static int alc_init_rx_ring(struct alc_softc *); 145 static void alc_init_smb(struct alc_softc *); 146 static void alc_init_tx_ring(struct alc_softc *); 147 static void alc_int_task(void *, int); 148 static void alc_intr(void *); 149 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 150 static void alc_mac_config(struct alc_softc *); 151 static int alc_miibus_readreg(device_t, int, int); 152 static void alc_miibus_statchg(device_t); 153 static int alc_miibus_writereg(device_t, int, int, int); 154 static int alc_mediachange(struct ifnet *); 155 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 156 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 157 static void alc_phy_down(struct alc_softc *); 158 static void alc_phy_reset(struct alc_softc *); 159 static int alc_probe(device_t); 160 static void alc_reset(struct alc_softc *); 161 static int alc_resume(device_t); 162 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 163 static int alc_rxintr(struct alc_softc *, int); 164 static void alc_rxfilter(struct alc_softc *); 165 static void alc_rxvlan(struct alc_softc *); 166 #if 0 167 static void alc_setlinkspeed(struct alc_softc *); 168 /* XXX: WOL */ 169 static void alc_setwol(struct alc_softc *); 170 #endif 171 static int alc_shutdown(device_t); 172 static void alc_start(struct ifnet *); 173 static void alc_start_queue(struct alc_softc *); 174 static void alc_stats_clear(struct alc_softc *); 175 static void alc_stats_update(struct alc_softc *); 176 static void alc_stop(struct alc_softc *); 177 static void alc_stop_mac(struct alc_softc *); 178 static void alc_stop_queue(struct alc_softc *); 179 static int alc_suspend(device_t); 180 static void alc_sysctl_node(struct alc_softc *); 181 static void alc_tick(void *); 182 static void alc_tx_task(void *, int); 183 static void alc_txeof(struct alc_softc *); 184 static void alc_watchdog(struct alc_softc *); 185 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 186 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 187 188 static device_method_t alc_methods[] = { 189 /* Device interface. */ 190 DEVMETHOD(device_probe, alc_probe), 191 DEVMETHOD(device_attach, alc_attach), 192 DEVMETHOD(device_detach, alc_detach), 193 DEVMETHOD(device_shutdown, alc_shutdown), 194 DEVMETHOD(device_suspend, alc_suspend), 195 DEVMETHOD(device_resume, alc_resume), 196 197 /* MII interface. */ 198 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 199 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 200 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 201 202 { NULL, NULL } 203 }; 204 205 static driver_t alc_driver = { 206 "alc", 207 alc_methods, 208 sizeof(struct alc_softc) 209 }; 210 211 static devclass_t alc_devclass; 212 213 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, NULL, NULL); 214 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, NULL, NULL); 215 216 static struct resource_spec alc_res_spec_mem[] = { 217 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 218 { -1, 0, 0 } 219 }; 220 221 static struct resource_spec alc_irq_spec_legacy[] = { 222 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 223 { -1, 0, 0 } 224 }; 225 226 #ifdef OLD_MSI 227 static struct resource_spec alc_irq_spec_msi[] = { 228 { SYS_RES_IRQ, 1, RF_ACTIVE }, 229 { -1, 0, 0 } 230 }; 231 232 static struct resource_spec alc_irq_spec_msix[] = { 233 { SYS_RES_IRQ, 1, RF_ACTIVE }, 234 { -1, 0, 0 } 235 }; 236 #endif 237 238 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 239 240 static int 241 alc_miibus_readreg(device_t dev, int phy, int reg) 242 { 243 struct alc_softc *sc; 244 uint32_t v; 245 int i; 246 247 sc = device_get_softc(dev); 248 249 if (phy != sc->alc_phyaddr) 250 return (0); 251 252 /* 253 * For AR8132 fast ethernet controller, do not report 1000baseT 254 * capability to mii(4). Even though AR8132 uses the same 255 * model/revision number of F1 gigabit PHY, the PHY has no 256 * ability to establish 1000baseT link. 257 */ 258 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 259 reg == MII_EXTSR) 260 return (0); 261 262 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 263 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 264 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 265 DELAY(5); 266 v = CSR_READ_4(sc, ALC_MDIO); 267 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 268 break; 269 } 270 271 if (i == 0) { 272 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 273 return (0); 274 } 275 276 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 277 } 278 279 static int 280 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 281 { 282 struct alc_softc *sc; 283 uint32_t v; 284 int i; 285 286 sc = device_get_softc(dev); 287 288 if (phy != sc->alc_phyaddr) 289 return (0); 290 291 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 292 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 293 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 294 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 295 DELAY(5); 296 v = CSR_READ_4(sc, ALC_MDIO); 297 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 298 break; 299 } 300 301 if (i == 0) 302 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 303 304 return (0); 305 } 306 307 static void 308 alc_miibus_statchg(device_t dev) 309 { 310 struct alc_softc *sc; 311 struct mii_data *mii; 312 struct ifnet *ifp; 313 uint32_t reg; 314 315 sc = device_get_softc(dev); 316 317 mii = device_get_softc(sc->alc_miibus); 318 ifp = sc->alc_ifp; 319 if (mii == NULL || ifp == NULL || 320 (ifp->if_flags & IFF_RUNNING) == 0) 321 return; 322 323 sc->alc_flags &= ~ALC_FLAG_LINK; 324 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 325 (IFM_ACTIVE | IFM_AVALID)) { 326 switch (IFM_SUBTYPE(mii->mii_media_active)) { 327 case IFM_10_T: 328 case IFM_100_TX: 329 sc->alc_flags |= ALC_FLAG_LINK; 330 break; 331 case IFM_1000_T: 332 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 333 sc->alc_flags |= ALC_FLAG_LINK; 334 break; 335 default: 336 break; 337 } 338 } 339 alc_stop_queue(sc); 340 /* Stop Rx/Tx MACs. */ 341 alc_stop_mac(sc); 342 343 /* Program MACs with resolved speed/duplex/flow-control. */ 344 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 345 alc_start_queue(sc); 346 alc_mac_config(sc); 347 /* Re-enable Tx/Rx MACs. */ 348 reg = CSR_READ_4(sc, ALC_MAC_CFG); 349 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 350 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 351 } 352 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 353 } 354 355 static void 356 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 357 { 358 struct alc_softc *sc; 359 struct mii_data *mii; 360 361 sc = ifp->if_softc; 362 ALC_LOCK(sc); 363 if ((ifp->if_flags & IFF_UP) == 0) { 364 ALC_UNLOCK(sc); 365 return; 366 } 367 mii = device_get_softc(sc->alc_miibus); 368 369 mii_pollstat(mii); 370 ALC_UNLOCK(sc); 371 ifmr->ifm_status = mii->mii_media_status; 372 ifmr->ifm_active = mii->mii_media_active; 373 } 374 375 static int 376 alc_mediachange(struct ifnet *ifp) 377 { 378 struct alc_softc *sc; 379 struct mii_data *mii; 380 struct mii_softc *miisc; 381 int error; 382 383 sc = ifp->if_softc; 384 ALC_LOCK(sc); 385 mii = device_get_softc(sc->alc_miibus); 386 if (mii->mii_instance != 0) { 387 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 388 mii_phy_reset(miisc); 389 } 390 error = mii_mediachg(mii); 391 ALC_UNLOCK(sc); 392 393 return (error); 394 } 395 396 static struct alc_ident * 397 alc_find_ident(device_t dev) 398 { 399 struct alc_ident *ident; 400 uint16_t vendor, devid; 401 402 vendor = pci_get_vendor(dev); 403 devid = pci_get_device(dev); 404 for (ident = alc_ident_table; ident->name != NULL; ident++) { 405 if (vendor == ident->vendorid && devid == ident->deviceid) 406 return (ident); 407 } 408 return (NULL); 409 } 410 411 static int 412 alc_probe(device_t dev) 413 { 414 struct alc_ident *ident; 415 416 ident = alc_find_ident(dev); 417 if (ident != NULL) { 418 device_set_desc(dev, ident->name); 419 return (BUS_PROBE_DEFAULT); 420 } 421 return (ENXIO); 422 } 423 424 static void 425 alc_get_macaddr(struct alc_softc *sc) 426 { 427 uint32_t ea[2], opt; 428 uint16_t val; 429 int eeprom, i; 430 431 eeprom = 0; 432 opt = CSR_READ_4(sc, ALC_OPT_CFG); 433 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 434 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 435 /* 436 * EEPROM found, let TWSI reload EEPROM configuration. 437 * This will set ethernet address of controller. 438 */ 439 eeprom++; 440 switch (sc->alc_ident->deviceid) { 441 case DEVICEID_ATHEROS_AR8131: 442 case DEVICEID_ATHEROS_AR8132: 443 if ((opt & OPT_CFG_CLK_ENB) == 0) { 444 opt |= OPT_CFG_CLK_ENB; 445 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 446 CSR_READ_4(sc, ALC_OPT_CFG); 447 DELAY(1000); 448 } 449 break; 450 case DEVICEID_ATHEROS_AR8151: 451 case DEVICEID_ATHEROS_AR8151_V2: 452 case DEVICEID_ATHEROS_AR8152_B: 453 case DEVICEID_ATHEROS_AR8152_B2: 454 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 455 ALC_MII_DBG_ADDR, 0x00); 456 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 457 ALC_MII_DBG_DATA); 458 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 459 ALC_MII_DBG_DATA, val & 0xFF7F); 460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_ADDR, 0x3B); 462 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA); 464 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 465 ALC_MII_DBG_DATA, val | 0x0008); 466 DELAY(20); 467 break; 468 } 469 470 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 471 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 472 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 473 CSR_READ_4(sc, ALC_WOL_CFG); 474 475 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 476 TWSI_CFG_SW_LD_START); 477 478 for (i = 100; i > 0; i--) { 479 DELAY(1000); 480 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 481 TWSI_CFG_SW_LD_START) == 0) 482 break; 483 } 484 if (i == 0) 485 device_printf(sc->alc_dev, 486 "reloading EEPROM timeout!\n"); 487 } else { 488 if (bootverbose) 489 device_printf(sc->alc_dev, "EEPROM not found!\n"); 490 } 491 492 if (eeprom != 0) { 493 switch (sc->alc_ident->deviceid) { 494 case DEVICEID_ATHEROS_AR8131: 495 case DEVICEID_ATHEROS_AR8132: 496 if ((opt & OPT_CFG_CLK_ENB) != 0) { 497 opt &= ~OPT_CFG_CLK_ENB; 498 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 499 CSR_READ_4(sc, ALC_OPT_CFG); 500 DELAY(1000); 501 } 502 break; 503 case DEVICEID_ATHEROS_AR8151: 504 case DEVICEID_ATHEROS_AR8151_V2: 505 case DEVICEID_ATHEROS_AR8152_B: 506 case DEVICEID_ATHEROS_AR8152_B2: 507 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 508 ALC_MII_DBG_ADDR, 0x00); 509 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 510 ALC_MII_DBG_DATA); 511 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 512 ALC_MII_DBG_DATA, val | 0x0080); 513 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 514 ALC_MII_DBG_ADDR, 0x3B); 515 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 516 ALC_MII_DBG_DATA); 517 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 518 ALC_MII_DBG_DATA, val & 0xFFF7); 519 DELAY(20); 520 break; 521 } 522 } 523 524 ea[0] = CSR_READ_4(sc, ALC_PAR0); 525 ea[1] = CSR_READ_4(sc, ALC_PAR1); 526 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 527 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 528 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 529 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 530 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 531 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 532 } 533 534 static void 535 alc_disable_l0s_l1(struct alc_softc *sc) 536 { 537 uint32_t pmcfg; 538 539 /* Another magic from vendor. */ 540 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 541 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 542 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 543 PM_CFG_SERDES_PD_EX_L1); 544 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 545 PM_CFG_SERDES_L1_ENB; 546 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 547 } 548 549 static void 550 alc_phy_reset(struct alc_softc *sc) 551 { 552 uint16_t data; 553 554 /* Reset magic from Linux. */ 555 CSR_WRITE_2(sc, ALC_GPHY_CFG, 556 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 557 CSR_READ_2(sc, ALC_GPHY_CFG); 558 DELAY(10 * 1000); 559 560 CSR_WRITE_2(sc, ALC_GPHY_CFG, 561 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 562 GPHY_CFG_SEL_ANA_RESET); 563 CSR_READ_2(sc, ALC_GPHY_CFG); 564 DELAY(10 * 1000); 565 566 /* DSP fixup, Vendor magic. */ 567 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_ADDR, 0x000A); 570 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 571 ALC_MII_DBG_DATA); 572 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 573 ALC_MII_DBG_DATA, data & 0xDFFF); 574 } 575 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 576 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 578 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 579 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 580 ALC_MII_DBG_ADDR, 0x003B); 581 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 582 ALC_MII_DBG_DATA); 583 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 584 ALC_MII_DBG_DATA, data & 0xFFF7); 585 DELAY(20 * 1000); 586 } 587 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 588 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 589 ALC_MII_DBG_ADDR, 0x0029); 590 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 591 ALC_MII_DBG_DATA, 0x929D); 592 } 593 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 594 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 595 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 596 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 597 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 598 ALC_MII_DBG_ADDR, 0x0029); 599 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 600 ALC_MII_DBG_DATA, 0xB6DD); 601 } 602 603 /* Load DSP codes, vendor magic. */ 604 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 605 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 606 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 607 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 608 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 609 ALC_MII_DBG_DATA, data); 610 611 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 612 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 613 ANA_SERDES_EN_LCKDT; 614 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 615 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 616 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 617 ALC_MII_DBG_DATA, data); 618 619 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 620 ANA_LONG_CABLE_TH_100_MASK) | 621 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 622 ANA_SHORT_CABLE_TH_100_SHIFT) | 623 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 624 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 625 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 626 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 627 ALC_MII_DBG_DATA, data); 628 629 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 630 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 631 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 632 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 633 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 634 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 635 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 636 ALC_MII_DBG_DATA, data); 637 638 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 639 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 640 ANA_OEN_125M; 641 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 642 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 643 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 644 ALC_MII_DBG_DATA, data); 645 DELAY(1000); 646 } 647 648 static void 649 alc_phy_down(struct alc_softc *sc) 650 { 651 switch (sc->alc_ident->deviceid) { 652 case DEVICEID_ATHEROS_AR8151: 653 case DEVICEID_ATHEROS_AR8151_V2: 654 /* 655 * GPHY power down caused more problems on AR8151 v2.0. 656 * When driver is reloaded after GPHY power down, 657 * accesses to PHY/MAC registers hung the system. Only 658 * cold boot recovered from it. I'm not sure whether 659 * AR8151 v1.0 also requires this one though. I don't 660 * have AR8151 v1.0 controller in hand. 661 * The only option left is to isolate the PHY and 662 * initiates power down the PHY which in turn saves 663 * more power when driver is unloaded. 664 */ 665 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 666 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 667 break; 668 default: 669 /* Force PHY down. */ 670 CSR_WRITE_2(sc, ALC_GPHY_CFG, 671 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 672 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 673 GPHY_CFG_PWDOWN_HW); 674 DELAY(1000); 675 break; 676 } 677 678 } 679 680 static void 681 alc_aspm(struct alc_softc *sc, int media) 682 { 683 uint32_t pmcfg; 684 uint16_t linkcfg; 685 686 ALC_LOCK_ASSERT(sc); 687 688 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 689 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 690 (ALC_FLAG_APS | ALC_FLAG_PCIE)) { 691 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 692 PCIR_EXPRESS_LINK_CTL); 693 } else { 694 linkcfg = 0; 695 } 696 697 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 698 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 699 pmcfg |= PM_CFG_MAC_ASPM_CHK; 700 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 701 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 702 703 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 704 /* Disable extended sync except AR8152 B v1.0 */ 705 linkcfg &= ~0x80; 706 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 707 sc->alc_rev == ATHEROS_AR8152_B_V10) 708 linkcfg |= 0x80; 709 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 710 linkcfg); 711 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 712 PM_CFG_HOTRST); 713 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 714 PM_CFG_L1_ENTRY_TIMER_SHIFT); 715 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 716 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 717 PM_CFG_PM_REQ_TIMER_SHIFT); 718 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 719 } 720 721 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 722 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 723 pmcfg |= PM_CFG_ASPM_L0S_ENB; 724 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 725 pmcfg |= PM_CFG_ASPM_L1_ENB; 726 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 727 if (sc->alc_ident->deviceid == 728 DEVICEID_ATHEROS_AR8152_B) { 729 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 730 } 731 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 732 PM_CFG_SERDES_PLL_L1_ENB | 733 PM_CFG_SERDES_BUDS_RX_L1_ENB); 734 pmcfg |= PM_CFG_CLK_SWH_L1; 735 if (media == IFM_100_TX || media == IFM_1000_T) { 736 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 737 switch (sc->alc_ident->deviceid) { 738 case DEVICEID_ATHEROS_AR8152_B: 739 pmcfg |= (7 << 740 PM_CFG_L1_ENTRY_TIMER_SHIFT); 741 break; 742 case DEVICEID_ATHEROS_AR8152_B2: 743 case DEVICEID_ATHEROS_AR8151_V2: 744 pmcfg |= (4 << 745 PM_CFG_L1_ENTRY_TIMER_SHIFT); 746 break; 747 default: 748 pmcfg |= (15 << 749 PM_CFG_L1_ENTRY_TIMER_SHIFT); 750 break; 751 } 752 } 753 } else { 754 pmcfg |= PM_CFG_SERDES_L1_ENB | 755 PM_CFG_SERDES_PLL_L1_ENB | 756 PM_CFG_SERDES_BUDS_RX_L1_ENB; 757 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 758 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 759 } 760 } else { 761 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 762 PM_CFG_SERDES_PLL_L1_ENB); 763 pmcfg |= PM_CFG_CLK_SWH_L1; 764 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 765 pmcfg |= PM_CFG_ASPM_L1_ENB; 766 } 767 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 768 } 769 770 static int 771 alc_attach(device_t dev) 772 { 773 struct alc_softc *sc; 774 struct ifnet *ifp; 775 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 776 uint16_t burst; 777 int base, error, i, msic, msixc, state; 778 uint32_t cap, ctl, val; 779 780 error = 0; 781 sc = device_get_softc(dev); 782 sc->alc_dev = dev; 783 784 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE); 785 callout_init_mp(&sc->alc_tick_ch); 786 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 787 sc->alc_ident = alc_find_ident(dev); 788 789 /* Map the device. */ 790 pci_enable_busmaster(dev); 791 sc->alc_res_spec = alc_res_spec_mem; 792 sc->alc_irq_spec = alc_irq_spec_legacy; 793 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 794 if (error != 0) { 795 device_printf(dev, "cannot allocate memory resources.\n"); 796 goto fail; 797 } 798 799 /* Set PHY address. */ 800 sc->alc_phyaddr = ALC_PHY_ADDR; 801 802 /* Initialize DMA parameters. */ 803 sc->alc_dma_rd_burst = 0; 804 sc->alc_dma_wr_burst = 0; 805 sc->alc_rcb = DMA_CFG_RCB_64; 806 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 807 sc->alc_flags |= ALC_FLAG_PCIE; 808 sc->alc_expcap = base; 809 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 810 sc->alc_dma_rd_burst = 811 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 812 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 813 if (bootverbose) { 814 device_printf(dev, "Read request size : %u bytes.\n", 815 alc_dma_burst[sc->alc_dma_rd_burst]); 816 device_printf(dev, "TLP payload size : %u bytes.\n", 817 alc_dma_burst[sc->alc_dma_wr_burst]); 818 } 819 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 820 sc->alc_dma_rd_burst = 3; 821 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 822 sc->alc_dma_wr_burst = 3; 823 /* Clear data link and flow-control protocol error. */ 824 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 825 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 826 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 827 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 828 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 829 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 830 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 831 PCIE_PHYMISC_FORCE_RCV_DET); 832 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 833 sc->alc_rev == ATHEROS_AR8152_B_V10) { 834 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 835 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 836 PCIE_PHYMISC2_SERDES_TH_MASK); 837 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 838 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 839 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 840 } 841 842 /* Disable ASPM L0S and L1. */ 843 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 844 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 845 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 846 if ((ctl & 0x08) != 0) 847 sc->alc_rcb = DMA_CFG_RCB_128; 848 if (bootverbose) 849 device_printf(dev, "RCB %u bytes\n", 850 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 851 state = ctl & 0x03; 852 if (state & 0x01) 853 sc->alc_flags |= ALC_FLAG_L0S; 854 if (state & 0x02) 855 sc->alc_flags |= ALC_FLAG_L1S; 856 if (bootverbose) 857 device_printf(sc->alc_dev, "ASPM %s %s\n", 858 aspm_state[state], 859 state == 0 ? "disabled" : "enabled"); 860 alc_disable_l0s_l1(sc); 861 } else { 862 if (bootverbose) 863 device_printf(sc->alc_dev, "no ASPM support\n"); 864 } 865 } 866 867 /* Reset PHY. */ 868 alc_phy_reset(sc); 869 870 /* Reset the ethernet controller. */ 871 alc_reset(sc); 872 873 /* 874 * One odd thing is AR8132 uses the same PHY hardware(F1 875 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 876 * the PHY supports 1000Mbps but that's not true. The PHY 877 * used in AR8132 can't establish gigabit link even if it 878 * shows the same PHY model/revision number of AR8131. 879 */ 880 switch (sc->alc_ident->deviceid) { 881 case DEVICEID_ATHEROS_AR8152_B: 882 case DEVICEID_ATHEROS_AR8152_B2: 883 sc->alc_flags |= ALC_FLAG_APS; 884 /* FALLTHROUGH */ 885 case DEVICEID_ATHEROS_AR8132: 886 sc->alc_flags |= ALC_FLAG_FASTETHER; 887 break; 888 case DEVICEID_ATHEROS_AR8151: 889 case DEVICEID_ATHEROS_AR8151_V2: 890 sc->alc_flags |= ALC_FLAG_APS; 891 /* FALLTHROUGH */ 892 default: 893 break; 894 } 895 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 896 897 /* 898 * It seems that AR813x/AR815x has silicon bug for SMB. In 899 * addition, Atheros said that enabling SMB wouldn't improve 900 * performance. However I think it's bad to access lots of 901 * registers to extract MAC statistics. 902 */ 903 sc->alc_flags |= ALC_FLAG_SMB_BUG; 904 905 /* 906 * Don't use Tx CMB. It is known to have silicon bug. 907 */ 908 sc->alc_flags |= ALC_FLAG_CMB_BUG; 909 sc->alc_rev = pci_get_revid(dev); 910 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 911 MASTER_CHIP_REV_SHIFT; 912 if (bootverbose) { 913 device_printf(dev, "PCI device revision : 0x%04x\n", 914 sc->alc_rev); 915 device_printf(dev, "Chip id/revision : 0x%04x\n", 916 sc->alc_chip_rev); 917 } 918 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 919 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 920 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 921 922 /* Allocate IRQ resources. */ 923 msixc = pci_msix_count(dev); 924 msic = pci_msi_count(dev); 925 if (bootverbose) { 926 device_printf(dev, "MSIX count : %d\n", msixc); 927 device_printf(dev, "MSI count : %d\n", msic); 928 } 929 930 #ifdef OLD_MSI 931 /* Prefer MSIX over MSI. */ 932 if (msix_disable == 0 || msi_disable == 0) { 933 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 934 pci_alloc_msix(dev, &msixc) == 0) { 935 if (msic == ALC_MSIX_MESSAGES) { 936 device_printf(dev, 937 "Using %d MSIX message(s).\n", msixc); 938 sc->alc_flags |= ALC_FLAG_MSIX; 939 sc->alc_irq_spec = alc_irq_spec_msix; 940 } else 941 pci_release_msi(dev); 942 } 943 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 944 msic == ALC_MSI_MESSAGES && 945 pci_alloc_msi(dev, &msic) == 0) { 946 if (msic == ALC_MSI_MESSAGES) { 947 device_printf(dev, 948 "Using %d MSI message(s).\n", msic); 949 sc->alc_flags |= ALC_FLAG_MSI; 950 sc->alc_irq_spec = alc_irq_spec_msi; 951 } else 952 pci_release_msi(dev); 953 } 954 } 955 #endif 956 957 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 958 if (error != 0) { 959 device_printf(dev, "cannot allocate IRQ resources.\n"); 960 goto fail; 961 } 962 963 /* Create device sysctl node. */ 964 alc_sysctl_node(sc); 965 966 if ((error = alc_dma_alloc(sc) != 0)) 967 goto fail; 968 969 /* Load station address. */ 970 alc_get_macaddr(sc); 971 972 ifp = sc->alc_ifp = &sc->arpcom.ac_if; 973 ifp->if_softc = sc; 974 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 975 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 976 ifp->if_ioctl = alc_ioctl; 977 ifp->if_start = alc_start; 978 ifp->if_init = alc_init; 979 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1; 980 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 981 ifq_set_ready(&ifp->if_snd); 982 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 983 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 984 #if 0 985 /* XXX: WOL */ 986 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 987 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 988 sc->alc_flags |= ALC_FLAG_PM; 989 sc->alc_pmcap = base; 990 } 991 #endif 992 ifp->if_capenable = ifp->if_capabilities; 993 994 /* Set up MII bus. */ 995 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 996 alc_mediastatus)) != 0) { 997 device_printf(dev, "no PHY found!\n"); 998 goto fail; 999 } 1000 1001 ether_ifattach(ifp, sc->alc_eaddr, NULL); 1002 1003 /* VLAN capability setup. */ 1004 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1005 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1006 ifp->if_capenable = ifp->if_capabilities; 1007 /* 1008 * XXX 1009 * It seems enabling Tx checksum offloading makes more trouble. 1010 * Sometimes the controller does not receive any frames when 1011 * Tx checksum offloading is enabled. I'm not sure whether this 1012 * is a bug in Tx checksum offloading logic or I got broken 1013 * sample boards. To safety, don't enable Tx checksum offloading 1014 * by default but give chance to users to toggle it if they know 1015 * their controllers work without problems. 1016 */ 1017 ifp->if_capenable &= ~IFCAP_TXCSUM; 1018 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1019 1020 /* Tell the upper layer(s) we support long frames. */ 1021 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1022 1023 /* Create local taskq. */ 1024 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1025 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK, 1026 taskqueue_thread_enqueue, &sc->alc_tq); 1027 if (sc->alc_tq == NULL) { 1028 device_printf(dev, "could not create taskqueue.\n"); 1029 ether_ifdetach(ifp); 1030 error = ENXIO; 1031 goto fail; 1032 } 1033 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 1034 device_get_nameunit(sc->alc_dev)); 1035 1036 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1037 msic = ALC_MSIX_MESSAGES; 1038 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1039 msic = ALC_MSI_MESSAGES; 1040 else 1041 msic = 1; 1042 for (i = 0; i < msic; i++) { 1043 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE, 1044 alc_intr, sc, 1045 &sc->alc_intrhand[i], NULL); 1046 if (error != 0) 1047 break; 1048 } 1049 if (error != 0) { 1050 device_printf(dev, "could not set up interrupt handler.\n"); 1051 taskqueue_free(sc->alc_tq); 1052 sc->alc_tq = NULL; 1053 ether_ifdetach(ifp); 1054 goto fail; 1055 } 1056 1057 fail: 1058 if (error != 0) 1059 alc_detach(dev); 1060 1061 return (error); 1062 } 1063 1064 static int 1065 alc_detach(device_t dev) 1066 { 1067 struct alc_softc *sc; 1068 struct ifnet *ifp; 1069 int i, msic; 1070 1071 sc = device_get_softc(dev); 1072 1073 ifp = sc->alc_ifp; 1074 if (device_is_attached(dev)) { 1075 ALC_LOCK(sc); 1076 sc->alc_flags |= ALC_FLAG_DETACH; 1077 alc_stop(sc); 1078 ALC_UNLOCK(sc); 1079 #if 0 1080 /* XXX */ 1081 callout_drain(&sc->alc_tick_ch); 1082 #endif 1083 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1084 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1085 ether_ifdetach(ifp); 1086 } 1087 1088 if (sc->alc_tq != NULL) { 1089 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1090 taskqueue_free(sc->alc_tq); 1091 sc->alc_tq = NULL; 1092 } 1093 1094 if (sc->alc_miibus != NULL) { 1095 device_delete_child(dev, sc->alc_miibus); 1096 sc->alc_miibus = NULL; 1097 } 1098 bus_generic_detach(dev); 1099 alc_dma_free(sc); 1100 1101 if (ifp != NULL) { 1102 // XXX? if_free(ifp); 1103 sc->alc_ifp = NULL; 1104 } 1105 1106 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1107 msic = ALC_MSIX_MESSAGES; 1108 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1109 msic = ALC_MSI_MESSAGES; 1110 else 1111 msic = 1; 1112 for (i = 0; i < msic; i++) { 1113 if (sc->alc_intrhand[i] != NULL) { 1114 bus_teardown_intr(dev, sc->alc_irq[i], 1115 sc->alc_intrhand[i]); 1116 sc->alc_intrhand[i] = NULL; 1117 } 1118 } 1119 if (sc->alc_res[0] != NULL) 1120 alc_phy_down(sc); 1121 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1122 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1123 pci_release_msi(dev); 1124 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1125 lockuninit(&sc->alc_lock); 1126 1127 return (0); 1128 } 1129 1130 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1131 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1132 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1133 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1134 1135 static void 1136 alc_sysctl_node(struct alc_softc *sc) 1137 { 1138 struct sysctl_ctx_list *ctx; 1139 struct sysctl_oid *tree; 1140 struct sysctl_oid_list *child, *parent; 1141 struct alc_hw_stats *stats; 1142 int error; 1143 1144 stats = &sc->alc_stats; 1145 ctx = &sc->alc_sysctl_ctx; 1146 sysctl_ctx_init(ctx); 1147 1148 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 1149 OID_AUTO, 1150 device_get_nameunit(sc->alc_dev), 1151 CTLFLAG_RD, 0, ""); 1152 if (tree == NULL) { 1153 device_printf(sc->alc_dev, "can't add sysctl node\n"); 1154 return; 1155 } 1156 child = SYSCTL_CHILDREN(tree); 1157 1158 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1159 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1160 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1161 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1162 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1163 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1164 /* Pull in device tunables. */ 1165 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1166 error = resource_int_value(device_get_name(sc->alc_dev), 1167 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1168 if (error == 0) { 1169 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1170 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1171 device_printf(sc->alc_dev, "int_rx_mod value out of " 1172 "range; using default: %d\n", 1173 ALC_IM_RX_TIMER_DEFAULT); 1174 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1175 } 1176 } 1177 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1178 error = resource_int_value(device_get_name(sc->alc_dev), 1179 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1180 if (error == 0) { 1181 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1182 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1183 device_printf(sc->alc_dev, "int_tx_mod value out of " 1184 "range; using default: %d\n", 1185 ALC_IM_TX_TIMER_DEFAULT); 1186 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1187 } 1188 } 1189 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1190 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1191 sysctl_hw_alc_proc_limit, "I", 1192 "max number of Rx events to process"); 1193 /* Pull in device tunables. */ 1194 sc->alc_process_limit = ALC_PROC_DEFAULT; 1195 error = resource_int_value(device_get_name(sc->alc_dev), 1196 device_get_unit(sc->alc_dev), "process_limit", 1197 &sc->alc_process_limit); 1198 if (error == 0) { 1199 if (sc->alc_process_limit < ALC_PROC_MIN || 1200 sc->alc_process_limit > ALC_PROC_MAX) { 1201 device_printf(sc->alc_dev, 1202 "process_limit value out of range; " 1203 "using default: %d\n", ALC_PROC_DEFAULT); 1204 sc->alc_process_limit = ALC_PROC_DEFAULT; 1205 } 1206 } 1207 1208 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1209 NULL, "ALC statistics"); 1210 parent = SYSCTL_CHILDREN(tree); 1211 1212 /* Rx statistics. */ 1213 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1214 NULL, "Rx MAC statistics"); 1215 child = SYSCTL_CHILDREN(tree); 1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1217 &stats->rx_frames, "Good frames"); 1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1219 &stats->rx_bcast_frames, "Good broadcast frames"); 1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1221 &stats->rx_mcast_frames, "Good multicast frames"); 1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1223 &stats->rx_pause_frames, "Pause control frames"); 1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1225 &stats->rx_control_frames, "Control frames"); 1226 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1227 &stats->rx_crcerrs, "CRC errors"); 1228 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1229 &stats->rx_lenerrs, "Frames with length mismatched"); 1230 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1231 &stats->rx_bytes, "Good octets"); 1232 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1233 &stats->rx_bcast_bytes, "Good broadcast octets"); 1234 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1235 &stats->rx_mcast_bytes, "Good multicast octets"); 1236 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1237 &stats->rx_runts, "Too short frames"); 1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1239 &stats->rx_fragments, "Fragmented frames"); 1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1241 &stats->rx_pkts_64, "64 bytes frames"); 1242 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1243 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1244 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1245 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1246 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1247 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1249 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1251 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1252 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1253 &stats->rx_pkts_1519_max, "1519 to max frames"); 1254 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1255 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1256 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1257 &stats->rx_fifo_oflows, "FIFO overflows"); 1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1259 &stats->rx_rrs_errs, "Return status write-back errors"); 1260 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1261 &stats->rx_alignerrs, "Alignment errors"); 1262 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1263 &stats->rx_pkts_filtered, 1264 "Frames dropped due to address filtering"); 1265 1266 /* Tx statistics. */ 1267 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1268 NULL, "Tx MAC statistics"); 1269 child = SYSCTL_CHILDREN(tree); 1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1271 &stats->tx_frames, "Good frames"); 1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1273 &stats->tx_bcast_frames, "Good broadcast frames"); 1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1275 &stats->tx_mcast_frames, "Good multicast frames"); 1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1277 &stats->tx_pause_frames, "Pause control frames"); 1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1279 &stats->tx_control_frames, "Control frames"); 1280 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1281 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1282 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1283 &stats->tx_excess_defer, "Frames with derferrals"); 1284 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1285 &stats->tx_bytes, "Good octets"); 1286 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1287 &stats->tx_bcast_bytes, "Good broadcast octets"); 1288 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1289 &stats->tx_mcast_bytes, "Good multicast octets"); 1290 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1291 &stats->tx_pkts_64, "64 bytes frames"); 1292 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1293 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1294 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1295 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1296 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1297 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1298 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1299 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1300 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1301 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1302 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1303 &stats->tx_pkts_1519_max, "1519 to max frames"); 1304 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1305 &stats->tx_single_colls, "Single collisions"); 1306 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1307 &stats->tx_multi_colls, "Multiple collisions"); 1308 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1309 &stats->tx_late_colls, "Late collisions"); 1310 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1311 &stats->tx_excess_colls, "Excessive collisions"); 1312 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1313 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1314 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1315 &stats->tx_underrun, "FIFO underruns"); 1316 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1317 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1318 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1319 &stats->tx_lenerrs, "Frames with length mismatched"); 1320 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1321 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1322 } 1323 1324 #undef ALC_SYSCTL_STAT_ADD32 1325 #undef ALC_SYSCTL_STAT_ADD64 1326 1327 struct alc_dmamap_arg { 1328 bus_addr_t alc_busaddr; 1329 }; 1330 1331 static void 1332 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1333 { 1334 struct alc_dmamap_arg *ctx; 1335 1336 if (error != 0) 1337 return; 1338 1339 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1340 1341 ctx = (struct alc_dmamap_arg *)arg; 1342 ctx->alc_busaddr = segs[0].ds_addr; 1343 } 1344 1345 /* 1346 * Normal and high Tx descriptors shares single Tx high address. 1347 * Four Rx descriptor/return rings and CMB shares the same Rx 1348 * high address. 1349 */ 1350 static int 1351 alc_check_boundary(struct alc_softc *sc) 1352 { 1353 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1354 1355 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1356 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1357 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1358 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1359 1360 /* 4GB boundary crossing is not allowed. */ 1361 if ((ALC_ADDR_HI(rx_ring_end) != 1362 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1363 (ALC_ADDR_HI(rr_ring_end) != 1364 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1365 (ALC_ADDR_HI(cmb_end) != 1366 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1367 (ALC_ADDR_HI(tx_ring_end) != 1368 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1369 return (EFBIG); 1370 /* 1371 * Make sure Rx return descriptor/Rx descriptor/CMB use 1372 * the same high address. 1373 */ 1374 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1375 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1376 return (EFBIG); 1377 1378 return (0); 1379 } 1380 1381 static int 1382 alc_dma_alloc(struct alc_softc *sc) 1383 { 1384 struct alc_txdesc *txd; 1385 struct alc_rxdesc *rxd; 1386 bus_addr_t lowaddr; 1387 struct alc_dmamap_arg ctx; 1388 int error, i; 1389 1390 lowaddr = BUS_SPACE_MAXADDR; 1391 again: 1392 /* Create parent DMA tag. */ 1393 error = bus_dma_tag_create( 1394 sc->alc_cdata.alc_parent_tag, /* parent */ 1395 1, 0, /* alignment, boundary */ 1396 lowaddr, /* lowaddr */ 1397 BUS_SPACE_MAXADDR, /* highaddr */ 1398 NULL, NULL, /* filter, filterarg */ 1399 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1400 0, /* nsegments */ 1401 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1402 0, /* flags */ 1403 &sc->alc_cdata.alc_parent_tag); 1404 if (error != 0) { 1405 device_printf(sc->alc_dev, 1406 "could not create parent DMA tag.\n"); 1407 goto fail; 1408 } 1409 1410 /* Create DMA tag for Tx descriptor ring. */ 1411 error = bus_dma_tag_create( 1412 sc->alc_cdata.alc_parent_tag, /* parent */ 1413 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1414 BUS_SPACE_MAXADDR, /* lowaddr */ 1415 BUS_SPACE_MAXADDR, /* highaddr */ 1416 NULL, NULL, /* filter, filterarg */ 1417 ALC_TX_RING_SZ, /* maxsize */ 1418 1, /* nsegments */ 1419 ALC_TX_RING_SZ, /* maxsegsize */ 1420 0, /* flags */ 1421 &sc->alc_cdata.alc_tx_ring_tag); 1422 if (error != 0) { 1423 device_printf(sc->alc_dev, 1424 "could not create Tx ring DMA tag.\n"); 1425 goto fail; 1426 } 1427 1428 /* Create DMA tag for Rx free descriptor ring. */ 1429 error = bus_dma_tag_create( 1430 sc->alc_cdata.alc_parent_tag, /* parent */ 1431 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1432 BUS_SPACE_MAXADDR, /* lowaddr */ 1433 BUS_SPACE_MAXADDR, /* highaddr */ 1434 NULL, NULL, /* filter, filterarg */ 1435 ALC_RX_RING_SZ, /* maxsize */ 1436 1, /* nsegments */ 1437 ALC_RX_RING_SZ, /* maxsegsize */ 1438 0, /* flags */ 1439 &sc->alc_cdata.alc_rx_ring_tag); 1440 if (error != 0) { 1441 device_printf(sc->alc_dev, 1442 "could not create Rx ring DMA tag.\n"); 1443 goto fail; 1444 } 1445 /* Create DMA tag for Rx return descriptor ring. */ 1446 error = bus_dma_tag_create( 1447 sc->alc_cdata.alc_parent_tag, /* parent */ 1448 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1449 BUS_SPACE_MAXADDR, /* lowaddr */ 1450 BUS_SPACE_MAXADDR, /* highaddr */ 1451 NULL, NULL, /* filter, filterarg */ 1452 ALC_RR_RING_SZ, /* maxsize */ 1453 1, /* nsegments */ 1454 ALC_RR_RING_SZ, /* maxsegsize */ 1455 0, /* flags */ 1456 &sc->alc_cdata.alc_rr_ring_tag); 1457 if (error != 0) { 1458 device_printf(sc->alc_dev, 1459 "could not create Rx return ring DMA tag.\n"); 1460 goto fail; 1461 } 1462 1463 /* Create DMA tag for coalescing message block. */ 1464 error = bus_dma_tag_create( 1465 sc->alc_cdata.alc_parent_tag, /* parent */ 1466 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1467 BUS_SPACE_MAXADDR, /* lowaddr */ 1468 BUS_SPACE_MAXADDR, /* highaddr */ 1469 NULL, NULL, /* filter, filterarg */ 1470 ALC_CMB_SZ, /* maxsize */ 1471 1, /* nsegments */ 1472 ALC_CMB_SZ, /* maxsegsize */ 1473 0, /* flags */ 1474 &sc->alc_cdata.alc_cmb_tag); 1475 if (error != 0) { 1476 device_printf(sc->alc_dev, 1477 "could not create CMB DMA tag.\n"); 1478 goto fail; 1479 } 1480 /* Create DMA tag for status message block. */ 1481 error = bus_dma_tag_create( 1482 sc->alc_cdata.alc_parent_tag, /* parent */ 1483 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1484 BUS_SPACE_MAXADDR, /* lowaddr */ 1485 BUS_SPACE_MAXADDR, /* highaddr */ 1486 NULL, NULL, /* filter, filterarg */ 1487 ALC_SMB_SZ, /* maxsize */ 1488 1, /* nsegments */ 1489 ALC_SMB_SZ, /* maxsegsize */ 1490 0, /* flags */ 1491 &sc->alc_cdata.alc_smb_tag); 1492 if (error != 0) { 1493 device_printf(sc->alc_dev, 1494 "could not create SMB DMA tag.\n"); 1495 goto fail; 1496 } 1497 1498 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1499 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1500 (void **)&sc->alc_rdata.alc_tx_ring, 1501 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1502 &sc->alc_cdata.alc_tx_ring_map); 1503 if (error != 0) { 1504 device_printf(sc->alc_dev, 1505 "could not allocate DMA'able memory for Tx ring.\n"); 1506 goto fail; 1507 } 1508 ctx.alc_busaddr = 0; 1509 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1510 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1511 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1512 if (error != 0 || ctx.alc_busaddr == 0) { 1513 device_printf(sc->alc_dev, 1514 "could not load DMA'able memory for Tx ring.\n"); 1515 goto fail; 1516 } 1517 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1518 1519 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1520 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1521 (void **)&sc->alc_rdata.alc_rx_ring, 1522 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1523 &sc->alc_cdata.alc_rx_ring_map); 1524 if (error != 0) { 1525 device_printf(sc->alc_dev, 1526 "could not allocate DMA'able memory for Rx ring.\n"); 1527 goto fail; 1528 } 1529 ctx.alc_busaddr = 0; 1530 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1531 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1532 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1533 if (error != 0 || ctx.alc_busaddr == 0) { 1534 device_printf(sc->alc_dev, 1535 "could not load DMA'able memory for Rx ring.\n"); 1536 goto fail; 1537 } 1538 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1539 1540 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1541 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1542 (void **)&sc->alc_rdata.alc_rr_ring, 1543 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1544 &sc->alc_cdata.alc_rr_ring_map); 1545 if (error != 0) { 1546 device_printf(sc->alc_dev, 1547 "could not allocate DMA'able memory for Rx return ring.\n"); 1548 goto fail; 1549 } 1550 ctx.alc_busaddr = 0; 1551 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1552 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1553 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1554 if (error != 0 || ctx.alc_busaddr == 0) { 1555 device_printf(sc->alc_dev, 1556 "could not load DMA'able memory for Tx ring.\n"); 1557 goto fail; 1558 } 1559 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1560 1561 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1562 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1563 (void **)&sc->alc_rdata.alc_cmb, 1564 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1565 &sc->alc_cdata.alc_cmb_map); 1566 if (error != 0) { 1567 device_printf(sc->alc_dev, 1568 "could not allocate DMA'able memory for CMB.\n"); 1569 goto fail; 1570 } 1571 ctx.alc_busaddr = 0; 1572 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1573 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1574 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1575 if (error != 0 || ctx.alc_busaddr == 0) { 1576 device_printf(sc->alc_dev, 1577 "could not load DMA'able memory for CMB.\n"); 1578 goto fail; 1579 } 1580 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1581 1582 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1583 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1584 (void **)&sc->alc_rdata.alc_smb, 1585 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1586 &sc->alc_cdata.alc_smb_map); 1587 if (error != 0) { 1588 device_printf(sc->alc_dev, 1589 "could not allocate DMA'able memory for SMB.\n"); 1590 goto fail; 1591 } 1592 ctx.alc_busaddr = 0; 1593 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1594 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1595 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1596 if (error != 0 || ctx.alc_busaddr == 0) { 1597 device_printf(sc->alc_dev, 1598 "could not load DMA'able memory for CMB.\n"); 1599 goto fail; 1600 } 1601 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1602 1603 /* Make sure we've not crossed 4GB boundary. */ 1604 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1605 (error = alc_check_boundary(sc)) != 0) { 1606 device_printf(sc->alc_dev, "4GB boundary crossed, " 1607 "switching to 32bit DMA addressing mode.\n"); 1608 alc_dma_free(sc); 1609 /* 1610 * Limit max allowable DMA address space to 32bit 1611 * and try again. 1612 */ 1613 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1614 goto again; 1615 } 1616 1617 /* 1618 * Create Tx buffer parent tag. 1619 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1620 * so it needs separate parent DMA tag as parent DMA address 1621 * space could be restricted to be within 32bit address space 1622 * by 4GB boundary crossing. 1623 */ 1624 error = bus_dma_tag_create( 1625 sc->alc_cdata.alc_parent_tag, /* parent */ 1626 1, 0, /* alignment, boundary */ 1627 BUS_SPACE_MAXADDR, /* lowaddr */ 1628 BUS_SPACE_MAXADDR, /* highaddr */ 1629 NULL, NULL, /* filter, filterarg */ 1630 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1631 0, /* nsegments */ 1632 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1633 0, /* flags */ 1634 &sc->alc_cdata.alc_buffer_tag); 1635 if (error != 0) { 1636 device_printf(sc->alc_dev, 1637 "could not create parent buffer DMA tag.\n"); 1638 goto fail; 1639 } 1640 1641 /* Create DMA tag for Tx buffers. */ 1642 error = bus_dma_tag_create( 1643 sc->alc_cdata.alc_buffer_tag, /* parent */ 1644 1, 0, /* alignment, boundary */ 1645 BUS_SPACE_MAXADDR, /* lowaddr */ 1646 BUS_SPACE_MAXADDR, /* highaddr */ 1647 NULL, NULL, /* filter, filterarg */ 1648 ALC_TSO_MAXSIZE, /* maxsize */ 1649 ALC_MAXTXSEGS, /* nsegments */ 1650 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1651 0, /* flags */ 1652 &sc->alc_cdata.alc_tx_tag); 1653 if (error != 0) { 1654 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1655 goto fail; 1656 } 1657 1658 /* Create DMA tag for Rx buffers. */ 1659 error = bus_dma_tag_create( 1660 sc->alc_cdata.alc_buffer_tag, /* parent */ 1661 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1662 BUS_SPACE_MAXADDR, /* lowaddr */ 1663 BUS_SPACE_MAXADDR, /* highaddr */ 1664 NULL, NULL, /* filter, filterarg */ 1665 MCLBYTES, /* maxsize */ 1666 1, /* nsegments */ 1667 MCLBYTES, /* maxsegsize */ 1668 0, /* flags */ 1669 &sc->alc_cdata.alc_rx_tag); 1670 if (error != 0) { 1671 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1672 goto fail; 1673 } 1674 /* Create DMA maps for Tx buffers. */ 1675 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1676 txd = &sc->alc_cdata.alc_txdesc[i]; 1677 txd->tx_m = NULL; 1678 txd->tx_dmamap = NULL; 1679 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 1680 BUS_DMA_WAITOK, &txd->tx_dmamap); 1681 if (error != 0) { 1682 device_printf(sc->alc_dev, 1683 "could not create Tx dmamap.\n"); 1684 goto fail; 1685 } 1686 } 1687 /* Create DMA maps for Rx buffers. */ 1688 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1689 BUS_DMA_WAITOK, 1690 &sc->alc_cdata.alc_rx_sparemap); 1691 if (error) { 1692 device_printf(sc->alc_dev, 1693 "could not create spare Rx dmamap.\n"); 1694 goto fail; 1695 } 1696 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1697 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1698 rxd->rx_m = NULL; 1699 rxd->rx_dmamap = NULL; 1700 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1701 BUS_DMA_WAITOK, 1702 &rxd->rx_dmamap); 1703 if (error != 0) { 1704 device_printf(sc->alc_dev, 1705 "could not create Rx dmamap.\n"); 1706 goto fail; 1707 } 1708 } 1709 1710 fail: 1711 return (error); 1712 } 1713 1714 static void 1715 alc_dma_free(struct alc_softc *sc) 1716 { 1717 struct alc_txdesc *txd; 1718 struct alc_rxdesc *rxd; 1719 int i; 1720 1721 /* Tx buffers. */ 1722 if (sc->alc_cdata.alc_tx_tag != NULL) { 1723 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1724 txd = &sc->alc_cdata.alc_txdesc[i]; 1725 if (txd->tx_dmamap != NULL) { 1726 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1727 txd->tx_dmamap); 1728 txd->tx_dmamap = NULL; 1729 } 1730 } 1731 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1732 sc->alc_cdata.alc_tx_tag = NULL; 1733 } 1734 /* Rx buffers */ 1735 if (sc->alc_cdata.alc_rx_tag != NULL) { 1736 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1737 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1738 if (rxd->rx_dmamap != NULL) { 1739 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1740 rxd->rx_dmamap); 1741 rxd->rx_dmamap = NULL; 1742 } 1743 } 1744 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1745 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1746 sc->alc_cdata.alc_rx_sparemap); 1747 sc->alc_cdata.alc_rx_sparemap = NULL; 1748 } 1749 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1750 sc->alc_cdata.alc_rx_tag = NULL; 1751 } 1752 /* Tx descriptor ring. */ 1753 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1754 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1755 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1756 sc->alc_cdata.alc_tx_ring_map); 1757 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1758 sc->alc_rdata.alc_tx_ring != NULL) 1759 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1760 sc->alc_rdata.alc_tx_ring, 1761 sc->alc_cdata.alc_tx_ring_map); 1762 sc->alc_rdata.alc_tx_ring = NULL; 1763 sc->alc_cdata.alc_tx_ring_map = NULL; 1764 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1765 sc->alc_cdata.alc_tx_ring_tag = NULL; 1766 } 1767 /* Rx ring. */ 1768 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1769 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1770 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1771 sc->alc_cdata.alc_rx_ring_map); 1772 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1773 sc->alc_rdata.alc_rx_ring != NULL) 1774 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1775 sc->alc_rdata.alc_rx_ring, 1776 sc->alc_cdata.alc_rx_ring_map); 1777 sc->alc_rdata.alc_rx_ring = NULL; 1778 sc->alc_cdata.alc_rx_ring_map = NULL; 1779 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1780 sc->alc_cdata.alc_rx_ring_tag = NULL; 1781 } 1782 /* Rx return ring. */ 1783 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1784 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1785 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1786 sc->alc_cdata.alc_rr_ring_map); 1787 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1788 sc->alc_rdata.alc_rr_ring != NULL) 1789 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1790 sc->alc_rdata.alc_rr_ring, 1791 sc->alc_cdata.alc_rr_ring_map); 1792 sc->alc_rdata.alc_rr_ring = NULL; 1793 sc->alc_cdata.alc_rr_ring_map = NULL; 1794 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1795 sc->alc_cdata.alc_rr_ring_tag = NULL; 1796 } 1797 /* CMB block */ 1798 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1799 if (sc->alc_cdata.alc_cmb_map != NULL) 1800 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1801 sc->alc_cdata.alc_cmb_map); 1802 if (sc->alc_cdata.alc_cmb_map != NULL && 1803 sc->alc_rdata.alc_cmb != NULL) 1804 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1805 sc->alc_rdata.alc_cmb, 1806 sc->alc_cdata.alc_cmb_map); 1807 sc->alc_rdata.alc_cmb = NULL; 1808 sc->alc_cdata.alc_cmb_map = NULL; 1809 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1810 sc->alc_cdata.alc_cmb_tag = NULL; 1811 } 1812 /* SMB block */ 1813 if (sc->alc_cdata.alc_smb_tag != NULL) { 1814 if (sc->alc_cdata.alc_smb_map != NULL) 1815 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1816 sc->alc_cdata.alc_smb_map); 1817 if (sc->alc_cdata.alc_smb_map != NULL && 1818 sc->alc_rdata.alc_smb != NULL) 1819 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1820 sc->alc_rdata.alc_smb, 1821 sc->alc_cdata.alc_smb_map); 1822 sc->alc_rdata.alc_smb = NULL; 1823 sc->alc_cdata.alc_smb_map = NULL; 1824 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1825 sc->alc_cdata.alc_smb_tag = NULL; 1826 } 1827 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1828 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1829 sc->alc_cdata.alc_buffer_tag = NULL; 1830 } 1831 if (sc->alc_cdata.alc_parent_tag != NULL) { 1832 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1833 sc->alc_cdata.alc_parent_tag = NULL; 1834 } 1835 } 1836 1837 static int 1838 alc_shutdown(device_t dev) 1839 { 1840 1841 return (alc_suspend(dev)); 1842 } 1843 1844 #if 0 1845 /* XXX: LINK SPEED */ 1846 /* 1847 * Note, this driver resets the link speed to 10/100Mbps by 1848 * restarting auto-negotiation in suspend/shutdown phase but we 1849 * don't know whether that auto-negotiation would succeed or not 1850 * as driver has no control after powering off/suspend operation. 1851 * If the renegotiation fail WOL may not work. Running at 1Gbps 1852 * will draw more power than 375mA at 3.3V which is specified in 1853 * PCI specification and that would result in complete 1854 * shutdowning power to ethernet controller. 1855 * 1856 * TODO 1857 * Save current negotiated media speed/duplex/flow-control to 1858 * softc and restore the same link again after resuming. PHY 1859 * handling such as power down/resetting to 100Mbps may be better 1860 * handled in suspend method in phy driver. 1861 */ 1862 static void 1863 alc_setlinkspeed(struct alc_softc *sc) 1864 { 1865 struct mii_data *mii; 1866 int aneg, i; 1867 1868 mii = device_get_softc(sc->alc_miibus); 1869 mii_pollstat(mii); 1870 aneg = 0; 1871 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1872 (IFM_ACTIVE | IFM_AVALID)) { 1873 switch IFM_SUBTYPE(mii->mii_media_active) { 1874 case IFM_10_T: 1875 case IFM_100_TX: 1876 return; 1877 case IFM_1000_T: 1878 aneg++; 1879 break; 1880 default: 1881 break; 1882 } 1883 } 1884 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1885 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1886 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1887 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1888 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1889 DELAY(1000); 1890 if (aneg != 0) { 1891 /* 1892 * Poll link state until alc(4) get a 10/100Mbps link. 1893 */ 1894 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1895 mii_pollstat(mii); 1896 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1897 == (IFM_ACTIVE | IFM_AVALID)) { 1898 switch (IFM_SUBTYPE( 1899 mii->mii_media_active)) { 1900 case IFM_10_T: 1901 case IFM_100_TX: 1902 alc_mac_config(sc); 1903 return; 1904 default: 1905 break; 1906 } 1907 } 1908 ALC_UNLOCK(sc); 1909 pause("alclnk", hz); 1910 ALC_LOCK(sc); 1911 } 1912 if (i == MII_ANEGTICKS_GIGE) 1913 device_printf(sc->alc_dev, 1914 "establishing a link failed, WOL may not work!"); 1915 } 1916 /* 1917 * No link, force MAC to have 100Mbps, full-duplex link. 1918 * This is the last resort and may/may not work. 1919 */ 1920 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1921 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1922 alc_mac_config(sc); 1923 } 1924 #endif 1925 1926 #if 0 1927 /* XXX: WOL */ 1928 static void 1929 alc_setwol(struct alc_softc *sc) 1930 { 1931 struct ifnet *ifp; 1932 uint32_t reg, pmcs; 1933 uint16_t pmstat; 1934 1935 ALC_LOCK_ASSERT(sc); 1936 1937 alc_disable_l0s_l1(sc); 1938 ifp = sc->alc_ifp; 1939 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1940 /* Disable WOL. */ 1941 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1942 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1943 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1944 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1945 /* Force PHY power down. */ 1946 alc_phy_down(sc); 1947 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1948 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1949 return; 1950 } 1951 1952 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1953 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1954 alc_setlinkspeed(sc); 1955 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1956 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1957 } 1958 1959 pmcs = 0; 1960 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1961 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1962 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1963 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1964 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1965 MAC_CFG_BCAST); 1966 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1967 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1968 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1969 reg |= MAC_CFG_RX_ENB; 1970 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1971 1972 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1973 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1974 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1975 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1976 /* WOL disabled, PHY power down. */ 1977 alc_phy_down(sc); 1978 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1979 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1980 1981 } 1982 /* Request PME. */ 1983 pmstat = pci_read_config(sc->alc_dev, 1984 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1985 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1986 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1987 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1988 pci_write_config(sc->alc_dev, 1989 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1990 } 1991 #endif 1992 1993 static int 1994 alc_suspend(device_t dev) 1995 { 1996 struct alc_softc *sc; 1997 1998 sc = device_get_softc(dev); 1999 2000 ALC_LOCK(sc); 2001 alc_stop(sc); 2002 #if 0 2003 /* XXX: WOL */ 2004 alc_setwol(sc); 2005 #endif 2006 ALC_UNLOCK(sc); 2007 2008 return (0); 2009 } 2010 2011 static int 2012 alc_resume(device_t dev) 2013 { 2014 struct alc_softc *sc; 2015 struct ifnet *ifp; 2016 uint16_t pmstat; 2017 2018 sc = device_get_softc(dev); 2019 2020 ALC_LOCK(sc); 2021 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2022 /* Disable PME and clear PME status. */ 2023 pmstat = pci_read_config(sc->alc_dev, 2024 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2025 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2026 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2027 pci_write_config(sc->alc_dev, 2028 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2029 } 2030 } 2031 /* Reset PHY. */ 2032 alc_phy_reset(sc); 2033 ifp = sc->alc_ifp; 2034 if ((ifp->if_flags & IFF_UP) != 0) { 2035 ifp->if_flags &= ~IFF_RUNNING; 2036 alc_init_locked(sc); 2037 } 2038 ALC_UNLOCK(sc); 2039 2040 return (0); 2041 } 2042 2043 static int 2044 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2045 { 2046 struct alc_txdesc *txd, *txd_last; 2047 struct tx_desc *desc; 2048 struct mbuf *m; 2049 #if 0 /* XXX: TSO */ 2050 struct ip *ip; 2051 #endif 2052 struct tcphdr *tcp; 2053 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2054 bus_dmamap_t map; 2055 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2056 int error, idx, nsegs, prod; 2057 2058 ALC_LOCK_ASSERT(sc); 2059 2060 M_ASSERTPKTHDR((*m_head)); 2061 2062 m = *m_head; 2063 tcp = NULL; 2064 ip_off = poff = 0; 2065 #if 0 /* XXX: TSO */ 2066 ip = NULL; 2067 2068 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2069 /* 2070 * AR813x/AR815x requires offset of TCP/UDP header in its 2071 * Tx descriptor to perform Tx checksum offloading. TSO 2072 * also requires TCP header offset and modification of 2073 * IP/TCP header. This kind of operation takes many CPU 2074 * cycles on FreeBSD so fast host CPU is required to get 2075 * smooth TSO performance. 2076 */ 2077 struct ether_header *eh; 2078 2079 if (M_WRITABLE(m) == 0) { 2080 /* Get a writable copy. */ 2081 m = m_dup(*m_head, MB_DONTWAIT); 2082 /* Release original mbufs. */ 2083 m_freem(*m_head); 2084 if (m == NULL) { 2085 *m_head = NULL; 2086 return (ENOBUFS); 2087 } 2088 *m_head = m; 2089 } 2090 2091 ip_off = sizeof(struct ether_header); 2092 m = m_pullup(m, ip_off + sizeof(struct ip)); 2093 if (m == NULL) { 2094 *m_head = NULL; 2095 return (ENOBUFS); 2096 } 2097 eh = mtod(m, struct ether_header *); 2098 /* 2099 * Check if hardware VLAN insertion is off. 2100 * Additional check for LLC/SNAP frame? 2101 */ 2102 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2103 ip_off = sizeof(struct ether_vlan_header); 2104 m = m_pullup(m, ip_off); 2105 if (m == NULL) { 2106 *m_head = NULL; 2107 return (ENOBUFS); 2108 } 2109 } 2110 m = m_pullup(m, ip_off + sizeof(struct ip)); 2111 if (m == NULL) { 2112 *m_head = NULL; 2113 return (ENOBUFS); 2114 } 2115 ip = (struct ip *)(mtod(m, char *) + ip_off); 2116 poff = ip_off + (ip->ip_hl << 2); 2117 2118 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2119 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2120 if (m == NULL) { 2121 *m_head = NULL; 2122 return (ENOBUFS); 2123 } 2124 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2125 m = m_pullup(m, poff + (tcp->th_off << 2)); 2126 if (m == NULL) { 2127 *m_head = NULL; 2128 return (ENOBUFS); 2129 } 2130 /* 2131 * Due to strict adherence of Microsoft NDIS 2132 * Large Send specification, hardware expects 2133 * a pseudo TCP checksum inserted by upper 2134 * stack. Unfortunately the pseudo TCP 2135 * checksum that NDIS refers to does not include 2136 * TCP payload length so driver should recompute 2137 * the pseudo checksum here. Hopefully this 2138 * wouldn't be much burden on modern CPUs. 2139 * 2140 * Reset IP checksum and recompute TCP pseudo 2141 * checksum as NDIS specification said. 2142 */ 2143 ip->ip_sum = 0; 2144 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2145 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2146 } 2147 *m_head = m; 2148 } 2149 #endif /* TSO */ 2150 2151 prod = sc->alc_cdata.alc_tx_prod; 2152 txd = &sc->alc_cdata.alc_txdesc[prod]; 2153 txd_last = txd; 2154 map = txd->tx_dmamap; 2155 2156 error = bus_dmamap_load_mbuf_defrag( 2157 sc->alc_cdata.alc_tx_tag, map, m_head, 2158 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 2159 if (error) { 2160 m_freem(*m_head); 2161 *m_head = NULL; 2162 return (error); 2163 } 2164 if (nsegs == 0) { 2165 m_freem(*m_head); 2166 *m_head = NULL; 2167 return (EIO); 2168 } 2169 2170 /* Check descriptor overrun. */ 2171 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2172 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2173 return (ENOBUFS); 2174 } 2175 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2176 2177 m = *m_head; 2178 cflags = TD_ETHERNET; 2179 vtag = 0; 2180 desc = NULL; 2181 idx = 0; 2182 /* Configure VLAN hardware tag insertion. */ 2183 if ((m->m_flags & M_VLANTAG) != 0) { 2184 vtag = htons(m->m_pkthdr.ether_vlantag); 2185 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2186 cflags |= TD_INS_VLAN_TAG; 2187 } 2188 /* Configure Tx checksum offload. */ 2189 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2190 #ifdef ALC_USE_CUSTOM_CSUM 2191 cflags |= TD_CUSTOM_CSUM; 2192 /* Set checksum start offset. */ 2193 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2194 TD_PLOAD_OFFSET_MASK; 2195 /* Set checksum insertion position of TCP/UDP. */ 2196 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2197 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2198 #else 2199 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2200 cflags |= TD_IPCSUM; 2201 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2202 cflags |= TD_TCPCSUM; 2203 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2204 cflags |= TD_UDPCSUM; 2205 /* Set TCP/UDP header offset. */ 2206 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2207 TD_L4HDR_OFFSET_MASK; 2208 #endif 2209 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2210 /* Request TSO and set MSS. */ 2211 cflags |= TD_TSO | TD_TSO_DESCV1; 2212 #if 0 2213 /* XXX: TSO */ 2214 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2215 TD_MSS_MASK; 2216 /* Set TCP header offset. */ 2217 #endif 2218 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2219 TD_TCPHDR_OFFSET_MASK; 2220 /* 2221 * AR813x/AR815x requires the first buffer should 2222 * only hold IP/TCP header data. Payload should 2223 * be handled in other descriptors. 2224 */ 2225 hdrlen = poff + (tcp->th_off << 2); 2226 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2227 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2228 desc->flags = htole32(cflags); 2229 desc->addr = htole64(txsegs[0].ds_addr); 2230 sc->alc_cdata.alc_tx_cnt++; 2231 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2232 if (m->m_len - hdrlen > 0) { 2233 /* Handle remaining payload of the first fragment. */ 2234 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2235 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2236 vtag)); 2237 desc->flags = htole32(cflags); 2238 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2239 sc->alc_cdata.alc_tx_cnt++; 2240 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2241 } 2242 /* Handle remaining fragments. */ 2243 idx = 1; 2244 } 2245 for (; idx < nsegs; idx++) { 2246 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2247 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2248 desc->flags = htole32(cflags); 2249 desc->addr = htole64(txsegs[idx].ds_addr); 2250 sc->alc_cdata.alc_tx_cnt++; 2251 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2252 } 2253 /* Update producer index. */ 2254 sc->alc_cdata.alc_tx_prod = prod; 2255 2256 /* Finally set EOP on the last descriptor. */ 2257 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2258 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2259 desc->flags |= htole32(TD_EOP); 2260 2261 /* Swap dmamap of the first and the last. */ 2262 txd = &sc->alc_cdata.alc_txdesc[prod]; 2263 map = txd_last->tx_dmamap; 2264 txd_last->tx_dmamap = txd->tx_dmamap; 2265 txd->tx_dmamap = map; 2266 txd->tx_m = m; 2267 2268 return (0); 2269 } 2270 2271 static void 2272 alc_tx_task(void *arg, int pending) 2273 { 2274 struct ifnet *ifp; 2275 2276 ifp = (struct ifnet *)arg; 2277 alc_start(ifp); 2278 } 2279 2280 static void 2281 alc_start(struct ifnet *ifp) 2282 { 2283 struct alc_softc *sc; 2284 struct mbuf *m_head; 2285 int enq; 2286 2287 sc = ifp->if_softc; 2288 2289 ALC_LOCK(sc); 2290 2291 /* Reclaim transmitted frames. */ 2292 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2293 alc_txeof(sc); 2294 2295 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 2296 ALC_UNLOCK(sc); 2297 return; 2298 } 2299 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2300 ifq_purge(&ifp->if_snd); 2301 ALC_UNLOCK(sc); 2302 return; 2303 } 2304 2305 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) { 2306 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2307 if (m_head == NULL) 2308 break; 2309 /* 2310 * Pack the data into the transmit ring. If we 2311 * don't have room, set the OACTIVE flag and wait 2312 * for the NIC to drain the ring. 2313 */ 2314 if (alc_encap(sc, &m_head)) { 2315 if (m_head == NULL) 2316 break; 2317 ifq_prepend(&ifp->if_snd, m_head); 2318 ifp->if_flags |= IFF_OACTIVE; 2319 break; 2320 } 2321 2322 enq++; 2323 /* 2324 * If there's a BPF listener, bounce a copy of this frame 2325 * to him. 2326 */ 2327 ETHER_BPF_MTAP(ifp, m_head); 2328 } 2329 2330 if (enq > 0) { 2331 /* Sync descriptors. */ 2332 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2333 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2334 /* Kick. Assume we're using normal Tx priority queue. */ 2335 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2336 (sc->alc_cdata.alc_tx_prod << 2337 MBOX_TD_PROD_LO_IDX_SHIFT) & 2338 MBOX_TD_PROD_LO_IDX_MASK); 2339 /* Set a timeout in case the chip goes out to lunch. */ 2340 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2341 } 2342 2343 ALC_UNLOCK(sc); 2344 } 2345 2346 static void 2347 alc_watchdog(struct alc_softc *sc) 2348 { 2349 struct ifnet *ifp; 2350 2351 ALC_LOCK_ASSERT(sc); 2352 2353 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2354 return; 2355 2356 ifp = sc->alc_ifp; 2357 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2358 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2359 ifp->if_oerrors++; 2360 ifp->if_flags &= ~IFF_RUNNING; 2361 alc_init_locked(sc); 2362 return; 2363 } 2364 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2365 ifp->if_oerrors++; 2366 ifp->if_flags &= ~IFF_RUNNING; 2367 alc_init_locked(sc); 2368 if (!ifq_is_empty(&ifp->if_snd)) 2369 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2370 } 2371 2372 static int 2373 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2374 { 2375 struct alc_softc *sc; 2376 struct ifreq *ifr; 2377 struct mii_data *mii; 2378 int error, mask; 2379 2380 (void)cr; 2381 sc = ifp->if_softc; 2382 ifr = (struct ifreq *)data; 2383 error = 0; 2384 switch (cmd) { 2385 case SIOCSIFMTU: 2386 if (ifr->ifr_mtu < ETHERMIN || 2387 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2388 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2389 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2390 ifr->ifr_mtu > ETHERMTU)) { 2391 error = EINVAL; 2392 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2393 ALC_LOCK(sc); 2394 ifp->if_mtu = ifr->ifr_mtu; 2395 /* AR813x/AR815x has 13 bits MSS field. */ 2396 if (ifp->if_mtu > ALC_TSO_MTU && 2397 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2398 ifp->if_capenable &= ~IFCAP_TSO4; 2399 ifp->if_hwassist &= ~CSUM_TSO; 2400 } 2401 ALC_UNLOCK(sc); 2402 } 2403 break; 2404 case SIOCSIFFLAGS: 2405 ALC_LOCK(sc); 2406 if ((ifp->if_flags & IFF_UP) != 0) { 2407 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2408 ((ifp->if_flags ^ sc->alc_if_flags) & 2409 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2410 alc_rxfilter(sc); 2411 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2412 alc_init_locked(sc); 2413 } else if ((ifp->if_flags & IFF_RUNNING) != 0) 2414 alc_stop(sc); 2415 sc->alc_if_flags = ifp->if_flags; 2416 ALC_UNLOCK(sc); 2417 break; 2418 case SIOCADDMULTI: 2419 case SIOCDELMULTI: 2420 ALC_LOCK(sc); 2421 if ((ifp->if_flags & IFF_RUNNING) != 0) 2422 alc_rxfilter(sc); 2423 ALC_UNLOCK(sc); 2424 break; 2425 case SIOCSIFMEDIA: 2426 case SIOCGIFMEDIA: 2427 mii = device_get_softc(sc->alc_miibus); 2428 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2429 break; 2430 case SIOCSIFCAP: 2431 ALC_LOCK(sc); 2432 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2433 if ((mask & IFCAP_TXCSUM) != 0 && 2434 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2435 ifp->if_capenable ^= IFCAP_TXCSUM; 2436 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2437 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2438 else 2439 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2440 } 2441 if ((mask & IFCAP_TSO4) != 0 && 2442 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2443 ifp->if_capenable ^= IFCAP_TSO4; 2444 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2445 /* AR813x/AR815x has 13 bits MSS field. */ 2446 if (ifp->if_mtu > ALC_TSO_MTU) { 2447 ifp->if_capenable &= ~IFCAP_TSO4; 2448 ifp->if_hwassist &= ~CSUM_TSO; 2449 } else 2450 ifp->if_hwassist |= CSUM_TSO; 2451 } else 2452 ifp->if_hwassist &= ~CSUM_TSO; 2453 } 2454 #if 0 2455 /* XXX: WOL */ 2456 if ((mask & IFCAP_WOL_MCAST) != 0 && 2457 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2458 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2459 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2460 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2461 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2462 #endif 2463 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2464 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2465 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2466 alc_rxvlan(sc); 2467 } 2468 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2469 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2470 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2471 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2472 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2473 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2474 /* 2475 * VLAN hardware tagging is required to do checksum 2476 * offload or TSO on VLAN interface. Checksum offload 2477 * on VLAN interface also requires hardware checksum 2478 * offload of parent interface. 2479 */ 2480 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2481 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2482 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2483 ifp->if_capenable &= 2484 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2485 ALC_UNLOCK(sc); 2486 // XXX VLAN_CAPABILITIES(ifp); 2487 break; 2488 default: 2489 error = ether_ioctl(ifp, cmd, data); 2490 break; 2491 } 2492 2493 return (error); 2494 } 2495 2496 static void 2497 alc_mac_config(struct alc_softc *sc) 2498 { 2499 struct mii_data *mii; 2500 uint32_t reg; 2501 2502 ALC_LOCK_ASSERT(sc); 2503 2504 mii = device_get_softc(sc->alc_miibus); 2505 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2506 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2507 MAC_CFG_SPEED_MASK); 2508 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2509 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2510 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 2511 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2512 } 2513 /* Reprogram MAC with resolved speed/duplex. */ 2514 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2515 case IFM_10_T: 2516 case IFM_100_TX: 2517 reg |= MAC_CFG_SPEED_10_100; 2518 break; 2519 case IFM_1000_T: 2520 reg |= MAC_CFG_SPEED_1000; 2521 break; 2522 } 2523 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2524 reg |= MAC_CFG_FULL_DUPLEX; 2525 #ifdef notyet 2526 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2527 reg |= MAC_CFG_TX_FC; 2528 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2529 reg |= MAC_CFG_RX_FC; 2530 #endif 2531 } 2532 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2533 } 2534 2535 static void 2536 alc_stats_clear(struct alc_softc *sc) 2537 { 2538 struct smb sb, *smb; 2539 uint32_t *reg; 2540 int i; 2541 2542 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2543 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2544 sc->alc_cdata.alc_smb_map, 2545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2546 smb = sc->alc_rdata.alc_smb; 2547 /* Update done, clear. */ 2548 smb->updated = 0; 2549 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2550 sc->alc_cdata.alc_smb_map, 2551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2552 } else { 2553 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2554 reg++) { 2555 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2556 i += sizeof(uint32_t); 2557 } 2558 /* Read Tx statistics. */ 2559 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2560 reg++) { 2561 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2562 i += sizeof(uint32_t); 2563 } 2564 } 2565 } 2566 2567 static void 2568 alc_stats_update(struct alc_softc *sc) 2569 { 2570 struct alc_hw_stats *stat; 2571 struct smb sb, *smb; 2572 struct ifnet *ifp; 2573 uint32_t *reg; 2574 int i; 2575 2576 ALC_LOCK_ASSERT(sc); 2577 2578 ifp = sc->alc_ifp; 2579 stat = &sc->alc_stats; 2580 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2581 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2582 sc->alc_cdata.alc_smb_map, 2583 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2584 smb = sc->alc_rdata.alc_smb; 2585 if (smb->updated == 0) 2586 return; 2587 } else { 2588 smb = &sb; 2589 /* Read Rx statistics. */ 2590 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2591 reg++) { 2592 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2593 i += sizeof(uint32_t); 2594 } 2595 /* Read Tx statistics. */ 2596 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2597 reg++) { 2598 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2599 i += sizeof(uint32_t); 2600 } 2601 } 2602 2603 /* Rx stats. */ 2604 stat->rx_frames += smb->rx_frames; 2605 stat->rx_bcast_frames += smb->rx_bcast_frames; 2606 stat->rx_mcast_frames += smb->rx_mcast_frames; 2607 stat->rx_pause_frames += smb->rx_pause_frames; 2608 stat->rx_control_frames += smb->rx_control_frames; 2609 stat->rx_crcerrs += smb->rx_crcerrs; 2610 stat->rx_lenerrs += smb->rx_lenerrs; 2611 stat->rx_bytes += smb->rx_bytes; 2612 stat->rx_runts += smb->rx_runts; 2613 stat->rx_fragments += smb->rx_fragments; 2614 stat->rx_pkts_64 += smb->rx_pkts_64; 2615 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2616 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2617 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2618 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2619 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2620 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2621 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2622 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2623 stat->rx_rrs_errs += smb->rx_rrs_errs; 2624 stat->rx_alignerrs += smb->rx_alignerrs; 2625 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2626 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2627 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2628 2629 /* Tx stats. */ 2630 stat->tx_frames += smb->tx_frames; 2631 stat->tx_bcast_frames += smb->tx_bcast_frames; 2632 stat->tx_mcast_frames += smb->tx_mcast_frames; 2633 stat->tx_pause_frames += smb->tx_pause_frames; 2634 stat->tx_excess_defer += smb->tx_excess_defer; 2635 stat->tx_control_frames += smb->tx_control_frames; 2636 stat->tx_deferred += smb->tx_deferred; 2637 stat->tx_bytes += smb->tx_bytes; 2638 stat->tx_pkts_64 += smb->tx_pkts_64; 2639 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2640 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2641 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2642 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2643 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2644 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2645 stat->tx_single_colls += smb->tx_single_colls; 2646 stat->tx_multi_colls += smb->tx_multi_colls; 2647 stat->tx_late_colls += smb->tx_late_colls; 2648 stat->tx_excess_colls += smb->tx_excess_colls; 2649 stat->tx_abort += smb->tx_abort; 2650 stat->tx_underrun += smb->tx_underrun; 2651 stat->tx_desc_underrun += smb->tx_desc_underrun; 2652 stat->tx_lenerrs += smb->tx_lenerrs; 2653 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2654 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2655 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2656 2657 /* Update counters in ifnet. */ 2658 ifp->if_opackets += smb->tx_frames; 2659 2660 ifp->if_collisions += smb->tx_single_colls + 2661 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2662 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2663 2664 /* 2665 * XXX 2666 * tx_pkts_truncated counter looks suspicious. It constantly 2667 * increments with no sign of Tx errors. This may indicate 2668 * the counter name is not correct one so I've removed the 2669 * counter in output errors. 2670 */ 2671 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2672 smb->tx_underrun; 2673 2674 ifp->if_ipackets += smb->rx_frames; 2675 2676 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2677 smb->rx_runts + smb->rx_pkts_truncated + 2678 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2679 smb->rx_alignerrs; 2680 2681 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2682 /* Update done, clear. */ 2683 smb->updated = 0; 2684 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2685 sc->alc_cdata.alc_smb_map, 2686 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2687 } 2688 } 2689 2690 static void 2691 alc_intr(void *arg) 2692 { 2693 struct alc_softc *sc; 2694 uint32_t status; 2695 2696 sc = (struct alc_softc *)arg; 2697 2698 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2699 if ((status & ALC_INTRS) == 0) { 2700 return; 2701 } 2702 /* Disable interrupts. */ 2703 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2704 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2705 2706 return; 2707 } 2708 2709 static void 2710 alc_int_task(void *arg, int pending) 2711 { 2712 struct alc_softc *sc; 2713 struct ifnet *ifp; 2714 uint32_t status; 2715 int more; 2716 2717 sc = (struct alc_softc *)arg; 2718 ifp = sc->alc_ifp; 2719 2720 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2721 more = atomic_readandclear_32(&sc->alc_morework); 2722 if (more != 0) 2723 status |= INTR_RX_PKT; 2724 if ((status & ALC_INTRS) == 0) 2725 goto done; 2726 2727 /* Acknowledge interrupts but still disable interrupts. */ 2728 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2729 2730 more = 0; 2731 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2732 if ((status & INTR_RX_PKT) != 0) { 2733 more = alc_rxintr(sc, sc->alc_process_limit); 2734 if (more == EAGAIN) 2735 atomic_set_int(&sc->alc_morework, 1); 2736 else if (more == EIO) { 2737 ALC_LOCK(sc); 2738 ifp->if_flags &= ~IFF_RUNNING; 2739 alc_init_locked(sc); 2740 ALC_UNLOCK(sc); 2741 return; 2742 } 2743 } 2744 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2745 INTR_TXQ_TO_RST)) != 0) { 2746 if ((status & INTR_DMA_RD_TO_RST) != 0) 2747 device_printf(sc->alc_dev, 2748 "DMA read error! -- resetting\n"); 2749 if ((status & INTR_DMA_WR_TO_RST) != 0) 2750 device_printf(sc->alc_dev, 2751 "DMA write error! -- resetting\n"); 2752 if ((status & INTR_TXQ_TO_RST) != 0) 2753 device_printf(sc->alc_dev, 2754 "TxQ reset! -- resetting\n"); 2755 ALC_LOCK(sc); 2756 ifp->if_flags &= ~IFF_RUNNING; 2757 alc_init_locked(sc); 2758 ALC_UNLOCK(sc); 2759 return; 2760 } 2761 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2762 !ifq_is_empty(&ifp->if_snd)) 2763 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2764 } 2765 2766 if (more == EAGAIN || 2767 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2768 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2769 return; 2770 } 2771 2772 done: 2773 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2774 /* Re-enable interrupts if we're running. */ 2775 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2776 } 2777 } 2778 2779 static void 2780 alc_txeof(struct alc_softc *sc) 2781 { 2782 struct ifnet *ifp; 2783 struct alc_txdesc *txd; 2784 uint32_t cons, prod; 2785 int prog; 2786 2787 ALC_LOCK_ASSERT(sc); 2788 2789 ifp = sc->alc_ifp; 2790 2791 if (sc->alc_cdata.alc_tx_cnt == 0) 2792 return; 2793 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2794 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2795 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2796 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2797 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2798 prod = sc->alc_rdata.alc_cmb->cons; 2799 } else 2800 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2801 /* Assume we're using normal Tx priority queue. */ 2802 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2803 MBOX_TD_CONS_LO_IDX_SHIFT; 2804 cons = sc->alc_cdata.alc_tx_cons; 2805 /* 2806 * Go through our Tx list and free mbufs for those 2807 * frames which have been transmitted. 2808 */ 2809 for (prog = 0; cons != prod; prog++, 2810 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2811 if (sc->alc_cdata.alc_tx_cnt <= 0) 2812 break; 2813 prog++; 2814 ifp->if_flags &= ~IFF_OACTIVE; 2815 sc->alc_cdata.alc_tx_cnt--; 2816 txd = &sc->alc_cdata.alc_txdesc[cons]; 2817 if (txd->tx_m != NULL) { 2818 /* Reclaim transmitted mbufs. */ 2819 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2820 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2821 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2822 txd->tx_dmamap); 2823 m_freem(txd->tx_m); 2824 txd->tx_m = NULL; 2825 } 2826 } 2827 2828 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2829 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2830 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2831 sc->alc_cdata.alc_tx_cons = cons; 2832 /* 2833 * Unarm watchdog timer only when there is no pending 2834 * frames in Tx queue. 2835 */ 2836 if (sc->alc_cdata.alc_tx_cnt == 0) 2837 sc->alc_watchdog_timer = 0; 2838 } 2839 2840 static int 2841 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2842 { 2843 struct mbuf *m; 2844 bus_dma_segment_t segs[1]; 2845 bus_dmamap_t map; 2846 int nsegs; 2847 int error; 2848 2849 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2850 if (m == NULL) 2851 return (ENOBUFS); 2852 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2853 #ifndef __NO_STRICT_ALIGNMENT 2854 m_adj(m, sizeof(uint64_t)); 2855 #endif 2856 2857 error = bus_dmamap_load_mbuf_segment( 2858 sc->alc_cdata.alc_rx_tag, 2859 sc->alc_cdata.alc_rx_sparemap, 2860 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 2861 if (error) { 2862 m_freem(m); 2863 return (ENOBUFS); 2864 } 2865 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2866 2867 if (rxd->rx_m != NULL) { 2868 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2869 BUS_DMASYNC_POSTREAD); 2870 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2871 } 2872 map = rxd->rx_dmamap; 2873 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2874 sc->alc_cdata.alc_rx_sparemap = map; 2875 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2876 BUS_DMASYNC_PREREAD); 2877 rxd->rx_m = m; 2878 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2879 return (0); 2880 } 2881 2882 static int 2883 alc_rxintr(struct alc_softc *sc, int count) 2884 { 2885 struct ifnet *ifp; 2886 struct rx_rdesc *rrd; 2887 uint32_t nsegs, status; 2888 int rr_cons, prog; 2889 2890 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2891 sc->alc_cdata.alc_rr_ring_map, 2892 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2893 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2894 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2895 rr_cons = sc->alc_cdata.alc_rr_cons; 2896 ifp = sc->alc_ifp; 2897 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2898 if (count-- <= 0) 2899 break; 2900 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2901 status = le32toh(rrd->status); 2902 if ((status & RRD_VALID) == 0) 2903 break; 2904 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2905 if (nsegs == 0) { 2906 /* This should not happen! */ 2907 device_printf(sc->alc_dev, 2908 "unexpected segment count -- resetting\n"); 2909 return (EIO); 2910 } 2911 alc_rxeof(sc, rrd); 2912 /* Clear Rx return status. */ 2913 rrd->status = 0; 2914 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2915 sc->alc_cdata.alc_rx_cons += nsegs; 2916 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2917 prog += nsegs; 2918 } 2919 2920 if (prog > 0) { 2921 /* Update the consumer index. */ 2922 sc->alc_cdata.alc_rr_cons = rr_cons; 2923 /* Sync Rx return descriptors. */ 2924 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2925 sc->alc_cdata.alc_rr_ring_map, 2926 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2927 /* 2928 * Sync updated Rx descriptors such that controller see 2929 * modified buffer addresses. 2930 */ 2931 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2932 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2933 /* 2934 * Let controller know availability of new Rx buffers. 2935 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2936 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2937 * only when Rx buffer pre-fetching is required. In 2938 * addition we already set ALC_RX_RD_FREE_THRESH to 2939 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2940 * it still seems that pre-fetching needs more 2941 * experimentation. 2942 */ 2943 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2944 sc->alc_cdata.alc_rx_cons); 2945 } 2946 2947 return (count > 0 ? 0 : EAGAIN); 2948 } 2949 2950 #ifndef __NO_STRICT_ALIGNMENT 2951 static struct mbuf * 2952 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2953 { 2954 struct mbuf *n; 2955 int i; 2956 uint16_t *src, *dst; 2957 2958 src = mtod(m, uint16_t *); 2959 dst = src - 3; 2960 2961 if (m->m_next == NULL) { 2962 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2963 *dst++ = *src++; 2964 m->m_data -= 6; 2965 return (m); 2966 } 2967 /* 2968 * Append a new mbuf to received mbuf chain and copy ethernet 2969 * header from the mbuf chain. This can save lots of CPU 2970 * cycles for jumbo frame. 2971 */ 2972 MGETHDR(n, MB_DONTWAIT, MT_DATA); 2973 if (n == NULL) { 2974 ifp->if_iqdrops++; 2975 m_freem(m); 2976 return (NULL); 2977 } 2978 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2979 m->m_data += ETHER_HDR_LEN; 2980 m->m_len -= ETHER_HDR_LEN; 2981 n->m_len = ETHER_HDR_LEN; 2982 M_MOVE_PKTHDR(n, m); 2983 n->m_next = m; 2984 return (n); 2985 } 2986 #endif 2987 2988 /* Receive a frame. */ 2989 static void 2990 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2991 { 2992 struct alc_rxdesc *rxd; 2993 struct ifnet *ifp; 2994 struct mbuf *mp, *m; 2995 uint32_t rdinfo, status, vtag; 2996 int count, nsegs, rx_cons; 2997 2998 ifp = sc->alc_ifp; 2999 status = le32toh(rrd->status); 3000 rdinfo = le32toh(rrd->rdinfo); 3001 rx_cons = RRD_RD_IDX(rdinfo); 3002 nsegs = RRD_RD_CNT(rdinfo); 3003 3004 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3005 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3006 /* 3007 * We want to pass the following frames to upper 3008 * layer regardless of error status of Rx return 3009 * ring. 3010 * 3011 * o IP/TCP/UDP checksum is bad. 3012 * o frame length and protocol specific length 3013 * does not match. 3014 * 3015 * Force network stack compute checksum for 3016 * errored frames. 3017 */ 3018 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3019 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 3020 RRD_ERR_RUNT) != 0) 3021 return; 3022 } 3023 3024 for (count = 0; count < nsegs; count++, 3025 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3026 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3027 mp = rxd->rx_m; 3028 /* Add a new receive buffer to the ring. */ 3029 if (alc_newbuf(sc, rxd) != 0) { 3030 ifp->if_iqdrops++; 3031 /* Reuse Rx buffers. */ 3032 if (sc->alc_cdata.alc_rxhead != NULL) 3033 m_freem(sc->alc_cdata.alc_rxhead); 3034 break; 3035 } 3036 3037 /* 3038 * Assume we've received a full sized frame. 3039 * Actual size is fixed when we encounter the end of 3040 * multi-segmented frame. 3041 */ 3042 mp->m_len = sc->alc_buf_size; 3043 3044 /* Chain received mbufs. */ 3045 if (sc->alc_cdata.alc_rxhead == NULL) { 3046 sc->alc_cdata.alc_rxhead = mp; 3047 sc->alc_cdata.alc_rxtail = mp; 3048 } else { 3049 mp->m_flags &= ~M_PKTHDR; 3050 sc->alc_cdata.alc_rxprev_tail = 3051 sc->alc_cdata.alc_rxtail; 3052 sc->alc_cdata.alc_rxtail->m_next = mp; 3053 sc->alc_cdata.alc_rxtail = mp; 3054 } 3055 3056 if (count == nsegs - 1) { 3057 /* Last desc. for this frame. */ 3058 m = sc->alc_cdata.alc_rxhead; 3059 m->m_flags |= M_PKTHDR; 3060 /* 3061 * It seems that L1C/L2C controller has no way 3062 * to tell hardware to strip CRC bytes. 3063 */ 3064 m->m_pkthdr.len = 3065 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3066 if (nsegs > 1) { 3067 /* Set last mbuf size. */ 3068 mp->m_len = sc->alc_cdata.alc_rxlen - 3069 (nsegs - 1) * sc->alc_buf_size; 3070 /* Remove the CRC bytes in chained mbufs. */ 3071 if (mp->m_len <= ETHER_CRC_LEN) { 3072 sc->alc_cdata.alc_rxtail = 3073 sc->alc_cdata.alc_rxprev_tail; 3074 sc->alc_cdata.alc_rxtail->m_len -= 3075 (ETHER_CRC_LEN - mp->m_len); 3076 sc->alc_cdata.alc_rxtail->m_next = NULL; 3077 m_freem(mp); 3078 } else { 3079 mp->m_len -= ETHER_CRC_LEN; 3080 } 3081 } else 3082 m->m_len = m->m_pkthdr.len; 3083 m->m_pkthdr.rcvif = ifp; 3084 /* 3085 * Due to hardware bugs, Rx checksum offloading 3086 * was intentionally disabled. 3087 */ 3088 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3089 (status & RRD_VLAN_TAG) != 0) { 3090 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3091 m->m_pkthdr.ether_vlantag = ntohs(vtag); 3092 m->m_flags |= M_VLANTAG; 3093 } 3094 #ifndef __NO_STRICT_ALIGNMENT 3095 m = alc_fixup_rx(ifp, m); 3096 if (m != NULL) 3097 #endif 3098 { 3099 /* Pass it on. */ 3100 (*ifp->if_input)(ifp, m); 3101 } 3102 } 3103 } 3104 /* Reset mbuf chains. */ 3105 ALC_RXCHAIN_RESET(sc); 3106 } 3107 3108 static void 3109 alc_tick(void *arg) 3110 { 3111 struct alc_softc *sc; 3112 struct mii_data *mii; 3113 3114 sc = (struct alc_softc *)arg; 3115 3116 ALC_LOCK(sc); 3117 3118 mii = device_get_softc(sc->alc_miibus); 3119 mii_tick(mii); 3120 alc_stats_update(sc); 3121 /* 3122 * alc(4) does not rely on Tx completion interrupts to reclaim 3123 * transferred buffers. Instead Tx completion interrupts are 3124 * used to hint for scheduling Tx task. So it's necessary to 3125 * release transmitted buffers by kicking Tx completion 3126 * handler. This limits the maximum reclamation delay to a hz. 3127 */ 3128 alc_txeof(sc); 3129 alc_watchdog(sc); 3130 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3131 ALC_UNLOCK(sc); 3132 } 3133 3134 static void 3135 alc_reset(struct alc_softc *sc) 3136 { 3137 uint32_t reg; 3138 int i; 3139 3140 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3141 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3142 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3143 3144 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3145 DELAY(10); 3146 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3147 break; 3148 } 3149 if (i == 0) 3150 device_printf(sc->alc_dev, "master reset timeout!\n"); 3151 3152 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3153 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3154 break; 3155 DELAY(10); 3156 } 3157 3158 if (i == 0) 3159 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3160 } 3161 3162 static void 3163 alc_init(void *xsc) 3164 { 3165 struct alc_softc *sc; 3166 3167 sc = (struct alc_softc *)xsc; 3168 ALC_LOCK(sc); 3169 alc_init_locked(sc); 3170 ALC_UNLOCK(sc); 3171 } 3172 3173 static void 3174 alc_init_locked(struct alc_softc *sc) 3175 { 3176 struct ifnet *ifp; 3177 struct mii_data *mii; 3178 uint8_t eaddr[ETHER_ADDR_LEN]; 3179 bus_addr_t paddr; 3180 uint32_t reg, rxf_hi, rxf_lo; 3181 3182 ALC_LOCK_ASSERT(sc); 3183 3184 ifp = sc->alc_ifp; 3185 mii = device_get_softc(sc->alc_miibus); 3186 3187 if ((ifp->if_flags & IFF_RUNNING) != 0) 3188 return; 3189 /* 3190 * Cancel any pending I/O. 3191 */ 3192 alc_stop(sc); 3193 /* 3194 * Reset the chip to a known state. 3195 */ 3196 alc_reset(sc); 3197 3198 /* Initialize Rx descriptors. */ 3199 if (alc_init_rx_ring(sc) != 0) { 3200 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3201 alc_stop(sc); 3202 return; 3203 } 3204 alc_init_rr_ring(sc); 3205 alc_init_tx_ring(sc); 3206 alc_init_cmb(sc); 3207 alc_init_smb(sc); 3208 3209 /* Reprogram the station address. */ 3210 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3211 CSR_WRITE_4(sc, ALC_PAR0, 3212 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3213 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3214 /* 3215 * Clear WOL status and disable all WOL feature as WOL 3216 * would interfere Rx operation under normal environments. 3217 */ 3218 CSR_READ_4(sc, ALC_WOL_CFG); 3219 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3220 /* Set Tx descriptor base addresses. */ 3221 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3222 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3223 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3224 /* We don't use high priority ring. */ 3225 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3226 /* Set Tx descriptor counter. */ 3227 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3228 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3229 /* Set Rx descriptor base addresses. */ 3230 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3231 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3232 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3233 /* We use one Rx ring. */ 3234 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3235 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3236 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3237 /* Set Rx descriptor counter. */ 3238 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3239 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3240 3241 /* 3242 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3243 * if it do not fit the buffer size. Rx return descriptor holds 3244 * a counter that indicates how many fragments were made by the 3245 * hardware. The buffer size should be multiple of 8 bytes. 3246 * Since hardware has limit on the size of buffer size, always 3247 * use the maximum value. 3248 * For strict-alignment architectures make sure to reduce buffer 3249 * size by 8 bytes to make room for alignment fixup. 3250 */ 3251 #ifndef __NO_STRICT_ALIGNMENT 3252 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3253 #else 3254 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3255 #endif 3256 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3257 3258 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3259 /* Set Rx return descriptor base addresses. */ 3260 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3261 /* We use one Rx return ring. */ 3262 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3263 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3264 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3265 /* Set Rx return descriptor counter. */ 3266 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3267 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3268 paddr = sc->alc_rdata.alc_cmb_paddr; 3269 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3270 paddr = sc->alc_rdata.alc_smb_paddr; 3271 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3272 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3273 3274 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3275 /* Reconfigure SRAM - Vendor magic. */ 3276 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3277 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3278 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3279 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3280 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3281 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3282 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3283 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3284 } 3285 3286 /* Tell hardware that we're ready to load DMA blocks. */ 3287 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3288 3289 /* Configure interrupt moderation timer. */ 3290 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3291 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3292 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3293 /* 3294 * We don't want to automatic interrupt clear as task queue 3295 * for the interrupt should know interrupt status. 3296 */ 3297 reg = MASTER_SA_TIMER_ENB; 3298 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3299 reg |= MASTER_IM_RX_TIMER_ENB; 3300 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3301 reg |= MASTER_IM_TX_TIMER_ENB; 3302 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3303 /* 3304 * Disable interrupt re-trigger timer. We don't want automatic 3305 * re-triggering of un-ACKed interrupts. 3306 */ 3307 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3308 /* Configure CMB. */ 3309 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3310 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3311 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3312 } else { 3313 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3314 } 3315 /* 3316 * Hardware can be configured to issue SMB interrupt based 3317 * on programmed interval. Since there is a callout that is 3318 * invoked for every hz in driver we use that instead of 3319 * relying on periodic SMB interrupt. 3320 */ 3321 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3322 /* Clear MAC statistics. */ 3323 alc_stats_clear(sc); 3324 3325 /* 3326 * Always use maximum frame size that controller can support. 3327 * Otherwise received frames that has larger frame length 3328 * than alc(4) MTU would be silently dropped in hardware. This 3329 * would make path-MTU discovery hard as sender wouldn't get 3330 * any responses from receiver. alc(4) supports 3331 * multi-fragmented frames on Rx path so it has no issue on 3332 * assembling fragmented frames. Using maximum frame size also 3333 * removes the need to reinitialize hardware when interface 3334 * MTU configuration was changed. 3335 * 3336 * Be conservative in what you do, be liberal in what you 3337 * accept from others - RFC 793. 3338 */ 3339 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3340 3341 /* Disable header split(?) */ 3342 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3343 3344 /* Configure IPG/IFG parameters. */ 3345 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3346 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3347 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3348 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3349 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3350 /* Set parameters for half-duplex media. */ 3351 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3352 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3353 HDPX_CFG_LCOL_MASK) | 3354 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3355 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3356 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3357 HDPX_CFG_ABEBT_MASK) | 3358 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3359 HDPX_CFG_JAMIPG_MASK)); 3360 /* 3361 * Set TSO/checksum offload threshold. For frames that is 3362 * larger than this threshold, hardware wouldn't do 3363 * TSO/checksum offloading. 3364 */ 3365 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3366 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3367 TSO_OFFLOAD_THRESH_MASK); 3368 /* Configure TxQ. */ 3369 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3370 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3371 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3372 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3373 reg >>= 1; 3374 } 3375 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3376 TXQ_CFG_TD_BURST_MASK; 3377 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3378 3379 /* Configure Rx free descriptor pre-fetching. */ 3380 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3381 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3382 RX_RD_FREE_THRESH_HI_MASK) | 3383 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3384 RX_RD_FREE_THRESH_LO_MASK)); 3385 3386 /* 3387 * Configure flow control parameters. 3388 * XON : 80% of Rx FIFO 3389 * XOFF : 30% of Rx FIFO 3390 */ 3391 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3392 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3393 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3394 rxf_hi = (reg * 8) / 10; 3395 rxf_lo = (reg * 3) / 10; 3396 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3397 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3398 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3399 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3400 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3401 } 3402 3403 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3404 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) { 3405 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3406 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3407 SERDES_PHY_CLK_SLOWDOWN); 3408 } 3409 3410 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3411 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3412 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3413 3414 /* Configure RxQ. */ 3415 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3416 RXQ_CFG_RD_BURST_MASK; 3417 reg |= RXQ_CFG_RSS_MODE_DIS; 3418 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3419 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3420 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3421 3422 /* Configure DMA parameters. */ 3423 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3424 reg |= sc->alc_rcb; 3425 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3426 reg |= DMA_CFG_CMB_ENB; 3427 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3428 reg |= DMA_CFG_SMB_ENB; 3429 else 3430 reg |= DMA_CFG_SMB_DIS; 3431 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3432 DMA_CFG_RD_BURST_SHIFT; 3433 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3434 DMA_CFG_WR_BURST_SHIFT; 3435 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3436 DMA_CFG_RD_DELAY_CNT_MASK; 3437 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3438 DMA_CFG_WR_DELAY_CNT_MASK; 3439 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3440 3441 /* 3442 * Configure Tx/Rx MACs. 3443 * - Auto-padding for short frames. 3444 * - Enable CRC generation. 3445 * Actual reconfiguration of MAC for resolved speed/duplex 3446 * is followed after detection of link establishment. 3447 * AR813x/AR815x always does checksum computation regardless 3448 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3449 * have bug in protocol field in Rx return structure so 3450 * these controllers can't handle fragmented frames. Disable 3451 * Rx checksum offloading until there is a newer controller 3452 * that has sane implementation. 3453 */ 3454 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3455 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3456 MAC_CFG_PREAMBLE_MASK); 3457 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3458 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3459 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3460 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3461 } 3462 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3463 reg |= MAC_CFG_SPEED_10_100; 3464 else 3465 reg |= MAC_CFG_SPEED_1000; 3466 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3467 3468 /* Set up the receive filter. */ 3469 alc_rxfilter(sc); 3470 alc_rxvlan(sc); 3471 3472 /* Acknowledge all pending interrupts and clear it. */ 3473 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3474 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3475 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3476 3477 sc->alc_flags &= ~ALC_FLAG_LINK; 3478 /* Switch to the current media. */ 3479 mii_mediachg(mii); 3480 3481 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3482 3483 ifp->if_flags |= IFF_RUNNING; 3484 ifp->if_flags &= ~IFF_OACTIVE; 3485 } 3486 3487 static void 3488 alc_stop(struct alc_softc *sc) 3489 { 3490 struct ifnet *ifp; 3491 struct alc_txdesc *txd; 3492 struct alc_rxdesc *rxd; 3493 uint32_t reg; 3494 int i; 3495 3496 ALC_LOCK_ASSERT(sc); 3497 /* 3498 * Mark the interface down and cancel the watchdog timer. 3499 */ 3500 ifp = sc->alc_ifp; 3501 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3502 sc->alc_flags &= ~ALC_FLAG_LINK; 3503 callout_stop(&sc->alc_tick_ch); 3504 sc->alc_watchdog_timer = 0; 3505 alc_stats_update(sc); 3506 /* Disable interrupts. */ 3507 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3508 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3509 alc_stop_queue(sc); 3510 /* Disable DMA. */ 3511 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3512 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3513 reg |= DMA_CFG_SMB_DIS; 3514 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3515 DELAY(1000); 3516 /* Stop Rx/Tx MACs. */ 3517 alc_stop_mac(sc); 3518 /* Disable interrupts which might be touched in taskq handler. */ 3519 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3520 3521 /* Reclaim Rx buffers that have been processed. */ 3522 if (sc->alc_cdata.alc_rxhead != NULL) 3523 m_freem(sc->alc_cdata.alc_rxhead); 3524 ALC_RXCHAIN_RESET(sc); 3525 /* 3526 * Free Tx/Rx mbufs still in the queues. 3527 */ 3528 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3529 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3530 if (rxd->rx_m != NULL) { 3531 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3532 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3533 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3534 rxd->rx_dmamap); 3535 m_freem(rxd->rx_m); 3536 rxd->rx_m = NULL; 3537 } 3538 } 3539 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3540 txd = &sc->alc_cdata.alc_txdesc[i]; 3541 if (txd->tx_m != NULL) { 3542 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3543 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3544 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3545 txd->tx_dmamap); 3546 m_freem(txd->tx_m); 3547 txd->tx_m = NULL; 3548 } 3549 } 3550 } 3551 3552 static void 3553 alc_stop_mac(struct alc_softc *sc) 3554 { 3555 uint32_t reg; 3556 int i; 3557 3558 ALC_LOCK_ASSERT(sc); 3559 3560 /* Disable Rx/Tx MAC. */ 3561 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3562 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3563 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3564 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3565 } 3566 for (i = ALC_TIMEOUT; i > 0; i--) { 3567 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3568 if (reg == 0) 3569 break; 3570 DELAY(10); 3571 } 3572 if (i == 0) 3573 device_printf(sc->alc_dev, 3574 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3575 } 3576 3577 static void 3578 alc_start_queue(struct alc_softc *sc) 3579 { 3580 uint32_t qcfg[] = { 3581 0, 3582 RXQ_CFG_QUEUE0_ENB, 3583 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3584 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3585 RXQ_CFG_ENB 3586 }; 3587 uint32_t cfg; 3588 3589 ALC_LOCK_ASSERT(sc); 3590 3591 /* Enable RxQ. */ 3592 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3593 cfg &= ~RXQ_CFG_ENB; 3594 cfg |= qcfg[1]; 3595 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3596 /* Enable TxQ. */ 3597 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3598 cfg |= TXQ_CFG_ENB; 3599 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3600 } 3601 3602 static void 3603 alc_stop_queue(struct alc_softc *sc) 3604 { 3605 uint32_t reg; 3606 int i; 3607 3608 ALC_LOCK_ASSERT(sc); 3609 3610 /* Disable RxQ. */ 3611 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3612 if ((reg & RXQ_CFG_ENB) != 0) { 3613 reg &= ~RXQ_CFG_ENB; 3614 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3615 } 3616 /* Disable TxQ. */ 3617 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3618 if ((reg & TXQ_CFG_ENB) == 0) { 3619 reg &= ~TXQ_CFG_ENB; 3620 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3621 } 3622 for (i = ALC_TIMEOUT; i > 0; i--) { 3623 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3624 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3625 break; 3626 DELAY(10); 3627 } 3628 if (i == 0) 3629 device_printf(sc->alc_dev, 3630 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3631 } 3632 3633 static void 3634 alc_init_tx_ring(struct alc_softc *sc) 3635 { 3636 struct alc_ring_data *rd; 3637 struct alc_txdesc *txd; 3638 int i; 3639 3640 ALC_LOCK_ASSERT(sc); 3641 3642 sc->alc_cdata.alc_tx_prod = 0; 3643 sc->alc_cdata.alc_tx_cons = 0; 3644 sc->alc_cdata.alc_tx_cnt = 0; 3645 3646 rd = &sc->alc_rdata; 3647 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3648 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3649 txd = &sc->alc_cdata.alc_txdesc[i]; 3650 txd->tx_m = NULL; 3651 } 3652 3653 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3654 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3655 } 3656 3657 static int 3658 alc_init_rx_ring(struct alc_softc *sc) 3659 { 3660 struct alc_ring_data *rd; 3661 struct alc_rxdesc *rxd; 3662 int i; 3663 3664 ALC_LOCK_ASSERT(sc); 3665 3666 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3667 sc->alc_morework = 0; 3668 rd = &sc->alc_rdata; 3669 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3670 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3671 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3672 rxd->rx_m = NULL; 3673 rxd->rx_desc = &rd->alc_rx_ring[i]; 3674 if (alc_newbuf(sc, rxd) != 0) 3675 return (ENOBUFS); 3676 } 3677 3678 /* 3679 * Since controller does not update Rx descriptors, driver 3680 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3681 * is enough to ensure coherence. 3682 */ 3683 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3684 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3685 /* Let controller know availability of new Rx buffers. */ 3686 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3687 3688 return (0); 3689 } 3690 3691 static void 3692 alc_init_rr_ring(struct alc_softc *sc) 3693 { 3694 struct alc_ring_data *rd; 3695 3696 ALC_LOCK_ASSERT(sc); 3697 3698 sc->alc_cdata.alc_rr_cons = 0; 3699 ALC_RXCHAIN_RESET(sc); 3700 3701 rd = &sc->alc_rdata; 3702 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3703 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3704 sc->alc_cdata.alc_rr_ring_map, 3705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3706 } 3707 3708 static void 3709 alc_init_cmb(struct alc_softc *sc) 3710 { 3711 struct alc_ring_data *rd; 3712 3713 ALC_LOCK_ASSERT(sc); 3714 3715 rd = &sc->alc_rdata; 3716 bzero(rd->alc_cmb, ALC_CMB_SZ); 3717 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3719 } 3720 3721 static void 3722 alc_init_smb(struct alc_softc *sc) 3723 { 3724 struct alc_ring_data *rd; 3725 3726 ALC_LOCK_ASSERT(sc); 3727 3728 rd = &sc->alc_rdata; 3729 bzero(rd->alc_smb, ALC_SMB_SZ); 3730 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3732 } 3733 3734 static void 3735 alc_rxvlan(struct alc_softc *sc) 3736 { 3737 struct ifnet *ifp; 3738 uint32_t reg; 3739 3740 ALC_LOCK_ASSERT(sc); 3741 3742 ifp = sc->alc_ifp; 3743 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3744 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3745 reg |= MAC_CFG_VLAN_TAG_STRIP; 3746 else 3747 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3748 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3749 } 3750 3751 static void 3752 alc_rxfilter(struct alc_softc *sc) 3753 { 3754 struct ifnet *ifp; 3755 struct ifmultiaddr *ifma; 3756 uint32_t crc; 3757 uint32_t mchash[2]; 3758 uint32_t rxcfg; 3759 3760 ALC_LOCK_ASSERT(sc); 3761 3762 ifp = sc->alc_ifp; 3763 3764 bzero(mchash, sizeof(mchash)); 3765 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3766 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3767 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3768 rxcfg |= MAC_CFG_BCAST; 3769 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3770 if ((ifp->if_flags & IFF_PROMISC) != 0) 3771 rxcfg |= MAC_CFG_PROMISC; 3772 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3773 rxcfg |= MAC_CFG_ALLMULTI; 3774 mchash[0] = 0xFFFFFFFF; 3775 mchash[1] = 0xFFFFFFFF; 3776 goto chipit; 3777 } 3778 3779 #if 0 3780 /* XXX */ 3781 if_maddr_rlock(ifp); 3782 #endif 3783 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3784 if (ifma->ifma_addr->sa_family != AF_LINK) 3785 continue; 3786 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3787 ifma->ifma_addr), ETHER_ADDR_LEN); 3788 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3789 } 3790 #if 0 3791 /* XXX */ 3792 if_maddr_runlock(ifp); 3793 #endif 3794 3795 chipit: 3796 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3797 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3798 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3799 } 3800 3801 static int 3802 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3803 { 3804 return (sysctl_int_range(oidp, arg1, arg2, req, 3805 ALC_PROC_MIN, ALC_PROC_MAX)); 3806 } 3807 3808 static int 3809 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3810 { 3811 3812 return (sysctl_int_range(oidp, arg1, arg2, req, 3813 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3814 } 3815