1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $ 28 */ 29 30 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/bitops.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/interrupt.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/serialize.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/in_cksum.h> 46 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/bpf.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/ifq_var.h> 54 #include <net/vlan/if_vlan_var.h> 55 #include <net/vlan/if_vlan_ether.h> 56 57 #include <netinet/ip.h> 58 #include <netinet/tcp.h> 59 60 #include <dev/netif/mii_layer/mii.h> 61 #include <dev/netif/mii_layer/miivar.h> 62 63 #include <bus/pci/pcireg.h> 64 #include <bus/pci/pcivar.h> 65 #include "pcidevs.h" 66 67 #include <dev/netif/alc/if_alcreg.h> 68 #include <dev/netif/alc/if_alcvar.h> 69 70 /* "device miibus" required. See GENERIC if you get errors here. */ 71 #include "miibus_if.h" 72 73 #undef ALC_USE_CUSTOM_CSUM 74 #ifdef ALC_USE_CUSTOM_CSUM 75 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 76 #else 77 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 78 #endif 79 80 #define ALC_LOCK(sc) 81 #define ALC_UNLOCK(sc) 82 #define ALC_LOCK_ASSERT(sc) 83 84 #define PCIER_LINK_CAP PCIER_LINKCAP 85 #define PCIEM_LINK_CAP_ASPM PCIEM_LNKCAP_ASPM_MASK 86 #define PCIER_LINK_CTL PCIER_LINKCTRL 87 #define PCIEM_LINK_CTL_RCB PCIEM_LNKCTL_RCB 88 #define PCIEM_LINK_CTL_ASPMC PCIEM_LNKCTL_ASPM_MASK 89 #define PCIEM_LINK_CTL_ASPMC_L0S PCIEM_LNKCTL_ASPM_L0S 90 #define PCIEM_LINK_CTL_ASPMC_L1 PCIEM_LNKCTL_ASPM_L1 91 #define PCIEM_LINK_CTL_EXTENDED_SYNC PCIEM_LNKCTL_EXTENDED_SYNC 92 #define PCIER_DEVICE_CTL PCIER_DEVCTRL 93 #define PCIEM_CTL_MAX_READ_REQUEST PCIEM_DEVCTL_MAX_READRQ_MASK 94 #define PCIEM_CTL_MAX_PAYLOAD PCIEM_DEVCTL_MAX_PAYLOAD_MASK 95 96 /* Tunables. */ 97 static int alc_msi_enable = 1; 98 TUNABLE_INT("hw.alc.msi.enable", &alc_msi_enable); 99 100 /* 101 * Devices supported by this driver. 102 */ 103 104 static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8161 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8161 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8161 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { 0, 0, 0, NULL} 128 }; 129 130 static int alc_attach(device_t); 131 static int alc_probe(device_t); 132 static int alc_detach(device_t); 133 static int alc_shutdown(device_t); 134 static int alc_suspend(device_t); 135 static int alc_resume(device_t); 136 static int alc_miibus_readreg(device_t, int, int); 137 static void alc_miibus_statchg(device_t); 138 static int alc_miibus_writereg(device_t, int, int, int); 139 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 140 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 141 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 142 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 143 static void alc_init(void *); 144 static void alc_start(struct ifnet *, struct ifaltq_subque *); 145 static void alc_watchdog(struct alc_softc *); 146 static int alc_mediachange(struct ifnet *); 147 static int alc_mediachange_locked(struct alc_softc *); 148 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 149 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 150 151 static void alc_aspm(struct alc_softc *, int, int); 152 static void alc_aspm_813x(struct alc_softc *, int); 153 static void alc_aspm_816x(struct alc_softc *, int); 154 #ifdef foo 155 static int alc_check_boundary(struct alc_softc *); 156 #endif 157 static void alc_config_msi(struct alc_softc *); 158 static void alc_disable_l0s_l1(struct alc_softc *); 159 static int alc_dma_alloc(struct alc_softc *); 160 static void alc_dma_free(struct alc_softc *); 161 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 162 static void alc_dsp_fixup(struct alc_softc *, int); 163 static int alc_encap(struct alc_softc *, struct mbuf **); 164 static struct alc_ident *alc_find_ident(device_t); 165 static void alc_get_macaddr(struct alc_softc *); 166 static void alc_get_macaddr_813x(struct alc_softc *); 167 static void alc_get_macaddr_816x(struct alc_softc *); 168 static void alc_get_macaddr_par(struct alc_softc *); 169 static void alc_init_cmb(struct alc_softc *); 170 static void alc_init_rr_ring(struct alc_softc *); 171 static int alc_init_rx_ring(struct alc_softc *); 172 static void alc_init_smb(struct alc_softc *); 173 static void alc_init_tx_ring(struct alc_softc *); 174 static void alc_intr(void *); 175 static void alc_mac_config(struct alc_softc *); 176 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 177 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 178 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 179 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 180 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *, boolean_t); 181 static void alc_osc_reset(struct alc_softc *); 182 static void alc_phy_down(struct alc_softc *); 183 static void alc_phy_reset(struct alc_softc *); 184 static void alc_phy_reset_813x(struct alc_softc *); 185 static void alc_phy_reset_816x(struct alc_softc *); 186 static void alc_reset(struct alc_softc *); 187 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 188 static int alc_rxintr(struct alc_softc *); 189 static void alc_rxfilter(struct alc_softc *); 190 static void alc_rxvlan(struct alc_softc *); 191 #if 0 192 static void alc_setlinkspeed(struct alc_softc *); 193 /* XXX: WOL */ 194 static void alc_setwol(struct alc_softc *); 195 static void alc_setwol_813x(struct alc_softc *); 196 static void alc_setwol_816x(struct alc_softc *); 197 #endif 198 static void alc_start_queue(struct alc_softc *); 199 static void alc_stats_clear(struct alc_softc *); 200 static void alc_stats_update(struct alc_softc *); 201 static void alc_stop(struct alc_softc *); 202 static void alc_stop_mac(struct alc_softc *); 203 static void alc_stop_queue(struct alc_softc *); 204 static void alc_sysctl_node(struct alc_softc *); 205 static void alc_tick(void *); 206 static void alc_txeof(struct alc_softc *); 207 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 208 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 209 210 static device_method_t alc_methods[] = { 211 /* Device interface. */ 212 DEVMETHOD(device_probe, alc_probe), 213 DEVMETHOD(device_attach, alc_attach), 214 DEVMETHOD(device_detach, alc_detach), 215 DEVMETHOD(device_shutdown, alc_shutdown), 216 DEVMETHOD(device_suspend, alc_suspend), 217 DEVMETHOD(device_resume, alc_resume), 218 219 /* MII interface. */ 220 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 221 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 222 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 223 224 { NULL, NULL } 225 }; 226 227 static DEFINE_CLASS_0(alc, alc_driver, alc_methods, sizeof(struct alc_softc)); 228 static devclass_t alc_devclass; 229 230 DECLARE_DUMMY_MODULE(if_alc); 231 DRIVER_MODULE(if_alc, pci, alc_driver, alc_devclass, NULL, NULL); 232 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, NULL, NULL); 233 234 static const uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 235 236 static int 237 alc_miibus_readreg(device_t dev, int phy, int reg) 238 { 239 struct alc_softc *sc; 240 int v; 241 242 sc = device_get_softc(dev); 243 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 244 v = alc_mii_readreg_816x(sc, phy, reg); 245 else 246 v = alc_mii_readreg_813x(sc, phy, reg); 247 return (v); 248 } 249 250 static uint32_t 251 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 252 { 253 uint32_t v; 254 int i; 255 256 /* 257 * For AR8132 fast ethernet controller, do not report 1000baseT 258 * capability to mii(4). Even though AR8132 uses the same 259 * model/revision number of F1 gigabit PHY, the PHY has no 260 * ability to establish 1000baseT link. 261 */ 262 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 263 reg == MII_EXTSR) 264 return (0); 265 266 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 267 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 268 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 269 DELAY(5); 270 v = CSR_READ_4(sc, ALC_MDIO); 271 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 272 break; 273 } 274 275 if (i == 0) { 276 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 277 return (0); 278 } 279 280 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 281 } 282 283 static uint32_t 284 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 285 { 286 uint32_t clk, v; 287 int i; 288 289 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 290 clk = MDIO_CLK_25_128; 291 else 292 clk = MDIO_CLK_25_4; 293 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 294 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 295 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 296 DELAY(5); 297 v = CSR_READ_4(sc, ALC_MDIO); 298 if ((v & MDIO_OP_BUSY) == 0) 299 break; 300 } 301 302 if (i == 0) { 303 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 304 return (0); 305 } 306 307 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 308 } 309 310 static int 311 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 312 { 313 struct alc_softc *sc; 314 int v; 315 316 sc = device_get_softc(dev); 317 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 318 v = alc_mii_writereg_816x(sc, phy, reg, val); 319 else 320 v = alc_mii_writereg_813x(sc, phy, reg, val); 321 return (v); 322 } 323 324 static uint32_t 325 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 326 { 327 uint32_t v; 328 int i; 329 330 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 331 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 332 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 333 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 334 DELAY(5); 335 v = CSR_READ_4(sc, ALC_MDIO); 336 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 337 break; 338 } 339 340 if (i == 0) 341 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 342 343 return (0); 344 } 345 346 static uint32_t 347 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 348 { 349 uint32_t clk, v; 350 int i; 351 352 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 353 clk = MDIO_CLK_25_128; 354 else 355 clk = MDIO_CLK_25_4; 356 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 357 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 358 MDIO_SUP_PREAMBLE | clk); 359 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 360 DELAY(5); 361 v = CSR_READ_4(sc, ALC_MDIO); 362 if ((v & MDIO_OP_BUSY) == 0) 363 break; 364 } 365 366 if (i == 0) 367 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 368 369 return (0); 370 } 371 372 static void 373 alc_miibus_statchg(device_t dev) 374 { 375 struct alc_softc *sc; 376 struct mii_data *mii; 377 struct ifnet *ifp; 378 uint32_t reg; 379 380 sc = device_get_softc(dev); 381 382 mii = device_get_softc(sc->alc_miibus); 383 ifp = sc->alc_ifp; 384 if (mii == NULL || ifp == NULL || 385 (ifp->if_flags & IFF_RUNNING) == 0) 386 return; 387 388 sc->alc_flags &= ~ALC_FLAG_LINK; 389 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 390 (IFM_ACTIVE | IFM_AVALID)) { 391 switch (IFM_SUBTYPE(mii->mii_media_active)) { 392 case IFM_10_T: 393 case IFM_100_TX: 394 sc->alc_flags |= ALC_FLAG_LINK; 395 break; 396 case IFM_1000_T: 397 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 398 sc->alc_flags |= ALC_FLAG_LINK; 399 break; 400 default: 401 break; 402 } 403 } 404 /* Stop Rx/Tx MACs. */ 405 alc_stop_mac(sc); 406 407 /* Program MACs with resolved speed/duplex/flow-control. */ 408 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 409 alc_start_queue(sc); 410 alc_mac_config(sc); 411 /* Re-enable Tx/Rx MACs. */ 412 reg = CSR_READ_4(sc, ALC_MAC_CFG); 413 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 414 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 415 } 416 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 417 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 418 } 419 420 static uint32_t 421 alc_miidbg_readreg(struct alc_softc *sc, int reg) 422 { 423 424 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 425 reg); 426 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 427 ALC_MII_DBG_DATA)); 428 } 429 430 static uint32_t 431 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 432 { 433 434 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 435 reg); 436 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_DATA, val)); 438 } 439 440 static uint32_t 441 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 442 { 443 uint32_t clk, v; 444 int i; 445 446 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 447 EXT_MDIO_DEVADDR(devaddr)); 448 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 449 clk = MDIO_CLK_25_128; 450 else 451 clk = MDIO_CLK_25_4; 452 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 453 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 454 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 455 DELAY(5); 456 v = CSR_READ_4(sc, ALC_MDIO); 457 if ((v & MDIO_OP_BUSY) == 0) 458 break; 459 } 460 461 if (i == 0) { 462 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 463 devaddr, reg); 464 return (0); 465 } 466 467 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 468 } 469 470 static uint32_t 471 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 472 { 473 uint32_t clk, v; 474 int i; 475 476 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 477 EXT_MDIO_DEVADDR(devaddr)); 478 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 479 clk = MDIO_CLK_25_128; 480 else 481 clk = MDIO_CLK_25_4; 482 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 483 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 484 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 485 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 486 DELAY(5); 487 v = CSR_READ_4(sc, ALC_MDIO); 488 if ((v & MDIO_OP_BUSY) == 0) 489 break; 490 } 491 492 if (i == 0) 493 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 494 devaddr, reg); 495 496 return (0); 497 } 498 499 static void 500 alc_dsp_fixup(struct alc_softc *sc, int media) 501 { 502 uint16_t agc, len, val; 503 504 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 505 return; 506 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 507 return; 508 509 /* 510 * Vendor PHY magic. 511 * 1000BT/AZ, wrong cable length 512 */ 513 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 514 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 515 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 516 EXT_CLDCTL6_CAB_LEN_MASK; 517 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 518 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 519 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 520 agc > DBG_AGC_LONG1G_LIMT) || 521 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 522 agc > DBG_AGC_LONG1G_LIMT)) { 523 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 524 DBG_AZ_ANADECT_LONG); 525 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 526 MII_EXT_ANEG_AFE); 527 val |= ANEG_AFEE_10BT_100M_TH; 528 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 529 val); 530 } else { 531 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 532 DBG_AZ_ANADECT_DEFAULT); 533 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 534 MII_EXT_ANEG_AFE); 535 val &= ~ANEG_AFEE_10BT_100M_TH; 536 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 537 val); 538 } 539 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 540 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 541 if (media == IFM_1000_T) { 542 /* 543 * Giga link threshold, raise the tolerance of 544 * noise 50%. 545 */ 546 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 547 val &= ~DBG_MSE20DB_TH_MASK; 548 val |= (DBG_MSE20DB_TH_HI << 549 DBG_MSE20DB_TH_SHIFT); 550 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 551 } else if (media == IFM_100_TX) 552 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 553 DBG_MSE16DB_UP); 554 } 555 } else { 556 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 557 val &= ~ANEG_AFEE_10BT_100M_TH; 558 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 559 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 560 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 561 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 562 DBG_MSE16DB_DOWN); 563 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 564 val &= ~DBG_MSE20DB_TH_MASK; 565 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 566 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 567 } 568 } 569 } 570 571 static void 572 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 573 { 574 struct alc_softc *sc; 575 struct mii_data *mii; 576 577 sc = ifp->if_softc; 578 if ((ifp->if_flags & IFF_UP) == 0) { 579 return; 580 } 581 mii = device_get_softc(sc->alc_miibus); 582 583 mii_pollstat(mii); 584 ifmr->ifm_status = mii->mii_media_status; 585 ifmr->ifm_active = mii->mii_media_active; 586 } 587 588 static int 589 alc_mediachange(struct ifnet *ifp) 590 { 591 struct alc_softc *sc; 592 int error; 593 594 sc = ifp->if_softc; 595 ALC_LOCK(sc); 596 error = alc_mediachange_locked(sc); 597 ALC_UNLOCK(sc); 598 599 return (error); 600 } 601 602 static int 603 alc_mediachange_locked(struct alc_softc *sc) 604 { 605 struct mii_data *mii; 606 struct mii_softc *miisc; 607 int error; 608 609 ALC_LOCK_ASSERT(sc); 610 611 mii = device_get_softc(sc->alc_miibus); 612 if (mii->mii_instance != 0) { 613 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 614 mii_phy_reset(miisc); 615 } 616 error = mii_mediachg(mii); 617 618 return (error); 619 } 620 621 static struct alc_ident * 622 alc_find_ident(device_t dev) 623 { 624 struct alc_ident *ident; 625 uint16_t vendor, devid; 626 627 vendor = pci_get_vendor(dev); 628 devid = pci_get_device(dev); 629 for (ident = alc_ident_table; ident->name != NULL; ident++) { 630 if (vendor == ident->vendorid && devid == ident->deviceid) 631 return (ident); 632 } 633 634 return (NULL); 635 } 636 637 static int 638 alc_probe(device_t dev) 639 { 640 struct alc_ident *ident; 641 642 ident = alc_find_ident(dev); 643 if (ident != NULL) { 644 device_set_desc(dev, ident->name); 645 return (BUS_PROBE_DEFAULT); 646 } 647 648 return (ENXIO); 649 } 650 651 static void 652 alc_get_macaddr(struct alc_softc *sc) 653 { 654 655 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 656 alc_get_macaddr_816x(sc); 657 else 658 alc_get_macaddr_813x(sc); 659 } 660 661 static void 662 alc_get_macaddr_813x(struct alc_softc *sc) 663 { 664 uint32_t opt; 665 uint16_t val; 666 int eeprom, i; 667 668 eeprom = 0; 669 opt = CSR_READ_4(sc, ALC_OPT_CFG); 670 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 671 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 672 /* 673 * EEPROM found, let TWSI reload EEPROM configuration. 674 * This will set ethernet address of controller. 675 */ 676 eeprom++; 677 switch (sc->alc_ident->deviceid) { 678 case DEVICEID_ATHEROS_AR8131: 679 case DEVICEID_ATHEROS_AR8132: 680 if ((opt & OPT_CFG_CLK_ENB) == 0) { 681 opt |= OPT_CFG_CLK_ENB; 682 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 683 CSR_READ_4(sc, ALC_OPT_CFG); 684 DELAY(1000); 685 } 686 break; 687 case DEVICEID_ATHEROS_AR8151: 688 case DEVICEID_ATHEROS_AR8151_V2: 689 case DEVICEID_ATHEROS_AR8152_B: 690 case DEVICEID_ATHEROS_AR8152_B2: 691 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 692 ALC_MII_DBG_ADDR, 0x00); 693 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 694 ALC_MII_DBG_DATA); 695 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 696 ALC_MII_DBG_DATA, val & 0xFF7F); 697 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 698 ALC_MII_DBG_ADDR, 0x3B); 699 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 700 ALC_MII_DBG_DATA); 701 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 702 ALC_MII_DBG_DATA, val | 0x0008); 703 DELAY(20); 704 break; 705 } 706 707 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 708 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 709 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 710 CSR_READ_4(sc, ALC_WOL_CFG); 711 712 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 713 TWSI_CFG_SW_LD_START); 714 for (i = 100; i > 0; i--) { 715 DELAY(1000); 716 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 717 TWSI_CFG_SW_LD_START) == 0) 718 break; 719 } 720 if (i == 0) 721 device_printf(sc->alc_dev, 722 "reloading EEPROM timeout!\n"); 723 } else { 724 if (bootverbose) 725 device_printf(sc->alc_dev, "EEPROM not found!\n"); 726 } 727 if (eeprom != 0) { 728 switch (sc->alc_ident->deviceid) { 729 case DEVICEID_ATHEROS_AR8131: 730 case DEVICEID_ATHEROS_AR8132: 731 if ((opt & OPT_CFG_CLK_ENB) != 0) { 732 opt &= ~OPT_CFG_CLK_ENB; 733 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 734 CSR_READ_4(sc, ALC_OPT_CFG); 735 DELAY(1000); 736 } 737 break; 738 case DEVICEID_ATHEROS_AR8151: 739 case DEVICEID_ATHEROS_AR8151_V2: 740 case DEVICEID_ATHEROS_AR8152_B: 741 case DEVICEID_ATHEROS_AR8152_B2: 742 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 743 ALC_MII_DBG_ADDR, 0x00); 744 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 745 ALC_MII_DBG_DATA); 746 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 747 ALC_MII_DBG_DATA, val | 0x0080); 748 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 749 ALC_MII_DBG_ADDR, 0x3B); 750 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 751 ALC_MII_DBG_DATA); 752 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 753 ALC_MII_DBG_DATA, val & 0xFFF7); 754 DELAY(20); 755 break; 756 } 757 } 758 759 alc_get_macaddr_par(sc); 760 } 761 762 static void 763 alc_get_macaddr_816x(struct alc_softc *sc) 764 { 765 uint32_t reg; 766 int i, reloaded; 767 768 reloaded = 0; 769 /* Try to reload station address via TWSI. */ 770 for (i = 100; i > 0; i--) { 771 reg = CSR_READ_4(sc, ALC_SLD); 772 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 773 break; 774 DELAY(1000); 775 } 776 if (i != 0) { 777 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 778 for (i = 100; i > 0; i--) { 779 DELAY(1000); 780 reg = CSR_READ_4(sc, ALC_SLD); 781 if ((reg & SLD_START) == 0) 782 break; 783 } 784 if (i != 0) 785 reloaded++; 786 else if (bootverbose) 787 device_printf(sc->alc_dev, 788 "reloading station address via TWSI timed out!\n"); 789 } 790 791 /* Try to reload station address from EEPROM or FLASH. */ 792 if (reloaded == 0) { 793 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 794 if ((reg & (EEPROM_LD_EEPROM_EXIST | 795 EEPROM_LD_FLASH_EXIST)) != 0) { 796 for (i = 100; i > 0; i--) { 797 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 798 if ((reg & (EEPROM_LD_PROGRESS | 799 EEPROM_LD_START)) == 0) 800 break; 801 DELAY(1000); 802 } 803 if (i != 0) { 804 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 805 EEPROM_LD_START); 806 for (i = 100; i > 0; i--) { 807 DELAY(1000); 808 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 809 if ((reg & EEPROM_LD_START) == 0) 810 break; 811 } 812 } else if (bootverbose) 813 device_printf(sc->alc_dev, 814 "reloading EEPROM/FLASH timed out!\n"); 815 } 816 } 817 818 alc_get_macaddr_par(sc); 819 } 820 821 static void 822 alc_get_macaddr_par(struct alc_softc *sc) 823 { 824 uint32_t ea[2]; 825 826 ea[0] = CSR_READ_4(sc, ALC_PAR0); 827 ea[1] = CSR_READ_4(sc, ALC_PAR1); 828 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 829 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 830 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 831 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 832 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 833 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 834 } 835 836 static void 837 alc_disable_l0s_l1(struct alc_softc *sc) 838 { 839 uint32_t pmcfg; 840 841 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 842 /* Another magic from vendor. */ 843 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 844 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 845 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 846 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 847 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 848 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 849 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 850 } 851 } 852 853 static void 854 alc_phy_reset(struct alc_softc *sc) 855 { 856 857 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 858 alc_phy_reset_816x(sc); 859 else 860 alc_phy_reset_813x(sc); 861 } 862 863 static void 864 alc_phy_reset_813x(struct alc_softc *sc) 865 { 866 uint16_t data; 867 868 /* Reset magic from Linux. */ 869 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 870 CSR_READ_2(sc, ALC_GPHY_CFG); 871 DELAY(10 * 1000); 872 873 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 874 GPHY_CFG_SEL_ANA_RESET); 875 CSR_READ_2(sc, ALC_GPHY_CFG); 876 DELAY(10 * 1000); 877 878 /* DSP fixup, Vendor magic. */ 879 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 880 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 881 ALC_MII_DBG_ADDR, 0x000A); 882 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 883 ALC_MII_DBG_DATA); 884 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 885 ALC_MII_DBG_DATA, data & 0xDFFF); 886 } 887 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 888 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 889 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 890 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 891 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 892 ALC_MII_DBG_ADDR, 0x003B); 893 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 894 ALC_MII_DBG_DATA); 895 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 896 ALC_MII_DBG_DATA, data & 0xFFF7); 897 DELAY(20 * 1000); 898 } 899 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 900 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 901 ALC_MII_DBG_ADDR, 0x0029); 902 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 903 ALC_MII_DBG_DATA, 0x929D); 904 } 905 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 906 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 907 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 908 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 909 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 910 ALC_MII_DBG_ADDR, 0x0029); 911 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 912 ALC_MII_DBG_DATA, 0xB6DD); 913 } 914 915 /* Load DSP codes, vendor magic. */ 916 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 917 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 918 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 919 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 920 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 921 ALC_MII_DBG_DATA, data); 922 923 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 924 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 925 ANA_SERDES_EN_LCKDT; 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_DATA, data); 930 931 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 932 ANA_LONG_CABLE_TH_100_MASK) | 933 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 934 ANA_SHORT_CABLE_TH_100_SHIFT) | 935 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 936 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 937 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 938 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 939 ALC_MII_DBG_DATA, data); 940 941 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 942 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 943 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 944 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 945 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 946 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 947 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 948 ALC_MII_DBG_DATA, data); 949 950 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 951 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 952 ANA_OEN_125M; 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_DATA, data); 957 DELAY(1000); 958 959 /* Disable hibernation. */ 960 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 961 0x0029); 962 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 963 ALC_MII_DBG_DATA); 964 data &= ~0x8000; 965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 966 data); 967 968 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 969 0x000B); 970 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 971 ALC_MII_DBG_DATA); 972 data &= ~0x8000; 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 974 data); 975 } 976 977 static void 978 alc_phy_reset_816x(struct alc_softc *sc) 979 { 980 uint32_t val; 981 982 val = CSR_READ_4(sc, ALC_GPHY_CFG); 983 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 984 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 985 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 986 val |= GPHY_CFG_SEL_ANA_RESET; 987 #ifdef notyet 988 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 989 #else 990 /* Disable PHY hibernation. */ 991 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 992 #endif 993 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 994 DELAY(10); 995 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 996 DELAY(800); 997 998 /* Vendor PHY magic. */ 999 #ifdef notyet 1000 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1001 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1002 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1003 EXT_VDRVBIAS_DEFAULT); 1004 #else 1005 /* Disable PHY hibernation. */ 1006 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1007 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1008 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1009 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1010 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1011 #endif 1012 1013 /* XXX Disable EEE. */ 1014 val = CSR_READ_4(sc, ALC_LPI_CTL); 1015 val &= ~LPI_CTL_ENB; 1016 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1017 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1018 1019 /* PHY power saving. */ 1020 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1021 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1022 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1023 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1024 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1025 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1026 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1027 1028 /* RTL8139C, 120m issue. */ 1029 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1030 ANEG_NLP78_120M_DEFAULT); 1031 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1032 ANEG_S3DIG10_DEFAULT); 1033 1034 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1035 /* Turn off half amplitude. */ 1036 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1037 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1038 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1039 /* Turn off Green feature. */ 1040 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1041 val |= DBG_GREENCFG2_BP_GREEN; 1042 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1043 /* Turn off half bias. */ 1044 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1045 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1046 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1047 } 1048 } 1049 1050 static void 1051 alc_phy_down(struct alc_softc *sc) 1052 { 1053 uint32_t gphy; 1054 1055 switch (sc->alc_ident->deviceid) { 1056 case DEVICEID_ATHEROS_AR8161: 1057 case DEVICEID_ATHEROS_E2200: 1058 case DEVICEID_ATHEROS_AR8162: 1059 case DEVICEID_ATHEROS_AR8171: 1060 case DEVICEID_ATHEROS_AR8172: 1061 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1062 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1063 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1064 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1065 GPHY_CFG_SEL_ANA_RESET; 1066 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1067 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1068 break; 1069 case DEVICEID_ATHEROS_AR8151: 1070 case DEVICEID_ATHEROS_AR8151_V2: 1071 case DEVICEID_ATHEROS_AR8152_B: 1072 case DEVICEID_ATHEROS_AR8152_B2: 1073 /* 1074 * GPHY power down caused more problems on AR8151 v2.0. 1075 * When driver is reloaded after GPHY power down, 1076 * accesses to PHY/MAC registers hung the system. Only 1077 * cold boot recovered from it. I'm not sure whether 1078 * AR8151 v1.0 also requires this one though. I don't 1079 * have AR8151 v1.0 controller in hand. 1080 * The only option left is to isolate the PHY and 1081 * initiates power down the PHY which in turn saves 1082 * more power when driver is unloaded. 1083 */ 1084 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1085 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1086 break; 1087 default: 1088 /* Force PHY down. */ 1089 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1090 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1091 GPHY_CFG_PWDOWN_HW); 1092 DELAY(1000); 1093 break; 1094 } 1095 } 1096 1097 static void 1098 alc_aspm(struct alc_softc *sc, int init, int media) 1099 { 1100 1101 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1102 alc_aspm_816x(sc, init); 1103 else 1104 alc_aspm_813x(sc, media); 1105 } 1106 1107 static void 1108 alc_aspm_813x(struct alc_softc *sc, int media) 1109 { 1110 uint32_t pmcfg; 1111 uint16_t linkcfg; 1112 1113 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1114 return; 1115 1116 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1117 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1118 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1119 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1120 PCIR_EXPRESS_LINK_CTL); 1121 else 1122 linkcfg = 0; 1123 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1124 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1125 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1126 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1127 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1128 1129 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1130 /* Disable extended sync except AR8152 B v1.0 */ 1131 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1132 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1133 sc->alc_rev == ATHEROS_AR8152_B_V10) 1134 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1135 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1136 linkcfg); 1137 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1138 PM_CFG_HOTRST); 1139 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1140 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1141 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1142 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1143 PM_CFG_PM_REQ_TIMER_SHIFT); 1144 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1145 } 1146 1147 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1148 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1149 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1150 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1151 pmcfg |= PM_CFG_ASPM_L1_ENB; 1152 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1153 if (sc->alc_ident->deviceid == 1154 DEVICEID_ATHEROS_AR8152_B) 1155 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1156 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1157 PM_CFG_SERDES_PLL_L1_ENB | 1158 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1159 pmcfg |= PM_CFG_CLK_SWH_L1; 1160 if (media == IFM_100_TX || media == IFM_1000_T) { 1161 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1162 switch (sc->alc_ident->deviceid) { 1163 case DEVICEID_ATHEROS_AR8152_B: 1164 pmcfg |= (7 << 1165 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1166 break; 1167 case DEVICEID_ATHEROS_AR8152_B2: 1168 case DEVICEID_ATHEROS_AR8151_V2: 1169 pmcfg |= (4 << 1170 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1171 break; 1172 default: 1173 pmcfg |= (15 << 1174 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1175 break; 1176 } 1177 } 1178 } else { 1179 pmcfg |= PM_CFG_SERDES_L1_ENB | 1180 PM_CFG_SERDES_PLL_L1_ENB | 1181 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1182 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1183 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1184 } 1185 } else { 1186 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1187 PM_CFG_SERDES_PLL_L1_ENB); 1188 pmcfg |= PM_CFG_CLK_SWH_L1; 1189 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1190 pmcfg |= PM_CFG_ASPM_L1_ENB; 1191 } 1192 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1193 } 1194 1195 static void 1196 alc_aspm_816x(struct alc_softc *sc, int init) 1197 { 1198 uint32_t pmcfg; 1199 1200 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1201 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1202 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1203 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1204 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1205 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1206 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1207 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1208 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1209 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1210 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1211 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1212 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1213 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1214 (sc->alc_rev & 0x01) != 0) 1215 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1216 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1217 /* Link up, enable both L0s, L1s. */ 1218 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1219 PM_CFG_MAC_ASPM_CHK; 1220 } else { 1221 if (init != 0) 1222 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1223 PM_CFG_MAC_ASPM_CHK; 1224 else if ((sc->alc_ifp->if_flags & IFF_RUNNING) != 0) 1225 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1226 } 1227 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1228 } 1229 1230 static void 1231 alc_init_pcie(struct alc_softc *sc) 1232 { 1233 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1234 uint32_t cap, ctl, val; 1235 int state; 1236 1237 /* Clear data link and flow-control protocol error. */ 1238 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1239 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1240 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1241 1242 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1243 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1244 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1245 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1246 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1247 PCIE_PHYMISC_FORCE_RCV_DET); 1248 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1249 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1250 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1251 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1252 PCIE_PHYMISC2_SERDES_TH_MASK); 1253 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1254 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1255 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1256 } 1257 /* Disable ASPM L0S and L1. */ 1258 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1259 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1260 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1261 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1262 sc->alc_rcb = DMA_CFG_RCB_128; 1263 if (bootverbose) 1264 device_printf(sc->alc_dev, "RCB %u bytes\n", 1265 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1266 state = ctl & PCIEM_LINK_CTL_ASPMC; 1267 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1268 sc->alc_flags |= ALC_FLAG_L0S; 1269 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1270 sc->alc_flags |= ALC_FLAG_L1S; 1271 if (bootverbose) 1272 device_printf(sc->alc_dev, "ASPM %s %s\n", 1273 aspm_state[state], 1274 state == 0 ? "disabled" : "enabled"); 1275 alc_disable_l0s_l1(sc); 1276 } else { 1277 if (bootverbose) 1278 device_printf(sc->alc_dev, 1279 "no ASPM support\n"); 1280 } 1281 } else { 1282 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1283 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1284 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1285 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1286 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1287 (sc->alc_rev & 0x01) != 0) { 1288 if ((val & MASTER_WAKEN_25M) == 0 || 1289 (val & MASTER_CLK_SEL_DIS) == 0) { 1290 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1291 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1292 } 1293 } else { 1294 if ((val & MASTER_WAKEN_25M) == 0 || 1295 (val & MASTER_CLK_SEL_DIS) != 0) { 1296 val |= MASTER_WAKEN_25M; 1297 val &= ~MASTER_CLK_SEL_DIS; 1298 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1299 } 1300 } 1301 } 1302 alc_aspm(sc, 1, IFM_UNKNOWN); 1303 } 1304 1305 static void 1306 alc_config_msi(struct alc_softc *sc) 1307 { 1308 uint32_t ctl, mod; 1309 1310 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1311 /* 1312 * It seems interrupt moderation is controlled by 1313 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1314 * Driver uses RX interrupt moderation parameter to 1315 * program ALC_MSI_RETRANS_TIMER register. 1316 */ 1317 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1318 ctl &= ~MSI_RETRANS_TIMER_MASK; 1319 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1320 mod = ALC_USECS(sc->alc_int_rx_mod); 1321 if (mod == 0) 1322 mod = 1; 1323 ctl |= mod; 1324 if (sc->alc_irq_type == PCI_INTR_TYPE_MSI) 1325 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1326 MSI_RETRANS_MASK_SEL_LINE); 1327 else 1328 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1329 } 1330 } 1331 1332 static int 1333 alc_attach(device_t dev) 1334 { 1335 struct alc_softc *sc; 1336 struct ifnet *ifp; 1337 uint16_t burst; 1338 int base, error; 1339 u_int intr_flags; 1340 1341 error = 0; 1342 sc = device_get_softc(dev); 1343 sc->alc_dev = dev; 1344 sc->alc_rev = pci_get_revid(dev); 1345 1346 callout_init_mp(&sc->alc_tick_ch); 1347 sc->alc_ident = alc_find_ident(dev); 1348 1349 /* Enable bus mastering */ 1350 pci_enable_busmaster(dev); 1351 1352 /* Map the device. */ 1353 sc->alc_res_rid = PCIR_BAR(0); 1354 sc->alc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1355 &sc->alc_res_rid, RF_ACTIVE); 1356 if (error != 0) { 1357 device_printf(dev, "cannot allocate memory resources.\n"); 1358 goto fail; 1359 } 1360 sc->alc_res_btag = rman_get_bustag(sc->alc_res); 1361 sc->alc_res_bhand = rman_get_bushandle(sc->alc_res); 1362 1363 /* Set PHY address. */ 1364 sc->alc_phyaddr = ALC_PHY_ADDR; 1365 1366 /* 1367 * One odd thing is AR8132 uses the same PHY hardware(F1 1368 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1369 * the PHY supports 1000Mbps but that's not true. The PHY 1370 * used in AR8132 can't establish gigabit link even if it 1371 * shows the same PHY model/revision number of AR8131. 1372 */ 1373 switch (sc->alc_ident->deviceid) { 1374 case DEVICEID_ATHEROS_AR8161: 1375 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1376 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1377 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1378 /* FALLTHROUGH */ 1379 case DEVICEID_ATHEROS_E2200: 1380 case DEVICEID_ATHEROS_AR8171: 1381 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1382 break; 1383 case DEVICEID_ATHEROS_AR8162: 1384 case DEVICEID_ATHEROS_AR8172: 1385 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1386 break; 1387 case DEVICEID_ATHEROS_AR8152_B: 1388 case DEVICEID_ATHEROS_AR8152_B2: 1389 sc->alc_flags |= ALC_FLAG_APS; 1390 /* FALLTHROUGH */ 1391 case DEVICEID_ATHEROS_AR8132: 1392 sc->alc_flags |= ALC_FLAG_FASTETHER; 1393 break; 1394 case DEVICEID_ATHEROS_AR8151: 1395 case DEVICEID_ATHEROS_AR8151_V2: 1396 sc->alc_flags |= ALC_FLAG_APS; 1397 /* FALLTHROUGH */ 1398 default: 1399 break; 1400 } 1401 sc->alc_flags |= ALC_FLAG_JUMBO; 1402 1403 /* 1404 * It seems that AR813x/AR815x has silicon bug for SMB. In 1405 * addition, Atheros said that enabling SMB wouldn't improve 1406 * performance. However I think it's bad to access lots of 1407 * registers to extract MAC statistics. 1408 */ 1409 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1410 1411 /* 1412 * Don't use Tx CMB. It is known to have silicon bug. 1413 */ 1414 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1415 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1416 MASTER_CHIP_REV_SHIFT; 1417 if (bootverbose) { 1418 device_printf(dev, "PCI device revision : 0x%04x\n", 1419 sc->alc_rev); 1420 device_printf(dev, "Chip id/revision : 0x%04x\n", 1421 sc->alc_chip_rev); 1422 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1423 device_printf(dev, "AR816x revision : 0x%x\n", 1424 AR816X_REV(sc->alc_rev)); 1425 } 1426 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1427 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1428 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1429 1430 /* Initialize DMA parameters. */ 1431 sc->alc_dma_rd_burst = 0; 1432 sc->alc_dma_wr_burst = 0; 1433 sc->alc_rcb = DMA_CFG_RCB_64; 1434 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 1435 sc->alc_flags |= ALC_FLAG_PCIE; 1436 sc->alc_expcap = base; 1437 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1438 sc->alc_dma_rd_burst = 1439 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1440 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1441 if (bootverbose) { 1442 device_printf(dev, "Read request size : %u bytes.\n", 1443 alc_dma_burst[sc->alc_dma_rd_burst]); 1444 device_printf(dev, "TLP payload size : %u bytes.\n", 1445 alc_dma_burst[sc->alc_dma_wr_burst]); 1446 } 1447 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1448 sc->alc_dma_rd_burst = 3; 1449 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1450 sc->alc_dma_wr_burst = 3; 1451 alc_init_pcie(sc); 1452 } 1453 1454 /* Reset PHY. */ 1455 alc_phy_reset(sc); 1456 1457 /* Reset the ethernet controller. */ 1458 alc_stop_mac(sc); 1459 alc_reset(sc); 1460 1461 sc->alc_irq_type = pci_alloc_1intr(dev, alc_msi_enable, 1462 &sc->alc_irq_rid, &intr_flags); 1463 1464 /* Allocate IRQ resources. */ 1465 sc->alc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1466 &sc->alc_irq_rid, intr_flags); 1467 if (error != 0) { 1468 device_printf(dev, "cannot allocate IRQ resources.\n"); 1469 goto fail; 1470 } 1471 1472 /* Create device sysctl node. */ 1473 alc_sysctl_node(sc); 1474 1475 if ((error = alc_dma_alloc(sc) != 0)) 1476 goto fail; 1477 1478 /* Load station address. */ 1479 alc_get_macaddr(sc); 1480 1481 ifp = sc->alc_ifp = &sc->arpcom.ac_if; 1482 ifp->if_softc = sc; 1483 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1484 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1485 ifp->if_ioctl = alc_ioctl; 1486 ifp->if_start = alc_start; 1487 ifp->if_init = alc_init; 1488 ifq_set_maxlen(&ifp->if_snd, ALC_TX_RING_CNT - 1); 1489 ifq_set_ready(&ifp->if_snd); 1490 ifp->if_capabilities = IFCAP_TXCSUM; 1491 ifp->if_hwassist = ALC_CSUM_FEATURES; 1492 #if 0 1493 /* XXX: WOL */ 1494 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 1495 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1496 sc->alc_flags |= ALC_FLAG_PM; 1497 sc->alc_pmcap = base; 1498 } 1499 #endif 1500 ifp->if_capenable = ifp->if_capabilities; 1501 1502 /* VLAN capability setup. */ 1503 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1504 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1505 ifp->if_capenable = ifp->if_capabilities; 1506 1507 /* 1508 * XXX 1509 * It seems enabling Tx checksum offloading makes more trouble. 1510 * Sometimes the controller does not receive any frames when 1511 * Tx checksum offloading is enabled. I'm not sure whether this 1512 * is a bug in Tx checksum offloading logic or I got broken 1513 * sample boards. To safety, don't enable Tx checksum offloading 1514 * by default but give chance to users to toggle it if they know 1515 * their controllers work without problems. 1516 * Fortunately, Tx checksum offloading for AR816x family 1517 * seems to work. 1518 */ 1519 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1520 ifp->if_capenable &= ~IFCAP_TXCSUM; 1521 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1522 } 1523 1524 /* Set up MII bus. */ 1525 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 1526 alc_mediastatus)) != 0) { 1527 device_printf(dev, "no PHY found!\n"); 1528 goto fail; 1529 } 1530 1531 ether_ifattach(ifp, sc->alc_eaddr, NULL); 1532 1533 /* Tell the upper layer(s) we support long frames. */ 1534 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1535 1536 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->alc_irq)); 1537 #if 0 1538 /* Create local taskq. */ 1539 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1540 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK, 1541 taskqueue_thread_enqueue, &sc->alc_tq); 1542 if (sc->alc_tq == NULL) { 1543 device_printf(dev, "could not create taskqueue.\n"); 1544 ether_ifdetach(ifp); 1545 error = ENXIO; 1546 goto fail; 1547 } 1548 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 1549 device_get_nameunit(sc->alc_dev)); 1550 1551 alc_config_msi(sc); 1552 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1553 msic = ALC_MSIX_MESSAGES; 1554 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1555 msic = ALC_MSI_MESSAGES; 1556 else 1557 msic = 1; 1558 for (i = 0; i < msic; i++) { 1559 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE, 1560 alc_intr, sc, 1561 &sc->alc_intrhand[i], NULL); 1562 if (error != 0) 1563 break; 1564 } 1565 if (error != 0) { 1566 device_printf(dev, "could not set up interrupt handler.\n"); 1567 taskqueue_free(sc->alc_tq); 1568 sc->alc_tq = NULL; 1569 ether_ifdetach(ifp); 1570 goto fail; 1571 } 1572 #else 1573 alc_config_msi(sc); 1574 error = bus_setup_intr(dev, sc->alc_irq, INTR_MPSAFE, alc_intr, sc, 1575 &sc->alc_intrhand, ifp->if_serializer); 1576 if (error) { 1577 device_printf(dev, "could not set up interrupt handler.\n"); 1578 ether_ifdetach(ifp); 1579 goto fail; 1580 } 1581 #endif 1582 1583 fail: 1584 if (error != 0) 1585 alc_detach(dev); 1586 1587 return (error); 1588 } 1589 1590 static int 1591 alc_detach(device_t dev) 1592 { 1593 struct alc_softc *sc = device_get_softc(dev); 1594 1595 if (device_is_attached(dev)) { 1596 struct ifnet *ifp = sc->alc_ifp; 1597 1598 lwkt_serialize_enter(ifp->if_serializer); 1599 alc_stop(sc); 1600 bus_teardown_intr(dev, sc->alc_irq, sc->alc_intrhand); 1601 lwkt_serialize_exit(ifp->if_serializer); 1602 1603 ether_ifdetach(ifp); 1604 } 1605 1606 if (sc->alc_miibus != NULL) 1607 device_delete_child(dev, sc->alc_miibus); 1608 bus_generic_detach(dev); 1609 1610 if (sc->alc_res != NULL) 1611 alc_phy_down(sc); 1612 1613 if (sc->alc_irq != NULL) { 1614 bus_release_resource(dev, SYS_RES_IRQ, sc->alc_irq_rid, 1615 sc->alc_irq); 1616 } 1617 if (sc->alc_irq_type == PCI_INTR_TYPE_MSI) 1618 pci_release_msi(dev); 1619 1620 if (sc->alc_res != NULL) { 1621 bus_release_resource(dev, SYS_RES_MEMORY, sc->alc_res_rid, 1622 sc->alc_res); 1623 } 1624 1625 alc_dma_free(sc); 1626 1627 return (0); 1628 } 1629 1630 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1631 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1632 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1633 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1634 1635 static void 1636 alc_sysctl_node(struct alc_softc *sc) 1637 { 1638 struct sysctl_ctx_list *ctx; 1639 struct sysctl_oid *tree; 1640 struct sysctl_oid_list *child, *parent; 1641 struct alc_hw_stats *stats; 1642 int error; 1643 1644 stats = &sc->alc_stats; 1645 ctx = device_get_sysctl_ctx(sc->alc_dev); 1646 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1647 1648 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1649 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1650 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1651 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1652 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1653 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1654 /* Pull in device tunables. */ 1655 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1656 error = resource_int_value(device_get_name(sc->alc_dev), 1657 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1658 if (error == 0) { 1659 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1660 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1661 device_printf(sc->alc_dev, "int_rx_mod value out of " 1662 "range; using default: %d\n", 1663 ALC_IM_RX_TIMER_DEFAULT); 1664 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1665 } 1666 } 1667 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1668 error = resource_int_value(device_get_name(sc->alc_dev), 1669 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1670 if (error == 0) { 1671 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1672 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1673 device_printf(sc->alc_dev, "int_tx_mod value out of " 1674 "range; using default: %d\n", 1675 ALC_IM_TX_TIMER_DEFAULT); 1676 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1677 } 1678 } 1679 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1680 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1681 sysctl_hw_alc_proc_limit, "I", 1682 "max number of Rx events to process"); 1683 /* Pull in device tunables. */ 1684 sc->alc_process_limit = ALC_PROC_DEFAULT; 1685 error = resource_int_value(device_get_name(sc->alc_dev), 1686 device_get_unit(sc->alc_dev), "process_limit", 1687 &sc->alc_process_limit); 1688 if (error == 0) { 1689 if (sc->alc_process_limit < ALC_PROC_MIN || 1690 sc->alc_process_limit > ALC_PROC_MAX) { 1691 device_printf(sc->alc_dev, 1692 "process_limit value out of range; " 1693 "using default: %d\n", ALC_PROC_DEFAULT); 1694 sc->alc_process_limit = ALC_PROC_DEFAULT; 1695 } 1696 } 1697 1698 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1699 NULL, "ALC statistics"); 1700 parent = SYSCTL_CHILDREN(tree); 1701 1702 /* Rx statistics. */ 1703 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1704 NULL, "Rx MAC statistics"); 1705 child = SYSCTL_CHILDREN(tree); 1706 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1707 &stats->rx_frames, "Good frames"); 1708 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1709 &stats->rx_bcast_frames, "Good broadcast frames"); 1710 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1711 &stats->rx_mcast_frames, "Good multicast frames"); 1712 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1713 &stats->rx_pause_frames, "Pause control frames"); 1714 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1715 &stats->rx_control_frames, "Control frames"); 1716 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1717 &stats->rx_crcerrs, "CRC errors"); 1718 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1719 &stats->rx_lenerrs, "Frames with length mismatched"); 1720 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1721 &stats->rx_bytes, "Good octets"); 1722 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1723 &stats->rx_bcast_bytes, "Good broadcast octets"); 1724 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1725 &stats->rx_mcast_bytes, "Good multicast octets"); 1726 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1727 &stats->rx_runts, "Too short frames"); 1728 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1729 &stats->rx_fragments, "Fragmented frames"); 1730 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1731 &stats->rx_pkts_64, "64 bytes frames"); 1732 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1733 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1734 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1735 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1736 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1737 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1738 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1739 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1740 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1741 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1742 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1743 &stats->rx_pkts_1519_max, "1519 to max frames"); 1744 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1745 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1746 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1747 &stats->rx_fifo_oflows, "FIFO overflows"); 1748 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1749 &stats->rx_rrs_errs, "Return status write-back errors"); 1750 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1751 &stats->rx_alignerrs, "Alignment errors"); 1752 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1753 &stats->rx_pkts_filtered, 1754 "Frames dropped due to address filtering"); 1755 1756 /* Tx statistics. */ 1757 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1758 NULL, "Tx MAC statistics"); 1759 child = SYSCTL_CHILDREN(tree); 1760 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1761 &stats->tx_frames, "Good frames"); 1762 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1763 &stats->tx_bcast_frames, "Good broadcast frames"); 1764 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1765 &stats->tx_mcast_frames, "Good multicast frames"); 1766 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1767 &stats->tx_pause_frames, "Pause control frames"); 1768 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1769 &stats->tx_control_frames, "Control frames"); 1770 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1771 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1772 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1773 &stats->tx_excess_defer, "Frames with derferrals"); 1774 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1775 &stats->tx_bytes, "Good octets"); 1776 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1777 &stats->tx_bcast_bytes, "Good broadcast octets"); 1778 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1779 &stats->tx_mcast_bytes, "Good multicast octets"); 1780 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1781 &stats->tx_pkts_64, "64 bytes frames"); 1782 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1783 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1784 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1785 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1786 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1787 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1788 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1789 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1790 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1791 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1792 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1793 &stats->tx_pkts_1519_max, "1519 to max frames"); 1794 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1795 &stats->tx_single_colls, "Single collisions"); 1796 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1797 &stats->tx_multi_colls, "Multiple collisions"); 1798 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1799 &stats->tx_late_colls, "Late collisions"); 1800 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1801 &stats->tx_excess_colls, "Excessive collisions"); 1802 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1803 &stats->tx_underrun, "FIFO underruns"); 1804 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1805 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1806 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1807 &stats->tx_lenerrs, "Frames with length mismatched"); 1808 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1809 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1810 } 1811 1812 #undef ALC_SYSCTL_STAT_ADD32 1813 #undef ALC_SYSCTL_STAT_ADD64 1814 1815 struct alc_dmamap_arg { 1816 bus_addr_t alc_busaddr; 1817 }; 1818 1819 static void 1820 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1821 { 1822 struct alc_dmamap_arg *ctx; 1823 1824 if (error != 0) 1825 return; 1826 1827 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1828 1829 ctx = (struct alc_dmamap_arg *)arg; 1830 ctx->alc_busaddr = segs[0].ds_addr; 1831 } 1832 1833 #ifdef foo 1834 /* 1835 * Normal and high Tx descriptors shares single Tx high address. 1836 * Four Rx descriptor/return rings and CMB shares the same Rx 1837 * high address. 1838 */ 1839 static int 1840 alc_check_boundary(struct alc_softc *sc) 1841 { 1842 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1843 1844 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1845 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1846 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1847 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1848 1849 /* 4GB boundary crossing is not allowed. */ 1850 if ((ALC_ADDR_HI(rx_ring_end) != 1851 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1852 (ALC_ADDR_HI(rr_ring_end) != 1853 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1854 (ALC_ADDR_HI(cmb_end) != 1855 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1856 (ALC_ADDR_HI(tx_ring_end) != 1857 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1858 return (EFBIG); 1859 /* 1860 * Make sure Rx return descriptor/Rx descriptor/CMB use 1861 * the same high address. 1862 */ 1863 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1864 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1865 return (EFBIG); 1866 1867 return (0); 1868 } 1869 #endif 1870 1871 static int 1872 alc_dma_alloc(struct alc_softc *sc) 1873 { 1874 struct alc_txdesc *txd; 1875 struct alc_rxdesc *rxd; 1876 struct alc_dmamap_arg ctx; 1877 int error, i; 1878 1879 /* Create parent DMA tag. */ 1880 error = bus_dma_tag_create( 1881 sc->alc_cdata.alc_parent_tag, /* parent */ 1882 1, 0, /* alignment, boundary */ 1883 BUS_SPACE_MAXADDR, /* lowaddr */ 1884 BUS_SPACE_MAXADDR, /* highaddr */ 1885 NULL, NULL, /* filter, filterarg */ 1886 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1887 0, /* nsegments */ 1888 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1889 0, /* flags */ 1890 &sc->alc_cdata.alc_parent_tag); 1891 if (error != 0) { 1892 device_printf(sc->alc_dev, 1893 "could not create parent DMA tag.\n"); 1894 goto fail; 1895 } 1896 1897 /* Create DMA tag for Tx descriptor ring. */ 1898 error = bus_dma_tag_create( 1899 sc->alc_cdata.alc_parent_tag, /* parent */ 1900 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1901 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1902 BUS_SPACE_MAXADDR, /* highaddr */ 1903 NULL, NULL, /* filter, filterarg */ 1904 ALC_TX_RING_SZ, /* maxsize */ 1905 1, /* nsegments */ 1906 ALC_TX_RING_SZ, /* maxsegsize */ 1907 0, /* flags */ 1908 &sc->alc_cdata.alc_tx_ring_tag); 1909 if (error != 0) { 1910 device_printf(sc->alc_dev, 1911 "could not create Tx ring DMA tag.\n"); 1912 goto fail; 1913 } 1914 1915 /* Create DMA tag for Rx free descriptor ring. */ 1916 error = bus_dma_tag_create( 1917 sc->alc_cdata.alc_parent_tag, /* parent */ 1918 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1919 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1920 BUS_SPACE_MAXADDR, /* highaddr */ 1921 NULL, NULL, /* filter, filterarg */ 1922 ALC_RX_RING_SZ, /* maxsize */ 1923 1, /* nsegments */ 1924 ALC_RX_RING_SZ, /* maxsegsize */ 1925 0, /* flags */ 1926 &sc->alc_cdata.alc_rx_ring_tag); 1927 if (error != 0) { 1928 device_printf(sc->alc_dev, 1929 "could not create Rx ring DMA tag.\n"); 1930 goto fail; 1931 } 1932 /* Create DMA tag for Rx return descriptor ring. */ 1933 error = bus_dma_tag_create( 1934 sc->alc_cdata.alc_parent_tag, /* parent */ 1935 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1936 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1937 BUS_SPACE_MAXADDR, /* highaddr */ 1938 NULL, NULL, /* filter, filterarg */ 1939 ALC_RR_RING_SZ, /* maxsize */ 1940 1, /* nsegments */ 1941 ALC_RR_RING_SZ, /* maxsegsize */ 1942 0, /* flags */ 1943 &sc->alc_cdata.alc_rr_ring_tag); 1944 if (error != 0) { 1945 device_printf(sc->alc_dev, 1946 "could not create Rx return ring DMA tag.\n"); 1947 goto fail; 1948 } 1949 1950 /* Create DMA tag for coalescing message block. */ 1951 error = bus_dma_tag_create( 1952 sc->alc_cdata.alc_parent_tag, /* parent */ 1953 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1954 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1955 BUS_SPACE_MAXADDR, /* highaddr */ 1956 NULL, NULL, /* filter, filterarg */ 1957 ALC_CMB_SZ, /* maxsize */ 1958 1, /* nsegments */ 1959 ALC_CMB_SZ, /* maxsegsize */ 1960 0, /* flags */ 1961 &sc->alc_cdata.alc_cmb_tag); 1962 if (error != 0) { 1963 device_printf(sc->alc_dev, 1964 "could not create CMB DMA tag.\n"); 1965 goto fail; 1966 } 1967 /* Create DMA tag for status message block. */ 1968 error = bus_dma_tag_create( 1969 sc->alc_cdata.alc_parent_tag, /* parent */ 1970 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1971 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1972 BUS_SPACE_MAXADDR, /* highaddr */ 1973 NULL, NULL, /* filter, filterarg */ 1974 ALC_SMB_SZ, /* maxsize */ 1975 1, /* nsegments */ 1976 ALC_SMB_SZ, /* maxsegsize */ 1977 0, /* flags */ 1978 &sc->alc_cdata.alc_smb_tag); 1979 if (error != 0) { 1980 device_printf(sc->alc_dev, 1981 "could not create SMB DMA tag.\n"); 1982 goto fail; 1983 } 1984 1985 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1986 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1987 (void **)&sc->alc_rdata.alc_tx_ring, 1988 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1989 &sc->alc_cdata.alc_tx_ring_map); 1990 if (error != 0) { 1991 device_printf(sc->alc_dev, 1992 "could not allocate DMA'able memory for Tx ring.\n"); 1993 goto fail; 1994 } 1995 ctx.alc_busaddr = 0; 1996 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1997 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1998 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1999 if (error != 0 || ctx.alc_busaddr == 0) { 2000 device_printf(sc->alc_dev, 2001 "could not load DMA'able memory for Tx ring.\n"); 2002 goto fail; 2003 } 2004 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2005 2006 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2007 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2008 (void **)&sc->alc_rdata.alc_rx_ring, 2009 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2010 &sc->alc_cdata.alc_rx_ring_map); 2011 if (error != 0) { 2012 device_printf(sc->alc_dev, 2013 "could not allocate DMA'able memory for Rx ring.\n"); 2014 goto fail; 2015 } 2016 ctx.alc_busaddr = 0; 2017 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2018 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2019 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2020 if (error != 0 || ctx.alc_busaddr == 0) { 2021 device_printf(sc->alc_dev, 2022 "could not load DMA'able memory for Rx ring.\n"); 2023 goto fail; 2024 } 2025 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2026 2027 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2028 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2029 (void **)&sc->alc_rdata.alc_rr_ring, 2030 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2031 &sc->alc_cdata.alc_rr_ring_map); 2032 if (error != 0) { 2033 device_printf(sc->alc_dev, 2034 "could not allocate DMA'able memory for Rx return ring.\n"); 2035 goto fail; 2036 } 2037 ctx.alc_busaddr = 0; 2038 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2039 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2040 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2041 if (error != 0 || ctx.alc_busaddr == 0) { 2042 device_printf(sc->alc_dev, 2043 "could not load DMA'able memory for Tx ring.\n"); 2044 goto fail; 2045 } 2046 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2047 2048 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2049 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2050 (void **)&sc->alc_rdata.alc_cmb, 2051 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2052 &sc->alc_cdata.alc_cmb_map); 2053 if (error != 0) { 2054 device_printf(sc->alc_dev, 2055 "could not allocate DMA'able memory for CMB.\n"); 2056 goto fail; 2057 } 2058 ctx.alc_busaddr = 0; 2059 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2060 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2061 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2062 if (error != 0 || ctx.alc_busaddr == 0) { 2063 device_printf(sc->alc_dev, 2064 "could not load DMA'able memory for CMB.\n"); 2065 goto fail; 2066 } 2067 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2068 2069 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2070 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2071 (void **)&sc->alc_rdata.alc_smb, 2072 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2073 &sc->alc_cdata.alc_smb_map); 2074 if (error != 0) { 2075 device_printf(sc->alc_dev, 2076 "could not allocate DMA'able memory for SMB.\n"); 2077 goto fail; 2078 } 2079 ctx.alc_busaddr = 0; 2080 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2081 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2082 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2083 if (error != 0 || ctx.alc_busaddr == 0) { 2084 device_printf(sc->alc_dev, 2085 "could not load DMA'able memory for CMB.\n"); 2086 goto fail; 2087 } 2088 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2089 2090 #ifdef foo 2091 /* 2092 * All of the status blocks and descriptor rings are 2093 * allocated at lower 4GB, their addresses high 32bits 2094 * part are same (all 0). 2095 */ 2096 2097 /* Make sure we've not crossed 4GB boundary. */ 2098 if ((error = alc_check_boundary(sc)) != 0) { 2099 device_printf(sc->alc_dev, "4GB boundary crossed, " 2100 "switching to 32bit DMA addressing mode.\n"); 2101 alc_dma_free(sc); 2102 /* 2103 * Limit max allowable DMA address space to 32bit 2104 * and try again. 2105 */ 2106 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2107 goto again; 2108 } 2109 #endif 2110 2111 /* 2112 * Create Tx buffer parent tag. 2113 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2114 * so it needs separate parent DMA tag as parent DMA address 2115 * space could be restricted to be within 32bit address space 2116 * by 4GB boundary crossing. 2117 */ 2118 error = bus_dma_tag_create( 2119 sc->alc_cdata.alc_parent_tag, /* parent */ 2120 1, 0, /* alignment, boundary */ 2121 BUS_SPACE_MAXADDR, /* lowaddr */ 2122 BUS_SPACE_MAXADDR, /* highaddr */ 2123 NULL, NULL, /* filter, filterarg */ 2124 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2125 0, /* nsegments */ 2126 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2127 0, /* flags */ 2128 &sc->alc_cdata.alc_buffer_tag); 2129 if (error != 0) { 2130 device_printf(sc->alc_dev, 2131 "could not create parent buffer DMA tag.\n"); 2132 goto fail; 2133 } 2134 2135 /* Create DMA tag for Tx buffers. */ 2136 error = bus_dma_tag_create( 2137 sc->alc_cdata.alc_buffer_tag, /* parent */ 2138 1, 0, /* alignment, boundary */ 2139 BUS_SPACE_MAXADDR, /* lowaddr */ 2140 BUS_SPACE_MAXADDR, /* highaddr */ 2141 NULL, NULL, /* filter, filterarg */ 2142 ALC_TSO_MAXSIZE, /* maxsize */ 2143 ALC_MAXTXSEGS, /* nsegments */ 2144 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2145 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, /* flags */ 2146 &sc->alc_cdata.alc_tx_tag); 2147 if (error != 0) { 2148 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2149 goto fail; 2150 } 2151 2152 /* Create DMA tag for Rx buffers. */ 2153 error = bus_dma_tag_create( 2154 sc->alc_cdata.alc_buffer_tag, /* parent */ 2155 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2156 BUS_SPACE_MAXADDR, /* lowaddr */ 2157 BUS_SPACE_MAXADDR, /* highaddr */ 2158 NULL, NULL, /* filter, filterarg */ 2159 MCLBYTES, /* maxsize */ 2160 1, /* nsegments */ 2161 MCLBYTES, /* maxsegsize */ 2162 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED, /* flags */ 2163 &sc->alc_cdata.alc_rx_tag); 2164 if (error != 0) { 2165 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2166 goto fail; 2167 } 2168 /* Create DMA maps for Tx buffers. */ 2169 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2170 txd = &sc->alc_cdata.alc_txdesc[i]; 2171 txd->tx_m = NULL; 2172 txd->tx_dmamap = NULL; 2173 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 2174 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 2175 &txd->tx_dmamap); 2176 if (error != 0) { 2177 device_printf(sc->alc_dev, 2178 "could not create Tx dmamap.\n"); 2179 goto fail; 2180 } 2181 } 2182 /* Create DMA maps for Rx buffers. */ 2183 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 2184 BUS_DMA_WAITOK, 2185 &sc->alc_cdata.alc_rx_sparemap); 2186 if (error) { 2187 device_printf(sc->alc_dev, 2188 "could not create spare Rx dmamap.\n"); 2189 goto fail; 2190 } 2191 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2192 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2193 rxd->rx_m = NULL; 2194 rxd->rx_dmamap = NULL; 2195 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 2196 BUS_DMA_WAITOK, 2197 &rxd->rx_dmamap); 2198 if (error != 0) { 2199 device_printf(sc->alc_dev, 2200 "could not create Rx dmamap.\n"); 2201 goto fail; 2202 } 2203 } 2204 2205 fail: 2206 return (error); 2207 } 2208 2209 static void 2210 alc_dma_free(struct alc_softc *sc) 2211 { 2212 struct alc_txdesc *txd; 2213 struct alc_rxdesc *rxd; 2214 int i; 2215 2216 /* Tx buffers. */ 2217 if (sc->alc_cdata.alc_tx_tag != NULL) { 2218 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2219 txd = &sc->alc_cdata.alc_txdesc[i]; 2220 if (txd->tx_dmamap != NULL) { 2221 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2222 txd->tx_dmamap); 2223 txd->tx_dmamap = NULL; 2224 } 2225 } 2226 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2227 sc->alc_cdata.alc_tx_tag = NULL; 2228 } 2229 /* Rx buffers */ 2230 if (sc->alc_cdata.alc_rx_tag != NULL) { 2231 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2232 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2233 if (rxd->rx_dmamap != NULL) { 2234 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2235 rxd->rx_dmamap); 2236 rxd->rx_dmamap = NULL; 2237 } 2238 } 2239 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2240 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2241 sc->alc_cdata.alc_rx_sparemap); 2242 sc->alc_cdata.alc_rx_sparemap = NULL; 2243 } 2244 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2245 sc->alc_cdata.alc_rx_tag = NULL; 2246 } 2247 /* Tx descriptor ring. */ 2248 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2249 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2250 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2251 sc->alc_cdata.alc_tx_ring_map); 2252 if (sc->alc_rdata.alc_tx_ring != NULL) 2253 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2254 sc->alc_rdata.alc_tx_ring, 2255 sc->alc_cdata.alc_tx_ring_map); 2256 sc->alc_rdata.alc_tx_ring_paddr = 0; 2257 sc->alc_rdata.alc_tx_ring = NULL; 2258 sc->alc_cdata.alc_tx_ring_map = NULL; 2259 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2260 sc->alc_cdata.alc_tx_ring_tag = NULL; 2261 } 2262 /* Rx ring. */ 2263 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2264 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2265 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2266 sc->alc_cdata.alc_rx_ring_map); 2267 if (sc->alc_rdata.alc_rx_ring != NULL) 2268 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2269 sc->alc_rdata.alc_rx_ring, 2270 sc->alc_cdata.alc_rx_ring_map); 2271 sc->alc_rdata.alc_rx_ring_paddr = 0; 2272 sc->alc_rdata.alc_rx_ring = NULL; 2273 sc->alc_cdata.alc_rx_ring_map = NULL; 2274 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2275 sc->alc_cdata.alc_rx_ring_tag = NULL; 2276 } 2277 /* Rx return ring. */ 2278 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2279 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2280 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2281 sc->alc_cdata.alc_rr_ring_map); 2282 if (sc->alc_rdata.alc_rr_ring != NULL) 2283 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2284 sc->alc_rdata.alc_rr_ring, 2285 sc->alc_cdata.alc_rr_ring_map); 2286 sc->alc_rdata.alc_rr_ring_paddr = 0; 2287 sc->alc_rdata.alc_rr_ring = NULL; 2288 sc->alc_cdata.alc_rr_ring_map = NULL; 2289 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2290 sc->alc_cdata.alc_rr_ring_tag = NULL; 2291 } 2292 /* CMB block */ 2293 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2294 if (sc->alc_rdata.alc_cmb_paddr != 0) 2295 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2296 sc->alc_cdata.alc_cmb_map); 2297 if (sc->alc_rdata.alc_cmb != NULL) 2298 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2299 sc->alc_rdata.alc_cmb, 2300 sc->alc_cdata.alc_cmb_map); 2301 sc->alc_rdata.alc_cmb_paddr = 0; 2302 sc->alc_rdata.alc_cmb = NULL; 2303 sc->alc_cdata.alc_cmb_map = NULL; 2304 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2305 sc->alc_cdata.alc_cmb_tag = NULL; 2306 } 2307 /* SMB block */ 2308 if (sc->alc_cdata.alc_smb_tag != NULL) { 2309 if (sc->alc_rdata.alc_smb_paddr != 0) 2310 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2311 sc->alc_cdata.alc_smb_map); 2312 if (sc->alc_rdata.alc_smb != NULL) 2313 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2314 sc->alc_rdata.alc_smb, 2315 sc->alc_cdata.alc_smb_map); 2316 sc->alc_rdata.alc_smb_paddr = 0; 2317 sc->alc_rdata.alc_smb = NULL; 2318 sc->alc_cdata.alc_smb_map = NULL; 2319 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2320 sc->alc_cdata.alc_smb_tag = NULL; 2321 } 2322 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2323 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2324 sc->alc_cdata.alc_buffer_tag = NULL; 2325 } 2326 if (sc->alc_cdata.alc_parent_tag != NULL) { 2327 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2328 sc->alc_cdata.alc_parent_tag = NULL; 2329 } 2330 } 2331 2332 static int 2333 alc_shutdown(device_t dev) 2334 { 2335 2336 return (alc_suspend(dev)); 2337 } 2338 2339 #if 0 2340 /* XXX: LINK SPEED */ 2341 /* 2342 * Note, this driver resets the link speed to 10/100Mbps by 2343 * restarting auto-negotiation in suspend/shutdown phase but we 2344 * don't know whether that auto-negotiation would succeed or not 2345 * as driver has no control after powering off/suspend operation. 2346 * If the renegotiation fail WOL may not work. Running at 1Gbps 2347 * will draw more power than 375mA at 3.3V which is specified in 2348 * PCI specification and that would result in complete 2349 * shutdowning power to ethernet controller. 2350 * 2351 * TODO 2352 * Save current negotiated media speed/duplex/flow-control to 2353 * softc and restore the same link again after resuming. PHY 2354 * handling such as power down/resetting to 100Mbps may be better 2355 * handled in suspend method in phy driver. 2356 */ 2357 static void 2358 alc_setlinkspeed(struct alc_softc *sc) 2359 { 2360 struct mii_data *mii; 2361 int aneg, i; 2362 2363 mii = device_get_softc(sc->alc_miibus); 2364 mii_pollstat(mii); 2365 aneg = 0; 2366 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2367 (IFM_ACTIVE | IFM_AVALID)) { 2368 switch IFM_SUBTYPE(mii->mii_media_active) { 2369 case IFM_10_T: 2370 case IFM_100_TX: 2371 return; 2372 case IFM_1000_T: 2373 aneg++; 2374 break; 2375 default: 2376 break; 2377 } 2378 } 2379 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2380 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2381 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2382 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2383 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2384 DELAY(1000); 2385 if (aneg != 0) { 2386 /* 2387 * Poll link state until alc(4) get a 10/100Mbps link. 2388 */ 2389 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2390 mii_pollstat(mii); 2391 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2392 == (IFM_ACTIVE | IFM_AVALID)) { 2393 switch (IFM_SUBTYPE( 2394 mii->mii_media_active)) { 2395 case IFM_10_T: 2396 case IFM_100_TX: 2397 alc_mac_config(sc); 2398 return; 2399 default: 2400 break; 2401 } 2402 } 2403 ALC_UNLOCK(sc); 2404 pause("alclnk", hz); 2405 ALC_LOCK(sc); 2406 } 2407 if (i == MII_ANEGTICKS_GIGE) 2408 device_printf(sc->alc_dev, 2409 "establishing a link failed, WOL may not work!"); 2410 } 2411 /* 2412 * No link, force MAC to have 100Mbps, full-duplex link. 2413 * This is the last resort and may/may not work. 2414 */ 2415 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2416 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2417 alc_mac_config(sc); 2418 } 2419 #endif 2420 2421 #if 0 2422 /* XXX: WOL */ 2423 static void 2424 alc_setwol(struct alc_softc *sc) 2425 { 2426 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2427 alc_setwol_816x(sc); 2428 else 2429 alc_setwol_813x(sc); 2430 } 2431 2432 static void 2433 alc_setwol_813x(struct alc_softc *sc) 2434 { 2435 struct ifnet *ifp; 2436 uint32_t reg, pmcs; 2437 uint16_t pmstat; 2438 2439 ALC_LOCK_ASSERT(sc); 2440 2441 alc_disable_l0s_l1(sc); 2442 ifp = sc->alc_ifp; 2443 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2444 /* Disable WOL. */ 2445 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2446 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2447 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2448 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2449 /* Force PHY power down. */ 2450 alc_phy_down(sc); 2451 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2452 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2453 return; 2454 } 2455 2456 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2457 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2458 alc_setlinkspeed(sc); 2459 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2460 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2461 } 2462 2463 pmcs = 0; 2464 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2465 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2466 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2467 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2468 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2469 MAC_CFG_BCAST); 2470 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2471 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2472 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2473 reg |= MAC_CFG_RX_ENB; 2474 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2475 2476 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2477 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2478 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2479 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2480 /* WOL disabled, PHY power down. */ 2481 alc_phy_down(sc); 2482 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2483 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2484 2485 } 2486 /* Request PME. */ 2487 pmstat = pci_read_config(sc->alc_dev, 2488 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2489 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2490 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2491 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2492 pci_write_config(sc->alc_dev, 2493 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2494 } 2495 2496 static void 2497 alc_setwol_816x(struct alc_softc *sc) 2498 { 2499 struct ifnet *ifp; 2500 uint32_t gphy, mac, master, pmcs, reg; 2501 uint16_t pmstat; 2502 2503 ALC_LOCK_ASSERT(sc); 2504 2505 ifp = sc->alc_ifp; 2506 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2507 master &= ~MASTER_CLK_SEL_DIS; 2508 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2509 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2510 GPHY_CFG_PHY_PLL_ON); 2511 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2512 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2513 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2514 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2515 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2516 } else { 2517 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2518 gphy |= GPHY_CFG_EXT_RESET; 2519 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2520 alc_setlinkspeed(sc); 2521 } 2522 pmcs = 0; 2523 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2524 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2525 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2526 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2527 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2528 MAC_CFG_BCAST); 2529 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2530 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2531 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2532 mac |= MAC_CFG_RX_ENB; 2533 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2534 ANEG_S3DIG10_SL); 2535 } 2536 2537 /* Enable OSC. */ 2538 reg = CSR_READ_4(sc, ALC_MISC); 2539 reg &= ~MISC_INTNLOSC_OPEN; 2540 CSR_WRITE_4(sc, ALC_MISC, reg); 2541 reg |= MISC_INTNLOSC_OPEN; 2542 CSR_WRITE_4(sc, ALC_MISC, reg); 2543 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2544 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2545 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2546 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2547 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2548 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2549 2550 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2551 /* Request PME. */ 2552 pmstat = pci_read_config(sc->alc_dev, 2553 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2554 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2555 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2556 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2557 pci_write_config(sc->alc_dev, 2558 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2559 } 2560 } 2561 2562 #endif 2563 2564 static int 2565 alc_suspend(device_t dev) 2566 { 2567 struct alc_softc *sc = device_get_softc(dev); 2568 struct ifnet *ifp = &sc->arpcom.ac_if; 2569 2570 lwkt_serialize_enter(ifp->if_serializer); 2571 alc_stop(sc); 2572 #if 0 2573 /* XXX: WOL */ 2574 alc_setwol(sc); 2575 #endif 2576 lwkt_serialize_exit(ifp->if_serializer); 2577 2578 return (0); 2579 } 2580 2581 static int 2582 alc_resume(device_t dev) 2583 { 2584 struct alc_softc *sc = device_get_softc(dev); 2585 struct ifnet *ifp = &sc->arpcom.ac_if; 2586 uint16_t pmstat; 2587 2588 lwkt_serialize_enter(ifp->if_serializer); 2589 2590 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2591 /* Disable PME and clear PME status. */ 2592 pmstat = pci_read_config(sc->alc_dev, 2593 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2594 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2595 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2596 pci_write_config(sc->alc_dev, 2597 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2598 } 2599 } 2600 2601 /* Reset PHY. */ 2602 alc_phy_reset(sc); 2603 if (ifp->if_flags & IFF_UP) 2604 alc_init(sc); 2605 2606 lwkt_serialize_exit(ifp->if_serializer); 2607 2608 return (0); 2609 } 2610 2611 static int 2612 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2613 { 2614 struct alc_txdesc *txd, *txd_last; 2615 struct tx_desc *desc; 2616 struct mbuf *m; 2617 struct ip *ip; 2618 struct tcphdr *tcp; 2619 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2620 bus_dmamap_t map; 2621 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2622 int error, idx, nsegs, prod; 2623 2624 M_ASSERTPKTHDR((*m_head)); 2625 2626 m = *m_head; 2627 ip = NULL; 2628 tcp = NULL; 2629 ip_off = poff = 0; 2630 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2631 /* 2632 * AR81[3567]x requires offset of TCP/UDP header in its 2633 * Tx descriptor to perform Tx checksum offloading. TSO 2634 * also requires TCP header offset and modification of 2635 * IP/TCP header. This kind of operation takes many CPU 2636 * cycles on FreeBSD so fast host CPU is required to get 2637 * smooth TSO performance. 2638 */ 2639 struct ether_header *eh; 2640 2641 if (M_WRITABLE(m) == 0) { 2642 /* Get a writable copy. */ 2643 m = m_dup(*m_head, M_NOWAIT); 2644 /* Release original mbufs. */ 2645 m_freem(*m_head); 2646 if (m == NULL) { 2647 *m_head = NULL; 2648 return (ENOBUFS); 2649 } 2650 *m_head = m; 2651 } 2652 2653 ip_off = sizeof(struct ether_header); 2654 m = m_pullup(m, ip_off + sizeof(struct ip)); 2655 if (m == NULL) { 2656 *m_head = NULL; 2657 return (ENOBUFS); 2658 } 2659 eh = mtod(m, struct ether_header *); 2660 /* 2661 * Check if hardware VLAN insertion is off. 2662 * Additional check for LLC/SNAP frame? 2663 */ 2664 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2665 ip_off = sizeof(struct ether_vlan_header); 2666 m = m_pullup(m, ip_off); 2667 if (m == NULL) { 2668 *m_head = NULL; 2669 return (ENOBUFS); 2670 } 2671 } 2672 m = m_pullup(m, ip_off + sizeof(struct ip)); 2673 if (m == NULL) { 2674 *m_head = NULL; 2675 return (ENOBUFS); 2676 } 2677 ip = (struct ip *)(mtod(m, char *) + ip_off); 2678 poff = ip_off + (ip->ip_hl << 2); 2679 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2680 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2681 if (m == NULL) { 2682 *m_head = NULL; 2683 return (ENOBUFS); 2684 } 2685 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2686 m = m_pullup(m, poff + (tcp->th_off << 2)); 2687 if (m == NULL) { 2688 *m_head = NULL; 2689 return (ENOBUFS); 2690 } 2691 /* 2692 * Due to strict adherence of Microsoft NDIS 2693 * Large Send specification, hardware expects 2694 * a pseudo TCP checksum inserted by upper 2695 * stack. Unfortunately the pseudo TCP 2696 * checksum that NDIS refers to does not include 2697 * TCP payload length so driver should recompute 2698 * the pseudo checksum here. Hopefully this 2699 * wouldn't be much burden on modern CPUs. 2700 * 2701 * Reset IP checksum and recompute TCP pseudo 2702 * checksum as NDIS specification said. 2703 */ 2704 ip = (struct ip *)(mtod(m, char *) + ip_off); 2705 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2706 ip->ip_sum = 0; 2707 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2708 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2709 } 2710 *m_head = m; 2711 } 2712 2713 prod = sc->alc_cdata.alc_tx_prod; 2714 txd = &sc->alc_cdata.alc_txdesc[prod]; 2715 txd_last = txd; 2716 map = txd->tx_dmamap; 2717 2718 error = bus_dmamap_load_mbuf_defrag( 2719 sc->alc_cdata.alc_tx_tag, map, m_head, 2720 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 2721 if (error) { 2722 m_freem(*m_head); 2723 *m_head = NULL; 2724 return (error); 2725 } 2726 if (nsegs == 0) { 2727 m_freem(*m_head); 2728 *m_head = NULL; 2729 return (EIO); 2730 } 2731 2732 /* Check descriptor overrun. */ 2733 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2734 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2735 return (ENOBUFS); 2736 } 2737 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2738 2739 m = *m_head; 2740 cflags = TD_ETHERNET; 2741 vtag = 0; 2742 desc = NULL; 2743 idx = 0; 2744 /* Configure VLAN hardware tag insertion. */ 2745 if ((m->m_flags & M_VLANTAG) != 0) { 2746 vtag = htons(m->m_pkthdr.ether_vlantag); 2747 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2748 cflags |= TD_INS_VLAN_TAG; 2749 } 2750 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2751 /* Request TSO and set MSS. */ 2752 cflags |= TD_TSO | TD_TSO_DESCV1; 2753 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2754 TD_MSS_MASK; 2755 /* Set TCP header offset. */ 2756 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2757 TD_TCPHDR_OFFSET_MASK; 2758 /* 2759 * AR81[3567]x requires the first buffer should 2760 * only hold IP/TCP header data. Payload should 2761 * be handled in other descriptors. 2762 */ 2763 hdrlen = poff + (tcp->th_off << 2); 2764 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2765 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2766 desc->flags = htole32(cflags); 2767 desc->addr = htole64(txsegs[0].ds_addr); 2768 sc->alc_cdata.alc_tx_cnt++; 2769 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2770 if (m->m_len - hdrlen > 0) { 2771 /* Handle remaining payload of the first fragment. */ 2772 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2773 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2774 vtag)); 2775 desc->flags = htole32(cflags); 2776 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2777 sc->alc_cdata.alc_tx_cnt++; 2778 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2779 } 2780 /* Handle remaining fragments. */ 2781 idx = 1; 2782 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2783 /* Configure Tx checksum offload. */ 2784 #ifdef ALC_USE_CUSTOM_CSUM 2785 cflags |= TD_CUSTOM_CSUM; 2786 /* Set checksum start offset. */ 2787 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2788 TD_PLOAD_OFFSET_MASK; 2789 /* Set checksum insertion position of TCP/UDP. */ 2790 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2791 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2792 #else 2793 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2794 cflags |= TD_IPCSUM; 2795 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2796 cflags |= TD_TCPCSUM; 2797 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2798 cflags |= TD_UDPCSUM; 2799 /* Set TCP/UDP header offset. */ 2800 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2801 TD_L4HDR_OFFSET_MASK; 2802 #endif 2803 } 2804 2805 for (; idx < nsegs; idx++) { 2806 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2807 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2808 desc->flags = htole32(cflags); 2809 desc->addr = htole64(txsegs[idx].ds_addr); 2810 sc->alc_cdata.alc_tx_cnt++; 2811 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2812 } 2813 /* Update producer index. */ 2814 sc->alc_cdata.alc_tx_prod = prod; 2815 2816 /* Finally set EOP on the last descriptor. */ 2817 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2818 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2819 desc->flags |= htole32(TD_EOP); 2820 2821 /* Swap dmamap of the first and the last. */ 2822 txd = &sc->alc_cdata.alc_txdesc[prod]; 2823 map = txd_last->tx_dmamap; 2824 txd_last->tx_dmamap = txd->tx_dmamap; 2825 txd->tx_dmamap = map; 2826 txd->tx_m = m; 2827 2828 return (0); 2829 } 2830 2831 static void 2832 alc_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2833 { 2834 struct alc_softc *sc = ifp->if_softc; 2835 struct mbuf *m_head; 2836 int enq; 2837 2838 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2839 ASSERT_SERIALIZED(ifp->if_serializer); 2840 2841 /* Reclaim transmitted frames. */ 2842 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2843 alc_txeof(sc); 2844 2845 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 2846 return; 2847 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2848 ifq_purge(&ifp->if_snd); 2849 return; 2850 } 2851 2852 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) { 2853 m_head = ifq_dequeue(&ifp->if_snd); 2854 if (m_head == NULL) 2855 break; 2856 /* 2857 * Pack the data into the transmit ring. If we 2858 * don't have room, set the OACTIVE flag and wait 2859 * for the NIC to drain the ring. 2860 */ 2861 if (alc_encap(sc, &m_head)) { 2862 if (m_head == NULL) 2863 break; 2864 ifq_prepend(&ifp->if_snd, m_head); 2865 ifq_set_oactive(&ifp->if_snd); 2866 break; 2867 } 2868 2869 enq++; 2870 /* 2871 * If there's a BPF listener, bounce a copy of this frame 2872 * to him. 2873 */ 2874 ETHER_BPF_MTAP(ifp, m_head); 2875 } 2876 2877 if (enq > 0) { 2878 /* Sync descriptors. */ 2879 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2880 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2881 /* Kick. Assume we're using normal Tx priority queue. */ 2882 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2883 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2884 (uint16_t)sc->alc_cdata.alc_tx_prod); 2885 else 2886 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2887 (sc->alc_cdata.alc_tx_prod << 2888 MBOX_TD_PROD_LO_IDX_SHIFT) & 2889 MBOX_TD_PROD_LO_IDX_MASK); 2890 /* Set a timeout in case the chip goes out to lunch. */ 2891 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2892 } 2893 } 2894 2895 static void 2896 alc_watchdog(struct alc_softc *sc) 2897 { 2898 struct ifnet *ifp = &sc->arpcom.ac_if; 2899 2900 ASSERT_SERIALIZED(ifp->if_serializer); 2901 2902 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2903 return; 2904 2905 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2906 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2907 IFNET_STAT_INC(ifp, oerrors, 1); 2908 alc_init(sc); 2909 return; 2910 } 2911 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2912 IFNET_STAT_INC(ifp, oerrors, 1); 2913 alc_init(sc); 2914 if (!ifq_is_empty(&ifp->if_snd)) 2915 if_devstart(ifp); 2916 } 2917 2918 static int 2919 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2920 { 2921 struct alc_softc *sc; 2922 struct ifreq *ifr; 2923 struct mii_data *mii; 2924 int error, mask; 2925 2926 ASSERT_SERIALIZED(ifp->if_serializer); 2927 2928 sc = ifp->if_softc; 2929 ifr = (struct ifreq *)data; 2930 error = 0; 2931 switch (cmd) { 2932 case SIOCSIFMTU: 2933 if (ifr->ifr_mtu < ETHERMIN || 2934 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2935 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2936 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2937 ifr->ifr_mtu > ETHERMTU)) { 2938 error = EINVAL; 2939 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2940 ifp->if_mtu = ifr->ifr_mtu; 2941 #if 0 2942 /* AR81[3567]x has 13 bits MSS field. */ 2943 if (ifp->if_mtu > ALC_TSO_MTU && 2944 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2945 ifp->if_capenable &= ~IFCAP_TSO4; 2946 ifp->if_hwassist &= ~CSUM_TSO; 2947 } 2948 #endif 2949 } 2950 break; 2951 case SIOCSIFFLAGS: 2952 if ((ifp->if_flags & IFF_UP) != 0) { 2953 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2954 ((ifp->if_flags ^ sc->alc_if_flags) & 2955 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2956 alc_rxfilter(sc); 2957 else if ((ifp->if_flags & IFF_RUNNING) == 0) 2958 alc_init(sc); 2959 } else if ((ifp->if_flags & IFF_RUNNING) != 0) 2960 alc_stop(sc); 2961 sc->alc_if_flags = ifp->if_flags; 2962 break; 2963 case SIOCADDMULTI: 2964 case SIOCDELMULTI: 2965 if ((ifp->if_flags & IFF_RUNNING) != 0) 2966 alc_rxfilter(sc); 2967 break; 2968 case SIOCSIFMEDIA: 2969 case SIOCGIFMEDIA: 2970 mii = device_get_softc(sc->alc_miibus); 2971 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2972 break; 2973 case SIOCSIFCAP: 2974 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2975 if ((mask & IFCAP_TXCSUM) != 0 && 2976 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2977 ifp->if_capenable ^= IFCAP_TXCSUM; 2978 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2979 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2980 else 2981 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2982 } 2983 #if 0 2984 /* XXX: WOL */ 2985 if ((mask & IFCAP_WOL_MCAST) != 0 && 2986 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2987 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2988 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2989 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2990 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2991 #endif 2992 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2993 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2994 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2995 alc_rxvlan(sc); 2996 } 2997 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2998 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2999 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3000 3001 /* 3002 * VLAN hardware tagging is required to do checksum 3003 * offload or TSO on VLAN interface. Checksum offload 3004 * on VLAN interface also requires hardware checksum 3005 * offload of parent interface. 3006 */ 3007 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 3008 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 3009 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3010 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 3011 // XXX VLAN_CAPABILITIES(ifp); 3012 break; 3013 default: 3014 error = ether_ioctl(ifp, cmd, data); 3015 break; 3016 } 3017 3018 return (error); 3019 } 3020 3021 static void 3022 alc_mac_config(struct alc_softc *sc) 3023 { 3024 struct mii_data *mii; 3025 uint32_t reg; 3026 3027 mii = device_get_softc(sc->alc_miibus); 3028 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3029 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3030 MAC_CFG_SPEED_MASK); 3031 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3032 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3033 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3034 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3035 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3036 } 3037 /* Reprogram MAC with resolved speed/duplex. */ 3038 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3039 case IFM_10_T: 3040 case IFM_100_TX: 3041 reg |= MAC_CFG_SPEED_10_100; 3042 break; 3043 case IFM_1000_T: 3044 reg |= MAC_CFG_SPEED_1000; 3045 break; 3046 } 3047 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3048 reg |= MAC_CFG_FULL_DUPLEX; 3049 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3050 reg |= MAC_CFG_TX_FC; 3051 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3052 reg |= MAC_CFG_RX_FC; 3053 } 3054 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3055 } 3056 3057 static void 3058 alc_stats_clear(struct alc_softc *sc) 3059 { 3060 struct smb sb, *smb; 3061 uint32_t *reg; 3062 int i; 3063 3064 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3065 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3066 sc->alc_cdata.alc_smb_map, 3067 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3068 smb = sc->alc_rdata.alc_smb; 3069 /* Update done, clear. */ 3070 smb->updated = 0; 3071 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3072 sc->alc_cdata.alc_smb_map, 3073 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3074 } else { 3075 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3076 reg++) { 3077 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3078 i += sizeof(uint32_t); 3079 } 3080 /* Read Tx statistics. */ 3081 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3082 reg++) { 3083 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3084 i += sizeof(uint32_t); 3085 } 3086 } 3087 } 3088 3089 static void 3090 alc_stats_update(struct alc_softc *sc) 3091 { 3092 struct alc_hw_stats *stat; 3093 struct smb sb, *smb; 3094 struct ifnet *ifp; 3095 uint32_t *reg; 3096 int i; 3097 3098 ifp = sc->alc_ifp; 3099 stat = &sc->alc_stats; 3100 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3101 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3102 sc->alc_cdata.alc_smb_map, 3103 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3104 smb = sc->alc_rdata.alc_smb; 3105 if (smb->updated == 0) 3106 return; 3107 } else { 3108 smb = &sb; 3109 /* Read Rx statistics. */ 3110 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3111 reg++) { 3112 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3113 i += sizeof(uint32_t); 3114 } 3115 /* Read Tx statistics. */ 3116 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3117 reg++) { 3118 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3119 i += sizeof(uint32_t); 3120 } 3121 } 3122 3123 /* Rx stats. */ 3124 stat->rx_frames += smb->rx_frames; 3125 stat->rx_bcast_frames += smb->rx_bcast_frames; 3126 stat->rx_mcast_frames += smb->rx_mcast_frames; 3127 stat->rx_pause_frames += smb->rx_pause_frames; 3128 stat->rx_control_frames += smb->rx_control_frames; 3129 stat->rx_crcerrs += smb->rx_crcerrs; 3130 stat->rx_lenerrs += smb->rx_lenerrs; 3131 stat->rx_bytes += smb->rx_bytes; 3132 stat->rx_runts += smb->rx_runts; 3133 stat->rx_fragments += smb->rx_fragments; 3134 stat->rx_pkts_64 += smb->rx_pkts_64; 3135 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3136 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3137 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3138 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3139 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3140 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3141 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3142 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3143 stat->rx_rrs_errs += smb->rx_rrs_errs; 3144 stat->rx_alignerrs += smb->rx_alignerrs; 3145 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3146 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3147 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3148 3149 /* Tx stats. */ 3150 stat->tx_frames += smb->tx_frames; 3151 stat->tx_bcast_frames += smb->tx_bcast_frames; 3152 stat->tx_mcast_frames += smb->tx_mcast_frames; 3153 stat->tx_pause_frames += smb->tx_pause_frames; 3154 stat->tx_excess_defer += smb->tx_excess_defer; 3155 stat->tx_control_frames += smb->tx_control_frames; 3156 stat->tx_deferred += smb->tx_deferred; 3157 stat->tx_bytes += smb->tx_bytes; 3158 stat->tx_pkts_64 += smb->tx_pkts_64; 3159 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3160 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3161 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3162 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3163 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3164 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3165 stat->tx_single_colls += smb->tx_single_colls; 3166 stat->tx_multi_colls += smb->tx_multi_colls; 3167 stat->tx_late_colls += smb->tx_late_colls; 3168 stat->tx_excess_colls += smb->tx_excess_colls; 3169 stat->tx_underrun += smb->tx_underrun; 3170 stat->tx_desc_underrun += smb->tx_desc_underrun; 3171 stat->tx_lenerrs += smb->tx_lenerrs; 3172 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3173 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3174 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3175 3176 /* Update counters in ifnet. */ 3177 IFNET_STAT_INC(ifp, opackets, smb->tx_frames); 3178 3179 IFNET_STAT_INC(ifp, collisions, smb->tx_single_colls + 3180 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3181 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3182 3183 IFNET_STAT_INC(ifp, oerrors, 3184 smb->tx_excess_colls + smb->tx_late_colls + smb->tx_underrun); 3185 3186 IFNET_STAT_INC(ifp, ipackets, smb->rx_frames); 3187 3188 IFNET_STAT_INC(ifp, ierrors, smb->rx_crcerrs + smb->rx_lenerrs + 3189 smb->rx_runts + smb->rx_pkts_truncated + 3190 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3191 smb->rx_alignerrs); 3192 3193 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3194 /* Update done, clear. */ 3195 smb->updated = 0; 3196 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3197 sc->alc_cdata.alc_smb_map, 3198 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3199 } 3200 } 3201 3202 static void 3203 alc_intr(void *arg) 3204 { 3205 struct alc_softc *sc = arg; 3206 struct ifnet *ifp = &sc->arpcom.ac_if; 3207 uint32_t status; 3208 3209 ASSERT_SERIALIZED(ifp->if_serializer); 3210 3211 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3212 if ((status & ALC_INTRS) == 0) 3213 return; 3214 3215 /* Acknowledge interrupts and disable interrupts. */ 3216 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3217 3218 if (ifp->if_flags & IFF_RUNNING) { 3219 if (status & INTR_RX_PKT) { 3220 if (alc_rxintr(sc)) { 3221 alc_init(sc); 3222 return; 3223 } 3224 } 3225 if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3226 INTR_TXQ_TO_RST)) { 3227 if (status & INTR_DMA_RD_TO_RST) { 3228 if_printf(ifp, 3229 "DMA read error! -- resetting\n"); 3230 } 3231 if (status & INTR_DMA_WR_TO_RST) { 3232 if_printf(ifp, 3233 "DMA write error! -- resetting\n"); 3234 } 3235 if (status & INTR_TXQ_TO_RST) 3236 if_printf(ifp, "TxQ reset! -- resetting\n"); 3237 alc_init(sc); 3238 return; 3239 } 3240 if (!ifq_is_empty(&ifp->if_snd)) 3241 if_devstart(ifp); 3242 3243 /* Re-enable interrupts */ 3244 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3245 } 3246 } 3247 3248 static void 3249 alc_txeof(struct alc_softc *sc) 3250 { 3251 struct ifnet *ifp; 3252 struct alc_txdesc *txd; 3253 uint32_t cons, prod; 3254 int prog; 3255 3256 ifp = sc->alc_ifp; 3257 3258 if (sc->alc_cdata.alc_tx_cnt == 0) 3259 return; 3260 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3261 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3262 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3263 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3264 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3265 prod = sc->alc_rdata.alc_cmb->cons; 3266 } else { 3267 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3268 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3269 else { 3270 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3271 /* Assume we're using normal Tx priority queue. */ 3272 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3273 MBOX_TD_CONS_LO_IDX_SHIFT; 3274 } 3275 } 3276 cons = sc->alc_cdata.alc_tx_cons; 3277 /* 3278 * Go through our Tx list and free mbufs for those 3279 * frames which have been transmitted. 3280 */ 3281 for (prog = 0; cons != prod; prog++, 3282 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3283 if (sc->alc_cdata.alc_tx_cnt <= 0) 3284 break; 3285 prog++; 3286 ifq_clr_oactive(&ifp->if_snd); 3287 sc->alc_cdata.alc_tx_cnt--; 3288 txd = &sc->alc_cdata.alc_txdesc[cons]; 3289 if (txd->tx_m != NULL) { 3290 /* Reclaim transmitted mbufs. */ 3291 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3292 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3293 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3294 txd->tx_dmamap); 3295 m_freem(txd->tx_m); 3296 txd->tx_m = NULL; 3297 } 3298 } 3299 3300 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3301 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3302 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3303 sc->alc_cdata.alc_tx_cons = cons; 3304 /* 3305 * Unarm watchdog timer only when there is no pending 3306 * frames in Tx queue. 3307 */ 3308 if (sc->alc_cdata.alc_tx_cnt == 0) 3309 sc->alc_watchdog_timer = 0; 3310 } 3311 3312 static int 3313 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd, boolean_t wait) 3314 { 3315 struct mbuf *m; 3316 bus_dma_segment_t segs[1]; 3317 bus_dmamap_t map; 3318 int nsegs; 3319 int error; 3320 3321 m = m_getcl(wait ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 3322 if (m == NULL) 3323 return (ENOBUFS); 3324 m->m_len = m->m_pkthdr.len = MCLBYTES; 3325 #ifdef foo 3326 /* Hardware require 4 bytes align */ 3327 m_adj(m, ETHER_ALIGN); 3328 #endif 3329 3330 error = bus_dmamap_load_mbuf_segment( 3331 sc->alc_cdata.alc_rx_tag, 3332 sc->alc_cdata.alc_rx_sparemap, 3333 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 3334 if (error) { 3335 m_freem(m); 3336 return (ENOBUFS); 3337 } 3338 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3339 3340 if (rxd->rx_m != NULL) { 3341 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3342 BUS_DMASYNC_POSTREAD); 3343 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3344 } 3345 map = rxd->rx_dmamap; 3346 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3347 sc->alc_cdata.alc_rx_sparemap = map; 3348 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3349 BUS_DMASYNC_PREREAD); 3350 rxd->rx_m = m; 3351 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3352 return (0); 3353 } 3354 3355 static int 3356 alc_rxintr(struct alc_softc *sc) 3357 { 3358 struct ifnet *ifp; 3359 struct rx_rdesc *rrd; 3360 uint32_t nsegs, status; 3361 int rr_cons, prog; 3362 3363 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3364 sc->alc_cdata.alc_rr_ring_map, 3365 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3366 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3367 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3368 rr_cons = sc->alc_cdata.alc_rr_cons; 3369 ifp = sc->alc_ifp; 3370 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 3371 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3372 status = le32toh(rrd->status); 3373 if ((status & RRD_VALID) == 0) 3374 break; 3375 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3376 if (nsegs == 0) { 3377 /* This should not happen! */ 3378 device_printf(sc->alc_dev, 3379 "unexpected segment count -- resetting\n"); 3380 return (EIO); 3381 } 3382 alc_rxeof(sc, rrd); 3383 /* Clear Rx return status. */ 3384 rrd->status = 0; 3385 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3386 sc->alc_cdata.alc_rx_cons += nsegs; 3387 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3388 prog += nsegs; 3389 } 3390 3391 if (prog > 0) { 3392 /* Update the consumer index. */ 3393 sc->alc_cdata.alc_rr_cons = rr_cons; 3394 /* Sync Rx return descriptors. */ 3395 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3396 sc->alc_cdata.alc_rr_ring_map, 3397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3398 /* 3399 * Sync updated Rx descriptors such that controller see 3400 * modified buffer addresses. 3401 */ 3402 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3403 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3404 /* 3405 * Let controller know availability of new Rx buffers. 3406 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3407 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3408 * only when Rx buffer pre-fetching is required. In 3409 * addition we already set ALC_RX_RD_FREE_THRESH to 3410 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3411 * it still seems that pre-fetching needs more 3412 * experimentation. 3413 */ 3414 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3415 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3416 (uint16_t)sc->alc_cdata.alc_rx_cons); 3417 else 3418 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3419 sc->alc_cdata.alc_rx_cons); 3420 } 3421 3422 return 0; 3423 } 3424 3425 /* Receive a frame. */ 3426 static void 3427 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3428 { 3429 struct alc_rxdesc *rxd; 3430 struct ifnet *ifp; 3431 struct mbuf *mp, *m; 3432 uint32_t rdinfo, status, vtag; 3433 int count, nsegs, rx_cons; 3434 3435 ifp = sc->alc_ifp; 3436 status = le32toh(rrd->status); 3437 rdinfo = le32toh(rrd->rdinfo); 3438 rx_cons = RRD_RD_IDX(rdinfo); 3439 nsegs = RRD_RD_CNT(rdinfo); 3440 3441 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3442 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3443 /* 3444 * We want to pass the following frames to upper 3445 * layer regardless of error status of Rx return 3446 * ring. 3447 * 3448 * o IP/TCP/UDP checksum is bad. 3449 * o frame length and protocol specific length 3450 * does not match. 3451 * 3452 * Force network stack compute checksum for 3453 * errored frames. 3454 */ 3455 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3456 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3457 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3458 return; 3459 } 3460 3461 for (count = 0; count < nsegs; count++, 3462 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3463 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3464 mp = rxd->rx_m; 3465 /* Add a new receive buffer to the ring. */ 3466 if (alc_newbuf(sc, rxd, FALSE) != 0) { 3467 IFNET_STAT_INC(ifp, iqdrops, 1); 3468 /* Reuse Rx buffers. */ 3469 if (sc->alc_cdata.alc_rxhead != NULL) 3470 m_freem(sc->alc_cdata.alc_rxhead); 3471 break; 3472 } 3473 3474 /* 3475 * Assume we've received a full sized frame. 3476 * Actual size is fixed when we encounter the end of 3477 * multi-segmented frame. 3478 */ 3479 mp->m_len = sc->alc_buf_size; 3480 3481 /* Chain received mbufs. */ 3482 if (sc->alc_cdata.alc_rxhead == NULL) { 3483 sc->alc_cdata.alc_rxhead = mp; 3484 sc->alc_cdata.alc_rxtail = mp; 3485 } else { 3486 /*mp->m_flags &= ~M_PKTHDR;*/ 3487 sc->alc_cdata.alc_rxprev_tail = 3488 sc->alc_cdata.alc_rxtail; 3489 sc->alc_cdata.alc_rxtail->m_next = mp; 3490 sc->alc_cdata.alc_rxtail = mp; 3491 } 3492 3493 if (count == nsegs - 1) { 3494 /* Last desc. for this frame. */ 3495 m = sc->alc_cdata.alc_rxhead; 3496 /*m->m_flags |= M_PKTHDR;*/ 3497 3498 /* 3499 * It seems that L1C/L2C controller has no way 3500 * to tell hardware to strip CRC bytes. 3501 */ 3502 m->m_pkthdr.len = 3503 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3504 if (nsegs > 1) { 3505 /* Set last mbuf size. */ 3506 mp->m_len = sc->alc_cdata.alc_rxlen - 3507 (nsegs - 1) * sc->alc_buf_size; 3508 /* Remove the CRC bytes in chained mbufs. */ 3509 if (mp->m_len <= ETHER_CRC_LEN) { 3510 sc->alc_cdata.alc_rxtail = 3511 sc->alc_cdata.alc_rxprev_tail; 3512 sc->alc_cdata.alc_rxtail->m_len -= 3513 (ETHER_CRC_LEN - mp->m_len); 3514 sc->alc_cdata.alc_rxtail->m_next = NULL; 3515 m_freem(mp); 3516 } else { 3517 mp->m_len -= ETHER_CRC_LEN; 3518 } 3519 } else 3520 m->m_len = m->m_pkthdr.len; 3521 m->m_pkthdr.rcvif = ifp; 3522 /* 3523 * Due to hardware bugs, Rx checksum offloading 3524 * was intentionally disabled. 3525 */ 3526 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3527 (status & RRD_VLAN_TAG) != 0) { 3528 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3529 m->m_pkthdr.ether_vlantag = ntohs(vtag); 3530 m->m_flags |= M_VLANTAG; 3531 } 3532 3533 /* Pass it on. */ 3534 ifp->if_input(ifp, m, NULL, -1); 3535 } 3536 } 3537 /* Reset mbuf chains. */ 3538 ALC_RXCHAIN_RESET(sc); 3539 } 3540 3541 static void 3542 alc_tick(void *arg) 3543 { 3544 struct alc_softc *sc = arg; 3545 struct ifnet *ifp = &sc->arpcom.ac_if; 3546 struct mii_data *mii; 3547 3548 lwkt_serialize_enter(ifp->if_serializer); 3549 3550 mii = device_get_softc(sc->alc_miibus); 3551 mii_tick(mii); 3552 alc_stats_update(sc); 3553 /* 3554 * alc(4) does not rely on Tx completion interrupts to reclaim 3555 * transferred buffers. Instead Tx completion interrupts are 3556 * used to hint for scheduling Tx task. So it's necessary to 3557 * release transmitted buffers by kicking Tx completion 3558 * handler. This limits the maximum reclamation delay to a hz. 3559 */ 3560 alc_txeof(sc); 3561 alc_watchdog(sc); 3562 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3563 3564 #if 0 3565 /* poll for debugging */ 3566 alc_intr(sc); 3567 #endif 3568 3569 lwkt_serialize_exit(ifp->if_serializer); 3570 } 3571 3572 static void 3573 alc_osc_reset(struct alc_softc *sc) 3574 { 3575 uint32_t reg; 3576 3577 reg = CSR_READ_4(sc, ALC_MISC3); 3578 reg &= ~MISC3_25M_BY_SW; 3579 reg |= MISC3_25M_NOTO_INTNL; 3580 CSR_WRITE_4(sc, ALC_MISC3, reg); 3581 3582 reg = CSR_READ_4(sc, ALC_MISC); 3583 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3584 /* 3585 * Restore over-current protection default value. 3586 * This value could be reset by MAC reset. 3587 */ 3588 reg &= ~MISC_PSW_OCP_MASK; 3589 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3590 reg &= ~MISC_INTNLOSC_OPEN; 3591 CSR_WRITE_4(sc, ALC_MISC, reg); 3592 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3593 reg = CSR_READ_4(sc, ALC_MISC2); 3594 reg &= ~MISC2_CALB_START; 3595 CSR_WRITE_4(sc, ALC_MISC2, reg); 3596 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3597 3598 } else { 3599 reg &= ~MISC_INTNLOSC_OPEN; 3600 /* Disable isolate for revision A devices. */ 3601 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3602 reg &= ~MISC_ISO_ENB; 3603 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3604 CSR_WRITE_4(sc, ALC_MISC, reg); 3605 } 3606 3607 DELAY(20); 3608 } 3609 3610 static void 3611 alc_reset(struct alc_softc *sc) 3612 { 3613 uint32_t pmcfg, reg; 3614 int i; 3615 3616 pmcfg = 0; 3617 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3618 /* Reset workaround. */ 3619 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3620 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3621 (sc->alc_rev & 0x01) != 0) { 3622 /* Disable L0s/L1s before reset. */ 3623 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3624 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3625 != 0) { 3626 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3627 PM_CFG_ASPM_L1_ENB); 3628 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3629 } 3630 } 3631 } 3632 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3633 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3634 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3635 3636 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3637 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3638 DELAY(10); 3639 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3640 break; 3641 } 3642 if (i == 0) 3643 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3644 } 3645 3646 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3647 DELAY(10); 3648 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3649 break; 3650 } 3651 if (i == 0) 3652 device_printf(sc->alc_dev, "master reset timeout!\n"); 3653 3654 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3655 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3656 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3657 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3658 break; 3659 DELAY(10); 3660 } 3661 3662 if (i == 0) 3663 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3664 3665 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3666 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3667 (sc->alc_rev & 0x01) != 0) { 3668 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3669 reg |= MASTER_CLK_SEL_DIS; 3670 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3671 /* Restore L0s/L1s config. */ 3672 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3673 != 0) 3674 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3675 } 3676 3677 alc_osc_reset(sc); 3678 reg = CSR_READ_4(sc, ALC_MISC3); 3679 reg &= ~MISC3_25M_BY_SW; 3680 reg |= MISC3_25M_NOTO_INTNL; 3681 CSR_WRITE_4(sc, ALC_MISC3, reg); 3682 reg = CSR_READ_4(sc, ALC_MISC); 3683 reg &= ~MISC_INTNLOSC_OPEN; 3684 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3685 reg &= ~MISC_ISO_ENB; 3686 CSR_WRITE_4(sc, ALC_MISC, reg); 3687 DELAY(20); 3688 } 3689 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3690 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3691 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3692 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3693 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3694 SERDES_PHY_CLK_SLOWDOWN); 3695 } 3696 3697 static void 3698 alc_init(void *xsc) 3699 { 3700 struct alc_softc *sc = xsc; 3701 struct ifnet *ifp = &sc->arpcom.ac_if; 3702 struct mii_data *mii; 3703 uint8_t eaddr[ETHER_ADDR_LEN]; 3704 bus_addr_t paddr; 3705 uint32_t reg, rxf_hi, rxf_lo; 3706 3707 ASSERT_SERIALIZED(ifp->if_serializer); 3708 3709 mii = device_get_softc(sc->alc_miibus); 3710 3711 /* 3712 * Cancel any pending I/O. 3713 */ 3714 alc_stop(sc); 3715 /* 3716 * Reset the chip to a known state. 3717 */ 3718 alc_reset(sc); 3719 3720 /* Initialize Rx descriptors. */ 3721 if (alc_init_rx_ring(sc) != 0) { 3722 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3723 alc_stop(sc); 3724 return; 3725 } 3726 alc_init_rr_ring(sc); 3727 alc_init_tx_ring(sc); 3728 alc_init_cmb(sc); 3729 alc_init_smb(sc); 3730 3731 /* Enable all clocks. */ 3732 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3733 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3734 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3735 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3736 CLK_GATING_RXMAC_ENB); 3737 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3738 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3739 IDLE_DECISN_TIMER_DEFAULT_1MS); 3740 } else 3741 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3742 3743 /* Reprogram the station address. */ 3744 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3745 CSR_WRITE_4(sc, ALC_PAR0, 3746 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3747 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3748 /* 3749 * Clear WOL status and disable all WOL feature as WOL 3750 * would interfere Rx operation under normal environments. 3751 */ 3752 CSR_READ_4(sc, ALC_WOL_CFG); 3753 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3754 /* Set Tx descriptor base addresses. */ 3755 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3756 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3757 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3758 /* We don't use high priority ring. */ 3759 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3760 /* Set Tx descriptor counter. */ 3761 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3762 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3763 /* Set Rx descriptor base addresses. */ 3764 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3765 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3766 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3767 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3768 /* We use one Rx ring. */ 3769 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3770 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3771 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3772 } 3773 /* Set Rx descriptor counter. */ 3774 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3775 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3776 3777 /* 3778 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3779 * if it do not fit the buffer size. Rx return descriptor holds 3780 * a counter that indicates how many fragments were made by the 3781 * hardware. The buffer size should be multiple of 8 bytes. 3782 * Since hardware has limit on the size of buffer size, always 3783 * use the maximum value. 3784 * For strict-alignment architectures make sure to reduce buffer 3785 * size by 8 bytes to make room for alignment fixup. 3786 */ 3787 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3788 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3789 3790 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3791 /* Set Rx return descriptor base addresses. */ 3792 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3793 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3794 /* We use one Rx return ring. */ 3795 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3796 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3797 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3798 } 3799 /* Set Rx return descriptor counter. */ 3800 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3801 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3802 paddr = sc->alc_rdata.alc_cmb_paddr; 3803 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3804 paddr = sc->alc_rdata.alc_smb_paddr; 3805 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3806 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3807 3808 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3809 /* Reconfigure SRAM - Vendor magic. */ 3810 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3811 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3812 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3813 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3814 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3815 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3816 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3817 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3818 } 3819 3820 /* Tell hardware that we're ready to load DMA blocks. */ 3821 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3822 3823 /* Configure interrupt moderation timer. */ 3824 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3825 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 3826 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3827 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3828 /* 3829 * We don't want to automatic interrupt clear as task queue 3830 * for the interrupt should know interrupt status. 3831 */ 3832 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3833 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 3834 reg |= MASTER_SA_TIMER_ENB; 3835 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3836 reg |= MASTER_IM_RX_TIMER_ENB; 3837 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 3838 ALC_USECS(sc->alc_int_tx_mod) != 0) 3839 reg |= MASTER_IM_TX_TIMER_ENB; 3840 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3841 /* 3842 * Disable interrupt re-trigger timer. We don't want automatic 3843 * re-triggering of un-ACKed interrupts. 3844 */ 3845 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3846 /* Configure CMB. */ 3847 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3848 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 3849 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 3850 ALC_USECS(sc->alc_int_tx_mod)); 3851 } else { 3852 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3853 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3854 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3855 } else 3856 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3857 } 3858 3859 /* 3860 * Hardware can be configured to issue SMB interrupt based 3861 * on programmed interval. Since there is a callout that is 3862 * invoked for every hz in driver we use that instead of 3863 * relying on periodic SMB interrupt. 3864 */ 3865 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3866 /* Clear MAC statistics. */ 3867 alc_stats_clear(sc); 3868 3869 /* 3870 * Always use maximum frame size that controller can support. 3871 * Otherwise received frames that has larger frame length 3872 * than alc(4) MTU would be silently dropped in hardware. This 3873 * would make path-MTU discovery hard as sender wouldn't get 3874 * any responses from receiver. alc(4) supports 3875 * multi-fragmented frames on Rx path so it has no issue on 3876 * assembling fragmented frames. Using maximum frame size also 3877 * removes the need to reinitialize hardware when interface 3878 * MTU configuration was changed. 3879 * 3880 * Be conservative in what you do, be liberal in what you 3881 * accept from others - RFC 793. 3882 */ 3883 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3884 3885 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3886 /* Disable header split(?) */ 3887 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3888 3889 /* Configure IPG/IFG parameters. */ 3890 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3891 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 3892 IPG_IFG_IPGT_MASK) | 3893 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 3894 IPG_IFG_MIFG_MASK) | 3895 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 3896 IPG_IFG_IPG1_MASK) | 3897 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 3898 IPG_IFG_IPG2_MASK)); 3899 /* Set parameters for half-duplex media. */ 3900 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3901 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3902 HDPX_CFG_LCOL_MASK) | 3903 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3904 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3905 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3906 HDPX_CFG_ABEBT_MASK) | 3907 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3908 HDPX_CFG_JAMIPG_MASK)); 3909 } 3910 3911 /* 3912 * Set TSO/checksum offload threshold. For frames that is 3913 * larger than this threshold, hardware wouldn't do 3914 * TSO/checksum offloading. 3915 */ 3916 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3917 TSO_OFFLOAD_THRESH_MASK; 3918 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3919 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 3920 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 3921 /* Configure TxQ. */ 3922 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3923 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3924 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3926 reg >>= 1; 3927 } 3928 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3929 TXQ_CFG_TD_BURST_MASK; 3930 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 3931 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3932 3933 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3934 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 3935 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 3936 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 3937 HQTD_CFG_BURST_ENB); 3938 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 3939 reg = WRR_PRI_RESTRICT_NONE; 3940 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 3941 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 3942 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 3943 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 3944 CSR_WRITE_4(sc, ALC_WRR, reg); 3945 } else { 3946 /* Configure Rx free descriptor pre-fetching. */ 3947 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3948 ((RX_RD_FREE_THRESH_HI_DEFAULT << 3949 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 3950 ((RX_RD_FREE_THRESH_LO_DEFAULT << 3951 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 3952 } 3953 3954 /* 3955 * Configure flow control parameters. 3956 * XON : 80% of Rx FIFO 3957 * XOFF : 30% of Rx FIFO 3958 */ 3959 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3960 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3961 reg &= SRAM_RX_FIFO_LEN_MASK; 3962 reg *= 8; 3963 if (reg > 8 * 1024) 3964 reg -= RX_FIFO_PAUSE_816X_RSVD; 3965 else 3966 reg -= RX_BUF_SIZE_MAX; 3967 reg /= 8; 3968 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3969 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3970 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3971 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 3972 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3973 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3974 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3975 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3976 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3977 rxf_hi = (reg * 8) / 10; 3978 rxf_lo = (reg * 3) / 10; 3979 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3980 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3981 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3982 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3983 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3984 } 3985 3986 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3987 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3988 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3989 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3990 } 3991 3992 /* Configure RxQ. */ 3993 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3994 RXQ_CFG_RD_BURST_MASK; 3995 reg |= RXQ_CFG_RSS_MODE_DIS; 3996 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3997 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 3998 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 3999 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4000 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4001 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4002 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 4003 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4004 4005 /* Configure DMA parameters. */ 4006 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4007 reg |= sc->alc_rcb; 4008 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4009 reg |= DMA_CFG_CMB_ENB; 4010 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4011 reg |= DMA_CFG_SMB_ENB; 4012 else 4013 reg |= DMA_CFG_SMB_DIS; 4014 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4015 DMA_CFG_RD_BURST_SHIFT; 4016 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4017 DMA_CFG_WR_BURST_SHIFT; 4018 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4019 DMA_CFG_RD_DELAY_CNT_MASK; 4020 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4021 DMA_CFG_WR_DELAY_CNT_MASK; 4022 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4023 switch (AR816X_REV(sc->alc_rev)) { 4024 case AR816X_REV_A0: 4025 case AR816X_REV_A1: 4026 reg |= DMA_CFG_RD_CHNL_SEL_1; 4027 break; 4028 case AR816X_REV_B0: 4029 /* FALLTHROUGH */ 4030 default: 4031 reg |= DMA_CFG_RD_CHNL_SEL_3; 4032 break; 4033 } 4034 } 4035 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4036 4037 /* 4038 * Configure Tx/Rx MACs. 4039 * - Auto-padding for short frames. 4040 * - Enable CRC generation. 4041 * Actual reconfiguration of MAC for resolved speed/duplex 4042 * is followed after detection of link establishment. 4043 * AR813x/AR815x always does checksum computation regardless 4044 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4045 * have bug in protocol field in Rx return structure so 4046 * these controllers can't handle fragmented frames. Disable 4047 * Rx checksum offloading until there is a newer controller 4048 * that has sane implementation. 4049 */ 4050 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4051 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4052 MAC_CFG_PREAMBLE_MASK); 4053 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4054 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4055 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4056 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 4057 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4058 } 4059 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4060 reg |= MAC_CFG_SPEED_10_100; 4061 else 4062 reg |= MAC_CFG_SPEED_1000; 4063 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4064 4065 /* Set up the receive filter. */ 4066 alc_rxfilter(sc); 4067 alc_rxvlan(sc); 4068 4069 /* Acknowledge all pending interrupts and clear it. */ 4070 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4071 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4072 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4073 4074 ifp->if_flags |= IFF_RUNNING; 4075 ifq_clr_oactive(&ifp->if_snd); 4076 4077 sc->alc_flags &= ~ALC_FLAG_LINK; 4078 /* Switch to the current media. */ 4079 /*mii_mediachg(mii);*/ 4080 alc_mediachange_locked(sc); 4081 4082 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4083 4084 } 4085 4086 static void 4087 alc_stop(struct alc_softc *sc) 4088 { 4089 struct ifnet *ifp = &sc->arpcom.ac_if; 4090 struct alc_txdesc *txd; 4091 struct alc_rxdesc *rxd; 4092 uint32_t reg; 4093 int i; 4094 4095 ASSERT_SERIALIZED(ifp->if_serializer); 4096 4097 /* 4098 * Mark the interface down and cancel the watchdog timer. 4099 */ 4100 ifp->if_flags &= ~IFF_RUNNING; 4101 ifq_clr_oactive(&ifp->if_snd); 4102 sc->alc_flags &= ~ALC_FLAG_LINK; 4103 callout_stop(&sc->alc_tick_ch); 4104 sc->alc_watchdog_timer = 0; 4105 alc_stats_update(sc); 4106 /* Disable interrupts. */ 4107 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4108 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4109 /* Disable DMA. */ 4110 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4111 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4112 reg |= DMA_CFG_SMB_DIS; 4113 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4114 DELAY(1000); 4115 /* Stop Rx/Tx MACs. */ 4116 alc_stop_mac(sc); 4117 /* Disable interrupts which might be touched in taskq handler. */ 4118 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4119 4120 /* Disable L0s/L1s */ 4121 alc_aspm(sc, 0, IFM_UNKNOWN); 4122 /* Reclaim Rx buffers that have been processed. */ 4123 if (sc->alc_cdata.alc_rxhead != NULL) 4124 m_freem(sc->alc_cdata.alc_rxhead); 4125 ALC_RXCHAIN_RESET(sc); 4126 /* 4127 * Free Tx/Rx mbufs still in the queues. 4128 */ 4129 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4130 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4131 if (rxd->rx_m != NULL) { 4132 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4133 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4134 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4135 rxd->rx_dmamap); 4136 m_freem(rxd->rx_m); 4137 rxd->rx_m = NULL; 4138 } 4139 } 4140 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4141 txd = &sc->alc_cdata.alc_txdesc[i]; 4142 if (txd->tx_m != NULL) { 4143 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4144 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4145 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4146 txd->tx_dmamap); 4147 m_freem(txd->tx_m); 4148 txd->tx_m = NULL; 4149 } 4150 } 4151 } 4152 4153 static void 4154 alc_stop_mac(struct alc_softc *sc) 4155 { 4156 uint32_t reg; 4157 int i; 4158 4159 alc_stop_queue(sc); 4160 /* Disable Rx/Tx MAC. */ 4161 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4162 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4163 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4164 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4165 } 4166 for (i = ALC_TIMEOUT; i > 0; i--) { 4167 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4168 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4169 break; 4170 DELAY(10); 4171 } 4172 if (i == 0) 4173 device_printf(sc->alc_dev, 4174 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4175 } 4176 4177 static void 4178 alc_start_queue(struct alc_softc *sc) 4179 { 4180 uint32_t qcfg[] = { 4181 0, 4182 RXQ_CFG_QUEUE0_ENB, 4183 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4184 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4185 RXQ_CFG_ENB 4186 }; 4187 uint32_t cfg; 4188 4189 /* Enable RxQ. */ 4190 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4191 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4192 cfg &= ~RXQ_CFG_ENB; 4193 cfg |= qcfg[1]; 4194 } else 4195 cfg |= RXQ_CFG_QUEUE0_ENB; 4196 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4197 /* Enable TxQ. */ 4198 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4199 cfg |= TXQ_CFG_ENB; 4200 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4201 } 4202 4203 static void 4204 alc_stop_queue(struct alc_softc *sc) 4205 { 4206 uint32_t reg; 4207 int i; 4208 4209 /* Disable RxQ. */ 4210 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4211 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4212 if ((reg & RXQ_CFG_ENB) != 0) { 4213 reg &= ~RXQ_CFG_ENB; 4214 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4215 } 4216 } else { 4217 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4218 reg &= ~RXQ_CFG_QUEUE0_ENB; 4219 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4220 } 4221 } 4222 /* Disable TxQ. */ 4223 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4224 if ((reg & TXQ_CFG_ENB) != 0) { 4225 reg &= ~TXQ_CFG_ENB; 4226 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4227 } 4228 DELAY(40); 4229 for (i = ALC_TIMEOUT; i > 0; i--) { 4230 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4231 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4232 break; 4233 DELAY(10); 4234 } 4235 if (i == 0) 4236 device_printf(sc->alc_dev, 4237 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4238 } 4239 4240 static void 4241 alc_init_tx_ring(struct alc_softc *sc) 4242 { 4243 struct alc_ring_data *rd; 4244 struct alc_txdesc *txd; 4245 int i; 4246 4247 sc->alc_cdata.alc_tx_prod = 0; 4248 sc->alc_cdata.alc_tx_cons = 0; 4249 sc->alc_cdata.alc_tx_cnt = 0; 4250 4251 rd = &sc->alc_rdata; 4252 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4253 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4254 txd = &sc->alc_cdata.alc_txdesc[i]; 4255 txd->tx_m = NULL; 4256 } 4257 4258 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4259 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4260 } 4261 4262 static int 4263 alc_init_rx_ring(struct alc_softc *sc) 4264 { 4265 struct alc_ring_data *rd; 4266 struct alc_rxdesc *rxd; 4267 int i; 4268 4269 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4270 rd = &sc->alc_rdata; 4271 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4272 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4273 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4274 rxd->rx_m = NULL; 4275 rxd->rx_desc = &rd->alc_rx_ring[i]; 4276 if (alc_newbuf(sc, rxd, TRUE) != 0) 4277 return (ENOBUFS); 4278 } 4279 4280 /* 4281 * Since controller does not update Rx descriptors, driver 4282 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4283 * is enough to ensure coherence. 4284 */ 4285 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4286 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4287 /* Let controller know availability of new Rx buffers. */ 4288 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4289 4290 return (0); 4291 } 4292 4293 static void 4294 alc_init_rr_ring(struct alc_softc *sc) 4295 { 4296 struct alc_ring_data *rd; 4297 4298 sc->alc_cdata.alc_rr_cons = 0; 4299 ALC_RXCHAIN_RESET(sc); 4300 4301 rd = &sc->alc_rdata; 4302 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4303 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4304 sc->alc_cdata.alc_rr_ring_map, 4305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4306 } 4307 4308 static void 4309 alc_init_cmb(struct alc_softc *sc) 4310 { 4311 struct alc_ring_data *rd; 4312 4313 rd = &sc->alc_rdata; 4314 bzero(rd->alc_cmb, ALC_CMB_SZ); 4315 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4316 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4317 } 4318 4319 static void 4320 alc_init_smb(struct alc_softc *sc) 4321 { 4322 struct alc_ring_data *rd; 4323 4324 rd = &sc->alc_rdata; 4325 bzero(rd->alc_smb, ALC_SMB_SZ); 4326 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4327 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4328 } 4329 4330 static void 4331 alc_rxvlan(struct alc_softc *sc) 4332 { 4333 struct ifnet *ifp; 4334 uint32_t reg; 4335 4336 ifp = sc->alc_ifp; 4337 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4338 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4339 reg |= MAC_CFG_VLAN_TAG_STRIP; 4340 else 4341 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4342 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4343 } 4344 4345 static void 4346 alc_rxfilter(struct alc_softc *sc) 4347 { 4348 struct ifnet *ifp; 4349 struct ifmultiaddr *ifma; 4350 uint32_t crc; 4351 uint32_t mchash[2]; 4352 uint32_t rxcfg; 4353 4354 ifp = sc->alc_ifp; 4355 4356 bzero(mchash, sizeof(mchash)); 4357 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4358 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4359 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4360 rxcfg |= MAC_CFG_BCAST; 4361 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4362 if ((ifp->if_flags & IFF_PROMISC) != 0) 4363 rxcfg |= MAC_CFG_PROMISC; 4364 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4365 rxcfg |= MAC_CFG_ALLMULTI; 4366 mchash[0] = 0xFFFFFFFF; 4367 mchash[1] = 0xFFFFFFFF; 4368 goto chipit; 4369 } 4370 4371 #if 0 4372 /* XXX */ 4373 if_maddr_rlock(ifp); 4374 #endif 4375 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4376 if (ifma->ifma_addr->sa_family != AF_LINK) 4377 continue; 4378 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4379 ifma->ifma_addr), ETHER_ADDR_LEN); 4380 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4381 } 4382 #if 0 4383 /* XXX */ 4384 if_maddr_runlock(ifp); 4385 #endif 4386 4387 chipit: 4388 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4389 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4390 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4391 } 4392 4393 static int 4394 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4395 { 4396 return (sysctl_int_range(oidp, arg1, arg2, req, 4397 ALC_PROC_MIN, ALC_PROC_MAX)); 4398 } 4399 4400 static int 4401 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4402 { 4403 4404 return (sysctl_int_range(oidp, arg1, arg2, req, 4405 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4406 } 4407