1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $ 28 * $DragonFly$ 29 */ 30 31 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/spinlock.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/ifq_var.h> 59 #include <net/vlan/if_vlan_var.h> 60 #include <net/vlan/if_vlan_ether.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include <bus/pci/pcireg.h> 71 #include <bus/pci/pcivar.h> 72 73 #include <machine/atomic.h> 74 /* 75 XXX 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 */ 79 80 #include "if_alcreg.h" 81 #include "if_alcvar.h" 82 83 /* "device miibus" required. See GENERIC if you get errors here. */ 84 #include "miibus_if.h" 85 #undef ALC_USE_CUSTOM_CSUM 86 87 #ifdef ALC_USE_CUSTOM_CSUM 88 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 89 #else 90 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 91 #endif 92 #ifndef IFCAP_VLAN_HWTSO 93 #define IFCAP_VLAN_HWTSO 0 94 #endif 95 96 MODULE_DEPEND(alc, pci, 1, 1, 1); 97 MODULE_DEPEND(alc, ether, 1, 1, 1); 98 MODULE_DEPEND(alc, miibus, 1, 1, 1); 99 100 /* Tunables. */ 101 static int msi_disable = 0; 102 static int msix_disable = 0; 103 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 104 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 105 106 /* 107 * Devices supported by this driver. 108 */ 109 110 static struct alc_ident alc_ident_table[] = { 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 112 "Atheros AR8131 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 114 "Atheros AR8132 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 116 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 118 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 120 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 122 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 123 { 0, 0, 0, NULL} 124 }; 125 126 static void alc_aspm(struct alc_softc *, int); 127 static int alc_attach(device_t); 128 static int alc_check_boundary(struct alc_softc *); 129 static int alc_detach(device_t); 130 static void alc_disable_l0s_l1(struct alc_softc *); 131 static int alc_dma_alloc(struct alc_softc *); 132 static void alc_dma_free(struct alc_softc *); 133 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 134 static int alc_encap(struct alc_softc *, struct mbuf **); 135 static struct alc_ident *alc_find_ident(device_t); 136 #ifndef __NO_STRICT_ALIGNMENT 137 static struct mbuf * 138 alc_fixup_rx(struct ifnet *, struct mbuf *); 139 #endif 140 static void alc_get_macaddr(struct alc_softc *); 141 static void alc_init(void *); 142 static void alc_init_cmb(struct alc_softc *); 143 static void alc_init_locked(struct alc_softc *); 144 static void alc_init_rr_ring(struct alc_softc *); 145 static int alc_init_rx_ring(struct alc_softc *); 146 static void alc_init_smb(struct alc_softc *); 147 static void alc_init_tx_ring(struct alc_softc *); 148 static void alc_int_task(void *, int); 149 static void alc_intr(void *); 150 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 151 static void alc_mac_config(struct alc_softc *); 152 static int alc_miibus_readreg(device_t, int, int); 153 static void alc_miibus_statchg(device_t); 154 static int alc_miibus_writereg(device_t, int, int, int); 155 static int alc_mediachange(struct ifnet *); 156 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 157 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 158 static void alc_phy_down(struct alc_softc *); 159 static void alc_phy_reset(struct alc_softc *); 160 static int alc_probe(device_t); 161 static void alc_reset(struct alc_softc *); 162 static int alc_resume(device_t); 163 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 164 static int alc_rxintr(struct alc_softc *, int); 165 static void alc_rxfilter(struct alc_softc *); 166 static void alc_rxvlan(struct alc_softc *); 167 #if 0 168 static void alc_setlinkspeed(struct alc_softc *); 169 /* XXX: WOL */ 170 static void alc_setwol(struct alc_softc *); 171 #endif 172 static int alc_shutdown(device_t); 173 static void alc_start(struct ifnet *); 174 static void alc_start_queue(struct alc_softc *); 175 static void alc_stats_clear(struct alc_softc *); 176 static void alc_stats_update(struct alc_softc *); 177 static void alc_stop(struct alc_softc *); 178 static void alc_stop_mac(struct alc_softc *); 179 static void alc_stop_queue(struct alc_softc *); 180 static int alc_suspend(device_t); 181 static void alc_sysctl_node(struct alc_softc *); 182 static void alc_tick(void *); 183 static void alc_tx_task(void *, int); 184 static void alc_txeof(struct alc_softc *); 185 static void alc_watchdog(struct alc_softc *); 186 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 187 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 188 189 static device_method_t alc_methods[] = { 190 /* Device interface. */ 191 DEVMETHOD(device_probe, alc_probe), 192 DEVMETHOD(device_attach, alc_attach), 193 DEVMETHOD(device_detach, alc_detach), 194 DEVMETHOD(device_shutdown, alc_shutdown), 195 DEVMETHOD(device_suspend, alc_suspend), 196 DEVMETHOD(device_resume, alc_resume), 197 198 /* MII interface. */ 199 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 200 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 201 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 202 203 { NULL, NULL } 204 }; 205 206 static driver_t alc_driver = { 207 "alc", 208 alc_methods, 209 sizeof(struct alc_softc) 210 }; 211 212 static devclass_t alc_devclass; 213 214 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 215 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 216 217 static struct resource_spec alc_res_spec_mem[] = { 218 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 219 { -1, 0, 0 } 220 }; 221 222 static struct resource_spec alc_irq_spec_legacy[] = { 223 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 224 { -1, 0, 0 } 225 }; 226 227 static struct resource_spec alc_irq_spec_msi[] = { 228 { SYS_RES_IRQ, 1, RF_ACTIVE }, 229 { -1, 0, 0 } 230 }; 231 232 static struct resource_spec alc_irq_spec_msix[] = { 233 { SYS_RES_IRQ, 1, RF_ACTIVE }, 234 { -1, 0, 0 } 235 }; 236 237 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 238 239 static int 240 alc_miibus_readreg(device_t dev, int phy, int reg) 241 { 242 struct alc_softc *sc; 243 uint32_t v; 244 int i; 245 246 sc = device_get_softc(dev); 247 248 if (phy != sc->alc_phyaddr) 249 return (0); 250 251 /* 252 * For AR8132 fast ethernet controller, do not report 1000baseT 253 * capability to mii(4). Even though AR8132 uses the same 254 * model/revision number of F1 gigabit PHY, the PHY has no 255 * ability to establish 1000baseT link. 256 */ 257 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 258 reg == MII_EXTSR) 259 return (0); 260 261 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 262 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 263 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 264 DELAY(5); 265 v = CSR_READ_4(sc, ALC_MDIO); 266 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 267 break; 268 } 269 270 if (i == 0) { 271 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 272 return (0); 273 } 274 275 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 276 } 277 278 static int 279 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 280 { 281 struct alc_softc *sc; 282 uint32_t v; 283 int i; 284 285 sc = device_get_softc(dev); 286 287 if (phy != sc->alc_phyaddr) 288 return (0); 289 290 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 291 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 292 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 293 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 294 DELAY(5); 295 v = CSR_READ_4(sc, ALC_MDIO); 296 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 297 break; 298 } 299 300 if (i == 0) 301 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 302 303 return (0); 304 } 305 306 static void 307 alc_miibus_statchg(device_t dev) 308 { 309 struct alc_softc *sc; 310 struct mii_data *mii; 311 struct ifnet *ifp; 312 uint32_t reg; 313 314 sc = device_get_softc(dev); 315 316 mii = device_get_softc(sc->alc_miibus); 317 ifp = sc->alc_ifp; 318 if (mii == NULL || ifp == NULL || 319 (ifp->if_flags & IFF_RUNNING) == 0) 320 return; 321 322 sc->alc_flags &= ~ALC_FLAG_LINK; 323 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 324 (IFM_ACTIVE | IFM_AVALID)) { 325 switch (IFM_SUBTYPE(mii->mii_media_active)) { 326 case IFM_10_T: 327 case IFM_100_TX: 328 sc->alc_flags |= ALC_FLAG_LINK; 329 break; 330 case IFM_1000_T: 331 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 332 sc->alc_flags |= ALC_FLAG_LINK; 333 break; 334 default: 335 break; 336 } 337 } 338 alc_stop_queue(sc); 339 /* Stop Rx/Tx MACs. */ 340 alc_stop_mac(sc); 341 342 /* Program MACs with resolved speed/duplex/flow-control. */ 343 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 344 alc_start_queue(sc); 345 alc_mac_config(sc); 346 /* Re-enable Tx/Rx MACs. */ 347 reg = CSR_READ_4(sc, ALC_MAC_CFG); 348 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 349 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 350 } 351 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 352 } 353 354 static void 355 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 356 { 357 struct alc_softc *sc; 358 struct mii_data *mii; 359 360 sc = ifp->if_softc; 361 ALC_LOCK(sc); 362 if ((ifp->if_flags & IFF_UP) == 0) { 363 ALC_UNLOCK(sc); 364 return; 365 } 366 mii = device_get_softc(sc->alc_miibus); 367 368 mii_pollstat(mii); 369 ALC_UNLOCK(sc); 370 ifmr->ifm_status = mii->mii_media_status; 371 ifmr->ifm_active = mii->mii_media_active; 372 } 373 374 static int 375 alc_mediachange(struct ifnet *ifp) 376 { 377 struct alc_softc *sc; 378 struct mii_data *mii; 379 struct mii_softc *miisc; 380 int error; 381 382 sc = ifp->if_softc; 383 ALC_LOCK(sc); 384 mii = device_get_softc(sc->alc_miibus); 385 if (mii->mii_instance != 0) { 386 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 387 mii_phy_reset(miisc); 388 } 389 error = mii_mediachg(mii); 390 ALC_UNLOCK(sc); 391 392 return (error); 393 } 394 395 static struct alc_ident * 396 alc_find_ident(device_t dev) 397 { 398 struct alc_ident *ident; 399 uint16_t vendor, devid; 400 401 vendor = pci_get_vendor(dev); 402 devid = pci_get_device(dev); 403 for (ident = alc_ident_table; ident->name != NULL; ident++) { 404 if (vendor == ident->vendorid && devid == ident->deviceid) 405 return (ident); 406 } 407 return (NULL); 408 } 409 410 static int 411 alc_probe(device_t dev) 412 { 413 struct alc_ident *ident; 414 415 ident = alc_find_ident(dev); 416 if (ident != NULL) { 417 device_set_desc(dev, ident->name); 418 return (BUS_PROBE_DEFAULT); 419 } 420 return (ENXIO); 421 } 422 423 static void 424 alc_get_macaddr(struct alc_softc *sc) 425 { 426 uint32_t ea[2], opt; 427 uint16_t val; 428 int eeprom, i; 429 430 eeprom = 0; 431 opt = CSR_READ_4(sc, ALC_OPT_CFG); 432 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 433 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 434 /* 435 * EEPROM found, let TWSI reload EEPROM configuration. 436 * This will set ethernet address of controller. 437 */ 438 eeprom++; 439 switch (sc->alc_ident->deviceid) { 440 case DEVICEID_ATHEROS_AR8131: 441 case DEVICEID_ATHEROS_AR8132: 442 if ((opt & OPT_CFG_CLK_ENB) == 0) { 443 opt |= OPT_CFG_CLK_ENB; 444 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 445 CSR_READ_4(sc, ALC_OPT_CFG); 446 DELAY(1000); 447 } 448 break; 449 case DEVICEID_ATHEROS_AR8151: 450 case DEVICEID_ATHEROS_AR8151_V2: 451 case DEVICEID_ATHEROS_AR8152_B: 452 case DEVICEID_ATHEROS_AR8152_B2: 453 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 454 ALC_MII_DBG_ADDR, 0x00); 455 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 456 ALC_MII_DBG_DATA); 457 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 458 ALC_MII_DBG_DATA, val & 0xFF7F); 459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_ADDR, 0x3B); 461 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_DATA); 463 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA, val | 0x0008); 465 DELAY(20); 466 break; 467 } 468 469 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 470 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 471 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 472 CSR_READ_4(sc, ALC_WOL_CFG); 473 474 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 475 TWSI_CFG_SW_LD_START); 476 477 for (i = 100; i > 0; i--) { 478 DELAY(1000); 479 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 480 TWSI_CFG_SW_LD_START) == 0) 481 break; 482 } 483 if (i == 0) 484 device_printf(sc->alc_dev, 485 "reloading EEPROM timeout!\n"); 486 } else { 487 if (bootverbose) 488 device_printf(sc->alc_dev, "EEPROM not found!\n"); 489 } 490 491 if (eeprom != 0) { 492 switch (sc->alc_ident->deviceid) { 493 case DEVICEID_ATHEROS_AR8131: 494 case DEVICEID_ATHEROS_AR8132: 495 if ((opt & OPT_CFG_CLK_ENB) != 0) { 496 opt &= ~OPT_CFG_CLK_ENB; 497 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 498 CSR_READ_4(sc, ALC_OPT_CFG); 499 DELAY(1000); 500 } 501 break; 502 case DEVICEID_ATHEROS_AR8151: 503 case DEVICEID_ATHEROS_AR8151_V2: 504 case DEVICEID_ATHEROS_AR8152_B: 505 case DEVICEID_ATHEROS_AR8152_B2: 506 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 507 ALC_MII_DBG_ADDR, 0x00); 508 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 509 ALC_MII_DBG_DATA); 510 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 511 ALC_MII_DBG_DATA, val | 0x0080); 512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_ADDR, 0x3B); 514 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_DATA); 516 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA, val & 0xFFF7); 518 DELAY(20); 519 break; 520 } 521 } 522 523 ea[0] = CSR_READ_4(sc, ALC_PAR0); 524 ea[1] = CSR_READ_4(sc, ALC_PAR1); 525 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 526 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 527 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 528 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 529 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 530 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 531 } 532 533 static void 534 alc_disable_l0s_l1(struct alc_softc *sc) 535 { 536 uint32_t pmcfg; 537 538 /* Another magic from vendor. */ 539 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 540 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 541 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 542 PM_CFG_SERDES_PD_EX_L1); 543 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 544 PM_CFG_SERDES_L1_ENB; 545 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 546 } 547 548 static void 549 alc_phy_reset(struct alc_softc *sc) 550 { 551 uint16_t data; 552 553 /* Reset magic from Linux. */ 554 CSR_WRITE_2(sc, ALC_GPHY_CFG, 555 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 556 CSR_READ_2(sc, ALC_GPHY_CFG); 557 DELAY(10 * 1000); 558 559 CSR_WRITE_2(sc, ALC_GPHY_CFG, 560 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 561 GPHY_CFG_SEL_ANA_RESET); 562 CSR_READ_2(sc, ALC_GPHY_CFG); 563 DELAY(10 * 1000); 564 565 /* DSP fixup, Vendor magic. */ 566 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 567 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 568 ALC_MII_DBG_ADDR, 0x000A); 569 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 570 ALC_MII_DBG_DATA); 571 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 572 ALC_MII_DBG_DATA, data & 0xDFFF); 573 } 574 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 575 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 576 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 578 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 579 ALC_MII_DBG_ADDR, 0x003B); 580 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 581 ALC_MII_DBG_DATA); 582 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 583 ALC_MII_DBG_DATA, data & 0xFFF7); 584 DELAY(20 * 1000); 585 } 586 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 587 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 588 ALC_MII_DBG_ADDR, 0x0029); 589 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 590 ALC_MII_DBG_DATA, 0x929D); 591 } 592 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 593 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 594 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 595 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 596 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 597 ALC_MII_DBG_ADDR, 0x0029); 598 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 599 ALC_MII_DBG_DATA, 0xB6DD); 600 } 601 602 /* Load DSP codes, vendor magic. */ 603 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 604 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 605 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 606 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 607 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 608 ALC_MII_DBG_DATA, data); 609 610 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 611 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 612 ANA_SERDES_EN_LCKDT; 613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_DATA, data); 617 618 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 619 ANA_LONG_CABLE_TH_100_MASK) | 620 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 621 ANA_SHORT_CABLE_TH_100_SHIFT) | 622 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 623 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 624 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 625 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_DATA, data); 627 628 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 629 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 630 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 631 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 632 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 633 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 634 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 635 ALC_MII_DBG_DATA, data); 636 637 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 638 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 639 ANA_OEN_125M; 640 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 641 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 642 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 643 ALC_MII_DBG_DATA, data); 644 DELAY(1000); 645 } 646 647 static void 648 alc_phy_down(struct alc_softc *sc) 649 { 650 switch (sc->alc_ident->deviceid) { 651 case DEVICEID_ATHEROS_AR8151: 652 case DEVICEID_ATHEROS_AR8151_V2: 653 /* 654 * GPHY power down caused more problems on AR8151 v2.0. 655 * When driver is reloaded after GPHY power down, 656 * accesses to PHY/MAC registers hung the system. Only 657 * cold boot recovered from it. I'm not sure whether 658 * AR8151 v1.0 also requires this one though. I don't 659 * have AR8151 v1.0 controller in hand. 660 * The only option left is to isolate the PHY and 661 * initiates power down the PHY which in turn saves 662 * more power when driver is unloaded. 663 */ 664 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 665 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 666 break; 667 default: 668 /* Force PHY down. */ 669 CSR_WRITE_2(sc, ALC_GPHY_CFG, 670 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 671 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 672 GPHY_CFG_PWDOWN_HW); 673 DELAY(1000); 674 break; 675 } 676 677 } 678 679 static void 680 alc_aspm(struct alc_softc *sc, int media) 681 { 682 uint32_t pmcfg; 683 uint16_t linkcfg; 684 685 ALC_LOCK_ASSERT(sc); 686 687 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 688 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 689 (ALC_FLAG_APS | ALC_FLAG_PCIE)) { 690 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 691 PCIR_EXPRESS_LINK_CTL); 692 } else { 693 linkcfg = 0; 694 } 695 696 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 697 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 698 pmcfg |= PM_CFG_MAC_ASPM_CHK; 699 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 700 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 701 702 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 703 /* Disable extended sync except AR8152 B v1.0 */ 704 linkcfg &= ~0x80; 705 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 706 sc->alc_rev == ATHEROS_AR8152_B_V10) 707 linkcfg |= 0x80; 708 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 709 linkcfg); 710 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 711 PM_CFG_HOTRST); 712 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 713 PM_CFG_L1_ENTRY_TIMER_SHIFT); 714 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 715 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 716 PM_CFG_PM_REQ_TIMER_SHIFT); 717 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 718 } 719 720 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 721 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 722 pmcfg |= PM_CFG_ASPM_L0S_ENB; 723 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 724 pmcfg |= PM_CFG_ASPM_L1_ENB; 725 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 726 if (sc->alc_ident->deviceid == 727 DEVICEID_ATHEROS_AR8152_B) { 728 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 729 } 730 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 731 PM_CFG_SERDES_PLL_L1_ENB | 732 PM_CFG_SERDES_BUDS_RX_L1_ENB); 733 pmcfg |= PM_CFG_CLK_SWH_L1; 734 if (media == IFM_100_TX || media == IFM_1000_T) { 735 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 736 switch (sc->alc_ident->deviceid) { 737 case DEVICEID_ATHEROS_AR8152_B: 738 pmcfg |= (7 << 739 PM_CFG_L1_ENTRY_TIMER_SHIFT); 740 break; 741 case DEVICEID_ATHEROS_AR8152_B2: 742 case DEVICEID_ATHEROS_AR8151_V2: 743 pmcfg |= (4 << 744 PM_CFG_L1_ENTRY_TIMER_SHIFT); 745 break; 746 default: 747 pmcfg |= (15 << 748 PM_CFG_L1_ENTRY_TIMER_SHIFT); 749 break; 750 } 751 } 752 } else { 753 pmcfg |= PM_CFG_SERDES_L1_ENB | 754 PM_CFG_SERDES_PLL_L1_ENB | 755 PM_CFG_SERDES_BUDS_RX_L1_ENB; 756 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 757 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 758 } 759 } else { 760 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 761 PM_CFG_SERDES_PLL_L1_ENB); 762 pmcfg |= PM_CFG_CLK_SWH_L1; 763 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 764 pmcfg |= PM_CFG_ASPM_L1_ENB; 765 } 766 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 767 } 768 769 static int 770 alc_attach(device_t dev) 771 { 772 struct alc_softc *sc; 773 struct ifnet *ifp; 774 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 775 uint16_t burst; 776 int base, error, i, msic, msixc, state; 777 uint32_t cap, ctl, val; 778 779 error = 0; 780 sc = device_get_softc(dev); 781 sc->alc_dev = dev; 782 783 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE); 784 callout_init_mp(&sc->alc_tick_ch); 785 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 786 sc->alc_ident = alc_find_ident(dev); 787 788 /* Map the device. */ 789 pci_enable_busmaster(dev); 790 sc->alc_res_spec = alc_res_spec_mem; 791 sc->alc_irq_spec = alc_irq_spec_legacy; 792 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 793 if (error != 0) { 794 device_printf(dev, "cannot allocate memory resources.\n"); 795 goto fail; 796 } 797 798 /* Set PHY address. */ 799 sc->alc_phyaddr = ALC_PHY_ADDR; 800 801 /* Initialize DMA parameters. */ 802 sc->alc_dma_rd_burst = 0; 803 sc->alc_dma_wr_burst = 0; 804 sc->alc_rcb = DMA_CFG_RCB_64; 805 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 806 sc->alc_flags |= ALC_FLAG_PCIE; 807 sc->alc_expcap = base; 808 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 809 sc->alc_dma_rd_burst = 810 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 811 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 812 if (bootverbose) { 813 device_printf(dev, "Read request size : %u bytes.\n", 814 alc_dma_burst[sc->alc_dma_rd_burst]); 815 device_printf(dev, "TLP payload size : %u bytes.\n", 816 alc_dma_burst[sc->alc_dma_wr_burst]); 817 } 818 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 819 sc->alc_dma_rd_burst = 3; 820 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 821 sc->alc_dma_wr_burst = 3; 822 /* Clear data link and flow-control protocol error. */ 823 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 824 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 825 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 826 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 827 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 828 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 829 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 830 PCIE_PHYMISC_FORCE_RCV_DET); 831 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 832 sc->alc_rev == ATHEROS_AR8152_B_V10) { 833 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 834 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 835 PCIE_PHYMISC2_SERDES_TH_MASK); 836 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 837 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 838 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 839 } 840 841 /* Disable ASPM L0S and L1. */ 842 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 843 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 844 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 845 if ((ctl & 0x08) != 0) 846 sc->alc_rcb = DMA_CFG_RCB_128; 847 if (bootverbose) 848 device_printf(dev, "RCB %u bytes\n", 849 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 850 state = ctl & 0x03; 851 if (state & 0x01) 852 sc->alc_flags |= ALC_FLAG_L0S; 853 if (state & 0x02) 854 sc->alc_flags |= ALC_FLAG_L1S; 855 if (bootverbose) 856 device_printf(sc->alc_dev, "ASPM %s %s\n", 857 aspm_state[state], 858 state == 0 ? "disabled" : "enabled"); 859 alc_disable_l0s_l1(sc); 860 } else { 861 if (bootverbose) 862 device_printf(sc->alc_dev, "no ASPM support\n"); 863 } 864 } 865 866 /* Reset PHY. */ 867 alc_phy_reset(sc); 868 869 /* Reset the ethernet controller. */ 870 alc_reset(sc); 871 872 /* 873 * One odd thing is AR8132 uses the same PHY hardware(F1 874 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 875 * the PHY supports 1000Mbps but that's not true. The PHY 876 * used in AR8132 can't establish gigabit link even if it 877 * shows the same PHY model/revision number of AR8131. 878 */ 879 switch (sc->alc_ident->deviceid) { 880 case DEVICEID_ATHEROS_AR8152_B: 881 case DEVICEID_ATHEROS_AR8152_B2: 882 sc->alc_flags |= ALC_FLAG_APS; 883 /* FALLTHROUGH */ 884 case DEVICEID_ATHEROS_AR8132: 885 sc->alc_flags |= ALC_FLAG_FASTETHER; 886 break; 887 case DEVICEID_ATHEROS_AR8151: 888 case DEVICEID_ATHEROS_AR8151_V2: 889 sc->alc_flags |= ALC_FLAG_APS; 890 /* FALLTHROUGH */ 891 default: 892 break; 893 } 894 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 895 896 /* 897 * It seems that AR813x/AR815x has silicon bug for SMB. In 898 * addition, Atheros said that enabling SMB wouldn't improve 899 * performance. However I think it's bad to access lots of 900 * registers to extract MAC statistics. 901 */ 902 sc->alc_flags |= ALC_FLAG_SMB_BUG; 903 904 /* 905 * Don't use Tx CMB. It is known to have silicon bug. 906 */ 907 sc->alc_flags |= ALC_FLAG_CMB_BUG; 908 sc->alc_rev = pci_get_revid(dev); 909 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 910 MASTER_CHIP_REV_SHIFT; 911 if (bootverbose) { 912 device_printf(dev, "PCI device revision : 0x%04x\n", 913 sc->alc_rev); 914 device_printf(dev, "Chip id/revision : 0x%04x\n", 915 sc->alc_chip_rev); 916 } 917 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 918 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 919 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 920 921 /* Allocate IRQ resources. */ 922 msixc = pci_msix_count(dev); 923 msic = pci_msi_count(dev); 924 if (bootverbose) { 925 device_printf(dev, "MSIX count : %d\n", msixc); 926 device_printf(dev, "MSI count : %d\n", msic); 927 } 928 /* Prefer MSIX over MSI. */ 929 if (msix_disable == 0 || msi_disable == 0) { 930 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 931 pci_alloc_msix(dev, &msixc) == 0) { 932 if (msic == ALC_MSIX_MESSAGES) { 933 device_printf(dev, 934 "Using %d MSIX message(s).\n", msixc); 935 sc->alc_flags |= ALC_FLAG_MSIX; 936 sc->alc_irq_spec = alc_irq_spec_msix; 937 } else 938 pci_release_msi(dev); 939 } 940 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 941 msic == ALC_MSI_MESSAGES && 942 pci_alloc_msi(dev, &msic) == 0) { 943 if (msic == ALC_MSI_MESSAGES) { 944 device_printf(dev, 945 "Using %d MSI message(s).\n", msic); 946 sc->alc_flags |= ALC_FLAG_MSI; 947 sc->alc_irq_spec = alc_irq_spec_msi; 948 } else 949 pci_release_msi(dev); 950 } 951 } 952 953 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 954 if (error != 0) { 955 device_printf(dev, "cannot allocate IRQ resources.\n"); 956 goto fail; 957 } 958 959 /* Create device sysctl node. */ 960 alc_sysctl_node(sc); 961 962 if ((error = alc_dma_alloc(sc) != 0)) 963 goto fail; 964 965 /* Load station address. */ 966 alc_get_macaddr(sc); 967 968 ifp = sc->alc_ifp = &sc->arpcom.ac_if; 969 ifp->if_softc = sc; 970 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 971 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 972 ifp->if_ioctl = alc_ioctl; 973 ifp->if_start = alc_start; 974 ifp->if_init = alc_init; 975 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1; 976 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 977 ifq_set_ready(&ifp->if_snd); 978 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 979 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 980 #if 0 981 /* XXX: WOL */ 982 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 983 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 984 sc->alc_flags |= ALC_FLAG_PM; 985 sc->alc_pmcap = base; 986 } 987 #endif 988 ifp->if_capenable = ifp->if_capabilities; 989 990 /* Set up MII bus. */ 991 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 992 alc_mediastatus)) != 0) { 993 device_printf(dev, "no PHY found!\n"); 994 goto fail; 995 } 996 997 ether_ifattach(ifp, sc->alc_eaddr, NULL); 998 999 /* VLAN capability setup. */ 1000 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1001 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1002 ifp->if_capenable = ifp->if_capabilities; 1003 /* 1004 * XXX 1005 * It seems enabling Tx checksum offloading makes more trouble. 1006 * Sometimes the controller does not receive any frames when 1007 * Tx checksum offloading is enabled. I'm not sure whether this 1008 * is a bug in Tx checksum offloading logic or I got broken 1009 * sample boards. To safety, don't enable Tx checksum offloading 1010 * by default but give chance to users to toggle it if they know 1011 * their controllers work without problems. 1012 */ 1013 ifp->if_capenable &= ~IFCAP_TXCSUM; 1014 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1015 1016 /* Tell the upper layer(s) we support long frames. */ 1017 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1018 1019 /* Create local taskq. */ 1020 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1021 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK, 1022 taskqueue_thread_enqueue, &sc->alc_tq); 1023 if (sc->alc_tq == NULL) { 1024 device_printf(dev, "could not create taskqueue.\n"); 1025 ether_ifdetach(ifp); 1026 error = ENXIO; 1027 goto fail; 1028 } 1029 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 1030 device_get_nameunit(sc->alc_dev)); 1031 1032 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1033 msic = ALC_MSIX_MESSAGES; 1034 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1035 msic = ALC_MSI_MESSAGES; 1036 else 1037 msic = 1; 1038 for (i = 0; i < msic; i++) { 1039 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE, 1040 alc_intr, sc, 1041 &sc->alc_intrhand[i], NULL); 1042 if (error != 0) 1043 break; 1044 } 1045 if (error != 0) { 1046 device_printf(dev, "could not set up interrupt handler.\n"); 1047 taskqueue_free(sc->alc_tq); 1048 sc->alc_tq = NULL; 1049 ether_ifdetach(ifp); 1050 goto fail; 1051 } 1052 1053 fail: 1054 if (error != 0) 1055 alc_detach(dev); 1056 1057 return (error); 1058 } 1059 1060 static int 1061 alc_detach(device_t dev) 1062 { 1063 struct alc_softc *sc; 1064 struct ifnet *ifp; 1065 int i, msic; 1066 1067 sc = device_get_softc(dev); 1068 1069 ifp = sc->alc_ifp; 1070 if (device_is_attached(dev)) { 1071 ALC_LOCK(sc); 1072 sc->alc_flags |= ALC_FLAG_DETACH; 1073 alc_stop(sc); 1074 ALC_UNLOCK(sc); 1075 #if 0 1076 /* XXX */ 1077 callout_drain(&sc->alc_tick_ch); 1078 #endif 1079 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1080 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1081 ether_ifdetach(ifp); 1082 } 1083 1084 if (sc->alc_tq != NULL) { 1085 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1086 taskqueue_free(sc->alc_tq); 1087 sc->alc_tq = NULL; 1088 } 1089 1090 if (sc->alc_miibus != NULL) { 1091 device_delete_child(dev, sc->alc_miibus); 1092 sc->alc_miibus = NULL; 1093 } 1094 bus_generic_detach(dev); 1095 alc_dma_free(sc); 1096 1097 if (ifp != NULL) { 1098 // XXX? if_free(ifp); 1099 sc->alc_ifp = NULL; 1100 } 1101 1102 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1103 msic = ALC_MSIX_MESSAGES; 1104 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1105 msic = ALC_MSI_MESSAGES; 1106 else 1107 msic = 1; 1108 for (i = 0; i < msic; i++) { 1109 if (sc->alc_intrhand[i] != NULL) { 1110 bus_teardown_intr(dev, sc->alc_irq[i], 1111 sc->alc_intrhand[i]); 1112 sc->alc_intrhand[i] = NULL; 1113 } 1114 } 1115 if (sc->alc_res[0] != NULL) 1116 alc_phy_down(sc); 1117 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1118 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1119 pci_release_msi(dev); 1120 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1121 lockuninit(&sc->alc_lock); 1122 1123 return (0); 1124 } 1125 1126 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1127 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1128 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1129 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1130 1131 static void 1132 alc_sysctl_node(struct alc_softc *sc) 1133 { 1134 struct sysctl_ctx_list *ctx; 1135 struct sysctl_oid *tree; 1136 struct sysctl_oid_list *child, *parent; 1137 struct alc_hw_stats *stats; 1138 int error; 1139 1140 stats = &sc->alc_stats; 1141 ctx = &sc->alc_sysctl_ctx; 1142 sysctl_ctx_init(ctx); 1143 1144 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 1145 OID_AUTO, 1146 device_get_nameunit(sc->alc_dev), 1147 CTLFLAG_RD, 0, ""); 1148 if (tree == NULL) { 1149 device_printf(sc->alc_dev, "can't add sysctl node\n"); 1150 return; 1151 } 1152 child = SYSCTL_CHILDREN(tree); 1153 1154 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1155 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1156 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1157 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1158 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1159 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1160 /* Pull in device tunables. */ 1161 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1162 error = resource_int_value(device_get_name(sc->alc_dev), 1163 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1164 if (error == 0) { 1165 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1166 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1167 device_printf(sc->alc_dev, "int_rx_mod value out of " 1168 "range; using default: %d\n", 1169 ALC_IM_RX_TIMER_DEFAULT); 1170 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1171 } 1172 } 1173 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1174 error = resource_int_value(device_get_name(sc->alc_dev), 1175 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1176 if (error == 0) { 1177 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1178 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1179 device_printf(sc->alc_dev, "int_tx_mod value out of " 1180 "range; using default: %d\n", 1181 ALC_IM_TX_TIMER_DEFAULT); 1182 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1183 } 1184 } 1185 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1186 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1187 sysctl_hw_alc_proc_limit, "I", 1188 "max number of Rx events to process"); 1189 /* Pull in device tunables. */ 1190 sc->alc_process_limit = ALC_PROC_DEFAULT; 1191 error = resource_int_value(device_get_name(sc->alc_dev), 1192 device_get_unit(sc->alc_dev), "process_limit", 1193 &sc->alc_process_limit); 1194 if (error == 0) { 1195 if (sc->alc_process_limit < ALC_PROC_MIN || 1196 sc->alc_process_limit > ALC_PROC_MAX) { 1197 device_printf(sc->alc_dev, 1198 "process_limit value out of range; " 1199 "using default: %d\n", ALC_PROC_DEFAULT); 1200 sc->alc_process_limit = ALC_PROC_DEFAULT; 1201 } 1202 } 1203 1204 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1205 NULL, "ALC statistics"); 1206 parent = SYSCTL_CHILDREN(tree); 1207 1208 /* Rx statistics. */ 1209 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1210 NULL, "Rx MAC statistics"); 1211 child = SYSCTL_CHILDREN(tree); 1212 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1213 &stats->rx_frames, "Good frames"); 1214 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1215 &stats->rx_bcast_frames, "Good broadcast frames"); 1216 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1217 &stats->rx_mcast_frames, "Good multicast frames"); 1218 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1219 &stats->rx_pause_frames, "Pause control frames"); 1220 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1221 &stats->rx_control_frames, "Control frames"); 1222 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1223 &stats->rx_crcerrs, "CRC errors"); 1224 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1225 &stats->rx_lenerrs, "Frames with length mismatched"); 1226 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1227 &stats->rx_bytes, "Good octets"); 1228 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1229 &stats->rx_bcast_bytes, "Good broadcast octets"); 1230 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1231 &stats->rx_mcast_bytes, "Good multicast octets"); 1232 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1233 &stats->rx_runts, "Too short frames"); 1234 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1235 &stats->rx_fragments, "Fragmented frames"); 1236 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1237 &stats->rx_pkts_64, "64 bytes frames"); 1238 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1239 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1240 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1241 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1242 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1243 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1244 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1245 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1246 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1247 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1248 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1249 &stats->rx_pkts_1519_max, "1519 to max frames"); 1250 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1251 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1252 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1253 &stats->rx_fifo_oflows, "FIFO overflows"); 1254 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1255 &stats->rx_rrs_errs, "Return status write-back errors"); 1256 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1257 &stats->rx_alignerrs, "Alignment errors"); 1258 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1259 &stats->rx_pkts_filtered, 1260 "Frames dropped due to address filtering"); 1261 1262 /* Tx statistics. */ 1263 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1264 NULL, "Tx MAC statistics"); 1265 child = SYSCTL_CHILDREN(tree); 1266 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1267 &stats->tx_frames, "Good frames"); 1268 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1269 &stats->tx_bcast_frames, "Good broadcast frames"); 1270 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1271 &stats->tx_mcast_frames, "Good multicast frames"); 1272 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1273 &stats->tx_pause_frames, "Pause control frames"); 1274 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1275 &stats->tx_control_frames, "Control frames"); 1276 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1277 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1278 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1279 &stats->tx_excess_defer, "Frames with derferrals"); 1280 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1281 &stats->tx_bytes, "Good octets"); 1282 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1283 &stats->tx_bcast_bytes, "Good broadcast octets"); 1284 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1285 &stats->tx_mcast_bytes, "Good multicast octets"); 1286 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1287 &stats->tx_pkts_64, "64 bytes frames"); 1288 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1289 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1290 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1291 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1292 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1293 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1294 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1295 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1296 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1297 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1298 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1299 &stats->tx_pkts_1519_max, "1519 to max frames"); 1300 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1301 &stats->tx_single_colls, "Single collisions"); 1302 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1303 &stats->tx_multi_colls, "Multiple collisions"); 1304 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1305 &stats->tx_late_colls, "Late collisions"); 1306 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1307 &stats->tx_excess_colls, "Excessive collisions"); 1308 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1309 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1310 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1311 &stats->tx_underrun, "FIFO underruns"); 1312 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1313 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1314 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1315 &stats->tx_lenerrs, "Frames with length mismatched"); 1316 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1317 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1318 } 1319 1320 #undef ALC_SYSCTL_STAT_ADD32 1321 #undef ALC_SYSCTL_STAT_ADD64 1322 1323 struct alc_dmamap_arg { 1324 bus_addr_t alc_busaddr; 1325 }; 1326 1327 static void 1328 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1329 { 1330 struct alc_dmamap_arg *ctx; 1331 1332 if (error != 0) 1333 return; 1334 1335 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1336 1337 ctx = (struct alc_dmamap_arg *)arg; 1338 ctx->alc_busaddr = segs[0].ds_addr; 1339 } 1340 1341 /* 1342 * Normal and high Tx descriptors shares single Tx high address. 1343 * Four Rx descriptor/return rings and CMB shares the same Rx 1344 * high address. 1345 */ 1346 static int 1347 alc_check_boundary(struct alc_softc *sc) 1348 { 1349 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1350 1351 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1352 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1353 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1354 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1355 1356 /* 4GB boundary crossing is not allowed. */ 1357 if ((ALC_ADDR_HI(rx_ring_end) != 1358 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1359 (ALC_ADDR_HI(rr_ring_end) != 1360 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1361 (ALC_ADDR_HI(cmb_end) != 1362 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1363 (ALC_ADDR_HI(tx_ring_end) != 1364 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1365 return (EFBIG); 1366 /* 1367 * Make sure Rx return descriptor/Rx descriptor/CMB use 1368 * the same high address. 1369 */ 1370 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1371 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1372 return (EFBIG); 1373 1374 return (0); 1375 } 1376 1377 static int 1378 alc_dma_alloc(struct alc_softc *sc) 1379 { 1380 struct alc_txdesc *txd; 1381 struct alc_rxdesc *rxd; 1382 bus_addr_t lowaddr; 1383 struct alc_dmamap_arg ctx; 1384 int error, i; 1385 1386 lowaddr = BUS_SPACE_MAXADDR; 1387 again: 1388 /* Create parent DMA tag. */ 1389 error = bus_dma_tag_create( 1390 sc->alc_cdata.alc_parent_tag, /* parent */ 1391 1, 0, /* alignment, boundary */ 1392 lowaddr, /* lowaddr */ 1393 BUS_SPACE_MAXADDR, /* highaddr */ 1394 NULL, NULL, /* filter, filterarg */ 1395 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1396 0, /* nsegments */ 1397 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1398 0, /* flags */ 1399 &sc->alc_cdata.alc_parent_tag); 1400 if (error != 0) { 1401 device_printf(sc->alc_dev, 1402 "could not create parent DMA tag.\n"); 1403 goto fail; 1404 } 1405 1406 /* Create DMA tag for Tx descriptor ring. */ 1407 error = bus_dma_tag_create( 1408 sc->alc_cdata.alc_parent_tag, /* parent */ 1409 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1410 BUS_SPACE_MAXADDR, /* lowaddr */ 1411 BUS_SPACE_MAXADDR, /* highaddr */ 1412 NULL, NULL, /* filter, filterarg */ 1413 ALC_TX_RING_SZ, /* maxsize */ 1414 1, /* nsegments */ 1415 ALC_TX_RING_SZ, /* maxsegsize */ 1416 0, /* flags */ 1417 &sc->alc_cdata.alc_tx_ring_tag); 1418 if (error != 0) { 1419 device_printf(sc->alc_dev, 1420 "could not create Tx ring DMA tag.\n"); 1421 goto fail; 1422 } 1423 1424 /* Create DMA tag for Rx free descriptor ring. */ 1425 error = bus_dma_tag_create( 1426 sc->alc_cdata.alc_parent_tag, /* parent */ 1427 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1428 BUS_SPACE_MAXADDR, /* lowaddr */ 1429 BUS_SPACE_MAXADDR, /* highaddr */ 1430 NULL, NULL, /* filter, filterarg */ 1431 ALC_RX_RING_SZ, /* maxsize */ 1432 1, /* nsegments */ 1433 ALC_RX_RING_SZ, /* maxsegsize */ 1434 0, /* flags */ 1435 &sc->alc_cdata.alc_rx_ring_tag); 1436 if (error != 0) { 1437 device_printf(sc->alc_dev, 1438 "could not create Rx ring DMA tag.\n"); 1439 goto fail; 1440 } 1441 /* Create DMA tag for Rx return descriptor ring. */ 1442 error = bus_dma_tag_create( 1443 sc->alc_cdata.alc_parent_tag, /* parent */ 1444 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1445 BUS_SPACE_MAXADDR, /* lowaddr */ 1446 BUS_SPACE_MAXADDR, /* highaddr */ 1447 NULL, NULL, /* filter, filterarg */ 1448 ALC_RR_RING_SZ, /* maxsize */ 1449 1, /* nsegments */ 1450 ALC_RR_RING_SZ, /* maxsegsize */ 1451 0, /* flags */ 1452 &sc->alc_cdata.alc_rr_ring_tag); 1453 if (error != 0) { 1454 device_printf(sc->alc_dev, 1455 "could not create Rx return ring DMA tag.\n"); 1456 goto fail; 1457 } 1458 1459 /* Create DMA tag for coalescing message block. */ 1460 error = bus_dma_tag_create( 1461 sc->alc_cdata.alc_parent_tag, /* parent */ 1462 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1463 BUS_SPACE_MAXADDR, /* lowaddr */ 1464 BUS_SPACE_MAXADDR, /* highaddr */ 1465 NULL, NULL, /* filter, filterarg */ 1466 ALC_CMB_SZ, /* maxsize */ 1467 1, /* nsegments */ 1468 ALC_CMB_SZ, /* maxsegsize */ 1469 0, /* flags */ 1470 &sc->alc_cdata.alc_cmb_tag); 1471 if (error != 0) { 1472 device_printf(sc->alc_dev, 1473 "could not create CMB DMA tag.\n"); 1474 goto fail; 1475 } 1476 /* Create DMA tag for status message block. */ 1477 error = bus_dma_tag_create( 1478 sc->alc_cdata.alc_parent_tag, /* parent */ 1479 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1480 BUS_SPACE_MAXADDR, /* lowaddr */ 1481 BUS_SPACE_MAXADDR, /* highaddr */ 1482 NULL, NULL, /* filter, filterarg */ 1483 ALC_SMB_SZ, /* maxsize */ 1484 1, /* nsegments */ 1485 ALC_SMB_SZ, /* maxsegsize */ 1486 0, /* flags */ 1487 &sc->alc_cdata.alc_smb_tag); 1488 if (error != 0) { 1489 device_printf(sc->alc_dev, 1490 "could not create SMB DMA tag.\n"); 1491 goto fail; 1492 } 1493 1494 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1495 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1496 (void **)&sc->alc_rdata.alc_tx_ring, 1497 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1498 &sc->alc_cdata.alc_tx_ring_map); 1499 if (error != 0) { 1500 device_printf(sc->alc_dev, 1501 "could not allocate DMA'able memory for Tx ring.\n"); 1502 goto fail; 1503 } 1504 ctx.alc_busaddr = 0; 1505 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1506 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1507 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1508 if (error != 0 || ctx.alc_busaddr == 0) { 1509 device_printf(sc->alc_dev, 1510 "could not load DMA'able memory for Tx ring.\n"); 1511 goto fail; 1512 } 1513 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1514 1515 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1516 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1517 (void **)&sc->alc_rdata.alc_rx_ring, 1518 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1519 &sc->alc_cdata.alc_rx_ring_map); 1520 if (error != 0) { 1521 device_printf(sc->alc_dev, 1522 "could not allocate DMA'able memory for Rx ring.\n"); 1523 goto fail; 1524 } 1525 ctx.alc_busaddr = 0; 1526 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1527 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1528 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1529 if (error != 0 || ctx.alc_busaddr == 0) { 1530 device_printf(sc->alc_dev, 1531 "could not load DMA'able memory for Rx ring.\n"); 1532 goto fail; 1533 } 1534 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1535 1536 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1537 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1538 (void **)&sc->alc_rdata.alc_rr_ring, 1539 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1540 &sc->alc_cdata.alc_rr_ring_map); 1541 if (error != 0) { 1542 device_printf(sc->alc_dev, 1543 "could not allocate DMA'able memory for Rx return ring.\n"); 1544 goto fail; 1545 } 1546 ctx.alc_busaddr = 0; 1547 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1548 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1549 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1550 if (error != 0 || ctx.alc_busaddr == 0) { 1551 device_printf(sc->alc_dev, 1552 "could not load DMA'able memory for Tx ring.\n"); 1553 goto fail; 1554 } 1555 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1556 1557 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1558 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1559 (void **)&sc->alc_rdata.alc_cmb, 1560 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1561 &sc->alc_cdata.alc_cmb_map); 1562 if (error != 0) { 1563 device_printf(sc->alc_dev, 1564 "could not allocate DMA'able memory for CMB.\n"); 1565 goto fail; 1566 } 1567 ctx.alc_busaddr = 0; 1568 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1569 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1570 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1571 if (error != 0 || ctx.alc_busaddr == 0) { 1572 device_printf(sc->alc_dev, 1573 "could not load DMA'able memory for CMB.\n"); 1574 goto fail; 1575 } 1576 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1577 1578 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1579 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1580 (void **)&sc->alc_rdata.alc_smb, 1581 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1582 &sc->alc_cdata.alc_smb_map); 1583 if (error != 0) { 1584 device_printf(sc->alc_dev, 1585 "could not allocate DMA'able memory for SMB.\n"); 1586 goto fail; 1587 } 1588 ctx.alc_busaddr = 0; 1589 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1590 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1591 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1592 if (error != 0 || ctx.alc_busaddr == 0) { 1593 device_printf(sc->alc_dev, 1594 "could not load DMA'able memory for CMB.\n"); 1595 goto fail; 1596 } 1597 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1598 1599 /* Make sure we've not crossed 4GB boundary. */ 1600 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1601 (error = alc_check_boundary(sc)) != 0) { 1602 device_printf(sc->alc_dev, "4GB boundary crossed, " 1603 "switching to 32bit DMA addressing mode.\n"); 1604 alc_dma_free(sc); 1605 /* 1606 * Limit max allowable DMA address space to 32bit 1607 * and try again. 1608 */ 1609 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1610 goto again; 1611 } 1612 1613 /* 1614 * Create Tx buffer parent tag. 1615 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1616 * so it needs separate parent DMA tag as parent DMA address 1617 * space could be restricted to be within 32bit address space 1618 * by 4GB boundary crossing. 1619 */ 1620 error = bus_dma_tag_create( 1621 sc->alc_cdata.alc_parent_tag, /* parent */ 1622 1, 0, /* alignment, boundary */ 1623 BUS_SPACE_MAXADDR, /* lowaddr */ 1624 BUS_SPACE_MAXADDR, /* highaddr */ 1625 NULL, NULL, /* filter, filterarg */ 1626 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1627 0, /* nsegments */ 1628 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1629 0, /* flags */ 1630 &sc->alc_cdata.alc_buffer_tag); 1631 if (error != 0) { 1632 device_printf(sc->alc_dev, 1633 "could not create parent buffer DMA tag.\n"); 1634 goto fail; 1635 } 1636 1637 /* Create DMA tag for Tx buffers. */ 1638 error = bus_dma_tag_create( 1639 sc->alc_cdata.alc_buffer_tag, /* parent */ 1640 1, 0, /* alignment, boundary */ 1641 BUS_SPACE_MAXADDR, /* lowaddr */ 1642 BUS_SPACE_MAXADDR, /* highaddr */ 1643 NULL, NULL, /* filter, filterarg */ 1644 ALC_TSO_MAXSIZE, /* maxsize */ 1645 ALC_MAXTXSEGS, /* nsegments */ 1646 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1647 0, /* flags */ 1648 &sc->alc_cdata.alc_tx_tag); 1649 if (error != 0) { 1650 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1651 goto fail; 1652 } 1653 1654 /* Create DMA tag for Rx buffers. */ 1655 error = bus_dma_tag_create( 1656 sc->alc_cdata.alc_buffer_tag, /* parent */ 1657 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1658 BUS_SPACE_MAXADDR, /* lowaddr */ 1659 BUS_SPACE_MAXADDR, /* highaddr */ 1660 NULL, NULL, /* filter, filterarg */ 1661 MCLBYTES, /* maxsize */ 1662 1, /* nsegments */ 1663 MCLBYTES, /* maxsegsize */ 1664 0, /* flags */ 1665 &sc->alc_cdata.alc_rx_tag); 1666 if (error != 0) { 1667 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1668 goto fail; 1669 } 1670 /* Create DMA maps for Tx buffers. */ 1671 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1672 txd = &sc->alc_cdata.alc_txdesc[i]; 1673 txd->tx_m = NULL; 1674 txd->tx_dmamap = NULL; 1675 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 1676 BUS_DMA_WAITOK, &txd->tx_dmamap); 1677 if (error != 0) { 1678 device_printf(sc->alc_dev, 1679 "could not create Tx dmamap.\n"); 1680 goto fail; 1681 } 1682 } 1683 /* Create DMA maps for Rx buffers. */ 1684 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1685 BUS_DMA_WAITOK, 1686 &sc->alc_cdata.alc_rx_sparemap); 1687 if (error) { 1688 device_printf(sc->alc_dev, 1689 "could not create spare Rx dmamap.\n"); 1690 goto fail; 1691 } 1692 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1693 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1694 rxd->rx_m = NULL; 1695 rxd->rx_dmamap = NULL; 1696 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1697 BUS_DMA_WAITOK, 1698 &rxd->rx_dmamap); 1699 if (error != 0) { 1700 device_printf(sc->alc_dev, 1701 "could not create Rx dmamap.\n"); 1702 goto fail; 1703 } 1704 } 1705 1706 fail: 1707 return (error); 1708 } 1709 1710 static void 1711 alc_dma_free(struct alc_softc *sc) 1712 { 1713 struct alc_txdesc *txd; 1714 struct alc_rxdesc *rxd; 1715 int i; 1716 1717 /* Tx buffers. */ 1718 if (sc->alc_cdata.alc_tx_tag != NULL) { 1719 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1720 txd = &sc->alc_cdata.alc_txdesc[i]; 1721 if (txd->tx_dmamap != NULL) { 1722 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1723 txd->tx_dmamap); 1724 txd->tx_dmamap = NULL; 1725 } 1726 } 1727 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1728 sc->alc_cdata.alc_tx_tag = NULL; 1729 } 1730 /* Rx buffers */ 1731 if (sc->alc_cdata.alc_rx_tag != NULL) { 1732 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1733 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1734 if (rxd->rx_dmamap != NULL) { 1735 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1736 rxd->rx_dmamap); 1737 rxd->rx_dmamap = NULL; 1738 } 1739 } 1740 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1741 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1742 sc->alc_cdata.alc_rx_sparemap); 1743 sc->alc_cdata.alc_rx_sparemap = NULL; 1744 } 1745 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1746 sc->alc_cdata.alc_rx_tag = NULL; 1747 } 1748 /* Tx descriptor ring. */ 1749 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1750 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1751 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1752 sc->alc_cdata.alc_tx_ring_map); 1753 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1754 sc->alc_rdata.alc_tx_ring != NULL) 1755 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1756 sc->alc_rdata.alc_tx_ring, 1757 sc->alc_cdata.alc_tx_ring_map); 1758 sc->alc_rdata.alc_tx_ring = NULL; 1759 sc->alc_cdata.alc_tx_ring_map = NULL; 1760 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1761 sc->alc_cdata.alc_tx_ring_tag = NULL; 1762 } 1763 /* Rx ring. */ 1764 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1765 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1766 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1767 sc->alc_cdata.alc_rx_ring_map); 1768 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1769 sc->alc_rdata.alc_rx_ring != NULL) 1770 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1771 sc->alc_rdata.alc_rx_ring, 1772 sc->alc_cdata.alc_rx_ring_map); 1773 sc->alc_rdata.alc_rx_ring = NULL; 1774 sc->alc_cdata.alc_rx_ring_map = NULL; 1775 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1776 sc->alc_cdata.alc_rx_ring_tag = NULL; 1777 } 1778 /* Rx return ring. */ 1779 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1780 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1781 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1782 sc->alc_cdata.alc_rr_ring_map); 1783 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1784 sc->alc_rdata.alc_rr_ring != NULL) 1785 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1786 sc->alc_rdata.alc_rr_ring, 1787 sc->alc_cdata.alc_rr_ring_map); 1788 sc->alc_rdata.alc_rr_ring = NULL; 1789 sc->alc_cdata.alc_rr_ring_map = NULL; 1790 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1791 sc->alc_cdata.alc_rr_ring_tag = NULL; 1792 } 1793 /* CMB block */ 1794 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1795 if (sc->alc_cdata.alc_cmb_map != NULL) 1796 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1797 sc->alc_cdata.alc_cmb_map); 1798 if (sc->alc_cdata.alc_cmb_map != NULL && 1799 sc->alc_rdata.alc_cmb != NULL) 1800 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1801 sc->alc_rdata.alc_cmb, 1802 sc->alc_cdata.alc_cmb_map); 1803 sc->alc_rdata.alc_cmb = NULL; 1804 sc->alc_cdata.alc_cmb_map = NULL; 1805 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1806 sc->alc_cdata.alc_cmb_tag = NULL; 1807 } 1808 /* SMB block */ 1809 if (sc->alc_cdata.alc_smb_tag != NULL) { 1810 if (sc->alc_cdata.alc_smb_map != NULL) 1811 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1812 sc->alc_cdata.alc_smb_map); 1813 if (sc->alc_cdata.alc_smb_map != NULL && 1814 sc->alc_rdata.alc_smb != NULL) 1815 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1816 sc->alc_rdata.alc_smb, 1817 sc->alc_cdata.alc_smb_map); 1818 sc->alc_rdata.alc_smb = NULL; 1819 sc->alc_cdata.alc_smb_map = NULL; 1820 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1821 sc->alc_cdata.alc_smb_tag = NULL; 1822 } 1823 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1824 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1825 sc->alc_cdata.alc_buffer_tag = NULL; 1826 } 1827 if (sc->alc_cdata.alc_parent_tag != NULL) { 1828 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1829 sc->alc_cdata.alc_parent_tag = NULL; 1830 } 1831 } 1832 1833 static int 1834 alc_shutdown(device_t dev) 1835 { 1836 1837 return (alc_suspend(dev)); 1838 } 1839 1840 #if 0 1841 /* XXX: LINK SPEED */ 1842 /* 1843 * Note, this driver resets the link speed to 10/100Mbps by 1844 * restarting auto-negotiation in suspend/shutdown phase but we 1845 * don't know whether that auto-negotiation would succeed or not 1846 * as driver has no control after powering off/suspend operation. 1847 * If the renegotiation fail WOL may not work. Running at 1Gbps 1848 * will draw more power than 375mA at 3.3V which is specified in 1849 * PCI specification and that would result in complete 1850 * shutdowning power to ethernet controller. 1851 * 1852 * TODO 1853 * Save current negotiated media speed/duplex/flow-control to 1854 * softc and restore the same link again after resuming. PHY 1855 * handling such as power down/resetting to 100Mbps may be better 1856 * handled in suspend method in phy driver. 1857 */ 1858 static void 1859 alc_setlinkspeed(struct alc_softc *sc) 1860 { 1861 struct mii_data *mii; 1862 int aneg, i; 1863 1864 mii = device_get_softc(sc->alc_miibus); 1865 mii_pollstat(mii); 1866 aneg = 0; 1867 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1868 (IFM_ACTIVE | IFM_AVALID)) { 1869 switch IFM_SUBTYPE(mii->mii_media_active) { 1870 case IFM_10_T: 1871 case IFM_100_TX: 1872 return; 1873 case IFM_1000_T: 1874 aneg++; 1875 break; 1876 default: 1877 break; 1878 } 1879 } 1880 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1881 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1882 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1883 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1884 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1885 DELAY(1000); 1886 if (aneg != 0) { 1887 /* 1888 * Poll link state until alc(4) get a 10/100Mbps link. 1889 */ 1890 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1891 mii_pollstat(mii); 1892 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1893 == (IFM_ACTIVE | IFM_AVALID)) { 1894 switch (IFM_SUBTYPE( 1895 mii->mii_media_active)) { 1896 case IFM_10_T: 1897 case IFM_100_TX: 1898 alc_mac_config(sc); 1899 return; 1900 default: 1901 break; 1902 } 1903 } 1904 ALC_UNLOCK(sc); 1905 pause("alclnk", hz); 1906 ALC_LOCK(sc); 1907 } 1908 if (i == MII_ANEGTICKS_GIGE) 1909 device_printf(sc->alc_dev, 1910 "establishing a link failed, WOL may not work!"); 1911 } 1912 /* 1913 * No link, force MAC to have 100Mbps, full-duplex link. 1914 * This is the last resort and may/may not work. 1915 */ 1916 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1917 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1918 alc_mac_config(sc); 1919 } 1920 #endif 1921 1922 #if 0 1923 /* XXX: WOL */ 1924 static void 1925 alc_setwol(struct alc_softc *sc) 1926 { 1927 struct ifnet *ifp; 1928 uint32_t reg, pmcs; 1929 uint16_t pmstat; 1930 1931 ALC_LOCK_ASSERT(sc); 1932 1933 alc_disable_l0s_l1(sc); 1934 ifp = sc->alc_ifp; 1935 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1936 /* Disable WOL. */ 1937 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1938 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1939 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1940 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1941 /* Force PHY power down. */ 1942 alc_phy_down(sc); 1943 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1944 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1945 return; 1946 } 1947 1948 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1949 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1950 alc_setlinkspeed(sc); 1951 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1952 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1953 } 1954 1955 pmcs = 0; 1956 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1957 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1958 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1959 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1960 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1961 MAC_CFG_BCAST); 1962 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1963 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1964 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1965 reg |= MAC_CFG_RX_ENB; 1966 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1967 1968 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1969 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1970 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1971 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1972 /* WOL disabled, PHY power down. */ 1973 alc_phy_down(sc); 1974 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1975 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1976 1977 } 1978 /* Request PME. */ 1979 pmstat = pci_read_config(sc->alc_dev, 1980 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1981 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1982 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1983 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1984 pci_write_config(sc->alc_dev, 1985 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1986 } 1987 #endif 1988 1989 static int 1990 alc_suspend(device_t dev) 1991 { 1992 struct alc_softc *sc; 1993 1994 sc = device_get_softc(dev); 1995 1996 ALC_LOCK(sc); 1997 alc_stop(sc); 1998 #if 0 1999 /* XXX: WOL */ 2000 alc_setwol(sc); 2001 #endif 2002 ALC_UNLOCK(sc); 2003 2004 return (0); 2005 } 2006 2007 static int 2008 alc_resume(device_t dev) 2009 { 2010 struct alc_softc *sc; 2011 struct ifnet *ifp; 2012 uint16_t pmstat; 2013 2014 sc = device_get_softc(dev); 2015 2016 ALC_LOCK(sc); 2017 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2018 /* Disable PME and clear PME status. */ 2019 pmstat = pci_read_config(sc->alc_dev, 2020 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2021 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2022 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2023 pci_write_config(sc->alc_dev, 2024 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2025 } 2026 } 2027 /* Reset PHY. */ 2028 alc_phy_reset(sc); 2029 ifp = sc->alc_ifp; 2030 if ((ifp->if_flags & IFF_UP) != 0) { 2031 ifp->if_flags &= ~IFF_RUNNING; 2032 alc_init_locked(sc); 2033 } 2034 ALC_UNLOCK(sc); 2035 2036 return (0); 2037 } 2038 2039 static int 2040 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2041 { 2042 struct alc_txdesc *txd, *txd_last; 2043 struct tx_desc *desc; 2044 struct mbuf *m; 2045 struct ip *ip; 2046 struct tcphdr *tcp; 2047 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2048 bus_dmamap_t map; 2049 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2050 int error, idx, nsegs, prod; 2051 2052 ALC_LOCK_ASSERT(sc); 2053 2054 M_ASSERTPKTHDR((*m_head)); 2055 2056 m = *m_head; 2057 ip = NULL; 2058 tcp = NULL; 2059 ip_off = poff = 0; 2060 #if 0 2061 /* XXX: TSO */ 2062 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2063 /* 2064 * AR813x/AR815x requires offset of TCP/UDP header in its 2065 * Tx descriptor to perform Tx checksum offloading. TSO 2066 * also requires TCP header offset and modification of 2067 * IP/TCP header. This kind of operation takes many CPU 2068 * cycles on FreeBSD so fast host CPU is required to get 2069 * smooth TSO performance. 2070 */ 2071 struct ether_header *eh; 2072 2073 if (M_WRITABLE(m) == 0) { 2074 /* Get a writable copy. */ 2075 m = m_dup(*m_head, MB_DONTWAIT); 2076 /* Release original mbufs. */ 2077 m_freem(*m_head); 2078 if (m == NULL) { 2079 *m_head = NULL; 2080 return (ENOBUFS); 2081 } 2082 *m_head = m; 2083 } 2084 2085 ip_off = sizeof(struct ether_header); 2086 m = m_pullup(m, ip_off + sizeof(struct ip)); 2087 if (m == NULL) { 2088 *m_head = NULL; 2089 return (ENOBUFS); 2090 } 2091 eh = mtod(m, struct ether_header *); 2092 /* 2093 * Check if hardware VLAN insertion is off. 2094 * Additional check for LLC/SNAP frame? 2095 */ 2096 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2097 ip_off = sizeof(struct ether_vlan_header); 2098 m = m_pullup(m, ip_off); 2099 if (m == NULL) { 2100 *m_head = NULL; 2101 return (ENOBUFS); 2102 } 2103 } 2104 m = m_pullup(m, ip_off + sizeof(struct ip)); 2105 if (m == NULL) { 2106 *m_head = NULL; 2107 return (ENOBUFS); 2108 } 2109 ip = (struct ip *)(mtod(m, char *) + ip_off); 2110 poff = ip_off + (ip->ip_hl << 2); 2111 2112 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2113 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2114 if (m == NULL) { 2115 *m_head = NULL; 2116 return (ENOBUFS); 2117 } 2118 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2119 m = m_pullup(m, poff + (tcp->th_off << 2)); 2120 if (m == NULL) { 2121 *m_head = NULL; 2122 return (ENOBUFS); 2123 } 2124 /* 2125 * Due to strict adherence of Microsoft NDIS 2126 * Large Send specification, hardware expects 2127 * a pseudo TCP checksum inserted by upper 2128 * stack. Unfortunately the pseudo TCP 2129 * checksum that NDIS refers to does not include 2130 * TCP payload length so driver should recompute 2131 * the pseudo checksum here. Hopefully this 2132 * wouldn't be much burden on modern CPUs. 2133 * 2134 * Reset IP checksum and recompute TCP pseudo 2135 * checksum as NDIS specification said. 2136 */ 2137 ip->ip_sum = 0; 2138 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2139 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2140 } 2141 *m_head = m; 2142 } 2143 #endif /* TSO */ 2144 2145 prod = sc->alc_cdata.alc_tx_prod; 2146 txd = &sc->alc_cdata.alc_txdesc[prod]; 2147 txd_last = txd; 2148 map = txd->tx_dmamap; 2149 2150 error = bus_dmamap_load_mbuf_defrag( 2151 sc->alc_cdata.alc_tx_tag, map, m_head, 2152 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 2153 if (error) { 2154 m_freem(*m_head); 2155 *m_head = NULL; 2156 return (error); 2157 } 2158 if (nsegs == 0) { 2159 m_freem(*m_head); 2160 *m_head = NULL; 2161 return (EIO); 2162 } 2163 2164 /* Check descriptor overrun. */ 2165 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2166 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2167 return (ENOBUFS); 2168 } 2169 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2170 2171 m = *m_head; 2172 cflags = TD_ETHERNET; 2173 vtag = 0; 2174 desc = NULL; 2175 idx = 0; 2176 /* Configure VLAN hardware tag insertion. */ 2177 if ((m->m_flags & M_VLANTAG) != 0) { 2178 vtag = htons(m->m_pkthdr.ether_vlantag); 2179 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2180 cflags |= TD_INS_VLAN_TAG; 2181 } 2182 /* Configure Tx checksum offload. */ 2183 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2184 #ifdef ALC_USE_CUSTOM_CSUM 2185 cflags |= TD_CUSTOM_CSUM; 2186 /* Set checksum start offset. */ 2187 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2188 TD_PLOAD_OFFSET_MASK; 2189 /* Set checksum insertion position of TCP/UDP. */ 2190 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2191 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2192 #else 2193 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2194 cflags |= TD_IPCSUM; 2195 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2196 cflags |= TD_TCPCSUM; 2197 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2198 cflags |= TD_UDPCSUM; 2199 /* Set TCP/UDP header offset. */ 2200 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2201 TD_L4HDR_OFFSET_MASK; 2202 #endif 2203 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2204 /* Request TSO and set MSS. */ 2205 cflags |= TD_TSO | TD_TSO_DESCV1; 2206 #if 0 2207 /* XXX: TSO */ 2208 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2209 TD_MSS_MASK; 2210 /* Set TCP header offset. */ 2211 #endif 2212 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2213 TD_TCPHDR_OFFSET_MASK; 2214 /* 2215 * AR813x/AR815x requires the first buffer should 2216 * only hold IP/TCP header data. Payload should 2217 * be handled in other descriptors. 2218 */ 2219 hdrlen = poff + (tcp->th_off << 2); 2220 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2221 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2222 desc->flags = htole32(cflags); 2223 desc->addr = htole64(txsegs[0].ds_addr); 2224 sc->alc_cdata.alc_tx_cnt++; 2225 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2226 if (m->m_len - hdrlen > 0) { 2227 /* Handle remaining payload of the first fragment. */ 2228 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2229 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2230 vtag)); 2231 desc->flags = htole32(cflags); 2232 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2233 sc->alc_cdata.alc_tx_cnt++; 2234 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2235 } 2236 /* Handle remaining fragments. */ 2237 idx = 1; 2238 } 2239 for (; idx < nsegs; idx++) { 2240 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2241 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2242 desc->flags = htole32(cflags); 2243 desc->addr = htole64(txsegs[idx].ds_addr); 2244 sc->alc_cdata.alc_tx_cnt++; 2245 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2246 } 2247 /* Update producer index. */ 2248 sc->alc_cdata.alc_tx_prod = prod; 2249 2250 /* Finally set EOP on the last descriptor. */ 2251 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2252 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2253 desc->flags |= htole32(TD_EOP); 2254 2255 /* Swap dmamap of the first and the last. */ 2256 txd = &sc->alc_cdata.alc_txdesc[prod]; 2257 map = txd_last->tx_dmamap; 2258 txd_last->tx_dmamap = txd->tx_dmamap; 2259 txd->tx_dmamap = map; 2260 txd->tx_m = m; 2261 2262 return (0); 2263 } 2264 2265 static void 2266 alc_tx_task(void *arg, int pending) 2267 { 2268 struct ifnet *ifp; 2269 2270 ifp = (struct ifnet *)arg; 2271 alc_start(ifp); 2272 } 2273 2274 static void 2275 alc_start(struct ifnet *ifp) 2276 { 2277 struct alc_softc *sc; 2278 struct mbuf *m_head; 2279 int enq; 2280 2281 sc = ifp->if_softc; 2282 2283 ALC_LOCK(sc); 2284 2285 /* Reclaim transmitted frames. */ 2286 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2287 alc_txeof(sc); 2288 2289 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 2290 ALC_UNLOCK(sc); 2291 return; 2292 } 2293 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2294 ifq_purge(&ifp->if_snd); 2295 ALC_UNLOCK(sc); 2296 return; 2297 } 2298 2299 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) { 2300 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2301 if (m_head == NULL) 2302 break; 2303 /* 2304 * Pack the data into the transmit ring. If we 2305 * don't have room, set the OACTIVE flag and wait 2306 * for the NIC to drain the ring. 2307 */ 2308 if (alc_encap(sc, &m_head)) { 2309 if (m_head == NULL) 2310 break; 2311 ifq_prepend(&ifp->if_snd, m_head); 2312 ifp->if_flags |= IFF_OACTIVE; 2313 break; 2314 } 2315 2316 enq++; 2317 /* 2318 * If there's a BPF listener, bounce a copy of this frame 2319 * to him. 2320 */ 2321 ETHER_BPF_MTAP(ifp, m_head); 2322 } 2323 2324 if (enq > 0) { 2325 /* Sync descriptors. */ 2326 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2327 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2328 /* Kick. Assume we're using normal Tx priority queue. */ 2329 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2330 (sc->alc_cdata.alc_tx_prod << 2331 MBOX_TD_PROD_LO_IDX_SHIFT) & 2332 MBOX_TD_PROD_LO_IDX_MASK); 2333 /* Set a timeout in case the chip goes out to lunch. */ 2334 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2335 } 2336 2337 ALC_UNLOCK(sc); 2338 } 2339 2340 static void 2341 alc_watchdog(struct alc_softc *sc) 2342 { 2343 struct ifnet *ifp; 2344 2345 ALC_LOCK_ASSERT(sc); 2346 2347 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2348 return; 2349 2350 ifp = sc->alc_ifp; 2351 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2352 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2353 ifp->if_oerrors++; 2354 ifp->if_flags &= ~IFF_RUNNING; 2355 alc_init_locked(sc); 2356 return; 2357 } 2358 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2359 ifp->if_oerrors++; 2360 ifp->if_flags &= ~IFF_RUNNING; 2361 alc_init_locked(sc); 2362 if (!ifq_is_empty(&ifp->if_snd)) 2363 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2364 } 2365 2366 static int 2367 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2368 { 2369 struct alc_softc *sc; 2370 struct ifreq *ifr; 2371 struct mii_data *mii; 2372 int error, mask; 2373 2374 (void)cr; 2375 sc = ifp->if_softc; 2376 ifr = (struct ifreq *)data; 2377 error = 0; 2378 switch (cmd) { 2379 case SIOCSIFMTU: 2380 if (ifr->ifr_mtu < ETHERMIN || 2381 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2382 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2383 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2384 ifr->ifr_mtu > ETHERMTU)) { 2385 error = EINVAL; 2386 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2387 ALC_LOCK(sc); 2388 ifp->if_mtu = ifr->ifr_mtu; 2389 /* AR813x/AR815x has 13 bits MSS field. */ 2390 if (ifp->if_mtu > ALC_TSO_MTU && 2391 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2392 ifp->if_capenable &= ~IFCAP_TSO4; 2393 ifp->if_hwassist &= ~CSUM_TSO; 2394 } 2395 ALC_UNLOCK(sc); 2396 } 2397 break; 2398 case SIOCSIFFLAGS: 2399 ALC_LOCK(sc); 2400 if ((ifp->if_flags & IFF_UP) != 0) { 2401 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2402 ((ifp->if_flags ^ sc->alc_if_flags) & 2403 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2404 alc_rxfilter(sc); 2405 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2406 alc_init_locked(sc); 2407 } else if ((ifp->if_flags & IFF_RUNNING) != 0) 2408 alc_stop(sc); 2409 sc->alc_if_flags = ifp->if_flags; 2410 ALC_UNLOCK(sc); 2411 break; 2412 case SIOCADDMULTI: 2413 case SIOCDELMULTI: 2414 ALC_LOCK(sc); 2415 if ((ifp->if_flags & IFF_RUNNING) != 0) 2416 alc_rxfilter(sc); 2417 ALC_UNLOCK(sc); 2418 break; 2419 case SIOCSIFMEDIA: 2420 case SIOCGIFMEDIA: 2421 mii = device_get_softc(sc->alc_miibus); 2422 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2423 break; 2424 case SIOCSIFCAP: 2425 ALC_LOCK(sc); 2426 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2427 if ((mask & IFCAP_TXCSUM) != 0 && 2428 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2429 ifp->if_capenable ^= IFCAP_TXCSUM; 2430 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2431 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2432 else 2433 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2434 } 2435 if ((mask & IFCAP_TSO4) != 0 && 2436 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2437 ifp->if_capenable ^= IFCAP_TSO4; 2438 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2439 /* AR813x/AR815x has 13 bits MSS field. */ 2440 if (ifp->if_mtu > ALC_TSO_MTU) { 2441 ifp->if_capenable &= ~IFCAP_TSO4; 2442 ifp->if_hwassist &= ~CSUM_TSO; 2443 } else 2444 ifp->if_hwassist |= CSUM_TSO; 2445 } else 2446 ifp->if_hwassist &= ~CSUM_TSO; 2447 } 2448 #if 0 2449 /* XXX: WOL */ 2450 if ((mask & IFCAP_WOL_MCAST) != 0 && 2451 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2452 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2453 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2454 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2455 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2456 #endif 2457 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2458 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2459 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2460 alc_rxvlan(sc); 2461 } 2462 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2463 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2464 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2465 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2466 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2467 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2468 /* 2469 * VLAN hardware tagging is required to do checksum 2470 * offload or TSO on VLAN interface. Checksum offload 2471 * on VLAN interface also requires hardware checksum 2472 * offload of parent interface. 2473 */ 2474 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2475 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2476 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2477 ifp->if_capenable &= 2478 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2479 ALC_UNLOCK(sc); 2480 // XXX VLAN_CAPABILITIES(ifp); 2481 break; 2482 default: 2483 error = ether_ioctl(ifp, cmd, data); 2484 break; 2485 } 2486 2487 return (error); 2488 } 2489 2490 static void 2491 alc_mac_config(struct alc_softc *sc) 2492 { 2493 struct mii_data *mii; 2494 uint32_t reg; 2495 2496 ALC_LOCK_ASSERT(sc); 2497 2498 mii = device_get_softc(sc->alc_miibus); 2499 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2500 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2501 MAC_CFG_SPEED_MASK); 2502 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2503 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2504 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 2505 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2506 } 2507 /* Reprogram MAC with resolved speed/duplex. */ 2508 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2509 case IFM_10_T: 2510 case IFM_100_TX: 2511 reg |= MAC_CFG_SPEED_10_100; 2512 break; 2513 case IFM_1000_T: 2514 reg |= MAC_CFG_SPEED_1000; 2515 break; 2516 } 2517 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2518 reg |= MAC_CFG_FULL_DUPLEX; 2519 #ifdef notyet 2520 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2521 reg |= MAC_CFG_TX_FC; 2522 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2523 reg |= MAC_CFG_RX_FC; 2524 #endif 2525 } 2526 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2527 } 2528 2529 static void 2530 alc_stats_clear(struct alc_softc *sc) 2531 { 2532 struct smb sb, *smb; 2533 uint32_t *reg; 2534 int i; 2535 2536 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2537 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2538 sc->alc_cdata.alc_smb_map, 2539 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2540 smb = sc->alc_rdata.alc_smb; 2541 /* Update done, clear. */ 2542 smb->updated = 0; 2543 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2544 sc->alc_cdata.alc_smb_map, 2545 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2546 } else { 2547 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2548 reg++) { 2549 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2550 i += sizeof(uint32_t); 2551 } 2552 /* Read Tx statistics. */ 2553 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2554 reg++) { 2555 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2556 i += sizeof(uint32_t); 2557 } 2558 } 2559 } 2560 2561 static void 2562 alc_stats_update(struct alc_softc *sc) 2563 { 2564 struct alc_hw_stats *stat; 2565 struct smb sb, *smb; 2566 struct ifnet *ifp; 2567 uint32_t *reg; 2568 int i; 2569 2570 ALC_LOCK_ASSERT(sc); 2571 2572 ifp = sc->alc_ifp; 2573 stat = &sc->alc_stats; 2574 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2575 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2576 sc->alc_cdata.alc_smb_map, 2577 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2578 smb = sc->alc_rdata.alc_smb; 2579 if (smb->updated == 0) 2580 return; 2581 } else { 2582 smb = &sb; 2583 /* Read Rx statistics. */ 2584 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2585 reg++) { 2586 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2587 i += sizeof(uint32_t); 2588 } 2589 /* Read Tx statistics. */ 2590 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2591 reg++) { 2592 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2593 i += sizeof(uint32_t); 2594 } 2595 } 2596 2597 /* Rx stats. */ 2598 stat->rx_frames += smb->rx_frames; 2599 stat->rx_bcast_frames += smb->rx_bcast_frames; 2600 stat->rx_mcast_frames += smb->rx_mcast_frames; 2601 stat->rx_pause_frames += smb->rx_pause_frames; 2602 stat->rx_control_frames += smb->rx_control_frames; 2603 stat->rx_crcerrs += smb->rx_crcerrs; 2604 stat->rx_lenerrs += smb->rx_lenerrs; 2605 stat->rx_bytes += smb->rx_bytes; 2606 stat->rx_runts += smb->rx_runts; 2607 stat->rx_fragments += smb->rx_fragments; 2608 stat->rx_pkts_64 += smb->rx_pkts_64; 2609 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2610 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2611 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2612 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2613 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2614 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2615 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2616 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2617 stat->rx_rrs_errs += smb->rx_rrs_errs; 2618 stat->rx_alignerrs += smb->rx_alignerrs; 2619 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2620 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2621 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2622 2623 /* Tx stats. */ 2624 stat->tx_frames += smb->tx_frames; 2625 stat->tx_bcast_frames += smb->tx_bcast_frames; 2626 stat->tx_mcast_frames += smb->tx_mcast_frames; 2627 stat->tx_pause_frames += smb->tx_pause_frames; 2628 stat->tx_excess_defer += smb->tx_excess_defer; 2629 stat->tx_control_frames += smb->tx_control_frames; 2630 stat->tx_deferred += smb->tx_deferred; 2631 stat->tx_bytes += smb->tx_bytes; 2632 stat->tx_pkts_64 += smb->tx_pkts_64; 2633 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2634 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2635 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2636 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2637 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2638 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2639 stat->tx_single_colls += smb->tx_single_colls; 2640 stat->tx_multi_colls += smb->tx_multi_colls; 2641 stat->tx_late_colls += smb->tx_late_colls; 2642 stat->tx_excess_colls += smb->tx_excess_colls; 2643 stat->tx_abort += smb->tx_abort; 2644 stat->tx_underrun += smb->tx_underrun; 2645 stat->tx_desc_underrun += smb->tx_desc_underrun; 2646 stat->tx_lenerrs += smb->tx_lenerrs; 2647 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2648 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2649 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2650 2651 /* Update counters in ifnet. */ 2652 ifp->if_opackets += smb->tx_frames; 2653 2654 ifp->if_collisions += smb->tx_single_colls + 2655 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2656 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2657 2658 /* 2659 * XXX 2660 * tx_pkts_truncated counter looks suspicious. It constantly 2661 * increments with no sign of Tx errors. This may indicate 2662 * the counter name is not correct one so I've removed the 2663 * counter in output errors. 2664 */ 2665 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2666 smb->tx_underrun; 2667 2668 ifp->if_ipackets += smb->rx_frames; 2669 2670 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2671 smb->rx_runts + smb->rx_pkts_truncated + 2672 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2673 smb->rx_alignerrs; 2674 2675 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2676 /* Update done, clear. */ 2677 smb->updated = 0; 2678 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2679 sc->alc_cdata.alc_smb_map, 2680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2681 } 2682 } 2683 2684 static void 2685 alc_intr(void *arg) 2686 { 2687 struct alc_softc *sc; 2688 uint32_t status; 2689 2690 sc = (struct alc_softc *)arg; 2691 2692 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2693 if ((status & ALC_INTRS) == 0) { 2694 return; 2695 } 2696 /* Disable interrupts. */ 2697 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2698 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2699 2700 return; 2701 } 2702 2703 static void 2704 alc_int_task(void *arg, int pending) 2705 { 2706 struct alc_softc *sc; 2707 struct ifnet *ifp; 2708 uint32_t status; 2709 int more; 2710 2711 sc = (struct alc_softc *)arg; 2712 ifp = sc->alc_ifp; 2713 2714 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2715 more = atomic_readandclear_32(&sc->alc_morework); 2716 if (more != 0) 2717 status |= INTR_RX_PKT; 2718 if ((status & ALC_INTRS) == 0) 2719 goto done; 2720 2721 /* Acknowledge interrupts but still disable interrupts. */ 2722 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2723 2724 more = 0; 2725 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2726 if ((status & INTR_RX_PKT) != 0) { 2727 more = alc_rxintr(sc, sc->alc_process_limit); 2728 if (more == EAGAIN) 2729 atomic_set_int(&sc->alc_morework, 1); 2730 else if (more == EIO) { 2731 ALC_LOCK(sc); 2732 ifp->if_flags &= ~IFF_RUNNING; 2733 alc_init_locked(sc); 2734 ALC_UNLOCK(sc); 2735 return; 2736 } 2737 } 2738 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2739 INTR_TXQ_TO_RST)) != 0) { 2740 if ((status & INTR_DMA_RD_TO_RST) != 0) 2741 device_printf(sc->alc_dev, 2742 "DMA read error! -- resetting\n"); 2743 if ((status & INTR_DMA_WR_TO_RST) != 0) 2744 device_printf(sc->alc_dev, 2745 "DMA write error! -- resetting\n"); 2746 if ((status & INTR_TXQ_TO_RST) != 0) 2747 device_printf(sc->alc_dev, 2748 "TxQ reset! -- resetting\n"); 2749 ALC_LOCK(sc); 2750 ifp->if_flags &= ~IFF_RUNNING; 2751 alc_init_locked(sc); 2752 ALC_UNLOCK(sc); 2753 return; 2754 } 2755 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2756 !ifq_is_empty(&ifp->if_snd)) 2757 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2758 } 2759 2760 if (more == EAGAIN || 2761 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2762 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2763 return; 2764 } 2765 2766 done: 2767 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2768 /* Re-enable interrupts if we're running. */ 2769 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2770 } 2771 } 2772 2773 static void 2774 alc_txeof(struct alc_softc *sc) 2775 { 2776 struct ifnet *ifp; 2777 struct alc_txdesc *txd; 2778 uint32_t cons, prod; 2779 int prog; 2780 2781 ALC_LOCK_ASSERT(sc); 2782 2783 ifp = sc->alc_ifp; 2784 2785 if (sc->alc_cdata.alc_tx_cnt == 0) 2786 return; 2787 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2788 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2789 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2790 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2791 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2792 prod = sc->alc_rdata.alc_cmb->cons; 2793 } else 2794 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2795 /* Assume we're using normal Tx priority queue. */ 2796 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2797 MBOX_TD_CONS_LO_IDX_SHIFT; 2798 cons = sc->alc_cdata.alc_tx_cons; 2799 /* 2800 * Go through our Tx list and free mbufs for those 2801 * frames which have been transmitted. 2802 */ 2803 for (prog = 0; cons != prod; prog++, 2804 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2805 if (sc->alc_cdata.alc_tx_cnt <= 0) 2806 break; 2807 prog++; 2808 ifp->if_flags &= ~IFF_OACTIVE; 2809 sc->alc_cdata.alc_tx_cnt--; 2810 txd = &sc->alc_cdata.alc_txdesc[cons]; 2811 if (txd->tx_m != NULL) { 2812 /* Reclaim transmitted mbufs. */ 2813 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2814 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2815 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2816 txd->tx_dmamap); 2817 m_freem(txd->tx_m); 2818 txd->tx_m = NULL; 2819 } 2820 } 2821 2822 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2823 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2824 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2825 sc->alc_cdata.alc_tx_cons = cons; 2826 /* 2827 * Unarm watchdog timer only when there is no pending 2828 * frames in Tx queue. 2829 */ 2830 if (sc->alc_cdata.alc_tx_cnt == 0) 2831 sc->alc_watchdog_timer = 0; 2832 } 2833 2834 static int 2835 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2836 { 2837 struct mbuf *m; 2838 bus_dma_segment_t segs[1]; 2839 bus_dmamap_t map; 2840 int nsegs; 2841 int error; 2842 2843 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2844 if (m == NULL) 2845 return (ENOBUFS); 2846 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2847 #ifndef __NO_STRICT_ALIGNMENT 2848 m_adj(m, sizeof(uint64_t)); 2849 #endif 2850 2851 error = bus_dmamap_load_mbuf_segment( 2852 sc->alc_cdata.alc_rx_tag, 2853 sc->alc_cdata.alc_rx_sparemap, 2854 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 2855 if (error) { 2856 m_freem(m); 2857 return (ENOBUFS); 2858 } 2859 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2860 2861 if (rxd->rx_m != NULL) { 2862 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2863 BUS_DMASYNC_POSTREAD); 2864 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2865 } 2866 map = rxd->rx_dmamap; 2867 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2868 sc->alc_cdata.alc_rx_sparemap = map; 2869 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2870 BUS_DMASYNC_PREREAD); 2871 rxd->rx_m = m; 2872 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2873 return (0); 2874 } 2875 2876 static int 2877 alc_rxintr(struct alc_softc *sc, int count) 2878 { 2879 struct ifnet *ifp; 2880 struct rx_rdesc *rrd; 2881 uint32_t nsegs, status; 2882 int rr_cons, prog; 2883 2884 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2885 sc->alc_cdata.alc_rr_ring_map, 2886 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2887 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2888 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2889 rr_cons = sc->alc_cdata.alc_rr_cons; 2890 ifp = sc->alc_ifp; 2891 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2892 if (count-- <= 0) 2893 break; 2894 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2895 status = le32toh(rrd->status); 2896 if ((status & RRD_VALID) == 0) 2897 break; 2898 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2899 if (nsegs == 0) { 2900 /* This should not happen! */ 2901 device_printf(sc->alc_dev, 2902 "unexpected segment count -- resetting\n"); 2903 return (EIO); 2904 } 2905 alc_rxeof(sc, rrd); 2906 /* Clear Rx return status. */ 2907 rrd->status = 0; 2908 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2909 sc->alc_cdata.alc_rx_cons += nsegs; 2910 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2911 prog += nsegs; 2912 } 2913 2914 if (prog > 0) { 2915 /* Update the consumer index. */ 2916 sc->alc_cdata.alc_rr_cons = rr_cons; 2917 /* Sync Rx return descriptors. */ 2918 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2919 sc->alc_cdata.alc_rr_ring_map, 2920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2921 /* 2922 * Sync updated Rx descriptors such that controller see 2923 * modified buffer addresses. 2924 */ 2925 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2926 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2927 /* 2928 * Let controller know availability of new Rx buffers. 2929 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2930 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2931 * only when Rx buffer pre-fetching is required. In 2932 * addition we already set ALC_RX_RD_FREE_THRESH to 2933 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2934 * it still seems that pre-fetching needs more 2935 * experimentation. 2936 */ 2937 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2938 sc->alc_cdata.alc_rx_cons); 2939 } 2940 2941 return (count > 0 ? 0 : EAGAIN); 2942 } 2943 2944 #ifndef __NO_STRICT_ALIGNMENT 2945 static struct mbuf * 2946 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2947 { 2948 struct mbuf *n; 2949 int i; 2950 uint16_t *src, *dst; 2951 2952 src = mtod(m, uint16_t *); 2953 dst = src - 3; 2954 2955 if (m->m_next == NULL) { 2956 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2957 *dst++ = *src++; 2958 m->m_data -= 6; 2959 return (m); 2960 } 2961 /* 2962 * Append a new mbuf to received mbuf chain and copy ethernet 2963 * header from the mbuf chain. This can save lots of CPU 2964 * cycles for jumbo frame. 2965 */ 2966 MGETHDR(n, MB_DONTWAIT, MT_DATA); 2967 if (n == NULL) { 2968 ifp->if_iqdrops++; 2969 m_freem(m); 2970 return (NULL); 2971 } 2972 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2973 m->m_data += ETHER_HDR_LEN; 2974 m->m_len -= ETHER_HDR_LEN; 2975 n->m_len = ETHER_HDR_LEN; 2976 M_MOVE_PKTHDR(n, m); 2977 n->m_next = m; 2978 return (n); 2979 } 2980 #endif 2981 2982 /* Receive a frame. */ 2983 static void 2984 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2985 { 2986 struct alc_rxdesc *rxd; 2987 struct ifnet *ifp; 2988 struct mbuf *mp, *m; 2989 uint32_t rdinfo, status, vtag; 2990 int count, nsegs, rx_cons; 2991 2992 ifp = sc->alc_ifp; 2993 status = le32toh(rrd->status); 2994 rdinfo = le32toh(rrd->rdinfo); 2995 rx_cons = RRD_RD_IDX(rdinfo); 2996 nsegs = RRD_RD_CNT(rdinfo); 2997 2998 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2999 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3000 /* 3001 * We want to pass the following frames to upper 3002 * layer regardless of error status of Rx return 3003 * ring. 3004 * 3005 * o IP/TCP/UDP checksum is bad. 3006 * o frame length and protocol specific length 3007 * does not match. 3008 * 3009 * Force network stack compute checksum for 3010 * errored frames. 3011 */ 3012 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3013 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 3014 RRD_ERR_RUNT) != 0) 3015 return; 3016 } 3017 3018 for (count = 0; count < nsegs; count++, 3019 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3020 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3021 mp = rxd->rx_m; 3022 /* Add a new receive buffer to the ring. */ 3023 if (alc_newbuf(sc, rxd) != 0) { 3024 ifp->if_iqdrops++; 3025 /* Reuse Rx buffers. */ 3026 if (sc->alc_cdata.alc_rxhead != NULL) 3027 m_freem(sc->alc_cdata.alc_rxhead); 3028 break; 3029 } 3030 3031 /* 3032 * Assume we've received a full sized frame. 3033 * Actual size is fixed when we encounter the end of 3034 * multi-segmented frame. 3035 */ 3036 mp->m_len = sc->alc_buf_size; 3037 3038 /* Chain received mbufs. */ 3039 if (sc->alc_cdata.alc_rxhead == NULL) { 3040 sc->alc_cdata.alc_rxhead = mp; 3041 sc->alc_cdata.alc_rxtail = mp; 3042 } else { 3043 mp->m_flags &= ~M_PKTHDR; 3044 sc->alc_cdata.alc_rxprev_tail = 3045 sc->alc_cdata.alc_rxtail; 3046 sc->alc_cdata.alc_rxtail->m_next = mp; 3047 sc->alc_cdata.alc_rxtail = mp; 3048 } 3049 3050 if (count == nsegs - 1) { 3051 /* Last desc. for this frame. */ 3052 m = sc->alc_cdata.alc_rxhead; 3053 m->m_flags |= M_PKTHDR; 3054 /* 3055 * It seems that L1C/L2C controller has no way 3056 * to tell hardware to strip CRC bytes. 3057 */ 3058 m->m_pkthdr.len = 3059 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3060 if (nsegs > 1) { 3061 /* Set last mbuf size. */ 3062 mp->m_len = sc->alc_cdata.alc_rxlen - 3063 (nsegs - 1) * sc->alc_buf_size; 3064 /* Remove the CRC bytes in chained mbufs. */ 3065 if (mp->m_len <= ETHER_CRC_LEN) { 3066 sc->alc_cdata.alc_rxtail = 3067 sc->alc_cdata.alc_rxprev_tail; 3068 sc->alc_cdata.alc_rxtail->m_len -= 3069 (ETHER_CRC_LEN - mp->m_len); 3070 sc->alc_cdata.alc_rxtail->m_next = NULL; 3071 m_freem(mp); 3072 } else { 3073 mp->m_len -= ETHER_CRC_LEN; 3074 } 3075 } else 3076 m->m_len = m->m_pkthdr.len; 3077 m->m_pkthdr.rcvif = ifp; 3078 /* 3079 * Due to hardware bugs, Rx checksum offloading 3080 * was intentionally disabled. 3081 */ 3082 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3083 (status & RRD_VLAN_TAG) != 0) { 3084 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3085 m->m_pkthdr.ether_vlantag = ntohs(vtag); 3086 m->m_flags |= M_VLANTAG; 3087 } 3088 #ifndef __NO_STRICT_ALIGNMENT 3089 m = alc_fixup_rx(ifp, m); 3090 if (m != NULL) 3091 #endif 3092 { 3093 /* Pass it on. */ 3094 (*ifp->if_input)(ifp, m); 3095 } 3096 } 3097 } 3098 /* Reset mbuf chains. */ 3099 ALC_RXCHAIN_RESET(sc); 3100 } 3101 3102 static void 3103 alc_tick(void *arg) 3104 { 3105 struct alc_softc *sc; 3106 struct mii_data *mii; 3107 3108 sc = (struct alc_softc *)arg; 3109 3110 ALC_LOCK(sc); 3111 3112 mii = device_get_softc(sc->alc_miibus); 3113 mii_tick(mii); 3114 alc_stats_update(sc); 3115 /* 3116 * alc(4) does not rely on Tx completion interrupts to reclaim 3117 * transferred buffers. Instead Tx completion interrupts are 3118 * used to hint for scheduling Tx task. So it's necessary to 3119 * release transmitted buffers by kicking Tx completion 3120 * handler. This limits the maximum reclamation delay to a hz. 3121 */ 3122 alc_txeof(sc); 3123 alc_watchdog(sc); 3124 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3125 ALC_UNLOCK(sc); 3126 } 3127 3128 static void 3129 alc_reset(struct alc_softc *sc) 3130 { 3131 uint32_t reg; 3132 int i; 3133 3134 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3135 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3136 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3137 3138 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3139 DELAY(10); 3140 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3141 break; 3142 } 3143 if (i == 0) 3144 device_printf(sc->alc_dev, "master reset timeout!\n"); 3145 3146 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3147 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3148 break; 3149 DELAY(10); 3150 } 3151 3152 if (i == 0) 3153 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3154 } 3155 3156 static void 3157 alc_init(void *xsc) 3158 { 3159 struct alc_softc *sc; 3160 3161 sc = (struct alc_softc *)xsc; 3162 ALC_LOCK(sc); 3163 alc_init_locked(sc); 3164 ALC_UNLOCK(sc); 3165 } 3166 3167 static void 3168 alc_init_locked(struct alc_softc *sc) 3169 { 3170 struct ifnet *ifp; 3171 struct mii_data *mii; 3172 uint8_t eaddr[ETHER_ADDR_LEN]; 3173 bus_addr_t paddr; 3174 uint32_t reg, rxf_hi, rxf_lo; 3175 3176 ALC_LOCK_ASSERT(sc); 3177 3178 ifp = sc->alc_ifp; 3179 mii = device_get_softc(sc->alc_miibus); 3180 3181 if ((ifp->if_flags & IFF_RUNNING) != 0) 3182 return; 3183 /* 3184 * Cancel any pending I/O. 3185 */ 3186 alc_stop(sc); 3187 /* 3188 * Reset the chip to a known state. 3189 */ 3190 alc_reset(sc); 3191 3192 /* Initialize Rx descriptors. */ 3193 if (alc_init_rx_ring(sc) != 0) { 3194 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3195 alc_stop(sc); 3196 return; 3197 } 3198 alc_init_rr_ring(sc); 3199 alc_init_tx_ring(sc); 3200 alc_init_cmb(sc); 3201 alc_init_smb(sc); 3202 3203 /* Reprogram the station address. */ 3204 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3205 CSR_WRITE_4(sc, ALC_PAR0, 3206 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3207 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3208 /* 3209 * Clear WOL status and disable all WOL feature as WOL 3210 * would interfere Rx operation under normal environments. 3211 */ 3212 CSR_READ_4(sc, ALC_WOL_CFG); 3213 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3214 /* Set Tx descriptor base addresses. */ 3215 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3216 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3217 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3218 /* We don't use high priority ring. */ 3219 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3220 /* Set Tx descriptor counter. */ 3221 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3222 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3223 /* Set Rx descriptor base addresses. */ 3224 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3225 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3226 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3227 /* We use one Rx ring. */ 3228 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3229 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3230 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3231 /* Set Rx descriptor counter. */ 3232 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3233 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3234 3235 /* 3236 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3237 * if it do not fit the buffer size. Rx return descriptor holds 3238 * a counter that indicates how many fragments were made by the 3239 * hardware. The buffer size should be multiple of 8 bytes. 3240 * Since hardware has limit on the size of buffer size, always 3241 * use the maximum value. 3242 * For strict-alignment architectures make sure to reduce buffer 3243 * size by 8 bytes to make room for alignment fixup. 3244 */ 3245 #ifndef __NO_STRICT_ALIGNMENT 3246 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3247 #else 3248 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3249 #endif 3250 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3251 3252 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3253 /* Set Rx return descriptor base addresses. */ 3254 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3255 /* We use one Rx return ring. */ 3256 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3257 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3258 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3259 /* Set Rx return descriptor counter. */ 3260 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3261 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3262 paddr = sc->alc_rdata.alc_cmb_paddr; 3263 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3264 paddr = sc->alc_rdata.alc_smb_paddr; 3265 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3266 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3267 3268 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3269 /* Reconfigure SRAM - Vendor magic. */ 3270 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3271 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3272 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3273 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3274 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3275 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3276 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3277 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3278 } 3279 3280 /* Tell hardware that we're ready to load DMA blocks. */ 3281 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3282 3283 /* Configure interrupt moderation timer. */ 3284 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3285 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3286 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3287 /* 3288 * We don't want to automatic interrupt clear as task queue 3289 * for the interrupt should know interrupt status. 3290 */ 3291 reg = MASTER_SA_TIMER_ENB; 3292 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3293 reg |= MASTER_IM_RX_TIMER_ENB; 3294 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3295 reg |= MASTER_IM_TX_TIMER_ENB; 3296 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3297 /* 3298 * Disable interrupt re-trigger timer. We don't want automatic 3299 * re-triggering of un-ACKed interrupts. 3300 */ 3301 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3302 /* Configure CMB. */ 3303 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3304 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3305 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3306 } else { 3307 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3308 } 3309 /* 3310 * Hardware can be configured to issue SMB interrupt based 3311 * on programmed interval. Since there is a callout that is 3312 * invoked for every hz in driver we use that instead of 3313 * relying on periodic SMB interrupt. 3314 */ 3315 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3316 /* Clear MAC statistics. */ 3317 alc_stats_clear(sc); 3318 3319 /* 3320 * Always use maximum frame size that controller can support. 3321 * Otherwise received frames that has larger frame length 3322 * than alc(4) MTU would be silently dropped in hardware. This 3323 * would make path-MTU discovery hard as sender wouldn't get 3324 * any responses from receiver. alc(4) supports 3325 * multi-fragmented frames on Rx path so it has no issue on 3326 * assembling fragmented frames. Using maximum frame size also 3327 * removes the need to reinitialize hardware when interface 3328 * MTU configuration was changed. 3329 * 3330 * Be conservative in what you do, be liberal in what you 3331 * accept from others - RFC 793. 3332 */ 3333 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3334 3335 /* Disable header split(?) */ 3336 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3337 3338 /* Configure IPG/IFG parameters. */ 3339 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3340 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3341 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3342 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3343 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3344 /* Set parameters for half-duplex media. */ 3345 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3346 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3347 HDPX_CFG_LCOL_MASK) | 3348 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3349 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3350 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3351 HDPX_CFG_ABEBT_MASK) | 3352 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3353 HDPX_CFG_JAMIPG_MASK)); 3354 /* 3355 * Set TSO/checksum offload threshold. For frames that is 3356 * larger than this threshold, hardware wouldn't do 3357 * TSO/checksum offloading. 3358 */ 3359 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3360 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3361 TSO_OFFLOAD_THRESH_MASK); 3362 /* Configure TxQ. */ 3363 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3364 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3365 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3366 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3367 reg >>= 1; 3368 } 3369 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3370 TXQ_CFG_TD_BURST_MASK; 3371 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3372 3373 /* Configure Rx free descriptor pre-fetching. */ 3374 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3375 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3376 RX_RD_FREE_THRESH_HI_MASK) | 3377 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3378 RX_RD_FREE_THRESH_LO_MASK)); 3379 3380 /* 3381 * Configure flow control parameters. 3382 * XON : 80% of Rx FIFO 3383 * XOFF : 30% of Rx FIFO 3384 */ 3385 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3386 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3387 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3388 rxf_hi = (reg * 8) / 10; 3389 rxf_lo = (reg * 3) / 10; 3390 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3391 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3392 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3393 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3394 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3395 } 3396 3397 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3398 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) { 3399 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3400 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3401 SERDES_PHY_CLK_SLOWDOWN); 3402 } 3403 3404 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3405 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3406 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3407 3408 /* Configure RxQ. */ 3409 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3410 RXQ_CFG_RD_BURST_MASK; 3411 reg |= RXQ_CFG_RSS_MODE_DIS; 3412 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3413 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3414 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3415 3416 /* Configure DMA parameters. */ 3417 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3418 reg |= sc->alc_rcb; 3419 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3420 reg |= DMA_CFG_CMB_ENB; 3421 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3422 reg |= DMA_CFG_SMB_ENB; 3423 else 3424 reg |= DMA_CFG_SMB_DIS; 3425 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3426 DMA_CFG_RD_BURST_SHIFT; 3427 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3428 DMA_CFG_WR_BURST_SHIFT; 3429 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3430 DMA_CFG_RD_DELAY_CNT_MASK; 3431 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3432 DMA_CFG_WR_DELAY_CNT_MASK; 3433 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3434 3435 /* 3436 * Configure Tx/Rx MACs. 3437 * - Auto-padding for short frames. 3438 * - Enable CRC generation. 3439 * Actual reconfiguration of MAC for resolved speed/duplex 3440 * is followed after detection of link establishment. 3441 * AR813x/AR815x always does checksum computation regardless 3442 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3443 * have bug in protocol field in Rx return structure so 3444 * these controllers can't handle fragmented frames. Disable 3445 * Rx checksum offloading until there is a newer controller 3446 * that has sane implementation. 3447 */ 3448 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3449 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3450 MAC_CFG_PREAMBLE_MASK); 3451 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3452 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3453 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3454 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3455 } 3456 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3457 reg |= MAC_CFG_SPEED_10_100; 3458 else 3459 reg |= MAC_CFG_SPEED_1000; 3460 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3461 3462 /* Set up the receive filter. */ 3463 alc_rxfilter(sc); 3464 alc_rxvlan(sc); 3465 3466 /* Acknowledge all pending interrupts and clear it. */ 3467 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3468 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3469 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3470 3471 sc->alc_flags &= ~ALC_FLAG_LINK; 3472 /* Switch to the current media. */ 3473 mii_mediachg(mii); 3474 3475 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3476 3477 ifp->if_flags |= IFF_RUNNING; 3478 ifp->if_flags &= ~IFF_OACTIVE; 3479 } 3480 3481 static void 3482 alc_stop(struct alc_softc *sc) 3483 { 3484 struct ifnet *ifp; 3485 struct alc_txdesc *txd; 3486 struct alc_rxdesc *rxd; 3487 uint32_t reg; 3488 int i; 3489 3490 ALC_LOCK_ASSERT(sc); 3491 /* 3492 * Mark the interface down and cancel the watchdog timer. 3493 */ 3494 ifp = sc->alc_ifp; 3495 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3496 sc->alc_flags &= ~ALC_FLAG_LINK; 3497 callout_stop(&sc->alc_tick_ch); 3498 sc->alc_watchdog_timer = 0; 3499 alc_stats_update(sc); 3500 /* Disable interrupts. */ 3501 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3502 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3503 alc_stop_queue(sc); 3504 /* Disable DMA. */ 3505 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3506 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3507 reg |= DMA_CFG_SMB_DIS; 3508 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3509 DELAY(1000); 3510 /* Stop Rx/Tx MACs. */ 3511 alc_stop_mac(sc); 3512 /* Disable interrupts which might be touched in taskq handler. */ 3513 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3514 3515 /* Reclaim Rx buffers that have been processed. */ 3516 if (sc->alc_cdata.alc_rxhead != NULL) 3517 m_freem(sc->alc_cdata.alc_rxhead); 3518 ALC_RXCHAIN_RESET(sc); 3519 /* 3520 * Free Tx/Rx mbufs still in the queues. 3521 */ 3522 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3523 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3524 if (rxd->rx_m != NULL) { 3525 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3526 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3527 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3528 rxd->rx_dmamap); 3529 m_freem(rxd->rx_m); 3530 rxd->rx_m = NULL; 3531 } 3532 } 3533 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3534 txd = &sc->alc_cdata.alc_txdesc[i]; 3535 if (txd->tx_m != NULL) { 3536 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3537 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3538 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3539 txd->tx_dmamap); 3540 m_freem(txd->tx_m); 3541 txd->tx_m = NULL; 3542 } 3543 } 3544 } 3545 3546 static void 3547 alc_stop_mac(struct alc_softc *sc) 3548 { 3549 uint32_t reg; 3550 int i; 3551 3552 ALC_LOCK_ASSERT(sc); 3553 3554 /* Disable Rx/Tx MAC. */ 3555 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3556 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3557 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3558 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3559 } 3560 for (i = ALC_TIMEOUT; i > 0; i--) { 3561 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3562 if (reg == 0) 3563 break; 3564 DELAY(10); 3565 } 3566 if (i == 0) 3567 device_printf(sc->alc_dev, 3568 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3569 } 3570 3571 static void 3572 alc_start_queue(struct alc_softc *sc) 3573 { 3574 uint32_t qcfg[] = { 3575 0, 3576 RXQ_CFG_QUEUE0_ENB, 3577 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3578 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3579 RXQ_CFG_ENB 3580 }; 3581 uint32_t cfg; 3582 3583 ALC_LOCK_ASSERT(sc); 3584 3585 /* Enable RxQ. */ 3586 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3587 cfg &= ~RXQ_CFG_ENB; 3588 cfg |= qcfg[1]; 3589 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3590 /* Enable TxQ. */ 3591 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3592 cfg |= TXQ_CFG_ENB; 3593 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3594 } 3595 3596 static void 3597 alc_stop_queue(struct alc_softc *sc) 3598 { 3599 uint32_t reg; 3600 int i; 3601 3602 ALC_LOCK_ASSERT(sc); 3603 3604 /* Disable RxQ. */ 3605 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3606 if ((reg & RXQ_CFG_ENB) != 0) { 3607 reg &= ~RXQ_CFG_ENB; 3608 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3609 } 3610 /* Disable TxQ. */ 3611 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3612 if ((reg & TXQ_CFG_ENB) == 0) { 3613 reg &= ~TXQ_CFG_ENB; 3614 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3615 } 3616 for (i = ALC_TIMEOUT; i > 0; i--) { 3617 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3618 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3619 break; 3620 DELAY(10); 3621 } 3622 if (i == 0) 3623 device_printf(sc->alc_dev, 3624 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3625 } 3626 3627 static void 3628 alc_init_tx_ring(struct alc_softc *sc) 3629 { 3630 struct alc_ring_data *rd; 3631 struct alc_txdesc *txd; 3632 int i; 3633 3634 ALC_LOCK_ASSERT(sc); 3635 3636 sc->alc_cdata.alc_tx_prod = 0; 3637 sc->alc_cdata.alc_tx_cons = 0; 3638 sc->alc_cdata.alc_tx_cnt = 0; 3639 3640 rd = &sc->alc_rdata; 3641 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3642 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3643 txd = &sc->alc_cdata.alc_txdesc[i]; 3644 txd->tx_m = NULL; 3645 } 3646 3647 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3648 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3649 } 3650 3651 static int 3652 alc_init_rx_ring(struct alc_softc *sc) 3653 { 3654 struct alc_ring_data *rd; 3655 struct alc_rxdesc *rxd; 3656 int i; 3657 3658 ALC_LOCK_ASSERT(sc); 3659 3660 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3661 sc->alc_morework = 0; 3662 rd = &sc->alc_rdata; 3663 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3664 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3665 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3666 rxd->rx_m = NULL; 3667 rxd->rx_desc = &rd->alc_rx_ring[i]; 3668 if (alc_newbuf(sc, rxd) != 0) 3669 return (ENOBUFS); 3670 } 3671 3672 /* 3673 * Since controller does not update Rx descriptors, driver 3674 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3675 * is enough to ensure coherence. 3676 */ 3677 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3678 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3679 /* Let controller know availability of new Rx buffers. */ 3680 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3681 3682 return (0); 3683 } 3684 3685 static void 3686 alc_init_rr_ring(struct alc_softc *sc) 3687 { 3688 struct alc_ring_data *rd; 3689 3690 ALC_LOCK_ASSERT(sc); 3691 3692 sc->alc_cdata.alc_rr_cons = 0; 3693 ALC_RXCHAIN_RESET(sc); 3694 3695 rd = &sc->alc_rdata; 3696 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3697 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3698 sc->alc_cdata.alc_rr_ring_map, 3699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3700 } 3701 3702 static void 3703 alc_init_cmb(struct alc_softc *sc) 3704 { 3705 struct alc_ring_data *rd; 3706 3707 ALC_LOCK_ASSERT(sc); 3708 3709 rd = &sc->alc_rdata; 3710 bzero(rd->alc_cmb, ALC_CMB_SZ); 3711 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3713 } 3714 3715 static void 3716 alc_init_smb(struct alc_softc *sc) 3717 { 3718 struct alc_ring_data *rd; 3719 3720 ALC_LOCK_ASSERT(sc); 3721 3722 rd = &sc->alc_rdata; 3723 bzero(rd->alc_smb, ALC_SMB_SZ); 3724 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3725 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3726 } 3727 3728 static void 3729 alc_rxvlan(struct alc_softc *sc) 3730 { 3731 struct ifnet *ifp; 3732 uint32_t reg; 3733 3734 ALC_LOCK_ASSERT(sc); 3735 3736 ifp = sc->alc_ifp; 3737 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3738 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3739 reg |= MAC_CFG_VLAN_TAG_STRIP; 3740 else 3741 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3742 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3743 } 3744 3745 static void 3746 alc_rxfilter(struct alc_softc *sc) 3747 { 3748 struct ifnet *ifp; 3749 struct ifmultiaddr *ifma; 3750 uint32_t crc; 3751 uint32_t mchash[2]; 3752 uint32_t rxcfg; 3753 3754 ALC_LOCK_ASSERT(sc); 3755 3756 ifp = sc->alc_ifp; 3757 3758 bzero(mchash, sizeof(mchash)); 3759 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3760 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3761 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3762 rxcfg |= MAC_CFG_BCAST; 3763 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3764 if ((ifp->if_flags & IFF_PROMISC) != 0) 3765 rxcfg |= MAC_CFG_PROMISC; 3766 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3767 rxcfg |= MAC_CFG_ALLMULTI; 3768 mchash[0] = 0xFFFFFFFF; 3769 mchash[1] = 0xFFFFFFFF; 3770 goto chipit; 3771 } 3772 3773 #if 0 3774 /* XXX */ 3775 if_maddr_rlock(ifp); 3776 #endif 3777 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3778 if (ifma->ifma_addr->sa_family != AF_LINK) 3779 continue; 3780 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3781 ifma->ifma_addr), ETHER_ADDR_LEN); 3782 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3783 } 3784 #if 0 3785 /* XXX */ 3786 if_maddr_runlock(ifp); 3787 #endif 3788 3789 chipit: 3790 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3791 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3792 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3793 } 3794 3795 static int 3796 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3797 { 3798 return (sysctl_int_range(oidp, arg1, arg2, req, 3799 ALC_PROC_MIN, ALC_PROC_MAX)); 3800 } 3801 3802 static int 3803 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3804 { 3805 3806 return (sysctl_int_range(oidp, arg1, arg2, req, 3807 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3808 } 3809