1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alc.c,v 1.6 2009/09/29 23:03:16 yongari Exp $ 28 * $DragonFly$ 29 */ 30 31 /* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/module.h> 42 #include <sys/spinlock.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_llc.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/ifq_var.h> 59 #include <net/vlan/if_vlan_var.h> 60 #include <net/vlan/if_vlan_ether.h> 61 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/ip.h> 65 #include <netinet/tcp.h> 66 67 #include <dev/netif/mii_layer/mii.h> 68 #include <dev/netif/mii_layer/miivar.h> 69 70 #include <bus/pci/pcireg.h> 71 #include <bus/pci/pcivar.h> 72 73 #include <machine/atomic.h> 74 /* 75 XXX 76 #include <machine/bus.h> 77 #include <machine/in_cksum.h> 78 */ 79 80 #include "if_alcreg.h" 81 #include "if_alcvar.h" 82 83 /* "device miibus" required. See GENERIC if you get errors here. */ 84 #include "miibus_if.h" 85 #undef ALC_USE_CUSTOM_CSUM 86 87 #ifdef ALC_USE_CUSTOM_CSUM 88 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 89 #else 90 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 91 #endif 92 #ifndef IFCAP_VLAN_HWTSO 93 #define IFCAP_VLAN_HWTSO 0 94 #endif 95 96 MODULE_DEPEND(alc, pci, 1, 1, 1); 97 MODULE_DEPEND(alc, ether, 1, 1, 1); 98 MODULE_DEPEND(alc, miibus, 1, 1, 1); 99 100 /* Tunables. */ 101 static int msi_disable = 0; 102 static int msix_disable = 0; 103 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 104 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 105 106 /* 107 * Devices supported by this driver. 108 */ 109 110 static struct alc_ident alc_ident_table[] = { 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 112 "Atheros AR8131 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 114 "Atheros AR8132 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 116 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 118 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 120 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 122 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 123 { 0, 0, 0, NULL} 124 }; 125 126 static void alc_aspm(struct alc_softc *, int); 127 static int alc_attach(device_t); 128 static int alc_check_boundary(struct alc_softc *); 129 static int alc_detach(device_t); 130 static void alc_disable_l0s_l1(struct alc_softc *); 131 static int alc_dma_alloc(struct alc_softc *); 132 static void alc_dma_free(struct alc_softc *); 133 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 134 static int alc_encap(struct alc_softc *, struct mbuf **); 135 static struct alc_ident *alc_find_ident(device_t); 136 #ifndef __NO_STRICT_ALIGNMENT 137 static struct mbuf * 138 alc_fixup_rx(struct ifnet *, struct mbuf *); 139 #endif 140 static void alc_get_macaddr(struct alc_softc *); 141 static void alc_init(void *); 142 static void alc_init_cmb(struct alc_softc *); 143 static void alc_init_locked(struct alc_softc *); 144 static void alc_init_rr_ring(struct alc_softc *); 145 static int alc_init_rx_ring(struct alc_softc *); 146 static void alc_init_smb(struct alc_softc *); 147 static void alc_init_tx_ring(struct alc_softc *); 148 static void alc_int_task(void *, int); 149 static void alc_intr(void *); 150 static int alc_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 151 static void alc_mac_config(struct alc_softc *); 152 static int alc_miibus_readreg(device_t, int, int); 153 static void alc_miibus_statchg(device_t); 154 static int alc_miibus_writereg(device_t, int, int, int); 155 static int alc_mediachange(struct ifnet *); 156 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 157 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 158 static void alc_phy_down(struct alc_softc *); 159 static void alc_phy_reset(struct alc_softc *); 160 static int alc_probe(device_t); 161 static void alc_reset(struct alc_softc *); 162 static int alc_resume(device_t); 163 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 164 static int alc_rxintr(struct alc_softc *, int); 165 static void alc_rxfilter(struct alc_softc *); 166 static void alc_rxvlan(struct alc_softc *); 167 #if 0 168 static void alc_setlinkspeed(struct alc_softc *); 169 /* XXX: WOL */ 170 static void alc_setwol(struct alc_softc *); 171 #endif 172 static int alc_shutdown(device_t); 173 static void alc_start(struct ifnet *); 174 static void alc_start_queue(struct alc_softc *); 175 static void alc_stats_clear(struct alc_softc *); 176 static void alc_stats_update(struct alc_softc *); 177 static void alc_stop(struct alc_softc *); 178 static void alc_stop_mac(struct alc_softc *); 179 static void alc_stop_queue(struct alc_softc *); 180 static int alc_suspend(device_t); 181 static void alc_sysctl_node(struct alc_softc *); 182 static void alc_tick(void *); 183 static void alc_tx_task(void *, int); 184 static void alc_txeof(struct alc_softc *); 185 static void alc_watchdog(struct alc_softc *); 186 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 187 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 188 189 static device_method_t alc_methods[] = { 190 /* Device interface. */ 191 DEVMETHOD(device_probe, alc_probe), 192 DEVMETHOD(device_attach, alc_attach), 193 DEVMETHOD(device_detach, alc_detach), 194 DEVMETHOD(device_shutdown, alc_shutdown), 195 DEVMETHOD(device_suspend, alc_suspend), 196 DEVMETHOD(device_resume, alc_resume), 197 198 /* MII interface. */ 199 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 200 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 201 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 202 203 { NULL, NULL } 204 }; 205 206 static driver_t alc_driver = { 207 "alc", 208 alc_methods, 209 sizeof(struct alc_softc) 210 }; 211 212 static devclass_t alc_devclass; 213 214 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, NULL, NULL); 215 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, NULL, NULL); 216 217 static struct resource_spec alc_res_spec_mem[] = { 218 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 219 { -1, 0, 0 } 220 }; 221 222 static struct resource_spec alc_irq_spec_legacy[] = { 223 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 224 { -1, 0, 0 } 225 }; 226 227 #ifdef OLD_MSI 228 static struct resource_spec alc_irq_spec_msi[] = { 229 { SYS_RES_IRQ, 1, RF_ACTIVE }, 230 { -1, 0, 0 } 231 }; 232 233 static struct resource_spec alc_irq_spec_msix[] = { 234 { SYS_RES_IRQ, 1, RF_ACTIVE }, 235 { -1, 0, 0 } 236 }; 237 #endif 238 239 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 240 241 static int 242 alc_miibus_readreg(device_t dev, int phy, int reg) 243 { 244 struct alc_softc *sc; 245 uint32_t v; 246 int i; 247 248 sc = device_get_softc(dev); 249 250 if (phy != sc->alc_phyaddr) 251 return (0); 252 253 /* 254 * For AR8132 fast ethernet controller, do not report 1000baseT 255 * capability to mii(4). Even though AR8132 uses the same 256 * model/revision number of F1 gigabit PHY, the PHY has no 257 * ability to establish 1000baseT link. 258 */ 259 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 260 reg == MII_EXTSR) 261 return (0); 262 263 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 264 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 265 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 266 DELAY(5); 267 v = CSR_READ_4(sc, ALC_MDIO); 268 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 269 break; 270 } 271 272 if (i == 0) { 273 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 274 return (0); 275 } 276 277 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 278 } 279 280 static int 281 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 282 { 283 struct alc_softc *sc; 284 uint32_t v; 285 int i; 286 287 sc = device_get_softc(dev); 288 289 if (phy != sc->alc_phyaddr) 290 return (0); 291 292 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 293 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 294 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 295 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 296 DELAY(5); 297 v = CSR_READ_4(sc, ALC_MDIO); 298 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 299 break; 300 } 301 302 if (i == 0) 303 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 304 305 return (0); 306 } 307 308 static void 309 alc_miibus_statchg(device_t dev) 310 { 311 struct alc_softc *sc; 312 struct mii_data *mii; 313 struct ifnet *ifp; 314 uint32_t reg; 315 316 sc = device_get_softc(dev); 317 318 mii = device_get_softc(sc->alc_miibus); 319 ifp = sc->alc_ifp; 320 if (mii == NULL || ifp == NULL || 321 (ifp->if_flags & IFF_RUNNING) == 0) 322 return; 323 324 sc->alc_flags &= ~ALC_FLAG_LINK; 325 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 326 (IFM_ACTIVE | IFM_AVALID)) { 327 switch (IFM_SUBTYPE(mii->mii_media_active)) { 328 case IFM_10_T: 329 case IFM_100_TX: 330 sc->alc_flags |= ALC_FLAG_LINK; 331 break; 332 case IFM_1000_T: 333 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 334 sc->alc_flags |= ALC_FLAG_LINK; 335 break; 336 default: 337 break; 338 } 339 } 340 alc_stop_queue(sc); 341 /* Stop Rx/Tx MACs. */ 342 alc_stop_mac(sc); 343 344 /* Program MACs with resolved speed/duplex/flow-control. */ 345 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 346 alc_start_queue(sc); 347 alc_mac_config(sc); 348 /* Re-enable Tx/Rx MACs. */ 349 reg = CSR_READ_4(sc, ALC_MAC_CFG); 350 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 351 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 352 } 353 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 354 } 355 356 static void 357 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 358 { 359 struct alc_softc *sc; 360 struct mii_data *mii; 361 362 sc = ifp->if_softc; 363 ALC_LOCK(sc); 364 if ((ifp->if_flags & IFF_UP) == 0) { 365 ALC_UNLOCK(sc); 366 return; 367 } 368 mii = device_get_softc(sc->alc_miibus); 369 370 mii_pollstat(mii); 371 ALC_UNLOCK(sc); 372 ifmr->ifm_status = mii->mii_media_status; 373 ifmr->ifm_active = mii->mii_media_active; 374 } 375 376 static int 377 alc_mediachange(struct ifnet *ifp) 378 { 379 struct alc_softc *sc; 380 struct mii_data *mii; 381 struct mii_softc *miisc; 382 int error; 383 384 sc = ifp->if_softc; 385 ALC_LOCK(sc); 386 mii = device_get_softc(sc->alc_miibus); 387 if (mii->mii_instance != 0) { 388 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 389 mii_phy_reset(miisc); 390 } 391 error = mii_mediachg(mii); 392 ALC_UNLOCK(sc); 393 394 return (error); 395 } 396 397 static struct alc_ident * 398 alc_find_ident(device_t dev) 399 { 400 struct alc_ident *ident; 401 uint16_t vendor, devid; 402 403 vendor = pci_get_vendor(dev); 404 devid = pci_get_device(dev); 405 for (ident = alc_ident_table; ident->name != NULL; ident++) { 406 if (vendor == ident->vendorid && devid == ident->deviceid) 407 return (ident); 408 } 409 return (NULL); 410 } 411 412 static int 413 alc_probe(device_t dev) 414 { 415 struct alc_ident *ident; 416 417 ident = alc_find_ident(dev); 418 if (ident != NULL) { 419 device_set_desc(dev, ident->name); 420 return (BUS_PROBE_DEFAULT); 421 } 422 return (ENXIO); 423 } 424 425 static void 426 alc_get_macaddr(struct alc_softc *sc) 427 { 428 uint32_t ea[2], opt; 429 uint16_t val; 430 int eeprom, i; 431 432 eeprom = 0; 433 opt = CSR_READ_4(sc, ALC_OPT_CFG); 434 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 435 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 436 /* 437 * EEPROM found, let TWSI reload EEPROM configuration. 438 * This will set ethernet address of controller. 439 */ 440 eeprom++; 441 switch (sc->alc_ident->deviceid) { 442 case DEVICEID_ATHEROS_AR8131: 443 case DEVICEID_ATHEROS_AR8132: 444 if ((opt & OPT_CFG_CLK_ENB) == 0) { 445 opt |= OPT_CFG_CLK_ENB; 446 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 447 CSR_READ_4(sc, ALC_OPT_CFG); 448 DELAY(1000); 449 } 450 break; 451 case DEVICEID_ATHEROS_AR8151: 452 case DEVICEID_ATHEROS_AR8151_V2: 453 case DEVICEID_ATHEROS_AR8152_B: 454 case DEVICEID_ATHEROS_AR8152_B2: 455 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 456 ALC_MII_DBG_ADDR, 0x00); 457 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 458 ALC_MII_DBG_DATA); 459 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 460 ALC_MII_DBG_DATA, val & 0xFF7F); 461 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 462 ALC_MII_DBG_ADDR, 0x3B); 463 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 464 ALC_MII_DBG_DATA); 465 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 466 ALC_MII_DBG_DATA, val | 0x0008); 467 DELAY(20); 468 break; 469 } 470 471 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 472 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 473 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 474 CSR_READ_4(sc, ALC_WOL_CFG); 475 476 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 477 TWSI_CFG_SW_LD_START); 478 479 for (i = 100; i > 0; i--) { 480 DELAY(1000); 481 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 482 TWSI_CFG_SW_LD_START) == 0) 483 break; 484 } 485 if (i == 0) 486 device_printf(sc->alc_dev, 487 "reloading EEPROM timeout!\n"); 488 } else { 489 if (bootverbose) 490 device_printf(sc->alc_dev, "EEPROM not found!\n"); 491 } 492 493 if (eeprom != 0) { 494 switch (sc->alc_ident->deviceid) { 495 case DEVICEID_ATHEROS_AR8131: 496 case DEVICEID_ATHEROS_AR8132: 497 if ((opt & OPT_CFG_CLK_ENB) != 0) { 498 opt &= ~OPT_CFG_CLK_ENB; 499 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 500 CSR_READ_4(sc, ALC_OPT_CFG); 501 DELAY(1000); 502 } 503 break; 504 case DEVICEID_ATHEROS_AR8151: 505 case DEVICEID_ATHEROS_AR8151_V2: 506 case DEVICEID_ATHEROS_AR8152_B: 507 case DEVICEID_ATHEROS_AR8152_B2: 508 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 509 ALC_MII_DBG_ADDR, 0x00); 510 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 511 ALC_MII_DBG_DATA); 512 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 513 ALC_MII_DBG_DATA, val | 0x0080); 514 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 515 ALC_MII_DBG_ADDR, 0x3B); 516 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 517 ALC_MII_DBG_DATA); 518 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 519 ALC_MII_DBG_DATA, val & 0xFFF7); 520 DELAY(20); 521 break; 522 } 523 } 524 525 ea[0] = CSR_READ_4(sc, ALC_PAR0); 526 ea[1] = CSR_READ_4(sc, ALC_PAR1); 527 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 528 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 529 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 530 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 531 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 532 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 533 } 534 535 static void 536 alc_disable_l0s_l1(struct alc_softc *sc) 537 { 538 uint32_t pmcfg; 539 540 /* Another magic from vendor. */ 541 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 542 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 543 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 544 PM_CFG_SERDES_PD_EX_L1); 545 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 546 PM_CFG_SERDES_L1_ENB; 547 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 548 } 549 550 static void 551 alc_phy_reset(struct alc_softc *sc) 552 { 553 uint16_t data; 554 555 /* Reset magic from Linux. */ 556 CSR_WRITE_2(sc, ALC_GPHY_CFG, 557 GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET); 558 CSR_READ_2(sc, ALC_GPHY_CFG); 559 DELAY(10 * 1000); 560 561 CSR_WRITE_2(sc, ALC_GPHY_CFG, 562 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 563 GPHY_CFG_SEL_ANA_RESET); 564 CSR_READ_2(sc, ALC_GPHY_CFG); 565 DELAY(10 * 1000); 566 567 /* DSP fixup, Vendor magic. */ 568 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 569 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 570 ALC_MII_DBG_ADDR, 0x000A); 571 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 572 ALC_MII_DBG_DATA); 573 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 574 ALC_MII_DBG_DATA, data & 0xDFFF); 575 } 576 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 577 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 578 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 579 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 580 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 581 ALC_MII_DBG_ADDR, 0x003B); 582 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 583 ALC_MII_DBG_DATA); 584 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 585 ALC_MII_DBG_DATA, data & 0xFFF7); 586 DELAY(20 * 1000); 587 } 588 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 589 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 590 ALC_MII_DBG_ADDR, 0x0029); 591 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 592 ALC_MII_DBG_DATA, 0x929D); 593 } 594 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 595 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 596 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 597 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 598 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 599 ALC_MII_DBG_ADDR, 0x0029); 600 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 601 ALC_MII_DBG_DATA, 0xB6DD); 602 } 603 604 /* Load DSP codes, vendor magic. */ 605 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 606 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 607 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 608 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 609 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 610 ALC_MII_DBG_DATA, data); 611 612 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 613 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 614 ANA_SERDES_EN_LCKDT; 615 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 616 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 617 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 618 ALC_MII_DBG_DATA, data); 619 620 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 621 ANA_LONG_CABLE_TH_100_MASK) | 622 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 623 ANA_SHORT_CABLE_TH_100_SHIFT) | 624 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 625 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 626 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 627 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 628 ALC_MII_DBG_DATA, data); 629 630 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 631 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 632 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 633 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 634 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 635 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 636 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 637 ALC_MII_DBG_DATA, data); 638 639 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 640 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 641 ANA_OEN_125M; 642 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 643 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 644 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 645 ALC_MII_DBG_DATA, data); 646 DELAY(1000); 647 } 648 649 static void 650 alc_phy_down(struct alc_softc *sc) 651 { 652 switch (sc->alc_ident->deviceid) { 653 case DEVICEID_ATHEROS_AR8151: 654 case DEVICEID_ATHEROS_AR8151_V2: 655 /* 656 * GPHY power down caused more problems on AR8151 v2.0. 657 * When driver is reloaded after GPHY power down, 658 * accesses to PHY/MAC registers hung the system. Only 659 * cold boot recovered from it. I'm not sure whether 660 * AR8151 v1.0 also requires this one though. I don't 661 * have AR8151 v1.0 controller in hand. 662 * The only option left is to isolate the PHY and 663 * initiates power down the PHY which in turn saves 664 * more power when driver is unloaded. 665 */ 666 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 667 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 668 break; 669 default: 670 /* Force PHY down. */ 671 CSR_WRITE_2(sc, ALC_GPHY_CFG, 672 GPHY_CFG_EXT_RESET | GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 673 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 674 GPHY_CFG_PWDOWN_HW); 675 DELAY(1000); 676 break; 677 } 678 679 } 680 681 static void 682 alc_aspm(struct alc_softc *sc, int media) 683 { 684 uint32_t pmcfg; 685 uint16_t linkcfg; 686 687 ALC_LOCK_ASSERT(sc); 688 689 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 690 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 691 (ALC_FLAG_APS | ALC_FLAG_PCIE)) { 692 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 693 PCIR_EXPRESS_LINK_CTL); 694 } else { 695 linkcfg = 0; 696 } 697 698 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 699 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 700 pmcfg |= PM_CFG_MAC_ASPM_CHK; 701 pmcfg |= PM_CFG_SERDES_ENB | PM_CFG_RBER_ENB; 702 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 703 704 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 705 /* Disable extended sync except AR8152 B v1.0 */ 706 linkcfg &= ~0x80; 707 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 708 sc->alc_rev == ATHEROS_AR8152_B_V10) 709 linkcfg |= 0x80; 710 CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, 711 linkcfg); 712 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 713 PM_CFG_HOTRST); 714 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 715 PM_CFG_L1_ENTRY_TIMER_SHIFT); 716 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 717 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 718 PM_CFG_PM_REQ_TIMER_SHIFT); 719 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 720 } 721 722 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 723 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 724 pmcfg |= PM_CFG_ASPM_L0S_ENB; 725 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 726 pmcfg |= PM_CFG_ASPM_L1_ENB; 727 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 728 if (sc->alc_ident->deviceid == 729 DEVICEID_ATHEROS_AR8152_B) { 730 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 731 } 732 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 733 PM_CFG_SERDES_PLL_L1_ENB | 734 PM_CFG_SERDES_BUDS_RX_L1_ENB); 735 pmcfg |= PM_CFG_CLK_SWH_L1; 736 if (media == IFM_100_TX || media == IFM_1000_T) { 737 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 738 switch (sc->alc_ident->deviceid) { 739 case DEVICEID_ATHEROS_AR8152_B: 740 pmcfg |= (7 << 741 PM_CFG_L1_ENTRY_TIMER_SHIFT); 742 break; 743 case DEVICEID_ATHEROS_AR8152_B2: 744 case DEVICEID_ATHEROS_AR8151_V2: 745 pmcfg |= (4 << 746 PM_CFG_L1_ENTRY_TIMER_SHIFT); 747 break; 748 default: 749 pmcfg |= (15 << 750 PM_CFG_L1_ENTRY_TIMER_SHIFT); 751 break; 752 } 753 } 754 } else { 755 pmcfg |= PM_CFG_SERDES_L1_ENB | 756 PM_CFG_SERDES_PLL_L1_ENB | 757 PM_CFG_SERDES_BUDS_RX_L1_ENB; 758 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 759 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 760 } 761 } else { 762 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 763 PM_CFG_SERDES_PLL_L1_ENB); 764 pmcfg |= PM_CFG_CLK_SWH_L1; 765 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 766 pmcfg |= PM_CFG_ASPM_L1_ENB; 767 } 768 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 769 } 770 771 static int 772 alc_attach(device_t dev) 773 { 774 struct alc_softc *sc; 775 struct ifnet *ifp; 776 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 777 uint16_t burst; 778 int base, error, i, msic, msixc, state; 779 uint32_t cap, ctl, val; 780 781 error = 0; 782 sc = device_get_softc(dev); 783 sc->alc_dev = dev; 784 785 lockinit(&sc->alc_lock, "alc_lock", 0, LK_CANRECURSE); 786 callout_init_mp(&sc->alc_tick_ch); 787 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 788 sc->alc_ident = alc_find_ident(dev); 789 790 /* Map the device. */ 791 pci_enable_busmaster(dev); 792 sc->alc_res_spec = alc_res_spec_mem; 793 sc->alc_irq_spec = alc_irq_spec_legacy; 794 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 795 if (error != 0) { 796 device_printf(dev, "cannot allocate memory resources.\n"); 797 goto fail; 798 } 799 800 /* Set PHY address. */ 801 sc->alc_phyaddr = ALC_PHY_ADDR; 802 803 /* Initialize DMA parameters. */ 804 sc->alc_dma_rd_burst = 0; 805 sc->alc_dma_wr_burst = 0; 806 sc->alc_rcb = DMA_CFG_RCB_64; 807 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) { 808 sc->alc_flags |= ALC_FLAG_PCIE; 809 sc->alc_expcap = base; 810 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); 811 sc->alc_dma_rd_burst = 812 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; 813 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; 814 if (bootverbose) { 815 device_printf(dev, "Read request size : %u bytes.\n", 816 alc_dma_burst[sc->alc_dma_rd_burst]); 817 device_printf(dev, "TLP payload size : %u bytes.\n", 818 alc_dma_burst[sc->alc_dma_wr_burst]); 819 } 820 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 821 sc->alc_dma_rd_burst = 3; 822 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 823 sc->alc_dma_wr_burst = 3; 824 /* Clear data link and flow-control protocol error. */ 825 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 826 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 827 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 828 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 829 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 830 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 831 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 832 PCIE_PHYMISC_FORCE_RCV_DET); 833 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 834 sc->alc_rev == ATHEROS_AR8152_B_V10) { 835 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 836 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 837 PCIE_PHYMISC2_SERDES_TH_MASK); 838 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 839 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 840 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 841 } 842 843 /* Disable ASPM L0S and L1. */ 844 cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); 845 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 846 ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); 847 if ((ctl & 0x08) != 0) 848 sc->alc_rcb = DMA_CFG_RCB_128; 849 if (bootverbose) 850 device_printf(dev, "RCB %u bytes\n", 851 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 852 state = ctl & 0x03; 853 if (state & 0x01) 854 sc->alc_flags |= ALC_FLAG_L0S; 855 if (state & 0x02) 856 sc->alc_flags |= ALC_FLAG_L1S; 857 if (bootverbose) 858 device_printf(sc->alc_dev, "ASPM %s %s\n", 859 aspm_state[state], 860 state == 0 ? "disabled" : "enabled"); 861 alc_disable_l0s_l1(sc); 862 } else { 863 if (bootverbose) 864 device_printf(sc->alc_dev, "no ASPM support\n"); 865 } 866 } 867 868 /* Reset PHY. */ 869 alc_phy_reset(sc); 870 871 /* Reset the ethernet controller. */ 872 alc_reset(sc); 873 874 /* 875 * One odd thing is AR8132 uses the same PHY hardware(F1 876 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 877 * the PHY supports 1000Mbps but that's not true. The PHY 878 * used in AR8132 can't establish gigabit link even if it 879 * shows the same PHY model/revision number of AR8131. 880 */ 881 switch (sc->alc_ident->deviceid) { 882 case DEVICEID_ATHEROS_AR8152_B: 883 case DEVICEID_ATHEROS_AR8152_B2: 884 sc->alc_flags |= ALC_FLAG_APS; 885 /* FALLTHROUGH */ 886 case DEVICEID_ATHEROS_AR8132: 887 sc->alc_flags |= ALC_FLAG_FASTETHER; 888 break; 889 case DEVICEID_ATHEROS_AR8151: 890 case DEVICEID_ATHEROS_AR8151_V2: 891 sc->alc_flags |= ALC_FLAG_APS; 892 /* FALLTHROUGH */ 893 default: 894 break; 895 } 896 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 897 898 /* 899 * It seems that AR813x/AR815x has silicon bug for SMB. In 900 * addition, Atheros said that enabling SMB wouldn't improve 901 * performance. However I think it's bad to access lots of 902 * registers to extract MAC statistics. 903 */ 904 sc->alc_flags |= ALC_FLAG_SMB_BUG; 905 906 /* 907 * Don't use Tx CMB. It is known to have silicon bug. 908 */ 909 sc->alc_flags |= ALC_FLAG_CMB_BUG; 910 sc->alc_rev = pci_get_revid(dev); 911 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 912 MASTER_CHIP_REV_SHIFT; 913 if (bootverbose) { 914 device_printf(dev, "PCI device revision : 0x%04x\n", 915 sc->alc_rev); 916 device_printf(dev, "Chip id/revision : 0x%04x\n", 917 sc->alc_chip_rev); 918 } 919 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 920 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 921 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 922 923 /* Allocate IRQ resources. */ 924 msixc = pci_msix_count(dev); 925 msic = pci_msi_count(dev); 926 if (bootverbose) { 927 device_printf(dev, "MSIX count : %d\n", msixc); 928 device_printf(dev, "MSI count : %d\n", msic); 929 } 930 931 #ifdef OLD_MSI 932 /* Prefer MSIX over MSI. */ 933 if (msix_disable == 0 || msi_disable == 0) { 934 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 935 pci_alloc_msix(dev, &msixc) == 0) { 936 if (msic == ALC_MSIX_MESSAGES) { 937 device_printf(dev, 938 "Using %d MSIX message(s).\n", msixc); 939 sc->alc_flags |= ALC_FLAG_MSIX; 940 sc->alc_irq_spec = alc_irq_spec_msix; 941 } else 942 pci_release_msi(dev); 943 } 944 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 945 msic == ALC_MSI_MESSAGES && 946 pci_alloc_msi(dev, &msic) == 0) { 947 if (msic == ALC_MSI_MESSAGES) { 948 device_printf(dev, 949 "Using %d MSI message(s).\n", msic); 950 sc->alc_flags |= ALC_FLAG_MSI; 951 sc->alc_irq_spec = alc_irq_spec_msi; 952 } else 953 pci_release_msi(dev); 954 } 955 } 956 #endif 957 958 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 959 if (error != 0) { 960 device_printf(dev, "cannot allocate IRQ resources.\n"); 961 goto fail; 962 } 963 964 /* Create device sysctl node. */ 965 alc_sysctl_node(sc); 966 967 if ((error = alc_dma_alloc(sc) != 0)) 968 goto fail; 969 970 /* Load station address. */ 971 alc_get_macaddr(sc); 972 973 ifp = sc->alc_ifp = &sc->arpcom.ac_if; 974 ifp->if_softc = sc; 975 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 976 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 977 ifp->if_ioctl = alc_ioctl; 978 ifp->if_start = alc_start; 979 ifp->if_init = alc_init; 980 ifp->if_snd.ifq_maxlen = ALC_TX_RING_CNT - 1; 981 ifq_set_maxlen(&ifp->if_snd, ifp->if_snd.ifq_maxlen); 982 ifq_set_ready(&ifp->if_snd); 983 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 984 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 985 #if 0 986 /* XXX: WOL */ 987 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 988 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 989 sc->alc_flags |= ALC_FLAG_PM; 990 sc->alc_pmcap = base; 991 } 992 #endif 993 ifp->if_capenable = ifp->if_capabilities; 994 995 /* Set up MII bus. */ 996 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange, 997 alc_mediastatus)) != 0) { 998 device_printf(dev, "no PHY found!\n"); 999 goto fail; 1000 } 1001 1002 ether_ifattach(ifp, sc->alc_eaddr, NULL); 1003 1004 /* VLAN capability setup. */ 1005 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1006 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 1007 ifp->if_capenable = ifp->if_capabilities; 1008 /* 1009 * XXX 1010 * It seems enabling Tx checksum offloading makes more trouble. 1011 * Sometimes the controller does not receive any frames when 1012 * Tx checksum offloading is enabled. I'm not sure whether this 1013 * is a bug in Tx checksum offloading logic or I got broken 1014 * sample boards. To safety, don't enable Tx checksum offloading 1015 * by default but give chance to users to toggle it if they know 1016 * their controllers work without problems. 1017 */ 1018 ifp->if_capenable &= ~IFCAP_TXCSUM; 1019 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1020 1021 /* Tell the upper layer(s) we support long frames. */ 1022 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1023 1024 /* Create local taskq. */ 1025 TASK_INIT(&sc->alc_tx_task, 1, alc_tx_task, ifp); 1026 sc->alc_tq = taskqueue_create("alc_taskq", M_WAITOK, 1027 taskqueue_thread_enqueue, &sc->alc_tq); 1028 if (sc->alc_tq == NULL) { 1029 device_printf(dev, "could not create taskqueue.\n"); 1030 ether_ifdetach(ifp); 1031 error = ENXIO; 1032 goto fail; 1033 } 1034 taskqueue_start_threads(&sc->alc_tq, 1, TDPRI_KERN_DAEMON, -1, "%s taskq", 1035 device_get_nameunit(sc->alc_dev)); 1036 1037 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1038 msic = ALC_MSIX_MESSAGES; 1039 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1040 msic = ALC_MSI_MESSAGES; 1041 else 1042 msic = 1; 1043 for (i = 0; i < msic; i++) { 1044 error = bus_setup_intr(dev, sc->alc_irq[i], INTR_MPSAFE, 1045 alc_intr, sc, 1046 &sc->alc_intrhand[i], NULL); 1047 if (error != 0) 1048 break; 1049 } 1050 if (error != 0) { 1051 device_printf(dev, "could not set up interrupt handler.\n"); 1052 taskqueue_free(sc->alc_tq); 1053 sc->alc_tq = NULL; 1054 ether_ifdetach(ifp); 1055 goto fail; 1056 } 1057 1058 fail: 1059 if (error != 0) 1060 alc_detach(dev); 1061 1062 return (error); 1063 } 1064 1065 static int 1066 alc_detach(device_t dev) 1067 { 1068 struct alc_softc *sc; 1069 struct ifnet *ifp; 1070 int i, msic; 1071 1072 sc = device_get_softc(dev); 1073 1074 ifp = sc->alc_ifp; 1075 if (device_is_attached(dev)) { 1076 ALC_LOCK(sc); 1077 sc->alc_flags |= ALC_FLAG_DETACH; 1078 alc_stop(sc); 1079 ALC_UNLOCK(sc); 1080 #if 0 1081 /* XXX */ 1082 callout_drain(&sc->alc_tick_ch); 1083 #endif 1084 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1085 taskqueue_drain(sc->alc_tq, &sc->alc_tx_task); 1086 ether_ifdetach(ifp); 1087 } 1088 1089 if (sc->alc_tq != NULL) { 1090 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1091 taskqueue_free(sc->alc_tq); 1092 sc->alc_tq = NULL; 1093 } 1094 1095 if (sc->alc_miibus != NULL) { 1096 device_delete_child(dev, sc->alc_miibus); 1097 sc->alc_miibus = NULL; 1098 } 1099 bus_generic_detach(dev); 1100 alc_dma_free(sc); 1101 1102 if (ifp != NULL) { 1103 // XXX? if_free(ifp); 1104 sc->alc_ifp = NULL; 1105 } 1106 1107 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1108 msic = ALC_MSIX_MESSAGES; 1109 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1110 msic = ALC_MSI_MESSAGES; 1111 else 1112 msic = 1; 1113 for (i = 0; i < msic; i++) { 1114 if (sc->alc_intrhand[i] != NULL) { 1115 bus_teardown_intr(dev, sc->alc_irq[i], 1116 sc->alc_intrhand[i]); 1117 sc->alc_intrhand[i] = NULL; 1118 } 1119 } 1120 if (sc->alc_res[0] != NULL) 1121 alc_phy_down(sc); 1122 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1123 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1124 pci_release_msi(dev); 1125 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1126 lockuninit(&sc->alc_lock); 1127 1128 return (0); 1129 } 1130 1131 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1132 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1133 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1134 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1135 1136 static void 1137 alc_sysctl_node(struct alc_softc *sc) 1138 { 1139 struct sysctl_ctx_list *ctx; 1140 struct sysctl_oid *tree; 1141 struct sysctl_oid_list *child, *parent; 1142 struct alc_hw_stats *stats; 1143 int error; 1144 1145 stats = &sc->alc_stats; 1146 ctx = &sc->alc_sysctl_ctx; 1147 sysctl_ctx_init(ctx); 1148 1149 tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw), 1150 OID_AUTO, 1151 device_get_nameunit(sc->alc_dev), 1152 CTLFLAG_RD, 0, ""); 1153 if (tree == NULL) { 1154 device_printf(sc->alc_dev, "can't add sysctl node\n"); 1155 return; 1156 } 1157 child = SYSCTL_CHILDREN(tree); 1158 1159 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1160 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1161 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1162 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1163 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1164 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1165 /* Pull in device tunables. */ 1166 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1167 error = resource_int_value(device_get_name(sc->alc_dev), 1168 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1169 if (error == 0) { 1170 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1171 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1172 device_printf(sc->alc_dev, "int_rx_mod value out of " 1173 "range; using default: %d\n", 1174 ALC_IM_RX_TIMER_DEFAULT); 1175 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1176 } 1177 } 1178 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1179 error = resource_int_value(device_get_name(sc->alc_dev), 1180 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1181 if (error == 0) { 1182 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1183 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1184 device_printf(sc->alc_dev, "int_tx_mod value out of " 1185 "range; using default: %d\n", 1186 ALC_IM_TX_TIMER_DEFAULT); 1187 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1188 } 1189 } 1190 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1191 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1192 sysctl_hw_alc_proc_limit, "I", 1193 "max number of Rx events to process"); 1194 /* Pull in device tunables. */ 1195 sc->alc_process_limit = ALC_PROC_DEFAULT; 1196 error = resource_int_value(device_get_name(sc->alc_dev), 1197 device_get_unit(sc->alc_dev), "process_limit", 1198 &sc->alc_process_limit); 1199 if (error == 0) { 1200 if (sc->alc_process_limit < ALC_PROC_MIN || 1201 sc->alc_process_limit > ALC_PROC_MAX) { 1202 device_printf(sc->alc_dev, 1203 "process_limit value out of range; " 1204 "using default: %d\n", ALC_PROC_DEFAULT); 1205 sc->alc_process_limit = ALC_PROC_DEFAULT; 1206 } 1207 } 1208 1209 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1210 NULL, "ALC statistics"); 1211 parent = SYSCTL_CHILDREN(tree); 1212 1213 /* Rx statistics. */ 1214 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1215 NULL, "Rx MAC statistics"); 1216 child = SYSCTL_CHILDREN(tree); 1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1218 &stats->rx_frames, "Good frames"); 1219 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1220 &stats->rx_bcast_frames, "Good broadcast frames"); 1221 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1222 &stats->rx_mcast_frames, "Good multicast frames"); 1223 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1224 &stats->rx_pause_frames, "Pause control frames"); 1225 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1226 &stats->rx_control_frames, "Control frames"); 1227 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1228 &stats->rx_crcerrs, "CRC errors"); 1229 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1230 &stats->rx_lenerrs, "Frames with length mismatched"); 1231 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1232 &stats->rx_bytes, "Good octets"); 1233 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1234 &stats->rx_bcast_bytes, "Good broadcast octets"); 1235 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1236 &stats->rx_mcast_bytes, "Good multicast octets"); 1237 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1238 &stats->rx_runts, "Too short frames"); 1239 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1240 &stats->rx_fragments, "Fragmented frames"); 1241 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1242 &stats->rx_pkts_64, "64 bytes frames"); 1243 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1244 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1245 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1246 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1247 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1248 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1249 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1250 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1251 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1252 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1253 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1254 &stats->rx_pkts_1519_max, "1519 to max frames"); 1255 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1256 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1257 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1258 &stats->rx_fifo_oflows, "FIFO overflows"); 1259 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1260 &stats->rx_rrs_errs, "Return status write-back errors"); 1261 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1262 &stats->rx_alignerrs, "Alignment errors"); 1263 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1264 &stats->rx_pkts_filtered, 1265 "Frames dropped due to address filtering"); 1266 1267 /* Tx statistics. */ 1268 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1269 NULL, "Tx MAC statistics"); 1270 child = SYSCTL_CHILDREN(tree); 1271 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1272 &stats->tx_frames, "Good frames"); 1273 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1274 &stats->tx_bcast_frames, "Good broadcast frames"); 1275 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1276 &stats->tx_mcast_frames, "Good multicast frames"); 1277 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1278 &stats->tx_pause_frames, "Pause control frames"); 1279 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1280 &stats->tx_control_frames, "Control frames"); 1281 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1282 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1283 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1284 &stats->tx_excess_defer, "Frames with derferrals"); 1285 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1286 &stats->tx_bytes, "Good octets"); 1287 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1288 &stats->tx_bcast_bytes, "Good broadcast octets"); 1289 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1290 &stats->tx_mcast_bytes, "Good multicast octets"); 1291 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1292 &stats->tx_pkts_64, "64 bytes frames"); 1293 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1294 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1295 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1296 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1297 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1298 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1299 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1300 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1301 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1302 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1303 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1304 &stats->tx_pkts_1519_max, "1519 to max frames"); 1305 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1306 &stats->tx_single_colls, "Single collisions"); 1307 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1308 &stats->tx_multi_colls, "Multiple collisions"); 1309 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1310 &stats->tx_late_colls, "Late collisions"); 1311 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1312 &stats->tx_excess_colls, "Excessive collisions"); 1313 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1314 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1315 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1316 &stats->tx_underrun, "FIFO underruns"); 1317 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1318 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1319 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1320 &stats->tx_lenerrs, "Frames with length mismatched"); 1321 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1322 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1323 } 1324 1325 #undef ALC_SYSCTL_STAT_ADD32 1326 #undef ALC_SYSCTL_STAT_ADD64 1327 1328 struct alc_dmamap_arg { 1329 bus_addr_t alc_busaddr; 1330 }; 1331 1332 static void 1333 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1334 { 1335 struct alc_dmamap_arg *ctx; 1336 1337 if (error != 0) 1338 return; 1339 1340 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1341 1342 ctx = (struct alc_dmamap_arg *)arg; 1343 ctx->alc_busaddr = segs[0].ds_addr; 1344 } 1345 1346 /* 1347 * Normal and high Tx descriptors shares single Tx high address. 1348 * Four Rx descriptor/return rings and CMB shares the same Rx 1349 * high address. 1350 */ 1351 static int 1352 alc_check_boundary(struct alc_softc *sc) 1353 { 1354 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1355 1356 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1357 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1358 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1359 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1360 1361 /* 4GB boundary crossing is not allowed. */ 1362 if ((ALC_ADDR_HI(rx_ring_end) != 1363 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1364 (ALC_ADDR_HI(rr_ring_end) != 1365 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1366 (ALC_ADDR_HI(cmb_end) != 1367 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1368 (ALC_ADDR_HI(tx_ring_end) != 1369 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1370 return (EFBIG); 1371 /* 1372 * Make sure Rx return descriptor/Rx descriptor/CMB use 1373 * the same high address. 1374 */ 1375 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1376 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1377 return (EFBIG); 1378 1379 return (0); 1380 } 1381 1382 static int 1383 alc_dma_alloc(struct alc_softc *sc) 1384 { 1385 struct alc_txdesc *txd; 1386 struct alc_rxdesc *rxd; 1387 bus_addr_t lowaddr; 1388 struct alc_dmamap_arg ctx; 1389 int error, i; 1390 1391 lowaddr = BUS_SPACE_MAXADDR; 1392 again: 1393 /* Create parent DMA tag. */ 1394 error = bus_dma_tag_create( 1395 sc->alc_cdata.alc_parent_tag, /* parent */ 1396 1, 0, /* alignment, boundary */ 1397 lowaddr, /* lowaddr */ 1398 BUS_SPACE_MAXADDR, /* highaddr */ 1399 NULL, NULL, /* filter, filterarg */ 1400 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1401 0, /* nsegments */ 1402 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1403 0, /* flags */ 1404 &sc->alc_cdata.alc_parent_tag); 1405 if (error != 0) { 1406 device_printf(sc->alc_dev, 1407 "could not create parent DMA tag.\n"); 1408 goto fail; 1409 } 1410 1411 /* Create DMA tag for Tx descriptor ring. */ 1412 error = bus_dma_tag_create( 1413 sc->alc_cdata.alc_parent_tag, /* parent */ 1414 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1415 BUS_SPACE_MAXADDR, /* lowaddr */ 1416 BUS_SPACE_MAXADDR, /* highaddr */ 1417 NULL, NULL, /* filter, filterarg */ 1418 ALC_TX_RING_SZ, /* maxsize */ 1419 1, /* nsegments */ 1420 ALC_TX_RING_SZ, /* maxsegsize */ 1421 0, /* flags */ 1422 &sc->alc_cdata.alc_tx_ring_tag); 1423 if (error != 0) { 1424 device_printf(sc->alc_dev, 1425 "could not create Tx ring DMA tag.\n"); 1426 goto fail; 1427 } 1428 1429 /* Create DMA tag for Rx free descriptor ring. */ 1430 error = bus_dma_tag_create( 1431 sc->alc_cdata.alc_parent_tag, /* parent */ 1432 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1433 BUS_SPACE_MAXADDR, /* lowaddr */ 1434 BUS_SPACE_MAXADDR, /* highaddr */ 1435 NULL, NULL, /* filter, filterarg */ 1436 ALC_RX_RING_SZ, /* maxsize */ 1437 1, /* nsegments */ 1438 ALC_RX_RING_SZ, /* maxsegsize */ 1439 0, /* flags */ 1440 &sc->alc_cdata.alc_rx_ring_tag); 1441 if (error != 0) { 1442 device_printf(sc->alc_dev, 1443 "could not create Rx ring DMA tag.\n"); 1444 goto fail; 1445 } 1446 /* Create DMA tag for Rx return descriptor ring. */ 1447 error = bus_dma_tag_create( 1448 sc->alc_cdata.alc_parent_tag, /* parent */ 1449 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1450 BUS_SPACE_MAXADDR, /* lowaddr */ 1451 BUS_SPACE_MAXADDR, /* highaddr */ 1452 NULL, NULL, /* filter, filterarg */ 1453 ALC_RR_RING_SZ, /* maxsize */ 1454 1, /* nsegments */ 1455 ALC_RR_RING_SZ, /* maxsegsize */ 1456 0, /* flags */ 1457 &sc->alc_cdata.alc_rr_ring_tag); 1458 if (error != 0) { 1459 device_printf(sc->alc_dev, 1460 "could not create Rx return ring DMA tag.\n"); 1461 goto fail; 1462 } 1463 1464 /* Create DMA tag for coalescing message block. */ 1465 error = bus_dma_tag_create( 1466 sc->alc_cdata.alc_parent_tag, /* parent */ 1467 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1468 BUS_SPACE_MAXADDR, /* lowaddr */ 1469 BUS_SPACE_MAXADDR, /* highaddr */ 1470 NULL, NULL, /* filter, filterarg */ 1471 ALC_CMB_SZ, /* maxsize */ 1472 1, /* nsegments */ 1473 ALC_CMB_SZ, /* maxsegsize */ 1474 0, /* flags */ 1475 &sc->alc_cdata.alc_cmb_tag); 1476 if (error != 0) { 1477 device_printf(sc->alc_dev, 1478 "could not create CMB DMA tag.\n"); 1479 goto fail; 1480 } 1481 /* Create DMA tag for status message block. */ 1482 error = bus_dma_tag_create( 1483 sc->alc_cdata.alc_parent_tag, /* parent */ 1484 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1485 BUS_SPACE_MAXADDR, /* lowaddr */ 1486 BUS_SPACE_MAXADDR, /* highaddr */ 1487 NULL, NULL, /* filter, filterarg */ 1488 ALC_SMB_SZ, /* maxsize */ 1489 1, /* nsegments */ 1490 ALC_SMB_SZ, /* maxsegsize */ 1491 0, /* flags */ 1492 &sc->alc_cdata.alc_smb_tag); 1493 if (error != 0) { 1494 device_printf(sc->alc_dev, 1495 "could not create SMB DMA tag.\n"); 1496 goto fail; 1497 } 1498 1499 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1500 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1501 (void **)&sc->alc_rdata.alc_tx_ring, 1502 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1503 &sc->alc_cdata.alc_tx_ring_map); 1504 if (error != 0) { 1505 device_printf(sc->alc_dev, 1506 "could not allocate DMA'able memory for Tx ring.\n"); 1507 goto fail; 1508 } 1509 ctx.alc_busaddr = 0; 1510 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1511 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1512 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1513 if (error != 0 || ctx.alc_busaddr == 0) { 1514 device_printf(sc->alc_dev, 1515 "could not load DMA'able memory for Tx ring.\n"); 1516 goto fail; 1517 } 1518 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1519 1520 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1521 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1522 (void **)&sc->alc_rdata.alc_rx_ring, 1523 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1524 &sc->alc_cdata.alc_rx_ring_map); 1525 if (error != 0) { 1526 device_printf(sc->alc_dev, 1527 "could not allocate DMA'able memory for Rx ring.\n"); 1528 goto fail; 1529 } 1530 ctx.alc_busaddr = 0; 1531 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1532 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1533 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1534 if (error != 0 || ctx.alc_busaddr == 0) { 1535 device_printf(sc->alc_dev, 1536 "could not load DMA'able memory for Rx ring.\n"); 1537 goto fail; 1538 } 1539 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1540 1541 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1542 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1543 (void **)&sc->alc_rdata.alc_rr_ring, 1544 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1545 &sc->alc_cdata.alc_rr_ring_map); 1546 if (error != 0) { 1547 device_printf(sc->alc_dev, 1548 "could not allocate DMA'able memory for Rx return ring.\n"); 1549 goto fail; 1550 } 1551 ctx.alc_busaddr = 0; 1552 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1553 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1554 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1555 if (error != 0 || ctx.alc_busaddr == 0) { 1556 device_printf(sc->alc_dev, 1557 "could not load DMA'able memory for Tx ring.\n"); 1558 goto fail; 1559 } 1560 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1561 1562 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1563 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1564 (void **)&sc->alc_rdata.alc_cmb, 1565 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1566 &sc->alc_cdata.alc_cmb_map); 1567 if (error != 0) { 1568 device_printf(sc->alc_dev, 1569 "could not allocate DMA'able memory for CMB.\n"); 1570 goto fail; 1571 } 1572 ctx.alc_busaddr = 0; 1573 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1574 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1575 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1576 if (error != 0 || ctx.alc_busaddr == 0) { 1577 device_printf(sc->alc_dev, 1578 "could not load DMA'able memory for CMB.\n"); 1579 goto fail; 1580 } 1581 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1582 1583 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1584 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1585 (void **)&sc->alc_rdata.alc_smb, 1586 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1587 &sc->alc_cdata.alc_smb_map); 1588 if (error != 0) { 1589 device_printf(sc->alc_dev, 1590 "could not allocate DMA'able memory for SMB.\n"); 1591 goto fail; 1592 } 1593 ctx.alc_busaddr = 0; 1594 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1595 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1596 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1597 if (error != 0 || ctx.alc_busaddr == 0) { 1598 device_printf(sc->alc_dev, 1599 "could not load DMA'able memory for CMB.\n"); 1600 goto fail; 1601 } 1602 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1603 1604 /* Make sure we've not crossed 4GB boundary. */ 1605 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1606 (error = alc_check_boundary(sc)) != 0) { 1607 device_printf(sc->alc_dev, "4GB boundary crossed, " 1608 "switching to 32bit DMA addressing mode.\n"); 1609 alc_dma_free(sc); 1610 /* 1611 * Limit max allowable DMA address space to 32bit 1612 * and try again. 1613 */ 1614 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1615 goto again; 1616 } 1617 1618 /* 1619 * Create Tx buffer parent tag. 1620 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1621 * so it needs separate parent DMA tag as parent DMA address 1622 * space could be restricted to be within 32bit address space 1623 * by 4GB boundary crossing. 1624 */ 1625 error = bus_dma_tag_create( 1626 sc->alc_cdata.alc_parent_tag, /* parent */ 1627 1, 0, /* alignment, boundary */ 1628 BUS_SPACE_MAXADDR, /* lowaddr */ 1629 BUS_SPACE_MAXADDR, /* highaddr */ 1630 NULL, NULL, /* filter, filterarg */ 1631 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1632 0, /* nsegments */ 1633 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1634 0, /* flags */ 1635 &sc->alc_cdata.alc_buffer_tag); 1636 if (error != 0) { 1637 device_printf(sc->alc_dev, 1638 "could not create parent buffer DMA tag.\n"); 1639 goto fail; 1640 } 1641 1642 /* Create DMA tag for Tx buffers. */ 1643 error = bus_dma_tag_create( 1644 sc->alc_cdata.alc_buffer_tag, /* parent */ 1645 1, 0, /* alignment, boundary */ 1646 BUS_SPACE_MAXADDR, /* lowaddr */ 1647 BUS_SPACE_MAXADDR, /* highaddr */ 1648 NULL, NULL, /* filter, filterarg */ 1649 ALC_TSO_MAXSIZE, /* maxsize */ 1650 ALC_MAXTXSEGS, /* nsegments */ 1651 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1652 0, /* flags */ 1653 &sc->alc_cdata.alc_tx_tag); 1654 if (error != 0) { 1655 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1656 goto fail; 1657 } 1658 1659 /* Create DMA tag for Rx buffers. */ 1660 error = bus_dma_tag_create( 1661 sc->alc_cdata.alc_buffer_tag, /* parent */ 1662 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1663 BUS_SPACE_MAXADDR, /* lowaddr */ 1664 BUS_SPACE_MAXADDR, /* highaddr */ 1665 NULL, NULL, /* filter, filterarg */ 1666 MCLBYTES, /* maxsize */ 1667 1, /* nsegments */ 1668 MCLBYTES, /* maxsegsize */ 1669 0, /* flags */ 1670 &sc->alc_cdata.alc_rx_tag); 1671 if (error != 0) { 1672 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1673 goto fail; 1674 } 1675 /* Create DMA maps for Tx buffers. */ 1676 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1677 txd = &sc->alc_cdata.alc_txdesc[i]; 1678 txd->tx_m = NULL; 1679 txd->tx_dmamap = NULL; 1680 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 1681 BUS_DMA_WAITOK, &txd->tx_dmamap); 1682 if (error != 0) { 1683 device_printf(sc->alc_dev, 1684 "could not create Tx dmamap.\n"); 1685 goto fail; 1686 } 1687 } 1688 /* Create DMA maps for Rx buffers. */ 1689 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1690 BUS_DMA_WAITOK, 1691 &sc->alc_cdata.alc_rx_sparemap); 1692 if (error) { 1693 device_printf(sc->alc_dev, 1694 "could not create spare Rx dmamap.\n"); 1695 goto fail; 1696 } 1697 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1698 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1699 rxd->rx_m = NULL; 1700 rxd->rx_dmamap = NULL; 1701 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 1702 BUS_DMA_WAITOK, 1703 &rxd->rx_dmamap); 1704 if (error != 0) { 1705 device_printf(sc->alc_dev, 1706 "could not create Rx dmamap.\n"); 1707 goto fail; 1708 } 1709 } 1710 1711 fail: 1712 return (error); 1713 } 1714 1715 static void 1716 alc_dma_free(struct alc_softc *sc) 1717 { 1718 struct alc_txdesc *txd; 1719 struct alc_rxdesc *rxd; 1720 int i; 1721 1722 /* Tx buffers. */ 1723 if (sc->alc_cdata.alc_tx_tag != NULL) { 1724 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1725 txd = &sc->alc_cdata.alc_txdesc[i]; 1726 if (txd->tx_dmamap != NULL) { 1727 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1728 txd->tx_dmamap); 1729 txd->tx_dmamap = NULL; 1730 } 1731 } 1732 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1733 sc->alc_cdata.alc_tx_tag = NULL; 1734 } 1735 /* Rx buffers */ 1736 if (sc->alc_cdata.alc_rx_tag != NULL) { 1737 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1738 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1739 if (rxd->rx_dmamap != NULL) { 1740 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1741 rxd->rx_dmamap); 1742 rxd->rx_dmamap = NULL; 1743 } 1744 } 1745 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1746 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1747 sc->alc_cdata.alc_rx_sparemap); 1748 sc->alc_cdata.alc_rx_sparemap = NULL; 1749 } 1750 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1751 sc->alc_cdata.alc_rx_tag = NULL; 1752 } 1753 /* Tx descriptor ring. */ 1754 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1755 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1756 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1757 sc->alc_cdata.alc_tx_ring_map); 1758 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1759 sc->alc_rdata.alc_tx_ring != NULL) 1760 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1761 sc->alc_rdata.alc_tx_ring, 1762 sc->alc_cdata.alc_tx_ring_map); 1763 sc->alc_rdata.alc_tx_ring = NULL; 1764 sc->alc_cdata.alc_tx_ring_map = NULL; 1765 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1766 sc->alc_cdata.alc_tx_ring_tag = NULL; 1767 } 1768 /* Rx ring. */ 1769 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1770 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1771 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1772 sc->alc_cdata.alc_rx_ring_map); 1773 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1774 sc->alc_rdata.alc_rx_ring != NULL) 1775 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1776 sc->alc_rdata.alc_rx_ring, 1777 sc->alc_cdata.alc_rx_ring_map); 1778 sc->alc_rdata.alc_rx_ring = NULL; 1779 sc->alc_cdata.alc_rx_ring_map = NULL; 1780 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1781 sc->alc_cdata.alc_rx_ring_tag = NULL; 1782 } 1783 /* Rx return ring. */ 1784 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1785 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1786 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1787 sc->alc_cdata.alc_rr_ring_map); 1788 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1789 sc->alc_rdata.alc_rr_ring != NULL) 1790 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1791 sc->alc_rdata.alc_rr_ring, 1792 sc->alc_cdata.alc_rr_ring_map); 1793 sc->alc_rdata.alc_rr_ring = NULL; 1794 sc->alc_cdata.alc_rr_ring_map = NULL; 1795 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1796 sc->alc_cdata.alc_rr_ring_tag = NULL; 1797 } 1798 /* CMB block */ 1799 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1800 if (sc->alc_cdata.alc_cmb_map != NULL) 1801 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1802 sc->alc_cdata.alc_cmb_map); 1803 if (sc->alc_cdata.alc_cmb_map != NULL && 1804 sc->alc_rdata.alc_cmb != NULL) 1805 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1806 sc->alc_rdata.alc_cmb, 1807 sc->alc_cdata.alc_cmb_map); 1808 sc->alc_rdata.alc_cmb = NULL; 1809 sc->alc_cdata.alc_cmb_map = NULL; 1810 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1811 sc->alc_cdata.alc_cmb_tag = NULL; 1812 } 1813 /* SMB block */ 1814 if (sc->alc_cdata.alc_smb_tag != NULL) { 1815 if (sc->alc_cdata.alc_smb_map != NULL) 1816 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1817 sc->alc_cdata.alc_smb_map); 1818 if (sc->alc_cdata.alc_smb_map != NULL && 1819 sc->alc_rdata.alc_smb != NULL) 1820 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1821 sc->alc_rdata.alc_smb, 1822 sc->alc_cdata.alc_smb_map); 1823 sc->alc_rdata.alc_smb = NULL; 1824 sc->alc_cdata.alc_smb_map = NULL; 1825 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1826 sc->alc_cdata.alc_smb_tag = NULL; 1827 } 1828 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1829 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1830 sc->alc_cdata.alc_buffer_tag = NULL; 1831 } 1832 if (sc->alc_cdata.alc_parent_tag != NULL) { 1833 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1834 sc->alc_cdata.alc_parent_tag = NULL; 1835 } 1836 } 1837 1838 static int 1839 alc_shutdown(device_t dev) 1840 { 1841 1842 return (alc_suspend(dev)); 1843 } 1844 1845 #if 0 1846 /* XXX: LINK SPEED */ 1847 /* 1848 * Note, this driver resets the link speed to 10/100Mbps by 1849 * restarting auto-negotiation in suspend/shutdown phase but we 1850 * don't know whether that auto-negotiation would succeed or not 1851 * as driver has no control after powering off/suspend operation. 1852 * If the renegotiation fail WOL may not work. Running at 1Gbps 1853 * will draw more power than 375mA at 3.3V which is specified in 1854 * PCI specification and that would result in complete 1855 * shutdowning power to ethernet controller. 1856 * 1857 * TODO 1858 * Save current negotiated media speed/duplex/flow-control to 1859 * softc and restore the same link again after resuming. PHY 1860 * handling such as power down/resetting to 100Mbps may be better 1861 * handled in suspend method in phy driver. 1862 */ 1863 static void 1864 alc_setlinkspeed(struct alc_softc *sc) 1865 { 1866 struct mii_data *mii; 1867 int aneg, i; 1868 1869 mii = device_get_softc(sc->alc_miibus); 1870 mii_pollstat(mii); 1871 aneg = 0; 1872 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1873 (IFM_ACTIVE | IFM_AVALID)) { 1874 switch IFM_SUBTYPE(mii->mii_media_active) { 1875 case IFM_10_T: 1876 case IFM_100_TX: 1877 return; 1878 case IFM_1000_T: 1879 aneg++; 1880 break; 1881 default: 1882 break; 1883 } 1884 } 1885 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1886 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1887 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1888 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1889 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1890 DELAY(1000); 1891 if (aneg != 0) { 1892 /* 1893 * Poll link state until alc(4) get a 10/100Mbps link. 1894 */ 1895 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1896 mii_pollstat(mii); 1897 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1898 == (IFM_ACTIVE | IFM_AVALID)) { 1899 switch (IFM_SUBTYPE( 1900 mii->mii_media_active)) { 1901 case IFM_10_T: 1902 case IFM_100_TX: 1903 alc_mac_config(sc); 1904 return; 1905 default: 1906 break; 1907 } 1908 } 1909 ALC_UNLOCK(sc); 1910 pause("alclnk", hz); 1911 ALC_LOCK(sc); 1912 } 1913 if (i == MII_ANEGTICKS_GIGE) 1914 device_printf(sc->alc_dev, 1915 "establishing a link failed, WOL may not work!"); 1916 } 1917 /* 1918 * No link, force MAC to have 100Mbps, full-duplex link. 1919 * This is the last resort and may/may not work. 1920 */ 1921 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1922 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1923 alc_mac_config(sc); 1924 } 1925 #endif 1926 1927 #if 0 1928 /* XXX: WOL */ 1929 static void 1930 alc_setwol(struct alc_softc *sc) 1931 { 1932 struct ifnet *ifp; 1933 uint32_t reg, pmcs; 1934 uint16_t pmstat; 1935 1936 ALC_LOCK_ASSERT(sc); 1937 1938 alc_disable_l0s_l1(sc); 1939 ifp = sc->alc_ifp; 1940 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1941 /* Disable WOL. */ 1942 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1943 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1944 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1945 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1946 /* Force PHY power down. */ 1947 alc_phy_down(sc); 1948 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1949 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1950 return; 1951 } 1952 1953 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1954 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1955 alc_setlinkspeed(sc); 1956 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1957 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1958 } 1959 1960 pmcs = 0; 1961 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1962 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1963 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1964 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1965 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1966 MAC_CFG_BCAST); 1967 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1968 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1969 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1970 reg |= MAC_CFG_RX_ENB; 1971 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1972 1973 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1974 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1975 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1976 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1977 /* WOL disabled, PHY power down. */ 1978 alc_phy_down(sc); 1979 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1980 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1981 1982 } 1983 /* Request PME. */ 1984 pmstat = pci_read_config(sc->alc_dev, 1985 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1986 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1987 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1988 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1989 pci_write_config(sc->alc_dev, 1990 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1991 } 1992 #endif 1993 1994 static int 1995 alc_suspend(device_t dev) 1996 { 1997 struct alc_softc *sc; 1998 1999 sc = device_get_softc(dev); 2000 2001 ALC_LOCK(sc); 2002 alc_stop(sc); 2003 #if 0 2004 /* XXX: WOL */ 2005 alc_setwol(sc); 2006 #endif 2007 ALC_UNLOCK(sc); 2008 2009 return (0); 2010 } 2011 2012 static int 2013 alc_resume(device_t dev) 2014 { 2015 struct alc_softc *sc; 2016 struct ifnet *ifp; 2017 uint16_t pmstat; 2018 2019 sc = device_get_softc(dev); 2020 2021 ALC_LOCK(sc); 2022 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2023 /* Disable PME and clear PME status. */ 2024 pmstat = pci_read_config(sc->alc_dev, 2025 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2026 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2027 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2028 pci_write_config(sc->alc_dev, 2029 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2030 } 2031 } 2032 /* Reset PHY. */ 2033 alc_phy_reset(sc); 2034 ifp = sc->alc_ifp; 2035 if ((ifp->if_flags & IFF_UP) != 0) { 2036 ifp->if_flags &= ~IFF_RUNNING; 2037 alc_init_locked(sc); 2038 } 2039 ALC_UNLOCK(sc); 2040 2041 return (0); 2042 } 2043 2044 static int 2045 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2046 { 2047 struct alc_txdesc *txd, *txd_last; 2048 struct tx_desc *desc; 2049 struct mbuf *m; 2050 struct ip *ip; 2051 struct tcphdr *tcp; 2052 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2053 bus_dmamap_t map; 2054 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2055 int error, idx, nsegs, prod; 2056 2057 ALC_LOCK_ASSERT(sc); 2058 2059 M_ASSERTPKTHDR((*m_head)); 2060 2061 m = *m_head; 2062 ip = NULL; 2063 tcp = NULL; 2064 ip_off = poff = 0; 2065 #if 0 2066 /* XXX: TSO */ 2067 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2068 /* 2069 * AR813x/AR815x requires offset of TCP/UDP header in its 2070 * Tx descriptor to perform Tx checksum offloading. TSO 2071 * also requires TCP header offset and modification of 2072 * IP/TCP header. This kind of operation takes many CPU 2073 * cycles on FreeBSD so fast host CPU is required to get 2074 * smooth TSO performance. 2075 */ 2076 struct ether_header *eh; 2077 2078 if (M_WRITABLE(m) == 0) { 2079 /* Get a writable copy. */ 2080 m = m_dup(*m_head, MB_DONTWAIT); 2081 /* Release original mbufs. */ 2082 m_freem(*m_head); 2083 if (m == NULL) { 2084 *m_head = NULL; 2085 return (ENOBUFS); 2086 } 2087 *m_head = m; 2088 } 2089 2090 ip_off = sizeof(struct ether_header); 2091 m = m_pullup(m, ip_off + sizeof(struct ip)); 2092 if (m == NULL) { 2093 *m_head = NULL; 2094 return (ENOBUFS); 2095 } 2096 eh = mtod(m, struct ether_header *); 2097 /* 2098 * Check if hardware VLAN insertion is off. 2099 * Additional check for LLC/SNAP frame? 2100 */ 2101 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2102 ip_off = sizeof(struct ether_vlan_header); 2103 m = m_pullup(m, ip_off); 2104 if (m == NULL) { 2105 *m_head = NULL; 2106 return (ENOBUFS); 2107 } 2108 } 2109 m = m_pullup(m, ip_off + sizeof(struct ip)); 2110 if (m == NULL) { 2111 *m_head = NULL; 2112 return (ENOBUFS); 2113 } 2114 ip = (struct ip *)(mtod(m, char *) + ip_off); 2115 poff = ip_off + (ip->ip_hl << 2); 2116 2117 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2118 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2119 if (m == NULL) { 2120 *m_head = NULL; 2121 return (ENOBUFS); 2122 } 2123 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2124 m = m_pullup(m, poff + (tcp->th_off << 2)); 2125 if (m == NULL) { 2126 *m_head = NULL; 2127 return (ENOBUFS); 2128 } 2129 /* 2130 * Due to strict adherence of Microsoft NDIS 2131 * Large Send specification, hardware expects 2132 * a pseudo TCP checksum inserted by upper 2133 * stack. Unfortunately the pseudo TCP 2134 * checksum that NDIS refers to does not include 2135 * TCP payload length so driver should recompute 2136 * the pseudo checksum here. Hopefully this 2137 * wouldn't be much burden on modern CPUs. 2138 * 2139 * Reset IP checksum and recompute TCP pseudo 2140 * checksum as NDIS specification said. 2141 */ 2142 ip->ip_sum = 0; 2143 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2144 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2145 } 2146 *m_head = m; 2147 } 2148 #endif /* TSO */ 2149 2150 prod = sc->alc_cdata.alc_tx_prod; 2151 txd = &sc->alc_cdata.alc_txdesc[prod]; 2152 txd_last = txd; 2153 map = txd->tx_dmamap; 2154 2155 error = bus_dmamap_load_mbuf_defrag( 2156 sc->alc_cdata.alc_tx_tag, map, m_head, 2157 txsegs, ALC_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT); 2158 if (error) { 2159 m_freem(*m_head); 2160 *m_head = NULL; 2161 return (error); 2162 } 2163 if (nsegs == 0) { 2164 m_freem(*m_head); 2165 *m_head = NULL; 2166 return (EIO); 2167 } 2168 2169 /* Check descriptor overrun. */ 2170 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2171 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2172 return (ENOBUFS); 2173 } 2174 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2175 2176 m = *m_head; 2177 cflags = TD_ETHERNET; 2178 vtag = 0; 2179 desc = NULL; 2180 idx = 0; 2181 /* Configure VLAN hardware tag insertion. */ 2182 if ((m->m_flags & M_VLANTAG) != 0) { 2183 vtag = htons(m->m_pkthdr.ether_vlantag); 2184 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2185 cflags |= TD_INS_VLAN_TAG; 2186 } 2187 /* Configure Tx checksum offload. */ 2188 if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2189 #ifdef ALC_USE_CUSTOM_CSUM 2190 cflags |= TD_CUSTOM_CSUM; 2191 /* Set checksum start offset. */ 2192 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2193 TD_PLOAD_OFFSET_MASK; 2194 /* Set checksum insertion position of TCP/UDP. */ 2195 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2196 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2197 #else 2198 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2199 cflags |= TD_IPCSUM; 2200 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2201 cflags |= TD_TCPCSUM; 2202 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2203 cflags |= TD_UDPCSUM; 2204 /* Set TCP/UDP header offset. */ 2205 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2206 TD_L4HDR_OFFSET_MASK; 2207 #endif 2208 } else if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2209 /* Request TSO and set MSS. */ 2210 cflags |= TD_TSO | TD_TSO_DESCV1; 2211 #if 0 2212 /* XXX: TSO */ 2213 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2214 TD_MSS_MASK; 2215 /* Set TCP header offset. */ 2216 #endif 2217 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2218 TD_TCPHDR_OFFSET_MASK; 2219 /* 2220 * AR813x/AR815x requires the first buffer should 2221 * only hold IP/TCP header data. Payload should 2222 * be handled in other descriptors. 2223 */ 2224 hdrlen = poff + (tcp->th_off << 2); 2225 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2226 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2227 desc->flags = htole32(cflags); 2228 desc->addr = htole64(txsegs[0].ds_addr); 2229 sc->alc_cdata.alc_tx_cnt++; 2230 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2231 if (m->m_len - hdrlen > 0) { 2232 /* Handle remaining payload of the first fragment. */ 2233 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2234 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2235 vtag)); 2236 desc->flags = htole32(cflags); 2237 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2238 sc->alc_cdata.alc_tx_cnt++; 2239 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2240 } 2241 /* Handle remaining fragments. */ 2242 idx = 1; 2243 } 2244 for (; idx < nsegs; idx++) { 2245 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2246 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2247 desc->flags = htole32(cflags); 2248 desc->addr = htole64(txsegs[idx].ds_addr); 2249 sc->alc_cdata.alc_tx_cnt++; 2250 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2251 } 2252 /* Update producer index. */ 2253 sc->alc_cdata.alc_tx_prod = prod; 2254 2255 /* Finally set EOP on the last descriptor. */ 2256 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2257 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2258 desc->flags |= htole32(TD_EOP); 2259 2260 /* Swap dmamap of the first and the last. */ 2261 txd = &sc->alc_cdata.alc_txdesc[prod]; 2262 map = txd_last->tx_dmamap; 2263 txd_last->tx_dmamap = txd->tx_dmamap; 2264 txd->tx_dmamap = map; 2265 txd->tx_m = m; 2266 2267 return (0); 2268 } 2269 2270 static void 2271 alc_tx_task(void *arg, int pending) 2272 { 2273 struct ifnet *ifp; 2274 2275 ifp = (struct ifnet *)arg; 2276 alc_start(ifp); 2277 } 2278 2279 static void 2280 alc_start(struct ifnet *ifp) 2281 { 2282 struct alc_softc *sc; 2283 struct mbuf *m_head; 2284 int enq; 2285 2286 sc = ifp->if_softc; 2287 2288 ALC_LOCK(sc); 2289 2290 /* Reclaim transmitted frames. */ 2291 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2292 alc_txeof(sc); 2293 2294 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 2295 ALC_UNLOCK(sc); 2296 return; 2297 } 2298 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2299 ifq_purge(&ifp->if_snd); 2300 ALC_UNLOCK(sc); 2301 return; 2302 } 2303 2304 for (enq = 0; !ifq_is_empty(&ifp->if_snd); ) { 2305 m_head = ifq_dequeue(&ifp->if_snd, NULL); 2306 if (m_head == NULL) 2307 break; 2308 /* 2309 * Pack the data into the transmit ring. If we 2310 * don't have room, set the OACTIVE flag and wait 2311 * for the NIC to drain the ring. 2312 */ 2313 if (alc_encap(sc, &m_head)) { 2314 if (m_head == NULL) 2315 break; 2316 ifq_prepend(&ifp->if_snd, m_head); 2317 ifp->if_flags |= IFF_OACTIVE; 2318 break; 2319 } 2320 2321 enq++; 2322 /* 2323 * If there's a BPF listener, bounce a copy of this frame 2324 * to him. 2325 */ 2326 ETHER_BPF_MTAP(ifp, m_head); 2327 } 2328 2329 if (enq > 0) { 2330 /* Sync descriptors. */ 2331 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2332 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2333 /* Kick. Assume we're using normal Tx priority queue. */ 2334 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2335 (sc->alc_cdata.alc_tx_prod << 2336 MBOX_TD_PROD_LO_IDX_SHIFT) & 2337 MBOX_TD_PROD_LO_IDX_MASK); 2338 /* Set a timeout in case the chip goes out to lunch. */ 2339 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2340 } 2341 2342 ALC_UNLOCK(sc); 2343 } 2344 2345 static void 2346 alc_watchdog(struct alc_softc *sc) 2347 { 2348 struct ifnet *ifp; 2349 2350 ALC_LOCK_ASSERT(sc); 2351 2352 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2353 return; 2354 2355 ifp = sc->alc_ifp; 2356 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2357 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2358 ifp->if_oerrors++; 2359 ifp->if_flags &= ~IFF_RUNNING; 2360 alc_init_locked(sc); 2361 return; 2362 } 2363 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2364 ifp->if_oerrors++; 2365 ifp->if_flags &= ~IFF_RUNNING; 2366 alc_init_locked(sc); 2367 if (!ifq_is_empty(&ifp->if_snd)) 2368 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2369 } 2370 2371 static int 2372 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 2373 { 2374 struct alc_softc *sc; 2375 struct ifreq *ifr; 2376 struct mii_data *mii; 2377 int error, mask; 2378 2379 (void)cr; 2380 sc = ifp->if_softc; 2381 ifr = (struct ifreq *)data; 2382 error = 0; 2383 switch (cmd) { 2384 case SIOCSIFMTU: 2385 if (ifr->ifr_mtu < ETHERMIN || 2386 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2387 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2388 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2389 ifr->ifr_mtu > ETHERMTU)) { 2390 error = EINVAL; 2391 } else if (ifp->if_mtu != ifr->ifr_mtu) { 2392 ALC_LOCK(sc); 2393 ifp->if_mtu = ifr->ifr_mtu; 2394 /* AR813x/AR815x has 13 bits MSS field. */ 2395 if (ifp->if_mtu > ALC_TSO_MTU && 2396 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2397 ifp->if_capenable &= ~IFCAP_TSO4; 2398 ifp->if_hwassist &= ~CSUM_TSO; 2399 } 2400 ALC_UNLOCK(sc); 2401 } 2402 break; 2403 case SIOCSIFFLAGS: 2404 ALC_LOCK(sc); 2405 if ((ifp->if_flags & IFF_UP) != 0) { 2406 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2407 ((ifp->if_flags ^ sc->alc_if_flags) & 2408 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2409 alc_rxfilter(sc); 2410 else if ((sc->alc_flags & ALC_FLAG_DETACH) == 0) 2411 alc_init_locked(sc); 2412 } else if ((ifp->if_flags & IFF_RUNNING) != 0) 2413 alc_stop(sc); 2414 sc->alc_if_flags = ifp->if_flags; 2415 ALC_UNLOCK(sc); 2416 break; 2417 case SIOCADDMULTI: 2418 case SIOCDELMULTI: 2419 ALC_LOCK(sc); 2420 if ((ifp->if_flags & IFF_RUNNING) != 0) 2421 alc_rxfilter(sc); 2422 ALC_UNLOCK(sc); 2423 break; 2424 case SIOCSIFMEDIA: 2425 case SIOCGIFMEDIA: 2426 mii = device_get_softc(sc->alc_miibus); 2427 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2428 break; 2429 case SIOCSIFCAP: 2430 ALC_LOCK(sc); 2431 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2432 if ((mask & IFCAP_TXCSUM) != 0 && 2433 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2434 ifp->if_capenable ^= IFCAP_TXCSUM; 2435 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2436 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2437 else 2438 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2439 } 2440 if ((mask & IFCAP_TSO4) != 0 && 2441 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2442 ifp->if_capenable ^= IFCAP_TSO4; 2443 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2444 /* AR813x/AR815x has 13 bits MSS field. */ 2445 if (ifp->if_mtu > ALC_TSO_MTU) { 2446 ifp->if_capenable &= ~IFCAP_TSO4; 2447 ifp->if_hwassist &= ~CSUM_TSO; 2448 } else 2449 ifp->if_hwassist |= CSUM_TSO; 2450 } else 2451 ifp->if_hwassist &= ~CSUM_TSO; 2452 } 2453 #if 0 2454 /* XXX: WOL */ 2455 if ((mask & IFCAP_WOL_MCAST) != 0 && 2456 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2457 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2458 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2459 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2460 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2461 #endif 2462 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2463 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2464 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2465 alc_rxvlan(sc); 2466 } 2467 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2468 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2469 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2470 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2471 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2472 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2473 /* 2474 * VLAN hardware tagging is required to do checksum 2475 * offload or TSO on VLAN interface. Checksum offload 2476 * on VLAN interface also requires hardware checksum 2477 * offload of parent interface. 2478 */ 2479 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2480 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2481 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2482 ifp->if_capenable &= 2483 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2484 ALC_UNLOCK(sc); 2485 // XXX VLAN_CAPABILITIES(ifp); 2486 break; 2487 default: 2488 error = ether_ioctl(ifp, cmd, data); 2489 break; 2490 } 2491 2492 return (error); 2493 } 2494 2495 static void 2496 alc_mac_config(struct alc_softc *sc) 2497 { 2498 struct mii_data *mii; 2499 uint32_t reg; 2500 2501 ALC_LOCK_ASSERT(sc); 2502 2503 mii = device_get_softc(sc->alc_miibus); 2504 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2505 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2506 MAC_CFG_SPEED_MASK); 2507 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2508 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2509 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 2510 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2511 } 2512 /* Reprogram MAC with resolved speed/duplex. */ 2513 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2514 case IFM_10_T: 2515 case IFM_100_TX: 2516 reg |= MAC_CFG_SPEED_10_100; 2517 break; 2518 case IFM_1000_T: 2519 reg |= MAC_CFG_SPEED_1000; 2520 break; 2521 } 2522 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2523 reg |= MAC_CFG_FULL_DUPLEX; 2524 #ifdef notyet 2525 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2526 reg |= MAC_CFG_TX_FC; 2527 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2528 reg |= MAC_CFG_RX_FC; 2529 #endif 2530 } 2531 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2532 } 2533 2534 static void 2535 alc_stats_clear(struct alc_softc *sc) 2536 { 2537 struct smb sb, *smb; 2538 uint32_t *reg; 2539 int i; 2540 2541 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2542 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2543 sc->alc_cdata.alc_smb_map, 2544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2545 smb = sc->alc_rdata.alc_smb; 2546 /* Update done, clear. */ 2547 smb->updated = 0; 2548 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2549 sc->alc_cdata.alc_smb_map, 2550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2551 } else { 2552 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2553 reg++) { 2554 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2555 i += sizeof(uint32_t); 2556 } 2557 /* Read Tx statistics. */ 2558 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2559 reg++) { 2560 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2561 i += sizeof(uint32_t); 2562 } 2563 } 2564 } 2565 2566 static void 2567 alc_stats_update(struct alc_softc *sc) 2568 { 2569 struct alc_hw_stats *stat; 2570 struct smb sb, *smb; 2571 struct ifnet *ifp; 2572 uint32_t *reg; 2573 int i; 2574 2575 ALC_LOCK_ASSERT(sc); 2576 2577 ifp = sc->alc_ifp; 2578 stat = &sc->alc_stats; 2579 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2580 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2581 sc->alc_cdata.alc_smb_map, 2582 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2583 smb = sc->alc_rdata.alc_smb; 2584 if (smb->updated == 0) 2585 return; 2586 } else { 2587 smb = &sb; 2588 /* Read Rx statistics. */ 2589 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2590 reg++) { 2591 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2592 i += sizeof(uint32_t); 2593 } 2594 /* Read Tx statistics. */ 2595 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2596 reg++) { 2597 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2598 i += sizeof(uint32_t); 2599 } 2600 } 2601 2602 /* Rx stats. */ 2603 stat->rx_frames += smb->rx_frames; 2604 stat->rx_bcast_frames += smb->rx_bcast_frames; 2605 stat->rx_mcast_frames += smb->rx_mcast_frames; 2606 stat->rx_pause_frames += smb->rx_pause_frames; 2607 stat->rx_control_frames += smb->rx_control_frames; 2608 stat->rx_crcerrs += smb->rx_crcerrs; 2609 stat->rx_lenerrs += smb->rx_lenerrs; 2610 stat->rx_bytes += smb->rx_bytes; 2611 stat->rx_runts += smb->rx_runts; 2612 stat->rx_fragments += smb->rx_fragments; 2613 stat->rx_pkts_64 += smb->rx_pkts_64; 2614 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2615 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2616 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2617 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2618 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2619 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2620 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2621 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2622 stat->rx_rrs_errs += smb->rx_rrs_errs; 2623 stat->rx_alignerrs += smb->rx_alignerrs; 2624 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2625 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2626 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2627 2628 /* Tx stats. */ 2629 stat->tx_frames += smb->tx_frames; 2630 stat->tx_bcast_frames += smb->tx_bcast_frames; 2631 stat->tx_mcast_frames += smb->tx_mcast_frames; 2632 stat->tx_pause_frames += smb->tx_pause_frames; 2633 stat->tx_excess_defer += smb->tx_excess_defer; 2634 stat->tx_control_frames += smb->tx_control_frames; 2635 stat->tx_deferred += smb->tx_deferred; 2636 stat->tx_bytes += smb->tx_bytes; 2637 stat->tx_pkts_64 += smb->tx_pkts_64; 2638 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2639 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2640 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2641 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2642 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2643 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2644 stat->tx_single_colls += smb->tx_single_colls; 2645 stat->tx_multi_colls += smb->tx_multi_colls; 2646 stat->tx_late_colls += smb->tx_late_colls; 2647 stat->tx_excess_colls += smb->tx_excess_colls; 2648 stat->tx_abort += smb->tx_abort; 2649 stat->tx_underrun += smb->tx_underrun; 2650 stat->tx_desc_underrun += smb->tx_desc_underrun; 2651 stat->tx_lenerrs += smb->tx_lenerrs; 2652 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2653 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2654 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2655 2656 /* Update counters in ifnet. */ 2657 ifp->if_opackets += smb->tx_frames; 2658 2659 ifp->if_collisions += smb->tx_single_colls + 2660 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2661 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2662 2663 /* 2664 * XXX 2665 * tx_pkts_truncated counter looks suspicious. It constantly 2666 * increments with no sign of Tx errors. This may indicate 2667 * the counter name is not correct one so I've removed the 2668 * counter in output errors. 2669 */ 2670 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2671 smb->tx_underrun; 2672 2673 ifp->if_ipackets += smb->rx_frames; 2674 2675 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2676 smb->rx_runts + smb->rx_pkts_truncated + 2677 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2678 smb->rx_alignerrs; 2679 2680 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2681 /* Update done, clear. */ 2682 smb->updated = 0; 2683 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2684 sc->alc_cdata.alc_smb_map, 2685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2686 } 2687 } 2688 2689 static void 2690 alc_intr(void *arg) 2691 { 2692 struct alc_softc *sc; 2693 uint32_t status; 2694 2695 sc = (struct alc_softc *)arg; 2696 2697 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2698 if ((status & ALC_INTRS) == 0) { 2699 return; 2700 } 2701 /* Disable interrupts. */ 2702 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2703 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2704 2705 return; 2706 } 2707 2708 static void 2709 alc_int_task(void *arg, int pending) 2710 { 2711 struct alc_softc *sc; 2712 struct ifnet *ifp; 2713 uint32_t status; 2714 int more; 2715 2716 sc = (struct alc_softc *)arg; 2717 ifp = sc->alc_ifp; 2718 2719 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2720 more = atomic_readandclear_32(&sc->alc_morework); 2721 if (more != 0) 2722 status |= INTR_RX_PKT; 2723 if ((status & ALC_INTRS) == 0) 2724 goto done; 2725 2726 /* Acknowledge interrupts but still disable interrupts. */ 2727 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2728 2729 more = 0; 2730 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2731 if ((status & INTR_RX_PKT) != 0) { 2732 more = alc_rxintr(sc, sc->alc_process_limit); 2733 if (more == EAGAIN) 2734 atomic_set_int(&sc->alc_morework, 1); 2735 else if (more == EIO) { 2736 ALC_LOCK(sc); 2737 ifp->if_flags &= ~IFF_RUNNING; 2738 alc_init_locked(sc); 2739 ALC_UNLOCK(sc); 2740 return; 2741 } 2742 } 2743 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2744 INTR_TXQ_TO_RST)) != 0) { 2745 if ((status & INTR_DMA_RD_TO_RST) != 0) 2746 device_printf(sc->alc_dev, 2747 "DMA read error! -- resetting\n"); 2748 if ((status & INTR_DMA_WR_TO_RST) != 0) 2749 device_printf(sc->alc_dev, 2750 "DMA write error! -- resetting\n"); 2751 if ((status & INTR_TXQ_TO_RST) != 0) 2752 device_printf(sc->alc_dev, 2753 "TxQ reset! -- resetting\n"); 2754 ALC_LOCK(sc); 2755 ifp->if_flags &= ~IFF_RUNNING; 2756 alc_init_locked(sc); 2757 ALC_UNLOCK(sc); 2758 return; 2759 } 2760 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2761 !ifq_is_empty(&ifp->if_snd)) 2762 taskqueue_enqueue(sc->alc_tq, &sc->alc_tx_task); 2763 } 2764 2765 if (more == EAGAIN || 2766 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2767 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2768 return; 2769 } 2770 2771 done: 2772 if ((ifp->if_flags & IFF_RUNNING) != 0) { 2773 /* Re-enable interrupts if we're running. */ 2774 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2775 } 2776 } 2777 2778 static void 2779 alc_txeof(struct alc_softc *sc) 2780 { 2781 struct ifnet *ifp; 2782 struct alc_txdesc *txd; 2783 uint32_t cons, prod; 2784 int prog; 2785 2786 ALC_LOCK_ASSERT(sc); 2787 2788 ifp = sc->alc_ifp; 2789 2790 if (sc->alc_cdata.alc_tx_cnt == 0) 2791 return; 2792 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2793 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2794 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2795 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2796 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2797 prod = sc->alc_rdata.alc_cmb->cons; 2798 } else 2799 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2800 /* Assume we're using normal Tx priority queue. */ 2801 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2802 MBOX_TD_CONS_LO_IDX_SHIFT; 2803 cons = sc->alc_cdata.alc_tx_cons; 2804 /* 2805 * Go through our Tx list and free mbufs for those 2806 * frames which have been transmitted. 2807 */ 2808 for (prog = 0; cons != prod; prog++, 2809 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2810 if (sc->alc_cdata.alc_tx_cnt <= 0) 2811 break; 2812 prog++; 2813 ifp->if_flags &= ~IFF_OACTIVE; 2814 sc->alc_cdata.alc_tx_cnt--; 2815 txd = &sc->alc_cdata.alc_txdesc[cons]; 2816 if (txd->tx_m != NULL) { 2817 /* Reclaim transmitted mbufs. */ 2818 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2819 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2820 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2821 txd->tx_dmamap); 2822 m_freem(txd->tx_m); 2823 txd->tx_m = NULL; 2824 } 2825 } 2826 2827 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2828 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2829 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2830 sc->alc_cdata.alc_tx_cons = cons; 2831 /* 2832 * Unarm watchdog timer only when there is no pending 2833 * frames in Tx queue. 2834 */ 2835 if (sc->alc_cdata.alc_tx_cnt == 0) 2836 sc->alc_watchdog_timer = 0; 2837 } 2838 2839 static int 2840 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2841 { 2842 struct mbuf *m; 2843 bus_dma_segment_t segs[1]; 2844 bus_dmamap_t map; 2845 int nsegs; 2846 int error; 2847 2848 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2849 if (m == NULL) 2850 return (ENOBUFS); 2851 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2852 #ifndef __NO_STRICT_ALIGNMENT 2853 m_adj(m, sizeof(uint64_t)); 2854 #endif 2855 2856 error = bus_dmamap_load_mbuf_segment( 2857 sc->alc_cdata.alc_rx_tag, 2858 sc->alc_cdata.alc_rx_sparemap, 2859 m, segs, 1, &nsegs, BUS_DMA_NOWAIT); 2860 if (error) { 2861 m_freem(m); 2862 return (ENOBUFS); 2863 } 2864 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2865 2866 if (rxd->rx_m != NULL) { 2867 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2868 BUS_DMASYNC_POSTREAD); 2869 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2870 } 2871 map = rxd->rx_dmamap; 2872 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2873 sc->alc_cdata.alc_rx_sparemap = map; 2874 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2875 BUS_DMASYNC_PREREAD); 2876 rxd->rx_m = m; 2877 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2878 return (0); 2879 } 2880 2881 static int 2882 alc_rxintr(struct alc_softc *sc, int count) 2883 { 2884 struct ifnet *ifp; 2885 struct rx_rdesc *rrd; 2886 uint32_t nsegs, status; 2887 int rr_cons, prog; 2888 2889 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2890 sc->alc_cdata.alc_rr_ring_map, 2891 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2892 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2893 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2894 rr_cons = sc->alc_cdata.alc_rr_cons; 2895 ifp = sc->alc_ifp; 2896 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0;) { 2897 if (count-- <= 0) 2898 break; 2899 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2900 status = le32toh(rrd->status); 2901 if ((status & RRD_VALID) == 0) 2902 break; 2903 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2904 if (nsegs == 0) { 2905 /* This should not happen! */ 2906 device_printf(sc->alc_dev, 2907 "unexpected segment count -- resetting\n"); 2908 return (EIO); 2909 } 2910 alc_rxeof(sc, rrd); 2911 /* Clear Rx return status. */ 2912 rrd->status = 0; 2913 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2914 sc->alc_cdata.alc_rx_cons += nsegs; 2915 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2916 prog += nsegs; 2917 } 2918 2919 if (prog > 0) { 2920 /* Update the consumer index. */ 2921 sc->alc_cdata.alc_rr_cons = rr_cons; 2922 /* Sync Rx return descriptors. */ 2923 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2924 sc->alc_cdata.alc_rr_ring_map, 2925 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2926 /* 2927 * Sync updated Rx descriptors such that controller see 2928 * modified buffer addresses. 2929 */ 2930 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2931 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2932 /* 2933 * Let controller know availability of new Rx buffers. 2934 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2935 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2936 * only when Rx buffer pre-fetching is required. In 2937 * addition we already set ALC_RX_RD_FREE_THRESH to 2938 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2939 * it still seems that pre-fetching needs more 2940 * experimentation. 2941 */ 2942 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2943 sc->alc_cdata.alc_rx_cons); 2944 } 2945 2946 return (count > 0 ? 0 : EAGAIN); 2947 } 2948 2949 #ifndef __NO_STRICT_ALIGNMENT 2950 static struct mbuf * 2951 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2952 { 2953 struct mbuf *n; 2954 int i; 2955 uint16_t *src, *dst; 2956 2957 src = mtod(m, uint16_t *); 2958 dst = src - 3; 2959 2960 if (m->m_next == NULL) { 2961 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2962 *dst++ = *src++; 2963 m->m_data -= 6; 2964 return (m); 2965 } 2966 /* 2967 * Append a new mbuf to received mbuf chain and copy ethernet 2968 * header from the mbuf chain. This can save lots of CPU 2969 * cycles for jumbo frame. 2970 */ 2971 MGETHDR(n, MB_DONTWAIT, MT_DATA); 2972 if (n == NULL) { 2973 ifp->if_iqdrops++; 2974 m_freem(m); 2975 return (NULL); 2976 } 2977 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2978 m->m_data += ETHER_HDR_LEN; 2979 m->m_len -= ETHER_HDR_LEN; 2980 n->m_len = ETHER_HDR_LEN; 2981 M_MOVE_PKTHDR(n, m); 2982 n->m_next = m; 2983 return (n); 2984 } 2985 #endif 2986 2987 /* Receive a frame. */ 2988 static void 2989 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2990 { 2991 struct alc_rxdesc *rxd; 2992 struct ifnet *ifp; 2993 struct mbuf *mp, *m; 2994 uint32_t rdinfo, status, vtag; 2995 int count, nsegs, rx_cons; 2996 2997 ifp = sc->alc_ifp; 2998 status = le32toh(rrd->status); 2999 rdinfo = le32toh(rrd->rdinfo); 3000 rx_cons = RRD_RD_IDX(rdinfo); 3001 nsegs = RRD_RD_CNT(rdinfo); 3002 3003 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3004 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3005 /* 3006 * We want to pass the following frames to upper 3007 * layer regardless of error status of Rx return 3008 * ring. 3009 * 3010 * o IP/TCP/UDP checksum is bad. 3011 * o frame length and protocol specific length 3012 * does not match. 3013 * 3014 * Force network stack compute checksum for 3015 * errored frames. 3016 */ 3017 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3018 if ((RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | 3019 RRD_ERR_RUNT) != 0) 3020 return; 3021 } 3022 3023 for (count = 0; count < nsegs; count++, 3024 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3025 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3026 mp = rxd->rx_m; 3027 /* Add a new receive buffer to the ring. */ 3028 if (alc_newbuf(sc, rxd) != 0) { 3029 ifp->if_iqdrops++; 3030 /* Reuse Rx buffers. */ 3031 if (sc->alc_cdata.alc_rxhead != NULL) 3032 m_freem(sc->alc_cdata.alc_rxhead); 3033 break; 3034 } 3035 3036 /* 3037 * Assume we've received a full sized frame. 3038 * Actual size is fixed when we encounter the end of 3039 * multi-segmented frame. 3040 */ 3041 mp->m_len = sc->alc_buf_size; 3042 3043 /* Chain received mbufs. */ 3044 if (sc->alc_cdata.alc_rxhead == NULL) { 3045 sc->alc_cdata.alc_rxhead = mp; 3046 sc->alc_cdata.alc_rxtail = mp; 3047 } else { 3048 mp->m_flags &= ~M_PKTHDR; 3049 sc->alc_cdata.alc_rxprev_tail = 3050 sc->alc_cdata.alc_rxtail; 3051 sc->alc_cdata.alc_rxtail->m_next = mp; 3052 sc->alc_cdata.alc_rxtail = mp; 3053 } 3054 3055 if (count == nsegs - 1) { 3056 /* Last desc. for this frame. */ 3057 m = sc->alc_cdata.alc_rxhead; 3058 m->m_flags |= M_PKTHDR; 3059 /* 3060 * It seems that L1C/L2C controller has no way 3061 * to tell hardware to strip CRC bytes. 3062 */ 3063 m->m_pkthdr.len = 3064 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3065 if (nsegs > 1) { 3066 /* Set last mbuf size. */ 3067 mp->m_len = sc->alc_cdata.alc_rxlen - 3068 (nsegs - 1) * sc->alc_buf_size; 3069 /* Remove the CRC bytes in chained mbufs. */ 3070 if (mp->m_len <= ETHER_CRC_LEN) { 3071 sc->alc_cdata.alc_rxtail = 3072 sc->alc_cdata.alc_rxprev_tail; 3073 sc->alc_cdata.alc_rxtail->m_len -= 3074 (ETHER_CRC_LEN - mp->m_len); 3075 sc->alc_cdata.alc_rxtail->m_next = NULL; 3076 m_freem(mp); 3077 } else { 3078 mp->m_len -= ETHER_CRC_LEN; 3079 } 3080 } else 3081 m->m_len = m->m_pkthdr.len; 3082 m->m_pkthdr.rcvif = ifp; 3083 /* 3084 * Due to hardware bugs, Rx checksum offloading 3085 * was intentionally disabled. 3086 */ 3087 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3088 (status & RRD_VLAN_TAG) != 0) { 3089 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3090 m->m_pkthdr.ether_vlantag = ntohs(vtag); 3091 m->m_flags |= M_VLANTAG; 3092 } 3093 #ifndef __NO_STRICT_ALIGNMENT 3094 m = alc_fixup_rx(ifp, m); 3095 if (m != NULL) 3096 #endif 3097 { 3098 /* Pass it on. */ 3099 (*ifp->if_input)(ifp, m); 3100 } 3101 } 3102 } 3103 /* Reset mbuf chains. */ 3104 ALC_RXCHAIN_RESET(sc); 3105 } 3106 3107 static void 3108 alc_tick(void *arg) 3109 { 3110 struct alc_softc *sc; 3111 struct mii_data *mii; 3112 3113 sc = (struct alc_softc *)arg; 3114 3115 ALC_LOCK(sc); 3116 3117 mii = device_get_softc(sc->alc_miibus); 3118 mii_tick(mii); 3119 alc_stats_update(sc); 3120 /* 3121 * alc(4) does not rely on Tx completion interrupts to reclaim 3122 * transferred buffers. Instead Tx completion interrupts are 3123 * used to hint for scheduling Tx task. So it's necessary to 3124 * release transmitted buffers by kicking Tx completion 3125 * handler. This limits the maximum reclamation delay to a hz. 3126 */ 3127 alc_txeof(sc); 3128 alc_watchdog(sc); 3129 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3130 ALC_UNLOCK(sc); 3131 } 3132 3133 static void 3134 alc_reset(struct alc_softc *sc) 3135 { 3136 uint32_t reg; 3137 int i; 3138 3139 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3140 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3141 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3142 3143 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3144 DELAY(10); 3145 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3146 break; 3147 } 3148 if (i == 0) 3149 device_printf(sc->alc_dev, "master reset timeout!\n"); 3150 3151 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3152 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3153 break; 3154 DELAY(10); 3155 } 3156 3157 if (i == 0) 3158 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3159 } 3160 3161 static void 3162 alc_init(void *xsc) 3163 { 3164 struct alc_softc *sc; 3165 3166 sc = (struct alc_softc *)xsc; 3167 ALC_LOCK(sc); 3168 alc_init_locked(sc); 3169 ALC_UNLOCK(sc); 3170 } 3171 3172 static void 3173 alc_init_locked(struct alc_softc *sc) 3174 { 3175 struct ifnet *ifp; 3176 struct mii_data *mii; 3177 uint8_t eaddr[ETHER_ADDR_LEN]; 3178 bus_addr_t paddr; 3179 uint32_t reg, rxf_hi, rxf_lo; 3180 3181 ALC_LOCK_ASSERT(sc); 3182 3183 ifp = sc->alc_ifp; 3184 mii = device_get_softc(sc->alc_miibus); 3185 3186 if ((ifp->if_flags & IFF_RUNNING) != 0) 3187 return; 3188 /* 3189 * Cancel any pending I/O. 3190 */ 3191 alc_stop(sc); 3192 /* 3193 * Reset the chip to a known state. 3194 */ 3195 alc_reset(sc); 3196 3197 /* Initialize Rx descriptors. */ 3198 if (alc_init_rx_ring(sc) != 0) { 3199 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3200 alc_stop(sc); 3201 return; 3202 } 3203 alc_init_rr_ring(sc); 3204 alc_init_tx_ring(sc); 3205 alc_init_cmb(sc); 3206 alc_init_smb(sc); 3207 3208 /* Reprogram the station address. */ 3209 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3210 CSR_WRITE_4(sc, ALC_PAR0, 3211 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3212 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3213 /* 3214 * Clear WOL status and disable all WOL feature as WOL 3215 * would interfere Rx operation under normal environments. 3216 */ 3217 CSR_READ_4(sc, ALC_WOL_CFG); 3218 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3219 /* Set Tx descriptor base addresses. */ 3220 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3221 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3222 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3223 /* We don't use high priority ring. */ 3224 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3225 /* Set Tx descriptor counter. */ 3226 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3227 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3228 /* Set Rx descriptor base addresses. */ 3229 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3230 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3231 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3232 /* We use one Rx ring. */ 3233 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3234 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3235 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3236 /* Set Rx descriptor counter. */ 3237 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3238 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3239 3240 /* 3241 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3242 * if it do not fit the buffer size. Rx return descriptor holds 3243 * a counter that indicates how many fragments were made by the 3244 * hardware. The buffer size should be multiple of 8 bytes. 3245 * Since hardware has limit on the size of buffer size, always 3246 * use the maximum value. 3247 * For strict-alignment architectures make sure to reduce buffer 3248 * size by 8 bytes to make room for alignment fixup. 3249 */ 3250 #ifndef __NO_STRICT_ALIGNMENT 3251 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3252 #else 3253 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3254 #endif 3255 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3256 3257 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3258 /* Set Rx return descriptor base addresses. */ 3259 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3260 /* We use one Rx return ring. */ 3261 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3262 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3263 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3264 /* Set Rx return descriptor counter. */ 3265 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3266 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3267 paddr = sc->alc_rdata.alc_cmb_paddr; 3268 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3269 paddr = sc->alc_rdata.alc_smb_paddr; 3270 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3271 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3272 3273 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3274 /* Reconfigure SRAM - Vendor magic. */ 3275 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3276 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3277 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3278 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3279 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3280 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3281 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3282 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3283 } 3284 3285 /* Tell hardware that we're ready to load DMA blocks. */ 3286 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3287 3288 /* Configure interrupt moderation timer. */ 3289 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3290 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3291 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3292 /* 3293 * We don't want to automatic interrupt clear as task queue 3294 * for the interrupt should know interrupt status. 3295 */ 3296 reg = MASTER_SA_TIMER_ENB; 3297 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3298 reg |= MASTER_IM_RX_TIMER_ENB; 3299 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3300 reg |= MASTER_IM_TX_TIMER_ENB; 3301 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3302 /* 3303 * Disable interrupt re-trigger timer. We don't want automatic 3304 * re-triggering of un-ACKed interrupts. 3305 */ 3306 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3307 /* Configure CMB. */ 3308 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3309 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3310 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3311 } else { 3312 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3313 } 3314 /* 3315 * Hardware can be configured to issue SMB interrupt based 3316 * on programmed interval. Since there is a callout that is 3317 * invoked for every hz in driver we use that instead of 3318 * relying on periodic SMB interrupt. 3319 */ 3320 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3321 /* Clear MAC statistics. */ 3322 alc_stats_clear(sc); 3323 3324 /* 3325 * Always use maximum frame size that controller can support. 3326 * Otherwise received frames that has larger frame length 3327 * than alc(4) MTU would be silently dropped in hardware. This 3328 * would make path-MTU discovery hard as sender wouldn't get 3329 * any responses from receiver. alc(4) supports 3330 * multi-fragmented frames on Rx path so it has no issue on 3331 * assembling fragmented frames. Using maximum frame size also 3332 * removes the need to reinitialize hardware when interface 3333 * MTU configuration was changed. 3334 * 3335 * Be conservative in what you do, be liberal in what you 3336 * accept from others - RFC 793. 3337 */ 3338 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3339 3340 /* Disable header split(?) */ 3341 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3342 3343 /* Configure IPG/IFG parameters. */ 3344 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3345 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3346 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3347 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3348 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3349 /* Set parameters for half-duplex media. */ 3350 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3351 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3352 HDPX_CFG_LCOL_MASK) | 3353 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3354 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3355 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3356 HDPX_CFG_ABEBT_MASK) | 3357 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3358 HDPX_CFG_JAMIPG_MASK)); 3359 /* 3360 * Set TSO/checksum offload threshold. For frames that is 3361 * larger than this threshold, hardware wouldn't do 3362 * TSO/checksum offloading. 3363 */ 3364 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3365 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3366 TSO_OFFLOAD_THRESH_MASK); 3367 /* Configure TxQ. */ 3368 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3369 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3370 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3371 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3372 reg >>= 1; 3373 } 3374 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3375 TXQ_CFG_TD_BURST_MASK; 3376 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3377 3378 /* Configure Rx free descriptor pre-fetching. */ 3379 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3380 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3381 RX_RD_FREE_THRESH_HI_MASK) | 3382 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3383 RX_RD_FREE_THRESH_LO_MASK)); 3384 3385 /* 3386 * Configure flow control parameters. 3387 * XON : 80% of Rx FIFO 3388 * XOFF : 30% of Rx FIFO 3389 */ 3390 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3391 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3392 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3393 rxf_hi = (reg * 8) / 10; 3394 rxf_lo = (reg * 3) / 10; 3395 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3396 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3397 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3398 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3399 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3400 } 3401 3402 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3403 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) { 3404 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3405 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3406 SERDES_PHY_CLK_SLOWDOWN); 3407 } 3408 3409 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3410 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3411 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3412 3413 /* Configure RxQ. */ 3414 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3415 RXQ_CFG_RD_BURST_MASK; 3416 reg |= RXQ_CFG_RSS_MODE_DIS; 3417 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3418 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3419 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3420 3421 /* Configure DMA parameters. */ 3422 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3423 reg |= sc->alc_rcb; 3424 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3425 reg |= DMA_CFG_CMB_ENB; 3426 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3427 reg |= DMA_CFG_SMB_ENB; 3428 else 3429 reg |= DMA_CFG_SMB_DIS; 3430 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3431 DMA_CFG_RD_BURST_SHIFT; 3432 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3433 DMA_CFG_WR_BURST_SHIFT; 3434 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3435 DMA_CFG_RD_DELAY_CNT_MASK; 3436 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3437 DMA_CFG_WR_DELAY_CNT_MASK; 3438 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3439 3440 /* 3441 * Configure Tx/Rx MACs. 3442 * - Auto-padding for short frames. 3443 * - Enable CRC generation. 3444 * Actual reconfiguration of MAC for resolved speed/duplex 3445 * is followed after detection of link establishment. 3446 * AR813x/AR815x always does checksum computation regardless 3447 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3448 * have bug in protocol field in Rx return structure so 3449 * these controllers can't handle fragmented frames. Disable 3450 * Rx checksum offloading until there is a newer controller 3451 * that has sane implementation. 3452 */ 3453 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3454 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3455 MAC_CFG_PREAMBLE_MASK); 3456 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3457 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3458 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 3459 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3460 } 3461 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3462 reg |= MAC_CFG_SPEED_10_100; 3463 else 3464 reg |= MAC_CFG_SPEED_1000; 3465 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3466 3467 /* Set up the receive filter. */ 3468 alc_rxfilter(sc); 3469 alc_rxvlan(sc); 3470 3471 /* Acknowledge all pending interrupts and clear it. */ 3472 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3473 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3474 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3475 3476 sc->alc_flags &= ~ALC_FLAG_LINK; 3477 /* Switch to the current media. */ 3478 mii_mediachg(mii); 3479 3480 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3481 3482 ifp->if_flags |= IFF_RUNNING; 3483 ifp->if_flags &= ~IFF_OACTIVE; 3484 } 3485 3486 static void 3487 alc_stop(struct alc_softc *sc) 3488 { 3489 struct ifnet *ifp; 3490 struct alc_txdesc *txd; 3491 struct alc_rxdesc *rxd; 3492 uint32_t reg; 3493 int i; 3494 3495 ALC_LOCK_ASSERT(sc); 3496 /* 3497 * Mark the interface down and cancel the watchdog timer. 3498 */ 3499 ifp = sc->alc_ifp; 3500 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3501 sc->alc_flags &= ~ALC_FLAG_LINK; 3502 callout_stop(&sc->alc_tick_ch); 3503 sc->alc_watchdog_timer = 0; 3504 alc_stats_update(sc); 3505 /* Disable interrupts. */ 3506 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3507 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3508 alc_stop_queue(sc); 3509 /* Disable DMA. */ 3510 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3511 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3512 reg |= DMA_CFG_SMB_DIS; 3513 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3514 DELAY(1000); 3515 /* Stop Rx/Tx MACs. */ 3516 alc_stop_mac(sc); 3517 /* Disable interrupts which might be touched in taskq handler. */ 3518 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3519 3520 /* Reclaim Rx buffers that have been processed. */ 3521 if (sc->alc_cdata.alc_rxhead != NULL) 3522 m_freem(sc->alc_cdata.alc_rxhead); 3523 ALC_RXCHAIN_RESET(sc); 3524 /* 3525 * Free Tx/Rx mbufs still in the queues. 3526 */ 3527 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3528 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3529 if (rxd->rx_m != NULL) { 3530 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3531 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3532 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3533 rxd->rx_dmamap); 3534 m_freem(rxd->rx_m); 3535 rxd->rx_m = NULL; 3536 } 3537 } 3538 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3539 txd = &sc->alc_cdata.alc_txdesc[i]; 3540 if (txd->tx_m != NULL) { 3541 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3542 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3543 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3544 txd->tx_dmamap); 3545 m_freem(txd->tx_m); 3546 txd->tx_m = NULL; 3547 } 3548 } 3549 } 3550 3551 static void 3552 alc_stop_mac(struct alc_softc *sc) 3553 { 3554 uint32_t reg; 3555 int i; 3556 3557 ALC_LOCK_ASSERT(sc); 3558 3559 /* Disable Rx/Tx MAC. */ 3560 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3561 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3562 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 3563 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3564 } 3565 for (i = ALC_TIMEOUT; i > 0; i--) { 3566 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3567 if (reg == 0) 3568 break; 3569 DELAY(10); 3570 } 3571 if (i == 0) 3572 device_printf(sc->alc_dev, 3573 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3574 } 3575 3576 static void 3577 alc_start_queue(struct alc_softc *sc) 3578 { 3579 uint32_t qcfg[] = { 3580 0, 3581 RXQ_CFG_QUEUE0_ENB, 3582 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3583 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3584 RXQ_CFG_ENB 3585 }; 3586 uint32_t cfg; 3587 3588 ALC_LOCK_ASSERT(sc); 3589 3590 /* Enable RxQ. */ 3591 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3592 cfg &= ~RXQ_CFG_ENB; 3593 cfg |= qcfg[1]; 3594 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3595 /* Enable TxQ. */ 3596 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3597 cfg |= TXQ_CFG_ENB; 3598 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3599 } 3600 3601 static void 3602 alc_stop_queue(struct alc_softc *sc) 3603 { 3604 uint32_t reg; 3605 int i; 3606 3607 ALC_LOCK_ASSERT(sc); 3608 3609 /* Disable RxQ. */ 3610 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3611 if ((reg & RXQ_CFG_ENB) != 0) { 3612 reg &= ~RXQ_CFG_ENB; 3613 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3614 } 3615 /* Disable TxQ. */ 3616 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3617 if ((reg & TXQ_CFG_ENB) == 0) { 3618 reg &= ~TXQ_CFG_ENB; 3619 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3620 } 3621 for (i = ALC_TIMEOUT; i > 0; i--) { 3622 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3623 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3624 break; 3625 DELAY(10); 3626 } 3627 if (i == 0) 3628 device_printf(sc->alc_dev, 3629 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3630 } 3631 3632 static void 3633 alc_init_tx_ring(struct alc_softc *sc) 3634 { 3635 struct alc_ring_data *rd; 3636 struct alc_txdesc *txd; 3637 int i; 3638 3639 ALC_LOCK_ASSERT(sc); 3640 3641 sc->alc_cdata.alc_tx_prod = 0; 3642 sc->alc_cdata.alc_tx_cons = 0; 3643 sc->alc_cdata.alc_tx_cnt = 0; 3644 3645 rd = &sc->alc_rdata; 3646 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3647 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3648 txd = &sc->alc_cdata.alc_txdesc[i]; 3649 txd->tx_m = NULL; 3650 } 3651 3652 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3653 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3654 } 3655 3656 static int 3657 alc_init_rx_ring(struct alc_softc *sc) 3658 { 3659 struct alc_ring_data *rd; 3660 struct alc_rxdesc *rxd; 3661 int i; 3662 3663 ALC_LOCK_ASSERT(sc); 3664 3665 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3666 sc->alc_morework = 0; 3667 rd = &sc->alc_rdata; 3668 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3669 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3670 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3671 rxd->rx_m = NULL; 3672 rxd->rx_desc = &rd->alc_rx_ring[i]; 3673 if (alc_newbuf(sc, rxd) != 0) 3674 return (ENOBUFS); 3675 } 3676 3677 /* 3678 * Since controller does not update Rx descriptors, driver 3679 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3680 * is enough to ensure coherence. 3681 */ 3682 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3683 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3684 /* Let controller know availability of new Rx buffers. */ 3685 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3686 3687 return (0); 3688 } 3689 3690 static void 3691 alc_init_rr_ring(struct alc_softc *sc) 3692 { 3693 struct alc_ring_data *rd; 3694 3695 ALC_LOCK_ASSERT(sc); 3696 3697 sc->alc_cdata.alc_rr_cons = 0; 3698 ALC_RXCHAIN_RESET(sc); 3699 3700 rd = &sc->alc_rdata; 3701 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3702 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3703 sc->alc_cdata.alc_rr_ring_map, 3704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3705 } 3706 3707 static void 3708 alc_init_cmb(struct alc_softc *sc) 3709 { 3710 struct alc_ring_data *rd; 3711 3712 ALC_LOCK_ASSERT(sc); 3713 3714 rd = &sc->alc_rdata; 3715 bzero(rd->alc_cmb, ALC_CMB_SZ); 3716 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3718 } 3719 3720 static void 3721 alc_init_smb(struct alc_softc *sc) 3722 { 3723 struct alc_ring_data *rd; 3724 3725 ALC_LOCK_ASSERT(sc); 3726 3727 rd = &sc->alc_rdata; 3728 bzero(rd->alc_smb, ALC_SMB_SZ); 3729 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3730 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3731 } 3732 3733 static void 3734 alc_rxvlan(struct alc_softc *sc) 3735 { 3736 struct ifnet *ifp; 3737 uint32_t reg; 3738 3739 ALC_LOCK_ASSERT(sc); 3740 3741 ifp = sc->alc_ifp; 3742 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3743 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3744 reg |= MAC_CFG_VLAN_TAG_STRIP; 3745 else 3746 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3747 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3748 } 3749 3750 static void 3751 alc_rxfilter(struct alc_softc *sc) 3752 { 3753 struct ifnet *ifp; 3754 struct ifmultiaddr *ifma; 3755 uint32_t crc; 3756 uint32_t mchash[2]; 3757 uint32_t rxcfg; 3758 3759 ALC_LOCK_ASSERT(sc); 3760 3761 ifp = sc->alc_ifp; 3762 3763 bzero(mchash, sizeof(mchash)); 3764 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3765 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3766 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3767 rxcfg |= MAC_CFG_BCAST; 3768 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3769 if ((ifp->if_flags & IFF_PROMISC) != 0) 3770 rxcfg |= MAC_CFG_PROMISC; 3771 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3772 rxcfg |= MAC_CFG_ALLMULTI; 3773 mchash[0] = 0xFFFFFFFF; 3774 mchash[1] = 0xFFFFFFFF; 3775 goto chipit; 3776 } 3777 3778 #if 0 3779 /* XXX */ 3780 if_maddr_rlock(ifp); 3781 #endif 3782 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3783 if (ifma->ifma_addr->sa_family != AF_LINK) 3784 continue; 3785 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3786 ifma->ifma_addr), ETHER_ADDR_LEN); 3787 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3788 } 3789 #if 0 3790 /* XXX */ 3791 if_maddr_runlock(ifp); 3792 #endif 3793 3794 chipit: 3795 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3796 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3797 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3798 } 3799 3800 static int 3801 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3802 { 3803 return (sysctl_int_range(oidp, arg1, arg2, req, 3804 ALC_PROC_MIN, ALC_PROC_MAX)); 3805 } 3806 3807 static int 3808 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3809 { 3810 3811 return (sysctl_int_range(oidp, arg1, arg2, req, 3812 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3813 } 3814