1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR813x/AR815x device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47 #define DEVICEID_ATHEROS_AR8161 0x1091 48 #define DEVICEID_ATHEROS_E2200 0xE091 49 #define DEVICEID_ATHEROS_AR8162 0x1090 50 #define DEVICEID_ATHEROS_AR8171 0x10A1 51 #define DEVICEID_ATHEROS_AR8172 0x10A0 52 53 #define ATHEROS_AR8152_B_V10 0xC0 54 #define ATHEROS_AR8152_B_V11 0xC1 55 56 /* 57 * Atheros AR816x/AR817x revisions 58 */ 59 #define AR816X_REV_A0 0 60 #define AR816X_REV_A1 1 61 #define AR816X_REV_B0 2 62 #define AR816X_REV_C0 3 63 64 #define AR816X_REV_SHIFT 3 65 #define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) 66 67 /* 68 * From FreeBSD dev/pci/pcireg.h 69 * 70 * PCIM_xxx: mask to locate subfield in register 71 * PCIR_xxx: config register offset 72 */ 73 #define PCIR_EXPRESS_DEVICE_CTL 0x8 74 #define PCIR_EXPRESS_LINK_CAP 0xc 75 #define PCIR_EXPRESS_LINK_CTL 0x10 76 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 77 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 78 #define PCIM_LINK_CAP_ASPM 0x00000c00 79 80 /* 0x0000 - 0x02FF : PCIe configuration space */ 81 82 #define ALC_PEX_UNC_ERR_SEV 0x10C 83 #define PEX_UNC_ERR_SEV_TRN 0x00000001 84 #define PEX_UNC_ERR_SEV_DLP 0x00000010 85 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 86 #define PEX_UNC_ERR_SEV_FCP 0x00002000 87 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 88 #define PEX_UNC_ERR_SEV_CA 0x00008000 89 #define PEX_UNC_ERR_SEV_UC 0x00010000 90 #define PEX_UNC_ERR_SEV_ROV 0x00020000 91 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 92 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 93 #define PEX_UNC_ERR_SEV_UR 0x00100000 94 95 #define ALC_EEPROM_LD 0x204 /* AR816x */ 96 #define EEPROM_LD_START 0x00000001 97 #define EEPROM_LD_IDLE 0x00000010 98 #define EEPROM_LD_DONE 0x00000000 99 #define EEPROM_LD_PROGRESS 0x00000020 100 #define EEPROM_LD_EXIST 0x00000100 101 #define EEPROM_LD_EEPROM_EXIST 0x00000200 102 #define EEPROM_LD_FLASH_EXIST 0x00000400 103 #define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 104 #define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 105 106 #define ALC_TWSI_CFG 0x218 107 #define TWSI_CFG_SW_LD_START 0x00000800 108 #define TWSI_CFG_HW_LD_START 0x00001000 109 #define TWSI_CFG_LD_EXIST 0x00400000 110 111 #define ALC_SLD 0x218 /* AR816x */ 112 #define SLD_START 0x00000800 113 #define SLD_PROGRESS 0x00001000 114 #define SLD_IDLE 0x00002000 115 #define SLD_SLVADDR_MASK 0x007F0000 116 #define SLD_EXIST 0x00800000 117 #define SLD_FREQ_MASK 0x03000000 118 #define SLD_FREQ_100K 0x00000000 119 #define SLD_FREQ_200K 0x01000000 120 #define SLD_FREQ_300K 0x02000000 121 #define SLD_FREQ_400K 0x03000000 122 123 #define ALC_PCIE_PHYMISC 0x1000 124 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 125 126 #define ALC_PCIE_PHYMISC2 0x1004 127 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 128 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 129 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 130 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 131 132 #define ALC_PDLL_TRNS1 0x1104 133 #define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 134 135 #define ALC_TWSI_DEBUG 0x1108 136 #define TWSI_DEBUG_DEV_EXIST 0x20000000 137 138 #define ALC_EEPROM_CFG 0x12C0 139 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 140 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 141 #define EEPROM_CFG_ACK 0x40000000 142 #define EEPROM_CFG_RW 0x80000000 143 #define EEPROM_CFG_DATA_HI_SHIFT 0 144 #define EEPROM_CFG_ADDR_SHIFT 16 145 146 #define ALC_EEPROM_DATA_LO 0x12C4 147 148 #define ALC_OPT_CFG 0x12F0 149 #define OPT_CFG_CLK_ENB 0x00000002 150 151 #define ALC_PM_CFG 0x12F8 152 #define PM_CFG_SERDES_ENB 0x00000001 153 #define PM_CFG_RBER_ENB 0x00000002 154 #define PM_CFG_CLK_REQ_ENB 0x00000004 155 #define PM_CFG_ASPM_L1_ENB 0x00000008 156 #define PM_CFG_SERDES_L1_ENB 0x00000010 157 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 158 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 159 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 160 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 161 #define PM_CFG_RX_L1_AFTER_L0S 0x00000800 162 #define PM_CFG_ASPM_L0S_ENB 0x00001000 163 #define PM_CFG_CLK_SWH_L1 0x00002000 164 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 165 #define PM_CFG_PCIE_RECV 0x00008000 166 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 167 #define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 168 #define PM_CFG_TX_L1_AFTER_L0S 0x00080000 169 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 170 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 171 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 172 #define PM_CFG_SA_DLY_ENB 0x20000000 173 #define PM_CFG_MAC_ASPM_CHK 0x40000000 174 #define PM_CFG_HOTRST 0x80000000 175 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 176 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 177 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 178 #define PM_CFG_LCKDET_TIMER_SHIFT 24 179 180 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 181 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 182 #define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 183 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 184 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 185 #define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 186 187 #define ALC_LTSSM_ID_CFG 0x12FC 188 #define LTSSM_ID_WRO_ENB 0x00001000 189 190 #define ALC_MASTER_CFG 0x1400 191 #define MASTER_RESET 0x00000001 192 #define MASTER_TEST_MODE_MASK 0x0000000C 193 #define MASTER_BERT_START 0x00000010 194 #define MASTER_WAKEN_25M 0x00000020 195 #define MASTER_OOB_DIS_OFF 0x00000040 196 #define MASTER_SA_TIMER_ENB 0x00000080 197 #define MASTER_MTIMER_ENB 0x00000100 198 #define MASTER_MANUAL_INTR_ENB 0x00000200 199 #define MASTER_IM_TX_TIMER_ENB 0x00000400 200 #define MASTER_IM_RX_TIMER_ENB 0x00000800 201 #define MASTER_CLK_SEL_DIS 0x00001000 202 #define MASTER_CLK_SWH_MODE 0x00002000 203 #define MASTER_INTR_RD_CLR 0x00004000 204 #define MASTER_CHIP_REV_MASK 0x00FF0000 205 #define MASTER_CHIP_ID_MASK 0x7F000000 206 #define MASTER_OTP_SEL 0x80000000 207 #define MASTER_TEST_MODE_SHIFT 2 208 #define MASTER_CHIP_REV_SHIFT 16 209 #define MASTER_CHIP_ID_SHIFT 24 210 211 /* Number of ticks per usec for AR813x/AR815x. */ 212 #define ALC_TICK_USECS 2 213 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 214 215 #define ALC_MANUAL_TIMER 0x1404 216 217 #define ALC_IM_TIMER 0x1408 218 #define IM_TIMER_TX_MASK 0x0000FFFF 219 #define IM_TIMER_RX_MASK 0xFFFF0000 220 #define IM_TIMER_TX_SHIFT 0 221 #define IM_TIMER_RX_SHIFT 16 222 #define ALC_IM_TIMER_MIN 0 223 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 224 /* 225 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 226 * interrupts in a second. 227 */ 228 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 229 /* 230 * alc(4) does not rely on Tx completion interrupts, so set it 231 * somewhat large value to reduce Tx completion interrupts. 232 */ 233 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 234 235 #define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ 236 #define GPHY_CFG_EXT_RESET 0x0001 237 #define GPHY_CFG_RTL_MODE 0x0002 238 #define GPHY_CFG_LED_MODE 0x0004 239 #define GPHY_CFG_ANEG_NOW 0x0008 240 #define GPHY_CFG_RECV_ANEG 0x0010 241 #define GPHY_CFG_GATE_25M_ENB 0x0020 242 #define GPHY_CFG_LPW_EXIT 0x0040 243 #define GPHY_CFG_PHY_IDDQ 0x0080 244 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 245 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 246 #define GPHY_CFG_HIB_EN 0x0400 247 #define GPHY_CFG_HIB_PULSE 0x0800 248 #define GPHY_CFG_SEL_ANA_RESET 0x1000 249 #define GPHY_CFG_PHY_PLL_ON 0x2000 250 #define GPHY_CFG_PWDOWN_HW 0x4000 251 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 252 #define GPHY_CFG_100AB_ENB 0x00020000 253 254 #define ALC_IDLE_STATUS 0x1410 255 #define IDLE_STATUS_RXMAC 0x00000001 256 #define IDLE_STATUS_TXMAC 0x00000002 257 #define IDLE_STATUS_RXQ 0x00000004 258 #define IDLE_STATUS_TXQ 0x00000008 259 #define IDLE_STATUS_DMARD 0x00000010 260 #define IDLE_STATUS_DMAWR 0x00000020 261 #define IDLE_STATUS_SMB 0x00000040 262 #define IDLE_STATUS_CMB 0x00000080 263 264 #define ALC_MDIO 0x1414 265 #define MDIO_DATA_MASK 0x0000FFFF 266 #define MDIO_REG_ADDR_MASK 0x001F0000 267 #define MDIO_OP_READ 0x00200000 268 #define MDIO_OP_WRITE 0x00000000 269 #define MDIO_SUP_PREAMBLE 0x00400000 270 #define MDIO_OP_EXECUTE 0x00800000 271 #define MDIO_CLK_25_4 0x00000000 272 #define MDIO_CLK_25_6 0x02000000 273 #define MDIO_CLK_25_8 0x03000000 274 #define MDIO_CLK_25_10 0x04000000 275 #define MDIO_CLK_25_14 0x05000000 276 #define MDIO_CLK_25_20 0x06000000 277 #define MDIO_CLK_25_128 0x07000000 278 #define MDIO_OP_BUSY 0x08000000 279 #define MDIO_AP_ENB 0x10000000 280 #define MDIO_MODE_EXT 0x40000000 281 #define MDIO_DATA_SHIFT 0 282 #define MDIO_REG_ADDR_SHIFT 16 283 284 #define MDIO_REG_ADDR(x) \ 285 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 286 /* Default PHY address. */ 287 #define ALC_PHY_ADDR 0 288 289 #define ALC_PHY_STATUS 0x1418 290 #define PHY_STATUS_RECV_ENB 0x00000001 291 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 292 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 293 #define PHY_STATUS_LPW_STATE 0x80000000 294 #define PHY_STATIS_OE_PWSP_SHIFT 16 295 296 /* Packet memory BIST. */ 297 #define ALC_BIST0 0x141C 298 #define BIST0_ENB 0x00000001 299 #define BIST0_SRAM_FAIL 0x00000002 300 #define BIST0_FUSE_FLAG 0x00000004 301 302 /* PCIe retry buffer BIST. */ 303 #define ALC_BIST1 0x1420 304 #define BIST1_ENB 0x00000001 305 #define BIST1_SRAM_FAIL 0x00000002 306 #define BIST1_FUSE_FLAG 0x00000004 307 308 #define ALC_SERDES_LOCK 0x1424 309 #define SERDES_LOCK_DET 0x00000001 310 #define SERDES_LOCK_DET_ENB 0x00000002 311 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 312 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 313 314 #define ALC_LPI_CTL 0x1440 315 #define LPI_CTL_ENB 0x00000001 316 317 #define ALC_EXT_MDIO 0x1448 318 #define EXT_MDIO_REG_MASK 0x0000FFFF 319 #define EXT_MDIO_DEVADDR_MASK 0x001F0000 320 #define EXT_MDIO_REG_SHIFT 0 321 #define EXT_MDIO_DEVADDR_SHIFT 16 322 323 #define EXT_MDIO_REG(x) \ 324 (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) 325 #define EXT_MDIO_DEVADDR(x) \ 326 (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) 327 328 #define ALC_IDLE_DECISN_TIMER 0x1474 329 #define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 330 331 #define ALC_MAC_CFG 0x1480 332 #define MAC_CFG_TX_ENB 0x00000001 333 #define MAC_CFG_RX_ENB 0x00000002 334 #define MAC_CFG_TX_FC 0x00000004 335 #define MAC_CFG_RX_FC 0x00000008 336 #define MAC_CFG_LOOP 0x00000010 337 #define MAC_CFG_FULL_DUPLEX 0x00000020 338 #define MAC_CFG_TX_CRC_ENB 0x00000040 339 #define MAC_CFG_TX_AUTO_PAD 0x00000080 340 #define MAC_CFG_TX_LENCHK 0x00000100 341 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 342 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 343 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 344 #define MAC_CFG_PROMISC 0x00008000 345 #define MAC_CFG_TX_PAUSE 0x00010000 346 #define MAC_CFG_SCNT 0x00020000 347 #define MAC_CFG_SYNC_RST_TX 0x00040000 348 #define MAC_CFG_SIM_RST_TX 0x00080000 349 #define MAC_CFG_SPEED_MASK 0x00300000 350 #define MAC_CFG_SPEED_10_100 0x00100000 351 #define MAC_CFG_SPEED_1000 0x00200000 352 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 353 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 354 #define MAC_CFG_RXCSUM_ENB 0x01000000 355 #define MAC_CFG_ALLMULTI 0x02000000 356 #define MAC_CFG_BCAST 0x04000000 357 #define MAC_CFG_DBG 0x08000000 358 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 359 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 360 #define MAC_CFG_SPEED_MODE_SW 0x40000000 361 #define MAC_CFG_FAST_PAUSE 0x80000000 362 #define MAC_CFG_PREAMBLE_SHIFT 10 363 #define MAC_CFG_PREAMBLE_DEFAULT 7 364 365 #define ALC_IPG_IFG_CFG 0x1484 366 #define IPG_IFG_IPGT_MASK 0x0000007F 367 #define IPG_IFG_MIFG_MASK 0x0000FF00 368 #define IPG_IFG_IPG1_MASK 0x007F0000 369 #define IPG_IFG_IPG2_MASK 0x7F000000 370 #define IPG_IFG_IPGT_SHIFT 0 371 #define IPG_IFG_IPGT_DEFAULT 0x60 372 #define IPG_IFG_MIFG_SHIFT 8 373 #define IPG_IFG_MIFG_DEFAULT 0x50 374 #define IPG_IFG_IPG1_SHIFT 16 375 #define IPG_IFG_IPG1_DEFAULT 0x40 376 #define IPG_IFG_IPG2_SHIFT 24 377 #define IPG_IFG_IPG2_DEFAULT 0x60 378 379 /* Station address. */ 380 #define ALC_PAR0 0x1488 381 #define ALC_PAR1 0x148C 382 383 /* 64bit multicast hash register. */ 384 #define ALC_MAR0 0x1490 385 #define ALC_MAR1 0x1494 386 387 /* half-duplex parameter configuration. */ 388 #define ALC_HDPX_CFG 0x1498 389 #define HDPX_CFG_LCOL_MASK 0x000003FF 390 #define HDPX_CFG_RETRY_MASK 0x0000F000 391 #define HDPX_CFG_EXC_DEF_EN 0x00010000 392 #define HDPX_CFG_NO_BACK_C 0x00020000 393 #define HDPX_CFG_NO_BACK_P 0x00040000 394 #define HDPX_CFG_ABEBE 0x00080000 395 #define HDPX_CFG_ABEBT_MASK 0x00F00000 396 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 397 #define HDPX_CFG_LCOL_SHIFT 0 398 #define HDPX_CFG_LCOL_DEFAULT 0x37 399 #define HDPX_CFG_RETRY_SHIFT 12 400 #define HDPX_CFG_RETRY_DEFAULT 0x0F 401 #define HDPX_CFG_ABEBT_SHIFT 20 402 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 403 #define HDPX_CFG_JAMIPG_SHIFT 24 404 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 405 406 #define ALC_FRAME_SIZE 0x149C 407 408 #define ALC_WOL_CFG 0x14A0 409 #define WOL_CFG_PATTERN 0x00000001 410 #define WOL_CFG_PATTERN_ENB 0x00000002 411 #define WOL_CFG_MAGIC 0x00000004 412 #define WOL_CFG_MAGIC_ENB 0x00000008 413 #define WOL_CFG_LINK_CHG 0x00000010 414 #define WOL_CFG_LINK_CHG_ENB 0x00000020 415 #define WOL_CFG_PATTERN_DET 0x00000100 416 #define WOL_CFG_MAGIC_DET 0x00000200 417 #define WOL_CFG_LINK_CHG_DET 0x00000400 418 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 419 #define WOL_CFG_PATTERN0 0x00010000 420 #define WOL_CFG_PATTERN1 0x00020000 421 #define WOL_CFG_PATTERN2 0x00040000 422 #define WOL_CFG_PATTERN3 0x00080000 423 #define WOL_CFG_PATTERN4 0x00100000 424 #define WOL_CFG_PATTERN5 0x00200000 425 #define WOL_CFG_PATTERN6 0x00400000 426 427 /* WOL pattern length. */ 428 #define ALC_PATTERN_CFG0 0x14A4 429 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 430 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 431 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 432 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 433 434 #define ALC_PATTERN_CFG1 0x14A8 435 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 436 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 437 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 438 439 /* RSS */ 440 #define ALC_RSS_KEY0 0x14B0 441 442 #define ALC_RSS_KEY1 0x14B4 443 444 #define ALC_RSS_KEY2 0x14B8 445 446 #define ALC_RSS_KEY3 0x14BC 447 448 #define ALC_RSS_KEY4 0x14C0 449 450 #define ALC_RSS_KEY5 0x14C4 451 452 #define ALC_RSS_KEY6 0x14C8 453 454 #define ALC_RSS_KEY7 0x14CC 455 456 #define ALC_RSS_KEY8 0x14D0 457 458 #define ALC_RSS_KEY9 0x14D4 459 460 #define ALC_RSS_IDT_TABLE0 0x14E0 461 462 #define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ 463 464 #define ALC_RSS_IDT_TABLE1 0x14E4 465 466 #define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ 467 468 #define ALC_RSS_IDT_TABLE2 0x14E8 469 470 #define ALC_RSS_IDT_TABLE3 0x14EC 471 472 #define ALC_RSS_IDT_TABLE4 0x14F0 473 474 #define ALC_RSS_IDT_TABLE5 0x14F4 475 476 #define ALC_RSS_IDT_TABLE6 0x14F8 477 478 #define ALC_RSS_IDT_TABLE7 0x14FC 479 480 #define ALC_SRAM_RD0_ADDR 0x1500 481 482 #define ALC_SRAM_RD1_ADDR 0x1504 483 484 #define ALC_SRAM_RD2_ADDR 0x1508 485 486 #define ALC_SRAM_RD3_ADDR 0x150C 487 488 #define RD_HEAD_ADDR_MASK 0x000003FF 489 #define RD_TAIL_ADDR_MASK 0x03FF0000 490 #define RD_HEAD_ADDR_SHIFT 0 491 #define RD_TAIL_ADDR_SHIFT 16 492 493 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 494 #define RD_NIC_LEN_MASK 0x000003FF 495 496 #define ALC_RD_NIC_LEN1 0x1514 497 498 #define ALC_SRAM_TD_ADDR 0x1518 499 #define TD_HEAD_ADDR_MASK 0x000003FF 500 #define TD_TAIL_ADDR_MASK 0x03FF0000 501 #define TD_HEAD_ADDR_SHIFT 0 502 #define TD_TAIL_ADDR_SHIFT 16 503 504 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 505 #define SRAM_TD_LEN_MASK 0x000003FF 506 507 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 508 509 #define ALC_SRAM_RX_FIFO_LEN 0x1524 510 #define SRAM_RX_FIFO_LEN_MASK 0x00000FFF 511 #define SRAM_RX_FIFO_LEN_SHIFT 0 512 513 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 514 515 #define ALC_SRAM_TX_FIFO_LEN 0x152C 516 517 #define ALC_SRAM_TCPH_ADDR 0x1530 518 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 519 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 520 #define SRAM_TCPH_ADDR_SHIFT 0 521 #define SRAM_PKTH_ADDR_SHIFT 16 522 523 #define ALC_DMA_BLOCK 0x1534 524 #define DMA_BLOCK_LOAD 0x00000001 525 526 #define ALC_RX_BASE_ADDR_HI 0x1540 527 528 #define ALC_TX_BASE_ADDR_HI 0x1544 529 530 #define ALC_SMB_BASE_ADDR_HI 0x1548 531 532 #define ALC_SMB_BASE_ADDR_LO 0x154C 533 534 #define ALC_RD0_HEAD_ADDR_LO 0x1550 535 536 #define ALC_RD1_HEAD_ADDR_LO 0x1554 537 538 #define ALC_RD2_HEAD_ADDR_LO 0x1558 539 540 #define ALC_RD3_HEAD_ADDR_LO 0x155C 541 542 #define ALC_RD_RING_CNT 0x1560 543 #define RD_RING_CNT_MASK 0x00000FFF 544 #define RD_RING_CNT_SHIFT 0 545 546 #define ALC_RX_BUF_SIZE 0x1564 547 #define RX_BUF_SIZE_MASK 0x0000FFFF 548 /* 549 * If larger buffer size than 1536 is specified the controller 550 * will be locked up. This is hardware limitation. 551 */ 552 #define RX_BUF_SIZE_MAX 1536 553 554 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 555 556 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 557 558 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 559 560 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 561 562 #define ALC_RRD_RING_CNT 0x1578 563 #define RRD_RING_CNT_MASK 0x00000FFF 564 #define RRD_RING_CNT_SHIFT 0 565 566 #define ALC_TDH_HEAD_ADDR_LO 0x157C 567 568 #define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ 569 570 #define ALC_TDL_HEAD_ADDR_LO 0x1580 571 572 #define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ 573 574 #define ALC_TD_RING_CNT 0x1584 575 #define TD_RING_CNT_MASK 0x0000FFFF 576 #define TD_RING_CNT_SHIFT 0 577 578 #define ALC_CMB_BASE_ADDR_LO 0x1588 579 580 #define ALC_TXQ_CFG 0x1590 581 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 582 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 583 #define TXQ_CFG_ENB 0x00000020 584 #define TXQ_CFG_ENHANCED_MODE 0x00000040 585 #define TXQ_CFG_8023_ENB 0x00000080 586 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 587 #define TXQ_CFG_TD_BURST_SHIFT 0 588 #define TXQ_CFG_TD_BURST_DEFAULT 5 589 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 590 591 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 592 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 593 #define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 594 #define TSO_OFFLOAD_THRESH_SHIFT 0 595 #define TSO_OFFLOAD_THRESH_UNIT 8 596 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 597 598 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 599 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 600 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 601 #define TXF_WATER_MARK_BURST_ENB 0x80000000 602 #define TXF_WATER_MARK_LO_SHIFT 0 603 #define TXF_WATER_MARK_HI_SHIFT 16 604 605 #define ALC_THROUGHPUT_MON 0x159C 606 #define THROUGHPUT_MON_RATE_MASK 0x00000003 607 #define THROUGHPUT_MON_ENB 0x00000080 608 #define THROUGHPUT_MON_RATE_SHIFT 0 609 610 #define ALC_RXQ_CFG 0x15A0 611 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 612 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 613 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 614 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 615 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 616 #define RXQ_CFG_QUEUE1_ENB 0x00000010 617 #define RXQ_CFG_QUEUE2_ENB 0x00000020 618 #define RXQ_CFG_QUEUE3_ENB 0x00000040 619 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 620 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 621 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 622 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 623 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 624 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 625 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 626 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 627 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 628 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 629 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 630 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 631 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 632 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 633 #define RXQ_CFG_QUEUE0_ENB 0x80000000 634 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 635 #define RXQ_CFG_RD_BURST_DEFAULT 8 636 #define RXQ_CFG_RD_BURST_SHIFT 20 637 #define RXQ_CFG_ENB \ 638 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 639 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 640 641 /* AR816x specific bits */ 642 #define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 643 #define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 644 #define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 645 #define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 646 #define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C 647 #define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 648 #define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 649 #define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 650 #define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 651 652 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 653 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 654 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 655 #define RX_RD_FREE_THRESH_HI_SHIFT 0 656 #define RX_RD_FREE_THRESH_LO_SHIFT 6 657 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 658 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 659 660 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 661 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 662 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 663 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 664 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 665 666 /* 667 * Size = tx-packet(1522) + IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + 668 * rx-packet(1522) + delay-of-link(64) 669 * = 3212. 670 */ 671 #define RX_FIFO_PAUSE_816X_RSVD 3212 672 673 #define ALC_RD_DMA_CFG 0x15AC 674 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 675 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 676 #define RD_DMA_CFG_THRESH_SHIFT 0 677 #define RD_DMA_CFG_TIMER_SHIFT 16 678 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 679 #define RD_DMA_CFG_TIMER_DEFAULT 0 680 #define RD_DMA_CFG_TICK_USECS 8 681 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 682 683 #define ALC_RSS_HASH_VALUE 0x15B0 684 685 #define ALC_RSS_HASH_FLAG 0x15B4 686 687 #define ALC_RSS_CPU 0x15B8 688 689 #define ALC_DMA_CFG 0x15C0 690 #define DMA_CFG_IN_ORDER 0x00000001 691 #define DMA_CFG_ENH_ORDER 0x00000002 692 #define DMA_CFG_OUT_ORDER 0x00000004 693 #define DMA_CFG_RCB_64 0x00000000 694 #define DMA_CFG_RCB_128 0x00000008 695 #define DMA_CFG_PEND_AUTO_RST 0x00000008 696 #define DMA_CFG_RD_BURST_128 0x00000000 697 #define DMA_CFG_RD_BURST_256 0x00000010 698 #define DMA_CFG_RD_BURST_512 0x00000020 699 #define DMA_CFG_RD_BURST_1024 0x00000030 700 #define DMA_CFG_RD_BURST_2048 0x00000040 701 #define DMA_CFG_RD_BURST_4096 0x00000050 702 #define DMA_CFG_WR_BURST_128 0x00000000 703 #define DMA_CFG_WR_BURST_256 0x00000080 704 #define DMA_CFG_WR_BURST_512 0x00000100 705 #define DMA_CFG_WR_BURST_1024 0x00000180 706 #define DMA_CFG_WR_BURST_2048 0x00000200 707 #define DMA_CFG_WR_BURST_4096 0x00000280 708 #define DMA_CFG_RD_REQ_PRI 0x00000400 709 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 710 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 711 #define DMA_CFG_CMB_ENB 0x00100000 712 #define DMA_CFG_SMB_ENB 0x00200000 713 #define DMA_CFG_CMB_NOW 0x00400000 714 #define DMA_CFG_SMB_DIS 0x01000000 715 #define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 716 #define DMA_CFG_RD_CHNL_SEL_1 0x00000000 717 #define DMA_CFG_RD_CHNL_SEL_2 0x04000000 718 #define DMA_CFG_RD_CHNL_SEL_3 0x08000000 719 #define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 720 #define DMA_CFG_WSRAM_RDCTL 0x10000000 721 #define DMA_CFG_RD_PEND_CLR 0x20000000 722 #define DMA_CFG_WR_PEND_CLR 0x40000000 723 #define DMA_CFG_SMB_NOW 0x80000000 724 #define DMA_CFG_RD_BURST_MASK 0x07 725 #define DMA_CFG_RD_BURST_SHIFT 4 726 #define DMA_CFG_WR_BURST_MASK 0x07 727 #define DMA_CFG_WR_BURST_SHIFT 7 728 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 729 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 730 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 731 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 732 733 #define ALC_SMB_STAT_TIMER 0x15C4 734 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 735 #define SMB_STAT_TIMER_SHIFT 0 736 737 #define ALC_CMB_TD_THRESH 0x15C8 738 #define CMB_TD_THRESH_MASK 0x0000FFFF 739 #define CMB_TD_THRESH_SHIFT 0 740 741 #define ALC_CMB_TX_TIMER 0x15CC 742 #define CMB_TX_TIMER_MASK 0x0000FFFF 743 #define CMB_TX_TIMER_SHIFT 0 744 745 #define ALC_MSI_MAP_TBL1 0x15D0 746 747 #define ALC_MSI_ID_MAP 0x15D4 748 749 #define ALC_MSI_MAP_TBL2 0x15D8 750 751 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 752 753 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 754 755 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 756 757 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 758 759 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 760 #define MBOX_RD_PROD_SHIFT 0 761 762 #define ALC_MBOX_TD_PROD_IDX 0x15F0 763 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 764 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 765 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 766 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 767 768 #define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ 769 770 #define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ 771 772 #define ALC_MBOX_TD_CONS_IDX 0x15F4 773 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 774 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 775 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 776 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 777 778 #define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ 779 780 #define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ 781 782 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 783 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 784 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 785 #define MBOX_RD0_CONS_IDX_SHIFT 0 786 #define MBOX_RD1_CONS_IDX_SHIFT 16 787 788 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 789 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 790 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 791 #define MBOX_RD2_CONS_IDX_SHIFT 0 792 #define MBOX_RD3_CONS_IDX_SHIFT 16 793 794 #define ALC_INTR_STATUS 0x1600 795 #define INTR_SMB 0x00000001 796 #define INTR_TIMER 0x00000002 797 #define INTR_MANUAL_TIMER 0x00000004 798 #define INTR_RX_FIFO_OFLOW 0x00000008 799 #define INTR_RD0_UNDERRUN 0x00000010 800 #define INTR_RD1_UNDERRUN 0x00000020 801 #define INTR_RD2_UNDERRUN 0x00000040 802 #define INTR_RD3_UNDERRUN 0x00000080 803 #define INTR_TX_FIFO_UNDERRUN 0x00000100 804 #define INTR_DMA_RD_TO_RST 0x00000200 805 #define INTR_DMA_WR_TO_RST 0x00000400 806 #define INTR_TX_CREDIT 0x00000800 807 #define INTR_GPHY 0x00001000 808 #define INTR_GPHY_LOW_PW 0x00002000 809 #define INTR_TXQ_TO_RST 0x00004000 810 #define INTR_TX_PKT0 0x00008000 811 #define INTR_RX_PKT0 0x00010000 812 #define INTR_RX_PKT1 0x00020000 813 #define INTR_RX_PKT2 0x00040000 814 #define INTR_RX_PKT3 0x00080000 815 #define INTR_MAC_RX 0x00100000 816 #define INTR_MAC_TX 0x00200000 817 #define INTR_UNDERRUN 0x00400000 818 #define INTR_FRAME_ERROR 0x00800000 819 #define INTR_FRAME_OK 0x01000000 820 #define INTR_CSUM_ERROR 0x02000000 821 #define INTR_PHY_LINK_DOWN 0x04000000 822 #define INTR_DIS_INT 0x80000000 823 824 /* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ 825 #define INTR_TX_PKT1 0x00000020 826 #define INTR_TX_PKT2 0x00000040 827 #define INTR_TX_PKT3 0x00000080 828 #define INTR_RX_PKT4 0x08000000 829 #define INTR_RX_PKT5 0x10000000 830 #define INTR_RX_PKT6 0x20000000 831 #define INTR_RX_PKT7 0x40000000 832 833 /* Interrupt Mask Register */ 834 #define ALC_INTR_MASK 0x1604 835 836 #ifdef notyet 837 #define INTR_RX_PKT \ 838 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 839 INTR_RX_PKT3) 840 #define INTR_RD_UNDERRUN \ 841 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 842 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 843 #else 844 #define INTR_TX_PKT INTR_TX_PKT0 845 #define INTR_RX_PKT INTR_RX_PKT0 846 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 847 #endif 848 849 #define ALC_INTRS \ 850 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 851 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 852 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 853 INTR_TX_FIFO_UNDERRUN) 854 855 #define ALC_INTR_RETRIG_TIMER 0x1608 856 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 857 #define INTR_RETRIG_TIMER_SHIFT 0 858 859 #define ALC_HDS_CFG 0x160C 860 #define HDS_CFG_ENB 0x00000001 861 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 862 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 863 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 864 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 865 866 #define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ 867 868 #define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ 869 870 #define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ 871 872 #define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ 873 874 /* AR813x/AR815x registers for MAC statistics */ 875 #define ALC_RX_MIB_BASE 0x1700 876 877 #define ALC_TX_MIB_BASE 0x1760 878 879 #define ALC_DRV 0x1804 /* AR816x */ 880 #define DRV_ASPM_SPD10LMT_1M 0x00000000 881 #define DRV_ASPM_SPD10LMT_10M 0x00000001 882 #define DRV_ASPM_SPD10LMT_100M 0x00000002 883 #define DRV_ASPM_SPD10LMT_NO 0x00000003 884 #define DRV_ASPM_SPD10LMT_MASK 0x00000003 885 #define DRV_ASPM_SPD100LMT_1M 0x00000000 886 #define DRV_ASPM_SPD100LMT_10M 0x00000004 887 #define DRV_ASPM_SPD100LMT_100M 0x00000008 888 #define DRV_ASPM_SPD100LMT_NO 0x0000000C 889 #define DRV_ASPM_SPD100LMT_MASK 0x0000000C 890 #define DRV_ASPM_SPD1000LMT_100M 0x00000000 891 #define DRV_ASPM_SPD1000LMT_NO 0x00000010 892 #define DRV_ASPM_SPD1000LMT_1M 0x00000020 893 #define DRV_ASPM_SPD1000LMT_10M 0x00000030 894 #define DRV_ASPM_SPD1000LMT_MASK 0x00000000 895 #define DRV_WOLCAP_BIOS_EN 0x00000100 896 #define DRV_WOLMAGIC_EN 0x00000200 897 #define DRV_WOLLINKUP_EN 0x00000400 898 #define DRV_WOLPATTERN_EN 0x00000800 899 #define DRV_AZ_EN 0x00001000 900 #define DRV_WOLS5_BIOS_EN 0x00010000 901 #define DRV_WOLS5_EN 0x00020000 902 #define DRV_DISABLE 0x00040000 903 #define DRV_PHY_MASK 0x1FE00000 904 #define DRV_PHY_EEE 0x00200000 905 #define DRV_PHY_APAUSE 0x00400000 906 #define DRV_PHY_PAUSE 0x00800000 907 #define DRV_PHY_DUPLEX 0x01000000 908 #define DRV_PHY_10 0x02000000 909 #define DRV_PHY_100 0x04000000 910 #define DRV_PHY_1000 0x08000000 911 #define DRV_PHY_AUTO 0x10000000 912 #define DRV_PHY_SHIFT 21 913 914 #define ALC_CLK_GATING_CFG 0x1814 915 #define CLK_GATING_DMAW_ENB 0x0001 916 #define CLK_GATING_DMAR_ENB 0x0002 917 #define CLK_GATING_TXQ_ENB 0x0004 918 #define CLK_GATING_RXQ_ENB 0x0008 919 #define CLK_GATING_TXMAC_ENB 0x0010 920 #define CLK_GATING_RXMAC_ENB 0x0020 921 922 #define ALC_DEBUG_DATA0 0x1900 923 924 #define ALC_DEBUG_DATA1 0x1904 925 926 #define ALC_MSI_RETRANS_TIMER 0x1920 927 #define MSI_RETRANS_TIMER_MASK 0x0000FFFF 928 #define MSI_RETRANS_MASK_SEL_STD 0x00000000 929 #define MSI_RETRANS_MASK_SEL_LINE 0x00010000 930 #define MSI_RETRANS_TIMER_SHIFT 0 931 932 #define ALC_WRR 0x1938 933 #define WRR_PRI0_MASK 0x0000001F 934 #define WRR_PRI1_MASK 0x00001F00 935 #define WRR_PRI2_MASK 0x001F0000 936 #define WRR_PRI3_MASK 0x1F000000 937 #define WRR_PRI_RESTRICT_MASK 0x60000000 938 #define WRR_PRI_RESTRICT_ALL 0x00000000 939 #define WRR_PRI_RESTRICT_HI 0x20000000 940 #define WRR_PRI_RESTRICT_HI2 0x40000000 941 #define WRR_PRI_RESTRICT_NONE 0x60000000 942 #define WRR_PRI0_SHIFT 0 943 #define WRR_PRI1_SHIFT 8 944 #define WRR_PRI2_SHIFT 16 945 #define WRR_PRI3_SHIFT 24 946 #define WRR_PRI_DEFAULT 4 947 #define WRR_PRI_RESTRICT_SHIFT 29 948 949 #define ALC_HQTD_CFG 0x193C 950 #define HQTD_CFG_Q1_BURST_MASK 0x0000000F 951 #define HQTD_CFG_Q2_BURST_MASK 0x000000F0 952 #define HQTD_CFG_Q3_BURST_MASK 0x00000F00 953 #define HQTD_CFG_BURST_ENB 0x80000000 954 #define HQTD_CFG_Q1_BURST_SHIFT 0 955 #define HQTD_CFG_Q2_BURST_SHIFT 4 956 #define HQTD_CFG_Q3_BURST_SHIFT 8 957 958 #define ALC_MISC 0x19C0 959 #define MISC_INTNLOSC_OPEN 0x00000008 960 #define MISC_ISO_ENB 0x00001000 961 #define MISC_PSW_OCP_MASK 0x00E00000 962 #define MISC_PSW_OCP_SHIFT 21 963 #define MISC_PSW_OCP_DEFAULT 7 964 965 #define ALC_MISC2 0x19C8 966 #define MISC2_CALB_START 0x00000001 967 968 #define ALC_MISC3 0x19CC 969 #define MISC3_25M_NOTO_INTNL 0x00000001 970 #define MISC3_25M_BY_SW 0x00000002 971 972 #define ALC_MII_DBG_ADDR 0x1D 973 #define ALC_MII_DBG_DATA 0x1E 974 975 #define MII_ANA_CFG0 0x00 976 #define ANA_RESTART_CAL 0x0001 977 #define ANA_MANUL_SWICH_ON_MASK 0x001E 978 #define ANA_MAN_ENABLE 0x0020 979 #define ANA_SEL_HSP 0x0040 980 #define ANA_EN_HB 0x0080 981 #define ANA_EN_HBIAS 0x0100 982 #define ANA_OEN_125M 0x0200 983 #define ANA_EN_LCKDT 0x0400 984 #define ANA_LCKDT_PHY 0x0800 985 #define ANA_AFE_MODE 0x1000 986 #define ANA_VCO_SLOW 0x2000 987 #define ANA_VCO_FAST 0x4000 988 #define ANA_SEL_CLK125M_DSP 0x8000 989 #define ANA_MANUL_SWICH_ON_SHIFT 1 990 991 #define MII_DBG_ANACTL 0x00 992 #define DBG_ANACTL_DEFAULT 0x02EF 993 994 #define MII_ANA_CFG4 0x04 995 #define ANA_IECHO_ADJ_MASK 0x0F 996 #define ANA_IECHO_ADJ_3_MASK 0x000F 997 #define ANA_IECHO_ADJ_2_MASK 0x00F0 998 #define ANA_IECHO_ADJ_1_MASK 0x0F00 999 #define ANA_IECHO_ADJ_0_MASK 0xF000 1000 #define ANA_IECHO_ADJ_3_SHIFT 0 1001 #define ANA_IECHO_ADJ_2_SHIFT 4 1002 #define ANA_IECHO_ADJ_1_SHIFT 8 1003 #define ANA_IECHO_ADJ_0_SHIFT 12 1004 1005 #define MII_DBG_SYSMODCTL 0x04 1006 #define DBG_SYSMODCTL_DEFAULT 0xBB8B 1007 1008 #define MII_ANA_CFG5 0x05 1009 #define ANA_SERDES_CDR_BW_MASK 0x0003 1010 #define ANA_MS_PAD_DBG 0x0004 1011 #define ANA_SPEEDUP_DBG 0x0008 1012 #define ANA_SERDES_TH_LOS_MASK 0x0030 1013 #define ANA_SERDES_EN_DEEM 0x0040 1014 #define ANA_SERDES_TXELECIDLE 0x0080 1015 #define ANA_SERDES_BEACON 0x0100 1016 #define ANA_SERDES_HALFTXDR 0x0200 1017 #define ANA_SERDES_SEL_HSP 0x0400 1018 #define ANA_SERDES_EN_PLL 0x0800 1019 #define ANA_SERDES_EN 0x1000 1020 #define ANA_SERDES_EN_LCKDT 0x2000 1021 #define ANA_SERDES_CDR_BW_SHIFT 0 1022 #define ANA_SERDES_TH_LOS_SHIFT 4 1023 1024 #define MII_DBG_SRDSYSMOD 0x05 1025 #define DBG_SRDSYSMOD_DEFAULT 0x2C46 1026 1027 #define MII_ANA_CFG11 0x0B 1028 #define ANA_PS_HIB_EN 0x8000 1029 1030 #define MII_DBG_HIBNEG 0x0B 1031 #define DBG_HIBNEG_HIB_PULSE 0x1000 1032 #define DBG_HIBNEG_PSHIB_EN 0x8000 1033 #define DBG_HIBNEG_DEFAULT 0xBC40 1034 1035 #define MII_ANA_CFG18 0x12 1036 #define ANA_TEST_MODE_10BT_01MASK 0x0003 1037 #define ANA_LOOP_SEL_10BT 0x0004 1038 #define ANA_RGMII_MODE_SW 0x0008 1039 #define ANA_EN_LONGECABLE 0x0010 1040 #define ANA_TEST_MODE_10BT_2 0x0020 1041 #define ANA_EN_10BT_IDLE 0x0400 1042 #define ANA_EN_MASK_TB 0x0800 1043 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 1044 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 1045 #define ANA_TEST_MODE_10BT_01SHIFT 0 1046 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 1047 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 1048 1049 #define MII_DBG_TST10BTCFG 0x12 1050 #define DBG_TST10BTCFG_DEFAULT 0x4C04 1051 1052 #define MII_DBG_AZ_ANADECT 0x15 1053 #define DBG_AZ_ANADECT_DEFAULT 0x3220 1054 #define DBG_AZ_ANADECT_LONG 0x3210 1055 1056 #define MII_DBG_MSE16DB 0x18 1057 #define DBG_MSE16DB_UP 0x05EA 1058 #define DBG_MSE16DB_DOWN 0x02EA 1059 1060 #define MII_DBG_MSE20DB 0x1C 1061 #define DBG_MSE20DB_TH_MASK 0x01FC 1062 #define DBG_MSE20DB_TH_DEFAULT 0x2E 1063 #define DBG_MSE20DB_TH_HI 0x54 1064 #define DBG_MSE20DB_TH_SHIFT 2 1065 1066 #define MII_DBG_AGC 0x23 1067 #define DBG_AGC_2_VGA_MASK 0x3F00 1068 #define DBG_AGC_2_VGA_SHIFT 8 1069 #define DBG_AGC_LONG1G_LIMT 40 1070 #define DBG_AGC_LONG100M_LIMT 44 1071 1072 #define MII_ANA_CFG41 0x29 1073 #define ANA_TOP_PS_EN 0x8000 1074 1075 #define MII_DBG_LEGCYPS 0x29 1076 #define DBG_LEGCYPS_ENB 0x8000 1077 #define DBG_LEGCYPS_DEFAULT 0x129D 1078 1079 #define MII_ANA_CFG54 0x36 1080 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 1081 #define ANA_DESERVED 0x0040 1082 #define ANA_EN_LIT_CH 0x0080 1083 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 1084 #define ANA_BP_BAD_LINK_ACCUM 0x4000 1085 #define ANA_BP_SMALL_BW 0x8000 1086 #define ANA_LONG_CABLE_TH_100_SHIFT 0 1087 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 1088 1089 #define MII_DBG_TST100BTCFG 0x36 1090 #define DBG_TST100BTCFG_DEFAULT 0xE12C 1091 1092 #define MII_DBG_GREENCFG 0x3B 1093 #define DBG_GREENCFG_DEFAULT 0x7078 1094 1095 #define MII_DBG_GREENCFG2 0x3D 1096 #define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 1097 #define DBG_GREENCFG2_BP_GREEN 0x8000 1098 1099 /* Device addr 3 */ 1100 #define MII_EXT_PCS 3 1101 1102 #define MII_EXT_CLDCTL3 0x8003 1103 #define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 1104 1105 #define MII_EXT_CLDCTL5 0x8005 1106 #define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 1107 1108 #define MII_EXT_CLDCTL6 0x8006 1109 #define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF 1110 #define EXT_CLDCTL6_CAB_LEN_SHIFT 0 1111 #define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 1112 #define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 1113 1114 #define MII_EXT_VDRVBIAS 0x8062 1115 #define EXT_VDRVBIAS_DEFAULT 3 1116 1117 /* Device addr 7 */ 1118 #define MII_EXT_ANEG 7 1119 1120 #define MII_EXT_ANEG_LOCAL_EEEADV 0x3C 1121 #define ANEG_LOCA_EEEADV_100BT 0x0002 1122 #define ANEG_LOCA_EEEADV_1000BT 0x0004 1123 1124 #define MII_EXT_ANEG_AFE 0x801A 1125 #define ANEG_AFEE_10BT_100M_TH 0x0040 1126 1127 #define MII_EXT_ANEG_S3DIG10 0x8023 1128 #define ANEG_S3DIG10_SL 0x0001 1129 #define ANEG_S3DIG10_DEFAULT 0 1130 1131 #define MII_EXT_ANEG_NLP78 0x8027 1132 #define ANEG_NLP78_120M_DEFAULT 0x8A05 1133 1134 /* Statistics counters collected by the MAC. */ 1135 struct smb { 1136 /* Rx stats. */ 1137 uint32_t rx_frames; 1138 uint32_t rx_bcast_frames; 1139 uint32_t rx_mcast_frames; 1140 uint32_t rx_pause_frames; 1141 uint32_t rx_control_frames; 1142 uint32_t rx_crcerrs; 1143 uint32_t rx_lenerrs; 1144 uint32_t rx_bytes; 1145 uint32_t rx_runts; 1146 uint32_t rx_fragments; 1147 uint32_t rx_pkts_64; 1148 uint32_t rx_pkts_65_127; 1149 uint32_t rx_pkts_128_255; 1150 uint32_t rx_pkts_256_511; 1151 uint32_t rx_pkts_512_1023; 1152 uint32_t rx_pkts_1024_1518; 1153 uint32_t rx_pkts_1519_max; 1154 uint32_t rx_pkts_truncated; 1155 uint32_t rx_fifo_oflows; 1156 uint32_t rx_rrs_errs; 1157 uint32_t rx_alignerrs; 1158 uint32_t rx_bcast_bytes; 1159 uint32_t rx_mcast_bytes; 1160 uint32_t rx_pkts_filtered; 1161 /* Tx stats. */ 1162 uint32_t tx_frames; 1163 uint32_t tx_bcast_frames; 1164 uint32_t tx_mcast_frames; 1165 uint32_t tx_pause_frames; 1166 uint32_t tx_excess_defer; 1167 uint32_t tx_control_frames; 1168 uint32_t tx_deferred; 1169 uint32_t tx_bytes; 1170 uint32_t tx_pkts_64; 1171 uint32_t tx_pkts_65_127; 1172 uint32_t tx_pkts_128_255; 1173 uint32_t tx_pkts_256_511; 1174 uint32_t tx_pkts_512_1023; 1175 uint32_t tx_pkts_1024_1518; 1176 uint32_t tx_pkts_1519_max; 1177 uint32_t tx_single_colls; 1178 uint32_t tx_multi_colls; 1179 uint32_t tx_late_colls; 1180 uint32_t tx_excess_colls; 1181 uint32_t tx_underrun; 1182 uint32_t tx_desc_underrun; 1183 uint32_t tx_lenerrs; 1184 uint32_t tx_pkts_truncated; 1185 uint32_t tx_bcast_bytes; 1186 uint32_t tx_mcast_bytes; 1187 uint32_t updated; 1188 }; 1189 1190 /* CMB(Coalesing message block) */ 1191 struct cmb { 1192 uint32_t cons; 1193 }; 1194 1195 /* Rx free descriptor */ 1196 struct rx_desc { 1197 uint64_t addr; 1198 }; 1199 1200 /* Rx return descriptor */ 1201 struct rx_rdesc { 1202 uint32_t rdinfo; 1203 #define RRD_CSUM_MASK 0x0000FFFF 1204 #define RRD_RD_CNT_MASK 0x000F0000 1205 #define RRD_RD_IDX_MASK 0xFFF00000 1206 #define RRD_CSUM_SHIFT 0 1207 #define RRD_RD_CNT_SHIFT 16 1208 #define RRD_RD_IDX_SHIFT 20 1209 #define RRD_CSUM(x) \ 1210 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 1211 #define RRD_RD_CNT(x) \ 1212 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 1213 #define RRD_RD_IDX(x) \ 1214 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 1215 uint32_t rss; 1216 uint32_t vtag; 1217 #define RRD_VLAN_MASK 0x0000FFFF 1218 #define RRD_HEAD_LEN_MASK 0x00FF0000 1219 #define RRD_HDS_MASK 0x03000000 1220 #define RRD_HDS_NONE 0x00000000 1221 #define RRD_HDS_HEAD 0x01000000 1222 #define RRD_HDS_DATA 0x02000000 1223 #define RRD_CPU_MASK 0x0C000000 1224 #define RRD_HASH_FLAG_MASK 0xF0000000 1225 #define RRD_VLAN_SHIFT 0 1226 #define RRD_HEAD_LEN_SHIFT 16 1227 #define RRD_HDS_SHIFT 24 1228 #define RRD_CPU_SHIFT 26 1229 #define RRD_HASH_FLAG_SHIFT 28 1230 #define RRD_VLAN(x) \ 1231 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 1232 #define RRD_HEAD_LEN(x) \ 1233 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 1234 #define RRD_CPU(x) \ 1235 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 1236 uint32_t status; 1237 #define RRD_LEN_MASK 0x00003FFF 1238 #define RRD_LEN_SHIFT 0 1239 #define RRD_TCP_UDPCSUM_NOK 0x00004000 1240 #define RRD_IPCSUM_NOK 0x00008000 1241 #define RRD_VLAN_TAG 0x00010000 1242 #define RRD_PROTO_MASK 0x000E0000 1243 #define RRD_PROTO_IPV4 0x00020000 1244 #define RRD_PROTO_IPV6 0x000C0000 1245 #define RRD_ERR_SUM 0x00100000 1246 #define RRD_ERR_CRC 0x00200000 1247 #define RRD_ERR_ALIGN 0x00400000 1248 #define RRD_ERR_TRUNC 0x00800000 1249 #define RRD_ERR_RUNT 0x01000000 1250 #define RRD_ERR_ICMP 0x02000000 1251 #define RRD_BCAST 0x04000000 1252 #define RRD_MCAST 0x08000000 1253 #define RRD_SNAP_LLC 0x10000000 1254 #define RRD_ETHER 0x00000000 1255 #define RRD_FIFO_FULL 0x20000000 1256 #define RRD_ERR_LENGTH 0x40000000 1257 #define RRD_VALID 0x80000000 1258 #define RRD_BYTES(x) \ 1259 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 1260 #define RRD_IPV4(x) \ 1261 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 1262 }; 1263 1264 /* Tx descriptor */ 1265 struct tx_desc { 1266 uint32_t len; 1267 #define TD_BUFLEN_MASK 0x00003FFF 1268 #define TD_VLAN_MASK 0xFFFF0000 1269 #define TD_BUFLEN_SHIFT 0 1270 #define TX_BYTES(x) \ 1271 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 1272 #define TD_VLAN_SHIFT 16 1273 uint32_t flags; 1274 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 1275 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 1276 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 1277 #define TD_CUSTOM_CSUM 0x00000100 1278 #define TD_IPCSUM 0x00000200 1279 #define TD_TCPCSUM 0x00000400 1280 #define TD_UDPCSUM 0x00000800 1281 #define TD_TSO 0x00001000 1282 #define TD_TSO_DESCV1 0x00000000 1283 #define TD_TSO_DESCV2 0x00002000 1284 #define TD_CON_VLAN_TAG 0x00004000 1285 #define TD_INS_VLAN_TAG 0x00008000 1286 #define TD_IPV4_DESCV2 0x00010000 1287 #define TD_LLC_SNAP 0x00020000 1288 #define TD_ETHERNET 0x00000000 1289 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 1290 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 1291 #define TD_MSS_MASK 0x7FFC0000 1292 #define TD_EOP 0x80000000 1293 #define TD_L4HDR_OFFSET_SHIFT 0 1294 #define TD_TCPHDR_OFFSET_SHIFT 0 1295 #define TD_PLOAD_OFFSET_SHIFT 0 1296 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 1297 #define TD_MSS_SHIFT 18 1298 uint64_t addr; 1299 }; 1300 1301 #endif /* _IF_ALCREG_H */ 1302