1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMATE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 * $DragonFly$ 29 */ 30 31 #ifndef _IF_ALCREG_H 32 #define _IF_ALCREG_H 33 34 /* 35 * Atheros Communucations, Inc. PCI vendor ID 36 */ 37 #define VENDORID_ATHEROS 0x1969 38 39 /* 40 * Atheros AR8131/AR8132 device ID 41 */ 42 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 43 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 44 45 /* 46 * From FreeBSD dev/pci/pcireg.h 47 * 48 * PCIM_xxx: mask to locate subfield in register 49 * PCIR_xxx: config register offset 50 */ 51 #define PCIR_EXPRESS_DEVICE_CTL 0x8 52 #define PCIR_EXPRESS_LINK_CAP 0xc 53 #define PCIR_EXPRESS_LINK_CTL 0x10 54 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 55 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 56 #define PCIM_LINK_CAP_ASPM 0x00000c00 57 58 /* 0x0000 - 0x02FF : PCIe configuration space */ 59 60 #define ALC_PEX_UNC_ERR_SEV 0x10C 61 #define PEX_UNC_ERR_SEV_TRN 0x00000001 62 #define PEX_UNC_ERR_SEV_DLP 0x00000010 63 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 64 #define PEX_UNC_ERR_SEV_FCP 0x00002000 65 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 66 #define PEX_UNC_ERR_SEV_CA 0x00008000 67 #define PEX_UNC_ERR_SEV_UC 0x00010000 68 #define PEX_UNC_ERR_SEV_ROV 0x00020000 69 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 70 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 71 #define PEX_UNC_ERR_SEV_UR 0x00100000 72 73 #define ALC_TWSI_CFG 0x218 74 #define TWSI_CFG_SW_LD_START 0x00000800 75 #define TWSI_CFG_HW_LD_START 0x00001000 76 #define TWSI_CFG_LD_EXIST 0x00400000 77 78 #define ALC_PCIE_PHYMISC 0x1000 79 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 80 81 #define ALC_TWSI_DEBUG 0x1108 82 #define TWSI_DEBUG_DEV_EXIST 0x20000000 83 84 #define ALC_EEPROM_CFG 0x12C0 85 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 86 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 87 #define EEPROM_CFG_ACK 0x40000000 88 #define EEPROM_CFG_RW 0x80000000 89 #define EEPROM_CFG_DATA_HI_SHIFT 0 90 #define EEPROM_CFG_ADDR_SHIFT 16 91 92 #define ALC_EEPROM_DATA_LO 0x12C4 93 94 #define ALC_OPT_CFG 0x12F0 95 #define OPT_CFG_CLK_ENB 0x00000002 96 97 #define ALC_PM_CFG 0x12F8 98 #define PM_CFG_SERDES_ENB 0x00000001 99 #define PM_CFG_RBER_ENB 0x00000002 100 #define PM_CFG_CLK_REQ_ENB 0x00000004 101 #define PM_CFG_ASPM_L1_ENB 0x00000008 102 #define PM_CFG_SERDES_L1_ENB 0x00000010 103 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 104 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 105 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 106 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 107 #define PM_CFG_ASPM_L0S_ENB 0x00001000 108 #define PM_CFG_CLK_SWH_L1 0x00002000 109 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 110 #define PM_CFG_PCIE_RECV 0x00008000 111 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 112 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 113 #define PM_CFG_LCKDET_TIMER_MASK 0x3F000000 114 #define PM_CFG_MAC_ASPM_CHK 0x40000000 115 #define PM_CFG_HOTRST 0x80000000 116 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 117 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 118 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 119 #define PM_CFG_LCKDET_TIMER_SHIFT 24 120 121 #define ALC_MASTER_CFG 0x1400 122 #define MASTER_RESET 0x00000001 123 #define MASTER_BERT_START 0x00000010 124 #define MASTER_TEST_MODE_MASK 0x000000C0 125 #define MASTER_MTIMER_ENB 0x00000100 126 #define MASTER_MANUAL_INTR_ENB 0x00000200 127 #define MASTER_IM_TX_TIMER_ENB 0x00000400 128 #define MASTER_IM_RX_TIMER_ENB 0x00000800 129 #define MASTER_CLK_SEL_DIS 0x00001000 130 #define MASTER_CLK_SWH_MODE 0x00002000 131 #define MASTER_INTR_RD_CLR 0x00004000 132 #define MASTER_CHIP_REV_MASK 0x00FF0000 133 #define MASTER_CHIP_ID_MASK 0x7F000000 134 #define MASTER_OTP_SEL 0x80000000 135 #define MASTER_TEST_MODE_SHIFT 2 136 #define MASTER_CHIP_REV_SHIFT 16 137 #define MASTER_CHIP_ID_SHIFT 24 138 139 /* Number of ticks per usec for AR8131/AR8132. */ 140 #define ALC_TICK_USECS 2 141 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 142 143 #define ALC_MANUAL_TIMER 0x1404 144 145 #define ALC_IM_TIMER 0x1408 146 #define IM_TIMER_TX_MASK 0x0000FFFF 147 #define IM_TIMER_RX_MASK 0xFFFF0000 148 #define IM_TIMER_TX_SHIFT 0 149 #define IM_TIMER_RX_SHIFT 16 150 #define ALC_IM_TIMER_MIN 0 151 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 152 /* 153 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 154 * interrupts in a second. 155 */ 156 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 157 /* 158 * alc(4) does not rely on Tx completion interrupts, so set it 159 * somewhat large value to reduce Tx completion interrupts. 160 */ 161 #define ALC_IM_TX_TIMER_DEFAULT 50000 /* 50ms */ 162 163 #define ALC_GPHY_CFG 0x140C /* 16bits */ 164 #define GPHY_CFG_EXT_RESET 0x0001 165 #define GPHY_CFG_RTL_MODE 0x0002 166 #define GPHY_CFG_LED_MODE 0x0004 167 #define GPHY_CFG_ANEG_NOW 0x0008 168 #define GPHY_CFG_RECV_ANEG 0x0010 169 #define GPHY_CFG_GATE_25M_ENB 0x0020 170 #define GPHY_CFG_LPW_EXIT 0x0040 171 #define GPHY_CFG_PHY_IDDQ 0x0080 172 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 173 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 174 #define GPHY_CFG_HIB_EN 0x0400 175 #define GPHY_CFG_HIB_PULSE 0x0800 176 #define GPHY_CFG_SEL_ANA_RESET 0x1000 177 #define GPHY_CFG_PHY_PLL_ON 0x2000 178 #define GPHY_CFG_PWDOWN_HW 0x4000 179 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 180 181 #define ALC_IDLE_STATUS 0x1410 182 #define IDLE_STATUS_RXMAC 0x00000001 183 #define IDLE_STATUS_TXMAC 0x00000002 184 #define IDLE_STATUS_RXQ 0x00000004 185 #define IDLE_STATUS_TXQ 0x00000008 186 #define IDLE_STATUS_DMARD 0x00000010 187 #define IDLE_STATUS_DMAWR 0x00000020 188 #define IDLE_STATUS_SMB 0x00000040 189 #define IDLE_STATUS_CMB 0x00000080 190 191 #define ALC_MDIO 0x1414 192 #define MDIO_DATA_MASK 0x0000FFFF 193 #define MDIO_REG_ADDR_MASK 0x001F0000 194 #define MDIO_OP_READ 0x00200000 195 #define MDIO_OP_WRITE 0x00000000 196 #define MDIO_SUP_PREAMBLE 0x00400000 197 #define MDIO_OP_EXECUTE 0x00800000 198 #define MDIO_CLK_25_4 0x00000000 199 #define MDIO_CLK_25_6 0x02000000 200 #define MDIO_CLK_25_8 0x03000000 201 #define MDIO_CLK_25_10 0x04000000 202 #define MDIO_CLK_25_14 0x05000000 203 #define MDIO_CLK_25_20 0x06000000 204 #define MDIO_CLK_25_28 0x07000000 205 #define MDIO_OP_BUSY 0x08000000 206 #define MDIO_AP_ENB 0x10000000 207 #define MDIO_DATA_SHIFT 0 208 #define MDIO_REG_ADDR_SHIFT 16 209 210 #define MDIO_REG_ADDR(x) \ 211 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 212 /* Default PHY address. */ 213 #define ALC_PHY_ADDR 0 214 215 #define ALC_PHY_STATUS 0x1418 216 #define PHY_STATUS_RECV_ENB 0x00000001 217 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 218 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 219 #define PHY_STATUS_LPW_STATE 0x80000000 220 #define PHY_STATIS_OE_PWSP_SHIFT 16 221 222 /* Packet memory BIST. */ 223 #define ALC_BIST0 0x141C 224 #define BIST0_ENB 0x00000001 225 #define BIST0_SRAM_FAIL 0x00000002 226 #define BIST0_FUSE_FLAG 0x00000004 227 228 /* PCIe retry buffer BIST. */ 229 #define ALC_BIST1 0x1420 230 #define BIST1_ENB 0x00000001 231 #define BIST1_SRAM_FAIL 0x00000002 232 #define BIST1_FUSE_FLAG 0x00000004 233 234 #define ALC_SERDES_LOCK 0x1424 235 #define SERDES_LOCK_DET 0x00000001 236 #define SERDES_LOCK_DET_ENB 0x00000002 237 238 #define ALC_MAC_CFG 0x1480 239 #define MAC_CFG_TX_ENB 0x00000001 240 #define MAC_CFG_RX_ENB 0x00000002 241 #define MAC_CFG_TX_FC 0x00000004 242 #define MAC_CFG_RX_FC 0x00000008 243 #define MAC_CFG_LOOP 0x00000010 244 #define MAC_CFG_FULL_DUPLEX 0x00000020 245 #define MAC_CFG_TX_CRC_ENB 0x00000040 246 #define MAC_CFG_TX_AUTO_PAD 0x00000080 247 #define MAC_CFG_TX_LENCHK 0x00000100 248 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 249 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 250 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 251 #define MAC_CFG_PROMISC 0x00008000 252 #define MAC_CFG_TX_PAUSE 0x00010000 253 #define MAC_CFG_SCNT 0x00020000 254 #define MAC_CFG_SYNC_RST_TX 0x00040000 255 #define MAC_CFG_SIM_RST_TX 0x00080000 256 #define MAC_CFG_SPEED_MASK 0x00300000 257 #define MAC_CFG_SPEED_10_100 0x00100000 258 #define MAC_CFG_SPEED_1000 0x00200000 259 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 260 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 261 #define MAC_CFG_RXCSUM_ENB 0x01000000 262 #define MAC_CFG_ALLMULTI 0x02000000 263 #define MAC_CFG_BCAST 0x04000000 264 #define MAC_CFG_DBG 0x08000000 265 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 266 #define MAC_CFG_PREAMBLE_SHIFT 10 267 #define MAC_CFG_PREAMBLE_DEFAULT 7 268 269 #define ALC_IPG_IFG_CFG 0x1484 270 #define IPG_IFG_IPGT_MASK 0x0000007F 271 #define IPG_IFG_MIFG_MASK 0x0000FF00 272 #define IPG_IFG_IPG1_MASK 0x007F0000 273 #define IPG_IFG_IPG2_MASK 0x7F000000 274 #define IPG_IFG_IPGT_SHIFT 0 275 #define IPG_IFG_IPGT_DEFAULT 0x60 276 #define IPG_IFG_MIFG_SHIFT 8 277 #define IPG_IFG_MIFG_DEFAULT 0x50 278 #define IPG_IFG_IPG1_SHIFT 16 279 #define IPG_IFG_IPG1_DEFAULT 0x40 280 #define IPG_IFG_IPG2_SHIFT 24 281 #define IPG_IFG_IPG2_DEFAULT 0x60 282 283 /* Station address. */ 284 #define ALC_PAR0 0x1488 285 #define ALC_PAR1 0x148C 286 287 /* 64bit multicast hash register. */ 288 #define ALC_MAR0 0x1490 289 #define ALC_MAR1 0x1494 290 291 /* half-duplex parameter configuration. */ 292 #define ALC_HDPX_CFG 0x1498 293 #define HDPX_CFG_LCOL_MASK 0x000003FF 294 #define HDPX_CFG_RETRY_MASK 0x0000F000 295 #define HDPX_CFG_EXC_DEF_EN 0x00010000 296 #define HDPX_CFG_NO_BACK_C 0x00020000 297 #define HDPX_CFG_NO_BACK_P 0x00040000 298 #define HDPX_CFG_ABEBE 0x00080000 299 #define HDPX_CFG_ABEBT_MASK 0x00F00000 300 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 301 #define HDPX_CFG_LCOL_SHIFT 0 302 #define HDPX_CFG_LCOL_DEFAULT 0x37 303 #define HDPX_CFG_RETRY_SHIFT 12 304 #define HDPX_CFG_RETRY_DEFAULT 0x0F 305 #define HDPX_CFG_ABEBT_SHIFT 20 306 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 307 #define HDPX_CFG_JAMIPG_SHIFT 24 308 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 309 310 #define ALC_FRAME_SIZE 0x149C 311 312 #define ALC_WOL_CFG 0x14A0 313 #define WOL_CFG_PATTERN 0x00000001 314 #define WOL_CFG_PATTERN_ENB 0x00000002 315 #define WOL_CFG_MAGIC 0x00000004 316 #define WOL_CFG_MAGIC_ENB 0x00000008 317 #define WOL_CFG_LINK_CHG 0x00000010 318 #define WOL_CFG_LINK_CHG_ENB 0x00000020 319 #define WOL_CFG_PATTERN_DET 0x00000100 320 #define WOL_CFG_MAGIC_DET 0x00000200 321 #define WOL_CFG_LINK_CHG_DET 0x00000400 322 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 323 #define WOL_CFG_PATTERN0 0x00010000 324 #define WOL_CFG_PATTERN1 0x00020000 325 #define WOL_CFG_PATTERN2 0x00040000 326 #define WOL_CFG_PATTERN3 0x00080000 327 #define WOL_CFG_PATTERN4 0x00100000 328 #define WOL_CFG_PATTERN5 0x00200000 329 #define WOL_CFG_PATTERN6 0x00400000 330 331 /* WOL pattern length. */ 332 #define ALC_PATTERN_CFG0 0x14A4 333 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 334 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 335 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 336 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 337 338 #define ALC_PATTERN_CFG1 0x14A8 339 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 340 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 341 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 342 343 /* RSS */ 344 #define ALC_RSS_KEY0 0x14B0 345 346 #define ALC_RSS_KEY1 0x14B4 347 348 #define ALC_RSS_KEY2 0x14B8 349 350 #define ALC_RSS_KEY3 0x14BC 351 352 #define ALC_RSS_KEY4 0x14C0 353 354 #define ALC_RSS_KEY5 0x14C4 355 356 #define ALC_RSS_KEY6 0x14C8 357 358 #define ALC_RSS_KEY7 0x14CC 359 360 #define ALC_RSS_KEY8 0x14D0 361 362 #define ALC_RSS_KEY9 0x14D4 363 364 #define ALC_RSS_IDT_TABLE0 0x14E0 365 366 #define ALC_RSS_IDT_TABLE1 0x14E4 367 368 #define ALC_RSS_IDT_TABLE2 0x14E8 369 370 #define ALC_RSS_IDT_TABLE3 0x14EC 371 372 #define ALC_RSS_IDT_TABLE4 0x14F0 373 374 #define ALC_RSS_IDT_TABLE5 0x14F4 375 376 #define ALC_RSS_IDT_TABLE6 0x14F8 377 378 #define ALC_RSS_IDT_TABLE7 0x14FC 379 380 #define ALC_SRAM_RD0_ADDR 0x1500 381 382 #define ALC_SRAM_RD1_ADDR 0x1504 383 384 #define ALC_SRAM_RD2_ADDR 0x1508 385 386 #define ALC_SRAM_RD3_ADDR 0x150C 387 388 #define RD_HEAD_ADDR_MASK 0x000003FF 389 #define RD_TAIL_ADDR_MASK 0x03FF0000 390 #define RD_HEAD_ADDR_SHIFT 0 391 #define RD_TAIL_ADDR_SHIFT 16 392 393 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 394 #define RD_NIC_LEN_MASK 0x000003FF 395 396 #define ALC_RD_NIC_LEN1 0x1514 397 398 #define ALC_SRAM_TD_ADDR 0x1518 399 #define TD_HEAD_ADDR_MASK 0x000003FF 400 #define TD_TAIL_ADDR_MASK 0x03FF0000 401 #define TD_HEAD_ADDR_SHIFT 0 402 #define TD_TAIL_ADDR_SHIFT 16 403 404 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 405 #define SRAM_TD_LEN_MASK 0x000003FF 406 407 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 408 409 #define ALC_SRAM_RX_FIFO_LEN 0x1524 410 411 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 412 413 #define ALC_SRAM_TX_FIFO_LEN 0x152C 414 415 #define ALC_SRAM_TCPH_ADDR 0x1530 416 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 417 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 418 #define SRAM_TCPH_ADDR_SHIFT 0 419 #define SRAM_PKTH_ADDR_SHIFT 16 420 421 #define ALC_DMA_BLOCK 0x1534 422 #define DMA_BLOCK_LOAD 0x00000001 423 424 #define ALC_RX_BASE_ADDR_HI 0x1540 425 426 #define ALC_TX_BASE_ADDR_HI 0x1544 427 428 #define ALC_SMB_BASE_ADDR_HI 0x1548 429 430 #define ALC_SMB_BASE_ADDR_LO 0x154C 431 432 #define ALC_RD0_HEAD_ADDR_LO 0x1550 433 434 #define ALC_RD1_HEAD_ADDR_LO 0x1554 435 436 #define ALC_RD2_HEAD_ADDR_LO 0x1558 437 438 #define ALC_RD3_HEAD_ADDR_LO 0x155C 439 440 #define ALC_RD_RING_CNT 0x1560 441 #define RD_RING_CNT_MASK 0x00000FFF 442 #define RD_RING_CNT_SHIFT 0 443 444 #define ALC_RX_BUF_SIZE 0x1564 445 #define RX_BUF_SIZE_MASK 0x0000FFFF 446 /* 447 * If larger buffer size than 1536 is specified the controller 448 * will be locked up. This is hardware limitation. 449 */ 450 #define RX_BUF_SIZE_MAX 1536 451 452 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 453 454 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 455 456 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 457 458 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 459 460 #define ALC_RRD_RING_CNT 0x1578 461 #define RRD_RING_CNT_MASK 0x00000FFF 462 #define RRD_RING_CNT_SHIFT 0 463 464 #define ALC_TDH_HEAD_ADDR_LO 0x157C 465 466 #define ALC_TDL_HEAD_ADDR_LO 0x1580 467 468 #define ALC_TD_RING_CNT 0x1584 469 #define TD_RING_CNT_MASK 0x0000FFFF 470 #define TD_RING_CNT_SHIFT 0 471 472 #define ALC_CMB_BASE_ADDR_LO 0x1588 473 474 #define ALC_TXQ_CFG 0x1590 475 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 476 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 477 #define TXQ_CFG_ENB 0x00000020 478 #define TXQ_CFG_ENHANCED_MODE 0x00000040 479 #define TXQ_CFG_8023_ENB 0x00000080 480 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 481 #define TXQ_CFG_TD_BURST_SHIFT 0 482 #define TXQ_CFG_TD_BURST_DEFAULT 5 483 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 484 485 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 486 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 487 #define TSO_OFFLOAD_THRESH_SHIFT 0 488 #define TSO_OFFLOAD_THRESH_UNIT 8 489 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 490 491 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 492 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 493 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 494 #define TXF_WATER_MARK_BURST_ENB 0x80000000 495 #define TXF_WATER_MARK_LO_SHIFT 0 496 #define TXF_WATER_MARK_HI_SHIFT 16 497 498 #define ALC_THROUGHPUT_MON 0x159C 499 #define THROUGHPUT_MON_RATE_MASK 0x00000003 500 #define THROUGHPUT_MON_ENB 0x00000080 501 #define THROUGHPUT_MON_RATE_SHIFT 0 502 503 #define ALC_RXQ_CFG 0x15A0 504 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 505 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 506 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 507 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 508 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 509 #define RXQ_CFG_QUEUE1_ENB 0x00000010 510 #define RXQ_CFG_QUEUE2_ENB 0x00000020 511 #define RXQ_CFG_QUEUE3_ENB 0x00000040 512 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 513 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 514 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 515 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 516 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 517 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 518 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 519 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 520 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 521 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 522 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 523 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 524 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 525 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 526 #define RXQ_CFG_QUEUE0_ENB 0x80000000 527 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 528 #define RXQ_CFG_RD_BURST_DEFAULT 8 529 #define RXQ_CFG_RD_BURST_SHIFT 20 530 #define RXQ_CFG_ENB \ 531 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 532 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 533 534 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 535 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 536 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 537 #define RX_RD_FREE_THRESH_HI_SHIFT 0 538 #define RX_RD_FREE_THRESH_LO_SHIFT 6 539 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 540 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 541 542 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 543 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 544 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 545 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 546 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 547 548 #define ALC_RD_DMA_CFG 0x15AC 549 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 550 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 551 #define RD_DMA_CFG_THRESH_SHIFT 0 552 #define RD_DMA_CFG_TIMER_SHIFT 16 553 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 554 #define RD_DMA_CFG_TIMER_DEFAULT 0 555 #define RD_DMA_CFG_TICK_USECS 8 556 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 557 558 #define ALC_RSS_HASH_VALUE 0x15B0 559 560 #define ALC_RSS_HASH_FLAG 0x15B4 561 562 #define ALC_RSS_CPU 0x15B8 563 564 #define ALC_DMA_CFG 0x15C0 565 #define DMA_CFG_IN_ORDER 0x00000001 566 #define DMA_CFG_ENH_ORDER 0x00000002 567 #define DMA_CFG_OUT_ORDER 0x00000004 568 #define DMA_CFG_RCB_64 0x00000000 569 #define DMA_CFG_RCB_128 0x00000008 570 #define DMA_CFG_RD_BURST_128 0x00000000 571 #define DMA_CFG_RD_BURST_256 0x00000010 572 #define DMA_CFG_RD_BURST_512 0x00000020 573 #define DMA_CFG_RD_BURST_1024 0x00000030 574 #define DMA_CFG_RD_BURST_2048 0x00000040 575 #define DMA_CFG_RD_BURST_4096 0x00000050 576 #define DMA_CFG_WR_BURST_128 0x00000000 577 #define DMA_CFG_WR_BURST_256 0x00000080 578 #define DMA_CFG_WR_BURST_512 0x00000100 579 #define DMA_CFG_WR_BURST_1024 0x00000180 580 #define DMA_CFG_WR_BURST_2048 0x00000200 581 #define DMA_CFG_WR_BURST_4096 0x00000280 582 #define DMA_CFG_RD_REQ_PRI 0x00000400 583 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 584 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 585 #define DMA_CFG_CMB_ENB 0x00100000 586 #define DMA_CFG_SMB_ENB 0x00200000 587 #define DMA_CFG_CMB_NOW 0x00400000 588 #define DMA_CFG_SMB_DIS 0x01000000 589 #define DMA_CFG_SMB_NOW 0x80000000 590 #define DMA_CFG_RD_BURST_MASK 0x07 591 #define DMA_CFG_RD_BURST_SHIFT 4 592 #define DMA_CFG_WR_BURST_MASK 0x07 593 #define DMA_CFG_WR_BURST_SHIFT 7 594 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 595 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 596 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 597 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 598 599 #define ALC_SMB_STAT_TIMER 0x15C4 600 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 601 #define SMB_STAT_TIMER_SHIFT 0 602 603 #define ALC_CMB_TD_THRESH 0x15C8 604 #define CMB_TD_THRESH_MASK 0x0000FFFF 605 #define CMB_TD_THRESH_SHIFT 0 606 607 #define ALC_CMB_TX_TIMER 0x15CC 608 #define CMB_TX_TIMER_MASK 0x0000FFFF 609 #define CMB_TX_TIMER_SHIFT 0 610 611 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 612 613 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 614 615 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 616 617 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 618 619 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 620 #define MBOX_RD_PROD_SHIFT 0 621 622 #define ALC_MBOX_TD_PROD_IDX 0x15F0 623 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 624 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 625 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 626 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 627 628 #define ALC_MBOX_TD_CONS_IDX 0x15F4 629 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 630 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 631 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 632 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 633 634 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 635 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 636 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 637 #define MBOX_RD0_CONS_IDX_SHIFT 0 638 #define MBOX_RD1_CONS_IDX_SHIFT 16 639 640 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 641 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 642 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 643 #define MBOX_RD2_CONS_IDX_SHIFT 0 644 #define MBOX_RD3_CONS_IDX_SHIFT 16 645 646 #define ALC_INTR_STATUS 0x1600 647 #define INTR_SMB 0x00000001 648 #define INTR_TIMER 0x00000002 649 #define INTR_MANUAL_TIMER 0x00000004 650 #define INTR_RX_FIFO_OFLOW 0x00000008 651 #define INTR_RD0_UNDERRUN 0x00000010 652 #define INTR_RD1_UNDERRUN 0x00000020 653 #define INTR_RD2_UNDERRUN 0x00000040 654 #define INTR_RD3_UNDERRUN 0x00000080 655 #define INTR_TX_FIFO_UNDERRUN 0x00000100 656 #define INTR_DMA_RD_TO_RST 0x00000200 657 #define INTR_DMA_WR_TO_RST 0x00000400 658 #define INTR_TX_CREDIT 0x00000800 659 #define INTR_GPHY 0x00001000 660 #define INTR_GPHY_LOW_PW 0x00002000 661 #define INTR_TXQ_TO_RST 0x00004000 662 #define INTR_TX_PKT 0x00008000 663 #define INTR_RX_PKT0 0x00010000 664 #define INTR_RX_PKT1 0x00020000 665 #define INTR_RX_PKT2 0x00040000 666 #define INTR_RX_PKT3 0x00080000 667 #define INTR_MAC_RX 0x00100000 668 #define INTR_MAC_TX 0x00200000 669 #define INTR_UNDERRUN 0x00400000 670 #define INTR_FRAME_ERROR 0x00800000 671 #define INTR_FRAME_OK 0x01000000 672 #define INTR_CSUM_ERROR 0x02000000 673 #define INTR_PHY_LINK_DOWN 0x04000000 674 #define INTR_DIS_INT 0x80000000 675 676 /* Interrupt Mask Register */ 677 #define ALC_INTR_MASK 0x1604 678 679 #ifdef notyet 680 #define INTR_RX_PKT \ 681 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 682 INTR_RX_PKT3) 683 #define INTR_RD_UNDERRUN \ 684 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 685 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 686 #else 687 #define INTR_RX_PKT INTR_RX_PKT0 688 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 689 #endif 690 691 #define ALC_INTRS \ 692 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 693 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 694 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 695 INTR_TX_FIFO_UNDERRUN) 696 697 #define ALC_INTR_RETRIG_TIMER 0x1608 698 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 699 #define INTR_RETRIG_TIMER_SHIFT 0 700 701 #define ALC_HDS_CFG 0x160C 702 #define HDS_CFG_ENB 0x00000001 703 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 704 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 705 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 706 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 707 708 /* AR8131/AR8132 registers for MAC statistics */ 709 #define ALC_RX_MIB_BASE 0x1700 710 711 #define ALC_TX_MIB_BASE 0x1760 712 713 #define ALC_DEBUG_DATA0 0x1900 714 715 #define ALC_DEBUG_DATA1 0x1904 716 717 #define ALC_MII_DBG_ADDR 0x1D 718 #define ALC_MII_DBG_DATA 0x1E 719 720 #define MII_ANA_CFG0 0x00 721 #define ANA_RESTART_CAL 0x0001 722 #define ANA_MANUL_SWICH_ON_MASK 0x001E 723 #define ANA_MAN_ENABLE 0x0020 724 #define ANA_SEL_HSP 0x0040 725 #define ANA_EN_HB 0x0080 726 #define ANA_EN_HBIAS 0x0100 727 #define ANA_OEN_125M 0x0200 728 #define ANA_EN_LCKDT 0x0400 729 #define ANA_LCKDT_PHY 0x0800 730 #define ANA_AFE_MODE 0x1000 731 #define ANA_VCO_SLOW 0x2000 732 #define ANA_VCO_FAST 0x4000 733 #define ANA_SEL_CLK125M_DSP 0x8000 734 #define ANA_MANUL_SWICH_ON_SHIFT 1 735 736 #define MII_ANA_CFG4 0x04 737 #define ANA_IECHO_ADJ_MASK 0x0F 738 #define ANA_IECHO_ADJ_3_MASK 0x000F 739 #define ANA_IECHO_ADJ_2_MASK 0x00F0 740 #define ANA_IECHO_ADJ_1_MASK 0x0F00 741 #define ANA_IECHO_ADJ_0_MASK 0xF000 742 #define ANA_IECHO_ADJ_3_SHIFT 0 743 #define ANA_IECHO_ADJ_2_SHIFT 4 744 #define ANA_IECHO_ADJ_1_SHIFT 8 745 #define ANA_IECHO_ADJ_0_SHIFT 12 746 747 #define MII_ANA_CFG5 0x05 748 #define ANA_SERDES_CDR_BW_MASK 0x0003 749 #define ANA_MS_PAD_DBG 0x0004 750 #define ANA_SPEEDUP_DBG 0x0008 751 #define ANA_SERDES_TH_LOS_MASK 0x0030 752 #define ANA_SERDES_EN_DEEM 0x0040 753 #define ANA_SERDES_TXELECIDLE 0x0080 754 #define ANA_SERDES_BEACON 0x0100 755 #define ANA_SERDES_HALFTXDR 0x0200 756 #define ANA_SERDES_SEL_HSP 0x0400 757 #define ANA_SERDES_EN_PLL 0x0800 758 #define ANA_SERDES_EN 0x1000 759 #define ANA_SERDES_EN_LCKDT 0x2000 760 #define ANA_SERDES_CDR_BW_SHIFT 0 761 #define ANA_SERDES_TH_LOS_SHIFT 4 762 763 #define MII_ANA_CFG11 0x0B 764 #define ANA_PS_HIB_EN 0x8000 765 766 #define MII_ANA_CFG18 0x12 767 #define ANA_TEST_MODE_10BT_01MASK 0x0003 768 #define ANA_LOOP_SEL_10BT 0x0004 769 #define ANA_RGMII_MODE_SW 0x0008 770 #define ANA_EN_LONGECABLE 0x0010 771 #define ANA_TEST_MODE_10BT_2 0x0020 772 #define ANA_EN_10BT_IDLE 0x0400 773 #define ANA_EN_MASK_TB 0x0800 774 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 775 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 776 #define ANA_TEST_MODE_10BT_01SHIFT 0 777 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 778 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 779 780 #define MII_ANA_CFG41 0x29 781 #define ANA_TOP_PS_EN 0x8000 782 783 #define MII_ANA_CFG54 0x36 784 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 785 #define ANA_DESERVED 0x0040 786 #define ANA_EN_LIT_CH 0x0080 787 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 788 #define ANA_BP_BAD_LINK_ACCUM 0x4000 789 #define ANA_BP_SMALL_BW 0x8000 790 #define ANA_LONG_CABLE_TH_100_SHIFT 0 791 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 792 793 /* Statistics counters collected by the MAC. */ 794 struct smb { 795 /* Rx stats. */ 796 uint32_t rx_frames; 797 uint32_t rx_bcast_frames; 798 uint32_t rx_mcast_frames; 799 uint32_t rx_pause_frames; 800 uint32_t rx_control_frames; 801 uint32_t rx_crcerrs; 802 uint32_t rx_lenerrs; 803 uint32_t rx_bytes; 804 uint32_t rx_runts; 805 uint32_t rx_fragments; 806 uint32_t rx_pkts_64; 807 uint32_t rx_pkts_65_127; 808 uint32_t rx_pkts_128_255; 809 uint32_t rx_pkts_256_511; 810 uint32_t rx_pkts_512_1023; 811 uint32_t rx_pkts_1024_1518; 812 uint32_t rx_pkts_1519_max; 813 uint32_t rx_pkts_truncated; 814 uint32_t rx_fifo_oflows; 815 uint32_t rx_rrs_errs; 816 uint32_t rx_alignerrs; 817 uint32_t rx_bcast_bytes; 818 uint32_t rx_mcast_bytes; 819 uint32_t rx_pkts_filtered; 820 /* Tx stats. */ 821 uint32_t tx_frames; 822 uint32_t tx_bcast_frames; 823 uint32_t tx_mcast_frames; 824 uint32_t tx_pause_frames; 825 uint32_t tx_excess_defer; 826 uint32_t tx_control_frames; 827 uint32_t tx_deferred; 828 uint32_t tx_bytes; 829 uint32_t tx_pkts_64; 830 uint32_t tx_pkts_65_127; 831 uint32_t tx_pkts_128_255; 832 uint32_t tx_pkts_256_511; 833 uint32_t tx_pkts_512_1023; 834 uint32_t tx_pkts_1024_1518; 835 uint32_t tx_pkts_1519_max; 836 uint32_t tx_single_colls; 837 uint32_t tx_multi_colls; 838 uint32_t tx_late_colls; 839 uint32_t tx_excess_colls; 840 uint32_t tx_abort; 841 uint32_t tx_underrun; 842 uint32_t tx_desc_underrun; 843 uint32_t tx_lenerrs; 844 uint32_t tx_pkts_truncated; 845 uint32_t tx_bcast_bytes; 846 uint32_t tx_mcast_bytes; 847 uint32_t updated; 848 }; 849 850 /* CMB(Coalesing message block) */ 851 struct cmb { 852 uint32_t cons; 853 }; 854 855 /* Rx free descriptor */ 856 struct rx_desc { 857 uint64_t addr; 858 }; 859 860 /* Rx return descriptor */ 861 struct rx_rdesc { 862 uint32_t rdinfo; 863 #define RRD_CSUM_MASK 0x0000FFFF 864 #define RRD_RD_CNT_MASK 0x000F0000 865 #define RRD_RD_IDX_MASK 0xFFF00000 866 #define RRD_CSUM_SHIFT 0 867 #define RRD_RD_CNT_SHIFT 16 868 #define RRD_RD_IDX_SHIFT 20 869 #define RRD_CSUM(x) \ 870 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 871 #define RRD_RD_CNT(x) \ 872 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 873 #define RRD_RD_IDX(x) \ 874 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 875 uint32_t rss; 876 uint32_t vtag; 877 #define RRD_VLAN_MASK 0x0000FFFF 878 #define RRD_HEAD_LEN_MASK 0x00FF0000 879 #define RRD_HDS_MASK 0x03000000 880 #define RRD_HDS_NONE 0x00000000 881 #define RRD_HDS_HEAD 0x01000000 882 #define RRD_HDS_DATA 0x02000000 883 #define RRD_CPU_MASK 0x0C000000 884 #define RRD_HASH_FLAG_MASK 0xF0000000 885 #define RRD_VLAN_SHIFT 0 886 #define RRD_HEAD_LEN_SHIFT 16 887 #define RRD_HDS_SHIFT 24 888 #define RRD_CPU_SHIFT 26 889 #define RRD_HASH_FLAG_SHIFT 28 890 #define RRD_VLAN(x) \ 891 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 892 #define RRD_HEAD_LEN(x) \ 893 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 894 #define RRD_CPU(x) \ 895 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 896 uint32_t status; 897 #define RRD_LEN_MASK 0x00003FFF 898 #define RRD_LEN_SHIFT 0 899 #define RRD_TCP_UDPCSUM_NOK 0x00004000 900 #define RRD_IPCSUM_NOK 0x00008000 901 #define RRD_VLAN_TAG 0x00010000 902 #define RRD_PROTO_MASK 0x000E0000 903 #define RRD_PROTO_IPV4 0x00020000 904 #define RRD_PROTO_IPV6 0x000C0000 905 #define RRD_ERR_SUM 0x00100000 906 #define RRD_ERR_CRC 0x00200000 907 #define RRD_ERR_ALIGN 0x00400000 908 #define RRD_ERR_TRUNC 0x00800000 909 #define RRD_ERR_RUNT 0x01000000 910 #define RRD_ERR_ICMP 0x02000000 911 #define RRD_BCAST 0x04000000 912 #define RRD_MCAST 0x08000000 913 #define RRD_SNAP_LLC 0x10000000 914 #define RRD_ETHER 0x00000000 915 #define RRD_FIFO_FULL 0x20000000 916 #define RRD_ERR_LENGTH 0x40000000 917 #define RRD_VALID 0x80000000 918 #define RRD_BYTES(x) \ 919 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 920 #define RRD_IPV4(x) \ 921 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 922 }; 923 924 /* Tx descriptor */ 925 struct tx_desc { 926 uint32_t len; 927 #define TD_BUFLEN_MASK 0x00003FFF 928 #define TD_VLAN_MASK 0xFFFF0000 929 #define TD_BUFLEN_SHIFT 0 930 #define TX_BYTES(x) \ 931 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 932 #define TD_VLAN_SHIFT 16 933 uint32_t flags; 934 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 935 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 936 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 937 #define TD_CUSTOM_CSUM 0x00000100 938 #define TD_IPCSUM 0x00000200 939 #define TD_TCPCSUM 0x00000400 940 #define TD_UDPCSUM 0x00000800 941 #define TD_TSO 0x00001000 942 #define TD_TSO_DESCV1 0x00000000 943 #define TD_TSO_DESCV2 0x00002000 944 #define TD_CON_VLAN_TAG 0x00004000 945 #define TD_INS_VLAN_TAG 0x00008000 946 #define TD_IPV4_DESCV2 0x00010000 947 #define TD_LLC_SNAP 0x00020000 948 #define TD_ETHERNET 0x00000000 949 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 950 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 951 #define TD_MSS_MASK 0x7FFC0000 952 #define TD_EOP 0x80000000 953 #define TD_L4HDR_OFFSET_SHIFT 0 954 #define TD_TCPHDR_OFFSET_SHIFT 0 955 #define TD_PLOAD_OFFSET_SHIFT 0 956 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 957 #define TD_MSS_SHIFT 18 958 uint64_t addr; 959 }; 960 961 #endif /* _IF_ALCREG_H */ 962