xref: /dragonfly/sys/dev/netif/alc/if_alcvar.h (revision 0dace59e)
1 /*-
2  * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/alc/if_alcvar.h,v 1.1 2009/06/10 02:07:58 yongari Exp $
28  */
29 
30 #ifndef	_IF_ALCVAR_H
31 #define	_IF_ALCVAR_H
32 
33 #define	ALC_TX_RING_CNT		256
34 #define	ALC_TX_RING_ALIGN	sizeof(struct tx_desc)
35 #define	ALC_RX_RING_CNT		256
36 #define	ALC_RX_RING_ALIGN	sizeof(struct rx_desc)
37 #define	ALC_RX_BUF_ALIGN	4
38 #define	ALC_RR_RING_CNT		ALC_RX_RING_CNT
39 #define	ALC_RR_RING_ALIGN	sizeof(struct rx_rdesc)
40 #define	ALC_CMB_ALIGN		8
41 #define	ALC_SMB_ALIGN		8
42 
43 #define	ALC_TSO_MAXSEGSIZE	4096
44 #define	ALC_TSO_MAXSIZE		(65535 + sizeof(struct ether_vlan_header))
45 #define	ALC_MAXTXSEGS		32
46 
47 #define	ALC_ADDR_LO(x)		((uint64_t) (x) & 0xFFFFFFFF)
48 #define	ALC_ADDR_HI(x)		((uint64_t) (x) >> 32)
49 
50 #define	ALC_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
51 
52 /* Water mark to kick reclaiming Tx buffers. */
53 #define	ALC_TX_DESC_HIWAT	((ALC_TX_RING_CNT * 6) / 10)
54 
55 #define	ALC_TX_RING_SZ		\
56 	(sizeof(struct tx_desc) * ALC_TX_RING_CNT)
57 #define	ALC_RX_RING_SZ		\
58 	(sizeof(struct rx_desc) * ALC_RX_RING_CNT)
59 #define	ALC_RR_RING_SZ		\
60 	(sizeof(struct rx_rdesc) * ALC_RR_RING_CNT)
61 #define	ALC_CMB_SZ		(sizeof(struct cmb))
62 #define	ALC_SMB_SZ		(sizeof(struct smb))
63 
64 #define	ALC_PROC_MIN		16
65 #define	ALC_PROC_MAX		(ALC_RX_RING_CNT - 1)
66 #define	ALC_PROC_DEFAULT	(ALC_RX_RING_CNT / 4)
67 
68 /*
69  * The number of bits reserved for MSS in AR813x/AR815x controllers
70  * are 13 bits. This limits the maximum interface MTU size in TSO
71  * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper
72  * stack should not generate TCP segments with MSS greater than the
73  * limit. Also Atheros says that maximum MTU for TSO is 6KB.
74  */
75 #define	ALC_TSO_MTU		(6 * 1024)
76 
77 
78 struct alc_rxdesc {
79 	struct mbuf		*rx_m;
80 	bus_dmamap_t		rx_dmamap;
81 	struct rx_desc		*rx_desc;
82 };
83 
84 struct alc_txdesc {
85 	struct mbuf		*tx_m;
86 	bus_dmamap_t		tx_dmamap;
87 };
88 
89 struct alc_ring_data {
90 	struct tx_desc		*alc_tx_ring;
91 	bus_addr_t		alc_tx_ring_paddr;
92 	struct rx_desc		*alc_rx_ring;
93 	bus_addr_t		alc_rx_ring_paddr;
94 	struct rx_rdesc		*alc_rr_ring;
95 	bus_addr_t		alc_rr_ring_paddr;
96 	struct cmb		*alc_cmb;
97 	bus_addr_t		alc_cmb_paddr;
98 	struct smb		*alc_smb;
99 	bus_addr_t		alc_smb_paddr;
100 };
101 
102 struct alc_chain_data {
103 	bus_dma_tag_t		alc_parent_tag;
104 	bus_dma_tag_t		alc_buffer_tag;
105 	bus_dma_tag_t		alc_tx_tag;
106 	struct alc_txdesc	alc_txdesc[ALC_TX_RING_CNT];
107 	bus_dma_tag_t		alc_rx_tag;
108 	struct alc_rxdesc	alc_rxdesc[ALC_RX_RING_CNT];
109 	bus_dma_tag_t		alc_tx_ring_tag;
110 	bus_dmamap_t		alc_tx_ring_map;
111 	bus_dma_tag_t		alc_rx_ring_tag;
112 	bus_dmamap_t		alc_rx_ring_map;
113 	bus_dma_tag_t		alc_rr_ring_tag;
114 	bus_dmamap_t		alc_rr_ring_map;
115 	bus_dmamap_t		alc_rx_sparemap;
116 	bus_dma_tag_t		alc_cmb_tag;
117 	bus_dmamap_t		alc_cmb_map;
118 	bus_dma_tag_t		alc_smb_tag;
119 	bus_dmamap_t		alc_smb_map;
120 
121 	int			alc_tx_prod;
122 	int			alc_tx_cons;
123 	int			alc_tx_cnt;
124 	int			alc_rx_cons;
125 	int			alc_rr_cons;
126 	int			alc_rxlen;
127 
128 	struct mbuf		*alc_rxhead;
129 	struct mbuf		*alc_rxtail;
130 	struct mbuf		*alc_rxprev_tail;
131 };
132 
133 struct alc_hw_stats {
134 	/* Rx stats. */
135 	uint32_t rx_frames;
136 	uint32_t rx_bcast_frames;
137 	uint32_t rx_mcast_frames;
138 	uint32_t rx_pause_frames;
139 	uint32_t rx_control_frames;
140 	uint32_t rx_crcerrs;
141 	uint32_t rx_lenerrs;
142 	uint64_t rx_bytes;
143 	uint32_t rx_runts;
144 	uint32_t rx_fragments;
145 	uint32_t rx_pkts_64;
146 	uint32_t rx_pkts_65_127;
147 	uint32_t rx_pkts_128_255;
148 	uint32_t rx_pkts_256_511;
149 	uint32_t rx_pkts_512_1023;
150 	uint32_t rx_pkts_1024_1518;
151 	uint32_t rx_pkts_1519_max;
152 	uint32_t rx_pkts_truncated;
153 	uint32_t rx_fifo_oflows;
154 	uint32_t rx_rrs_errs;
155 	uint32_t rx_alignerrs;
156 	uint64_t rx_bcast_bytes;
157 	uint64_t rx_mcast_bytes;
158 	uint32_t rx_pkts_filtered;
159 	/* Tx stats. */
160 	uint32_t tx_frames;
161 	uint32_t tx_bcast_frames;
162 	uint32_t tx_mcast_frames;
163 	uint32_t tx_pause_frames;
164 	uint32_t tx_excess_defer;
165 	uint32_t tx_control_frames;
166 	uint32_t tx_deferred;
167 	uint64_t tx_bytes;
168 	uint32_t tx_pkts_64;
169 	uint32_t tx_pkts_65_127;
170 	uint32_t tx_pkts_128_255;
171 	uint32_t tx_pkts_256_511;
172 	uint32_t tx_pkts_512_1023;
173 	uint32_t tx_pkts_1024_1518;
174 	uint32_t tx_pkts_1519_max;
175 	uint32_t tx_single_colls;
176 	uint32_t tx_multi_colls;
177 	uint32_t tx_late_colls;
178 	uint32_t tx_excess_colls;
179 	uint32_t tx_abort;
180 	uint32_t tx_underrun;
181 	uint32_t tx_desc_underrun;
182 	uint32_t tx_lenerrs;
183 	uint32_t tx_pkts_truncated;
184 	uint64_t tx_bcast_bytes;
185 	uint64_t tx_mcast_bytes;
186 };
187 
188 struct alc_ident {
189 	uint16_t        vendorid;
190 	uint16_t        deviceid;
191 	uint32_t        max_framelen;
192 	const char      *name;
193 };
194 
195 /*
196  * Software state per device.
197  */
198 struct alc_softc {
199 	struct arpcom		arpcom;
200 	struct ifnet 		*alc_ifp;	/* points to arpcom.ac_if */
201 	device_t		alc_dev;
202 	device_t		alc_miibus;
203 	int			alc_res_rid;
204 	struct resource		*alc_res;
205 	bus_space_handle_t	alc_res_bhand;
206 	bus_space_tag_t		alc_res_btag;
207 	int			alc_irq_type;
208 	int			alc_irq_rid;
209 	struct resource		*alc_irq;
210 	void			*alc_intrhand;
211 	struct alc_ident	*alc_ident;
212 	int			alc_rev;
213 	int			alc_chip_rev;
214 	int			alc_phyaddr;
215 	uint8_t			alc_eaddr[ETHER_ADDR_LEN];
216 	uint32_t		alc_dma_rd_burst;
217 	uint32_t		alc_dma_wr_burst;
218 	uint32_t		alc_rcb;
219 	int			alc_expcap;
220 	int			alc_pmcap;
221 	int			alc_flags;
222 #define	ALC_FLAG_PCIE		0x0001
223 #define ALC_FLAG_PM		0x0010
224 #define	ALC_FLAG_FASTETHER	0x0020
225 #define	ALC_FLAG_JUMBO		0x0040
226 #define	ALC_FLAG_ASPM_MON	0x0080
227 #define	ALC_FLAG_CMB_BUG	0x0100
228 #define	ALC_FLAG_SMB_BUG	0x0200
229 #define ALC_FLAG_L0S		0x0400
230 #define ALC_FLAG_L1S		0x0800
231 #define ALC_FLAG_APS		0x1000
232 #define	ALC_FLAG_DETACH		0x4000
233 #define	ALC_FLAG_LINK		0x8000
234 
235 	struct callout		alc_tick_ch;
236 	struct alc_hw_stats	alc_stats;
237 	struct alc_chain_data	alc_cdata;
238 	struct alc_ring_data	alc_rdata;
239 	int			alc_if_flags;
240 	int			alc_watchdog_timer;
241 	int			alc_process_limit;
242 	int			alc_int_rx_mod;
243 	int			alc_int_tx_mod;
244 	int			alc_buf_size;
245 
246 	struct sysctl_ctx_list	alc_sysctl_ctx;
247 };
248 
249 /* Register access macros. */
250 #define CSR_WRITE_4(sc, reg, val)	\
251 	bus_space_write_4(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val))
252 #define CSR_READ_4(sc, reg)		\
253 	bus_space_read_4(sc->alc_res_btag, sc->alc_res_bhand, (reg))
254 #define CSR_WRITE_2(sc, reg, val)	\
255 	bus_space_write_2(sc->alc_res_btag, sc->alc_res_bhand, (reg), (val))
256 #define CSR_READ_2(sc, reg)		\
257 	bus_space_read_2(sc->alc_res_btag, sc->alc_res_bhand, (reg))
258 
259 #define	ALC_RXCHAIN_RESET(_sc)						\
260 do {									\
261 	(_sc)->alc_cdata.alc_rxhead = NULL;				\
262 	(_sc)->alc_cdata.alc_rxtail = NULL;				\
263 	(_sc)->alc_cdata.alc_rxprev_tail = NULL;			\
264 	(_sc)->alc_cdata.alc_rxlen = 0;					\
265 } while (0)
266 
267 #define	ALC_TX_TIMEOUT		5
268 #define	ALC_RESET_TIMEOUT	100
269 #define	ALC_TIMEOUT		1000
270 #define	ALC_PHY_TIMEOUT		1000
271 
272 #endif	/* _IF_ALCVAR_H */
273