1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcvar.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 */ 29 30 #ifndef _IF_ALCVAR_H 31 #define _IF_ALCVAR_H 32 33 #define ALC_TX_RING_CNT 256 34 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 35 #define ALC_RX_RING_CNT 256 36 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 37 #define ALC_RX_BUF_ALIGN 4 38 #define ALC_RR_RING_CNT ALC_RX_RING_CNT 39 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 40 #define ALC_CMB_ALIGN 8 41 #define ALC_SMB_ALIGN 8 42 43 #define ALC_TSO_MAXSEGSIZE 4096 44 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 45 #define ALC_MAXTXSEGS 32 46 47 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 48 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 49 50 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 51 52 /* Water mark to kick reclaiming Tx buffers. */ 53 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 54 55 #define ALC_MSI_MESSAGES 1 56 #define ALC_MSIX_MESSAGES 1 57 58 #define ALC_TX_RING_SZ \ 59 (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 60 #define ALC_RX_RING_SZ \ 61 (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 62 #define ALC_RR_RING_SZ \ 63 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 64 #define ALC_CMB_SZ (sizeof(struct cmb)) 65 #define ALC_SMB_SZ (sizeof(struct smb)) 66 67 #define ALC_PROC_MIN 16 68 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 69 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 70 71 /* 72 * The number of bits reserved for MSS in AR813x/AR815x controllers 73 * are 13 bits. This limits the maximum interface MTU size in TSO 74 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 75 * stack should not generate TCP segments with MSS greater than the 76 * limit. Also Atheros says that maximum MTU for TSO is 6KB. 77 */ 78 #define ALC_TSO_MTU (6 * 1024) 79 80 81 #ifndef IFCAP_TSO4 82 #define IFCAP_TSO4 0 83 #endif 84 85 #ifndef CSUM_TSO 86 #define CSUM_TSO 0 87 #endif 88 89 90 struct alc_rxdesc { 91 struct mbuf *rx_m; 92 bus_dmamap_t rx_dmamap; 93 struct rx_desc *rx_desc; 94 }; 95 96 struct alc_txdesc { 97 struct mbuf *tx_m; 98 bus_dmamap_t tx_dmamap; 99 }; 100 101 struct alc_ring_data { 102 struct tx_desc *alc_tx_ring; 103 bus_addr_t alc_tx_ring_paddr; 104 struct rx_desc *alc_rx_ring; 105 bus_addr_t alc_rx_ring_paddr; 106 struct rx_rdesc *alc_rr_ring; 107 bus_addr_t alc_rr_ring_paddr; 108 struct cmb *alc_cmb; 109 bus_addr_t alc_cmb_paddr; 110 struct smb *alc_smb; 111 bus_addr_t alc_smb_paddr; 112 }; 113 114 struct alc_chain_data { 115 bus_dma_tag_t alc_parent_tag; 116 bus_dma_tag_t alc_buffer_tag; 117 bus_dma_tag_t alc_tx_tag; 118 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 119 bus_dma_tag_t alc_rx_tag; 120 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 121 bus_dma_tag_t alc_tx_ring_tag; 122 bus_dmamap_t alc_tx_ring_map; 123 bus_dma_tag_t alc_rx_ring_tag; 124 bus_dmamap_t alc_rx_ring_map; 125 bus_dma_tag_t alc_rr_ring_tag; 126 bus_dmamap_t alc_rr_ring_map; 127 bus_dmamap_t alc_rx_sparemap; 128 bus_dma_tag_t alc_cmb_tag; 129 bus_dmamap_t alc_cmb_map; 130 bus_dma_tag_t alc_smb_tag; 131 bus_dmamap_t alc_smb_map; 132 133 int alc_tx_prod; 134 int alc_tx_cons; 135 int alc_tx_cnt; 136 int alc_rx_cons; 137 int alc_rr_cons; 138 int alc_rxlen; 139 140 struct mbuf *alc_rxhead; 141 struct mbuf *alc_rxtail; 142 struct mbuf *alc_rxprev_tail; 143 }; 144 145 struct alc_hw_stats { 146 /* Rx stats. */ 147 uint32_t rx_frames; 148 uint32_t rx_bcast_frames; 149 uint32_t rx_mcast_frames; 150 uint32_t rx_pause_frames; 151 uint32_t rx_control_frames; 152 uint32_t rx_crcerrs; 153 uint32_t rx_lenerrs; 154 uint64_t rx_bytes; 155 uint32_t rx_runts; 156 uint32_t rx_fragments; 157 uint32_t rx_pkts_64; 158 uint32_t rx_pkts_65_127; 159 uint32_t rx_pkts_128_255; 160 uint32_t rx_pkts_256_511; 161 uint32_t rx_pkts_512_1023; 162 uint32_t rx_pkts_1024_1518; 163 uint32_t rx_pkts_1519_max; 164 uint32_t rx_pkts_truncated; 165 uint32_t rx_fifo_oflows; 166 uint32_t rx_rrs_errs; 167 uint32_t rx_alignerrs; 168 uint64_t rx_bcast_bytes; 169 uint64_t rx_mcast_bytes; 170 uint32_t rx_pkts_filtered; 171 /* Tx stats. */ 172 uint32_t tx_frames; 173 uint32_t tx_bcast_frames; 174 uint32_t tx_mcast_frames; 175 uint32_t tx_pause_frames; 176 uint32_t tx_excess_defer; 177 uint32_t tx_control_frames; 178 uint32_t tx_deferred; 179 uint64_t tx_bytes; 180 uint32_t tx_pkts_64; 181 uint32_t tx_pkts_65_127; 182 uint32_t tx_pkts_128_255; 183 uint32_t tx_pkts_256_511; 184 uint32_t tx_pkts_512_1023; 185 uint32_t tx_pkts_1024_1518; 186 uint32_t tx_pkts_1519_max; 187 uint32_t tx_single_colls; 188 uint32_t tx_multi_colls; 189 uint32_t tx_late_colls; 190 uint32_t tx_excess_colls; 191 uint32_t tx_abort; 192 uint32_t tx_underrun; 193 uint32_t tx_desc_underrun; 194 uint32_t tx_lenerrs; 195 uint32_t tx_pkts_truncated; 196 uint64_t tx_bcast_bytes; 197 uint64_t tx_mcast_bytes; 198 }; 199 200 struct alc_ident { 201 uint16_t vendorid; 202 uint16_t deviceid; 203 uint32_t max_framelen; 204 const char *name; 205 }; 206 207 /* 208 * Software state per device. 209 */ 210 struct alc_softc { 211 struct arpcom arpcom; 212 struct ifnet *alc_ifp; /* points to arpcom.ac_if */ 213 device_t alc_dev; 214 device_t alc_miibus; 215 struct resource *alc_res[1]; 216 struct resource_spec *alc_res_spec; 217 struct resource *alc_irq[ALC_MSI_MESSAGES]; 218 struct resource_spec *alc_irq_spec; 219 void *alc_intrhand[ALC_MSI_MESSAGES]; 220 struct alc_ident *alc_ident; 221 int alc_rev; 222 int alc_chip_rev; 223 int alc_phyaddr; 224 uint8_t alc_eaddr[ETHER_ADDR_LEN]; 225 uint32_t alc_dma_rd_burst; 226 uint32_t alc_dma_wr_burst; 227 uint32_t alc_rcb; 228 int alc_expcap; 229 int alc_pmcap; 230 int alc_flags; 231 #define ALC_FLAG_PCIE 0x0001 232 #define ALC_FLAG_PCIX 0x0002 233 #define ALC_FLAG_MSI 0x0004 234 #define ALC_FLAG_MSIX 0x0008 235 #define ALC_FLAG_PM 0x0010 236 #define ALC_FLAG_FASTETHER 0x0020 237 #define ALC_FLAG_JUMBO 0x0040 238 #define ALC_FLAG_ASPM_MON 0x0080 239 #define ALC_FLAG_CMB_BUG 0x0100 240 #define ALC_FLAG_SMB_BUG 0x0200 241 #define ALC_FLAG_L0S 0x0400 242 #define ALC_FLAG_L1S 0x0800 243 #define ALC_FLAG_APS 0x1000 244 #define ALC_FLAG_DETACH 0x4000 245 #define ALC_FLAG_LINK 0x8000 246 247 struct callout alc_tick_ch; 248 struct alc_hw_stats alc_stats; 249 struct alc_chain_data alc_cdata; 250 struct alc_ring_data alc_rdata; 251 int alc_if_flags; 252 int alc_watchdog_timer; 253 int alc_process_limit; 254 volatile int alc_morework; 255 int alc_int_rx_mod; 256 int alc_int_tx_mod; 257 int alc_buf_size; 258 259 struct sysctl_ctx_list alc_sysctl_ctx; 260 261 struct task alc_int_task; 262 struct task alc_tx_task; 263 struct taskqueue *alc_tq; 264 struct lock alc_lock; 265 }; 266 267 /* Register access macros. */ 268 #define CSR_WRITE_4(_sc, reg, val) \ 269 bus_write_4((_sc)->alc_res[0], (reg), (val)) 270 #define CSR_WRITE_2(_sc, reg, val) \ 271 bus_write_2((_sc)->alc_res[0], (reg), (val)) 272 #define CSR_WRITE_1(_sc, reg, val) \ 273 bus_write_1((_sc)->alc_res[0], (reg), (val)) 274 #define CSR_READ_2(_sc, reg) \ 275 bus_read_2((_sc)->alc_res[0], (reg)) 276 #define CSR_READ_4(_sc, reg) \ 277 bus_read_4((_sc)->alc_res[0], (reg)) 278 279 #define ALC_RXCHAIN_RESET(_sc) \ 280 do { \ 281 (_sc)->alc_cdata.alc_rxhead = NULL; \ 282 (_sc)->alc_cdata.alc_rxtail = NULL; \ 283 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 284 (_sc)->alc_cdata.alc_rxlen = 0; \ 285 } while (0) 286 287 #define ALC_LOCK(_sc) lockmgr(&(_sc)->alc_lock, LK_EXCLUSIVE) 288 #define ALC_UNLOCK(_sc) lockmgr(&(_sc)->alc_lock, LK_RELEASE) 289 #define ALC_LOCK_ASSERT(_sc) KKASSERT(lockstatus(&(_sc)->alc_lock, curthread) != 0) 290 291 #define ALC_TX_TIMEOUT 5 292 #define ALC_RESET_TIMEOUT 100 293 #define ALC_TIMEOUT 1000 294 #define ALC_PHY_TIMEOUT 1000 295 296 #endif /* _IF_ALCVAR_H */ 297