1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/interrupt.h> 37 #include <sys/malloc.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/serialize.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/bpf.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_llc.h> 51 #include <net/if_media.h> 52 #include <net/ifq_var.h> 53 #include <net/vlan/if_vlan_var.h> 54 #include <net/vlan/if_vlan_ether.h> 55 56 #include <netinet/ip.h> 57 58 #include <dev/netif/mii_layer/miivar.h> 59 #include <dev/netif/mii_layer/jmphyreg.h> 60 61 #include <bus/pci/pcireg.h> 62 #include <bus/pci/pcivar.h> 63 #include <bus/pci/pcidevs.h> 64 65 #include <dev/netif/ale/if_alereg.h> 66 #include <dev/netif/ale/if_alevar.h> 67 68 /* "device miibus" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 /* For more information about Tx checksum offload issues see ale_encap(). */ 72 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 73 74 struct ale_dmamap_ctx { 75 int nsegs; 76 bus_dma_segment_t *segs; 77 }; 78 79 static int ale_probe(device_t); 80 static int ale_attach(device_t); 81 static int ale_detach(device_t); 82 static int ale_shutdown(device_t); 83 static int ale_suspend(device_t); 84 static int ale_resume(device_t); 85 86 static int ale_miibus_readreg(device_t, int, int); 87 static int ale_miibus_writereg(device_t, int, int, int); 88 static void ale_miibus_statchg(device_t); 89 90 static void ale_init(void *); 91 static void ale_start(struct ifnet *); 92 static int ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 93 static void ale_watchdog(struct ifnet *); 94 static int ale_mediachange(struct ifnet *); 95 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 static void ale_intr(void *); 98 static int ale_rxeof(struct ale_softc *sc); 99 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 static void ale_txeof(struct ale_softc *); 103 104 static int ale_dma_alloc(struct ale_softc *); 105 static void ale_dma_free(struct ale_softc *); 106 static int ale_check_boundary(struct ale_softc *); 107 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 108 static void ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int, 109 bus_size_t, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_init_rx_pages(struct ale_softc *); 112 static void ale_init_tx_ring(struct ale_softc *); 113 114 static void ale_stop(struct ale_softc *); 115 static void ale_tick(void *); 116 static void ale_get_macaddr(struct ale_softc *); 117 static void ale_mac_config(struct ale_softc *); 118 static void ale_phy_reset(struct ale_softc *); 119 static void ale_reset(struct ale_softc *); 120 static void ale_rxfilter(struct ale_softc *); 121 static void ale_rxvlan(struct ale_softc *); 122 static void ale_stats_clear(struct ale_softc *); 123 static void ale_stats_update(struct ale_softc *); 124 static void ale_stop_mac(struct ale_softc *); 125 #ifdef notyet 126 static void ale_setlinkspeed(struct ale_softc *); 127 static void ale_setwol(struct ale_softc *); 128 #endif 129 130 static void ale_sysctl_node(struct ale_softc *); 131 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 132 133 /* 134 * Devices supported by this driver. 135 */ 136 static struct ale_dev { 137 uint16_t ale_vendorid; 138 uint16_t ale_deviceid; 139 const char *ale_name; 140 } ale_devs[] = { 141 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 142 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 143 }; 144 145 static device_method_t ale_methods[] = { 146 /* Device interface. */ 147 DEVMETHOD(device_probe, ale_probe), 148 DEVMETHOD(device_attach, ale_attach), 149 DEVMETHOD(device_detach, ale_detach), 150 DEVMETHOD(device_shutdown, ale_shutdown), 151 DEVMETHOD(device_suspend, ale_suspend), 152 DEVMETHOD(device_resume, ale_resume), 153 154 /* Bus interface. */ 155 DEVMETHOD(bus_print_child, bus_generic_print_child), 156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 157 158 /* MII interface. */ 159 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 160 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 161 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 162 163 { NULL, NULL } 164 }; 165 166 static driver_t ale_driver = { 167 "ale", 168 ale_methods, 169 sizeof(struct ale_softc) 170 }; 171 172 static devclass_t ale_devclass; 173 174 DECLARE_DUMMY_MODULE(if_ale); 175 MODULE_DEPEND(if_ale, miibus, 1, 1, 1); 176 DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, 0, 0); 177 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 178 179 static int 180 ale_miibus_readreg(device_t dev, int phy, int reg) 181 { 182 struct ale_softc *sc; 183 uint32_t v; 184 int i; 185 186 sc = device_get_softc(dev); 187 188 if (phy != sc->ale_phyaddr) 189 return (0); 190 191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 192 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 193 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 194 DELAY(5); 195 v = CSR_READ_4(sc, ALE_MDIO); 196 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 197 break; 198 } 199 200 if (i == 0) { 201 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 202 return (0); 203 } 204 205 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 206 } 207 208 static int 209 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 210 { 211 struct ale_softc *sc; 212 uint32_t v; 213 int i; 214 215 sc = device_get_softc(dev); 216 217 if (phy != sc->ale_phyaddr) 218 return (0); 219 220 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 221 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 222 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 223 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 224 DELAY(5); 225 v = CSR_READ_4(sc, ALE_MDIO); 226 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 227 break; 228 } 229 230 if (i == 0) 231 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 232 233 return (0); 234 } 235 236 static void 237 ale_miibus_statchg(device_t dev) 238 { 239 struct ale_softc *sc = device_get_softc(dev); 240 struct ifnet *ifp = &sc->arpcom.ac_if; 241 struct mii_data *mii; 242 uint32_t reg; 243 244 ASSERT_SERIALIZED(ifp->if_serializer); 245 246 if ((ifp->if_flags & IFF_RUNNING) == 0) 247 return; 248 249 mii = device_get_softc(sc->ale_miibus); 250 251 sc->ale_flags &= ~ALE_FLAG_LINK; 252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 253 (IFM_ACTIVE | IFM_AVALID)) { 254 switch (IFM_SUBTYPE(mii->mii_media_active)) { 255 case IFM_10_T: 256 case IFM_100_TX: 257 sc->ale_flags |= ALE_FLAG_LINK; 258 break; 259 260 case IFM_1000_T: 261 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 262 sc->ale_flags |= ALE_FLAG_LINK; 263 break; 264 265 default: 266 break; 267 } 268 } 269 270 /* Stop Rx/Tx MACs. */ 271 ale_stop_mac(sc); 272 273 /* Program MACs with resolved speed/duplex/flow-control. */ 274 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 275 ale_mac_config(sc); 276 /* Reenable Tx/Rx MACs. */ 277 reg = CSR_READ_4(sc, ALE_MAC_CFG); 278 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 279 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 280 } 281 } 282 283 static void 284 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 285 { 286 struct ale_softc *sc = ifp->if_softc; 287 struct mii_data *mii = device_get_softc(sc->ale_miibus); 288 289 ASSERT_SERIALIZED(ifp->if_serializer); 290 291 mii_pollstat(mii); 292 ifmr->ifm_status = mii->mii_media_status; 293 ifmr->ifm_active = mii->mii_media_active; 294 } 295 296 static int 297 ale_mediachange(struct ifnet *ifp) 298 { 299 struct ale_softc *sc = ifp->if_softc; 300 struct mii_data *mii = device_get_softc(sc->ale_miibus); 301 int error; 302 303 ASSERT_SERIALIZED(ifp->if_serializer); 304 305 if (mii->mii_instance != 0) { 306 struct mii_softc *miisc; 307 308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 309 mii_phy_reset(miisc); 310 } 311 error = mii_mediachg(mii); 312 313 return (error); 314 } 315 316 static int 317 ale_probe(device_t dev) 318 { 319 struct ale_dev *sp; 320 int i; 321 uint16_t vendor, devid; 322 323 vendor = pci_get_vendor(dev); 324 devid = pci_get_device(dev); 325 sp = ale_devs; 326 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 327 if (vendor == sp->ale_vendorid && 328 devid == sp->ale_deviceid) { 329 device_set_desc(dev, sp->ale_name); 330 return (0); 331 } 332 sp++; 333 } 334 335 return (ENXIO); 336 } 337 338 static void 339 ale_get_macaddr(struct ale_softc *sc) 340 { 341 uint32_t ea[2], reg; 342 int i, vpdc; 343 344 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 345 if ((reg & SPI_VPD_ENB) != 0) { 346 reg &= ~SPI_VPD_ENB; 347 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 348 } 349 350 vpdc = pci_get_vpdcap_ptr(sc->ale_dev); 351 if (vpdc) { 352 /* 353 * PCI VPD capability found, let TWSI reload EEPROM. 354 * This will set ethernet address of controller. 355 */ 356 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 357 TWSI_CTRL_SW_LD_START); 358 for (i = 100; i > 0; i--) { 359 DELAY(1000); 360 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 361 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 362 break; 363 } 364 if (i == 0) 365 device_printf(sc->ale_dev, 366 "reloading EEPROM timeout!\n"); 367 } else { 368 if (bootverbose) 369 device_printf(sc->ale_dev, 370 "PCI VPD capability not found!\n"); 371 } 372 373 ea[0] = CSR_READ_4(sc, ALE_PAR0); 374 ea[1] = CSR_READ_4(sc, ALE_PAR1); 375 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 376 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 377 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 378 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 379 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 380 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 381 } 382 383 static void 384 ale_phy_reset(struct ale_softc *sc) 385 { 386 /* Reset magic from Linux. */ 387 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 388 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 389 GPHY_CTRL_PHY_PLL_ON); 390 DELAY(1000); 391 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 392 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 393 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 394 DELAY(1000); 395 396 #define ATPHY_DBG_ADDR 0x1D 397 #define ATPHY_DBG_DATA 0x1E 398 399 /* Enable hibernation mode. */ 400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401 ATPHY_DBG_ADDR, 0x0B); 402 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 403 ATPHY_DBG_DATA, 0xBC00); 404 /* Set Class A/B for all modes. */ 405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406 ATPHY_DBG_ADDR, 0x00); 407 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 408 ATPHY_DBG_DATA, 0x02EF); 409 /* Enable 10BT power saving. */ 410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 411 ATPHY_DBG_ADDR, 0x12); 412 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 413 ATPHY_DBG_DATA, 0x4C04); 414 /* Adjust 1000T power. */ 415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 416 ATPHY_DBG_ADDR, 0x04); 417 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 418 ATPHY_DBG_ADDR, 0x8BBB); 419 /* 10BT center tap voltage. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x05); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_ADDR, 0x2C46); 424 425 #undef ATPHY_DBG_ADDR 426 #undef ATPHY_DBG_DATA 427 DELAY(1000); 428 } 429 430 static int 431 ale_attach(device_t dev) 432 { 433 struct ale_softc *sc = device_get_softc(dev); 434 struct ifnet *ifp = &sc->arpcom.ac_if; 435 int error = 0; 436 uint32_t rxf_len, txf_len; 437 uint8_t pcie_ptr; 438 439 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 440 sc->ale_dev = dev; 441 442 callout_init(&sc->ale_tick_ch); 443 444 #ifndef BURN_BRIDGES 445 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 446 uint32_t irq, mem; 447 448 irq = pci_read_config(dev, PCIR_INTLINE, 4); 449 mem = pci_read_config(dev, ALE_PCIR_BAR, 4); 450 451 device_printf(dev, "chip is in D%d power mode " 452 "-- setting to D0\n", pci_get_powerstate(dev)); 453 454 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 455 456 pci_write_config(dev, PCIR_INTLINE, irq, 4); 457 pci_write_config(dev, ALE_PCIR_BAR, mem, 4); 458 } 459 #endif /* !BURN_BRIDGE */ 460 461 /* Enable bus mastering */ 462 pci_enable_busmaster(dev); 463 464 /* 465 * Allocate memory mapped IO 466 */ 467 sc->ale_mem_rid = ALE_PCIR_BAR; 468 sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 469 &sc->ale_mem_rid, RF_ACTIVE); 470 if (sc->ale_mem_res == NULL) { 471 device_printf(dev, "can't allocate IO memory\n"); 472 return ENXIO; 473 } 474 sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res); 475 sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res); 476 477 /* 478 * Allocate IRQ 479 */ 480 sc->ale_irq_rid = 0; 481 sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 482 &sc->ale_irq_rid, 483 RF_SHAREABLE | RF_ACTIVE); 484 if (sc->ale_irq_res == NULL) { 485 device_printf(dev, "can't allocate irq\n"); 486 error = ENXIO; 487 goto fail; 488 } 489 490 /* Set PHY address. */ 491 sc->ale_phyaddr = ALE_PHY_ADDR; 492 493 /* Reset PHY. */ 494 ale_phy_reset(sc); 495 496 /* Reset the ethernet controller. */ 497 ale_reset(sc); 498 499 /* Get PCI and chip id/revision. */ 500 sc->ale_rev = pci_get_revid(dev); 501 if (sc->ale_rev >= 0xF0) { 502 /* L2E Rev. B. AR8114 */ 503 sc->ale_flags |= ALE_FLAG_FASTETHER; 504 } else { 505 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 506 /* L1E AR8121 */ 507 sc->ale_flags |= ALE_FLAG_JUMBO; 508 } else { 509 /* L2E Rev. A. AR8113 */ 510 sc->ale_flags |= ALE_FLAG_FASTETHER; 511 } 512 } 513 514 /* 515 * All known controllers seems to require 4 bytes alignment 516 * of Tx buffers to make Tx checksum offload with custom 517 * checksum generation method work. 518 */ 519 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 520 521 /* 522 * All known controllers seems to have issues on Rx checksum 523 * offload for fragmented IP datagrams. 524 */ 525 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 526 527 /* 528 * Don't use Tx CMB. It is known to cause RRS update failure 529 * under certain circumstances. Typical phenomenon of the 530 * issue would be unexpected sequence number encountered in 531 * Rx handler. 532 */ 533 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 534 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 535 MASTER_CHIP_REV_SHIFT; 536 if (bootverbose) { 537 device_printf(dev, "PCI device revision : 0x%04x\n", 538 sc->ale_rev); 539 device_printf(dev, "Chip id/revision : 0x%04x\n", 540 sc->ale_chip_rev); 541 } 542 543 /* 544 * Uninitialized hardware returns an invalid chip id/revision 545 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 546 */ 547 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 548 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 549 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 550 rxf_len == 0xFFFFFFF) { 551 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 552 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 553 txf_len, rxf_len); 554 error = ENXIO; 555 goto fail; 556 } 557 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 558 559 /* Get DMA parameters from PCIe device control register. */ 560 pcie_ptr = pci_get_pciecap_ptr(dev); 561 if (pcie_ptr) { 562 uint16_t devctl; 563 564 sc->ale_flags |= ALE_FLAG_PCIE; 565 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 566 /* Max read request size. */ 567 sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) << 568 DMA_CFG_RD_BURST_SHIFT; 569 /* Max payload size. */ 570 sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) << 571 DMA_CFG_WR_BURST_SHIFT; 572 if (bootverbose) { 573 device_printf(dev, "Read request size : %d bytes.\n", 574 128 << ((devctl >> 12) & 0x07)); 575 device_printf(dev, "TLP payload size : %d bytes.\n", 576 128 << ((devctl >> 5) & 0x07)); 577 } 578 } else { 579 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 580 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 581 } 582 583 /* Create device sysctl node. */ 584 ale_sysctl_node(sc); 585 586 if ((error = ale_dma_alloc(sc) != 0)) 587 goto fail; 588 589 /* Load station address. */ 590 ale_get_macaddr(sc); 591 592 ifp->if_softc = sc; 593 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 594 ifp->if_ioctl = ale_ioctl; 595 ifp->if_start = ale_start; 596 ifp->if_init = ale_init; 597 ifp->if_watchdog = ale_watchdog; 598 ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1); 599 ifq_set_ready(&ifp->if_snd); 600 601 ifp->if_capabilities = IFCAP_RXCSUM | 602 IFCAP_VLAN_MTU | 603 IFCAP_VLAN_HWTAGGING; 604 #ifdef notyet 605 ifp->if_capabilities |= IFCAP_TXCSUM; 606 ifp->if_hwassist = ALE_CSUM_FEATURES; 607 #endif 608 ifp->if_capenable = ifp->if_capabilities; 609 610 /* Set up MII bus. */ 611 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 612 ale_mediastatus)) != 0) { 613 device_printf(dev, "no PHY found!\n"); 614 goto fail; 615 } 616 617 ether_ifattach(ifp, sc->ale_eaddr, NULL); 618 619 /* Tell the upper layer(s) we support long frames. */ 620 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 621 622 error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc, 623 &sc->ale_irq_handle, ifp->if_serializer); 624 if (error) { 625 device_printf(dev, "could not set up interrupt handler.\n"); 626 ether_ifdetach(ifp); 627 goto fail; 628 } 629 630 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->ale_irq_res)); 631 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 632 return 0; 633 fail: 634 ale_detach(dev); 635 return (error); 636 } 637 638 static int 639 ale_detach(device_t dev) 640 { 641 struct ale_softc *sc = device_get_softc(dev); 642 643 if (device_is_attached(dev)) { 644 struct ifnet *ifp = &sc->arpcom.ac_if; 645 646 lwkt_serialize_enter(ifp->if_serializer); 647 sc->ale_flags |= ALE_FLAG_DETACH; 648 ale_stop(sc); 649 bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle); 650 lwkt_serialize_exit(ifp->if_serializer); 651 652 ether_ifdetach(ifp); 653 } 654 655 if (sc->ale_sysctl_tree != NULL) 656 sysctl_ctx_free(&sc->ale_sysctl_ctx); 657 658 if (sc->ale_miibus != NULL) 659 device_delete_child(dev, sc->ale_miibus); 660 bus_generic_detach(dev); 661 662 if (sc->ale_irq_res != NULL) { 663 bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid, 664 sc->ale_irq_res); 665 } 666 if (sc->ale_mem_res != NULL) { 667 bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid, 668 sc->ale_mem_res); 669 } 670 671 ale_dma_free(sc); 672 673 return (0); 674 } 675 676 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 677 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 678 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 679 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 680 681 static void 682 ale_sysctl_node(struct ale_softc *sc) 683 { 684 struct sysctl_ctx_list *ctx; 685 struct sysctl_oid_list *child, *parent; 686 struct sysctl_oid *tree; 687 struct ale_hw_stats *stats; 688 int error; 689 690 sysctl_ctx_init(&sc->ale_sysctl_ctx); 691 sc->ale_sysctl_tree = SYSCTL_ADD_NODE(&sc->ale_sysctl_ctx, 692 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 693 device_get_nameunit(sc->ale_dev), 694 CTLFLAG_RD, 0, ""); 695 if (sc->ale_sysctl_tree == NULL) { 696 device_printf(sc->ale_dev, "can't add sysctl node\n"); 697 return; 698 } 699 700 stats = &sc->ale_stats; 701 ctx = &sc->ale_sysctl_ctx; 702 child = SYSCTL_CHILDREN(sc->ale_sysctl_tree); 703 704 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 705 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 706 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 707 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 708 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 709 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 710 711 /* 712 * Pull in device tunables. 713 */ 714 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 715 error = resource_int_value(device_get_name(sc->ale_dev), 716 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 717 if (error == 0) { 718 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 719 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 720 device_printf(sc->ale_dev, "int_rx_mod value out of " 721 "range; using default: %d\n", 722 ALE_IM_RX_TIMER_DEFAULT); 723 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 724 } 725 } 726 727 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 728 error = resource_int_value(device_get_name(sc->ale_dev), 729 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 730 if (error == 0) { 731 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 732 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 733 device_printf(sc->ale_dev, "int_tx_mod value out of " 734 "range; using default: %d\n", 735 ALE_IM_TX_TIMER_DEFAULT); 736 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 737 } 738 } 739 740 /* Misc statistics. */ 741 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 742 &stats->reset_brk_seq, 743 "Controller resets due to broken Rx sequnce number"); 744 745 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 746 NULL, "ATE statistics"); 747 parent = SYSCTL_CHILDREN(tree); 748 749 /* Rx statistics. */ 750 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 751 NULL, "Rx MAC statistics"); 752 child = SYSCTL_CHILDREN(tree); 753 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 754 &stats->rx_frames, "Good frames"); 755 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 756 &stats->rx_bcast_frames, "Good broadcast frames"); 757 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 758 &stats->rx_mcast_frames, "Good multicast frames"); 759 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 760 &stats->rx_pause_frames, "Pause control frames"); 761 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 762 &stats->rx_control_frames, "Control frames"); 763 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 764 &stats->rx_crcerrs, "CRC errors"); 765 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 766 &stats->rx_lenerrs, "Frames with length mismatched"); 767 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 768 &stats->rx_bytes, "Good octets"); 769 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 770 &stats->rx_bcast_bytes, "Good broadcast octets"); 771 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 772 &stats->rx_mcast_bytes, "Good multicast octets"); 773 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 774 &stats->rx_runts, "Too short frames"); 775 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 776 &stats->rx_fragments, "Fragmented frames"); 777 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 778 &stats->rx_pkts_64, "64 bytes frames"); 779 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 780 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 781 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 782 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 783 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 784 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 785 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 786 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 787 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 788 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 789 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 790 &stats->rx_pkts_1519_max, "1519 to max frames"); 791 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 792 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 793 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 794 &stats->rx_fifo_oflows, "FIFO overflows"); 795 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 796 &stats->rx_rrs_errs, "Return status write-back errors"); 797 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 798 &stats->rx_alignerrs, "Alignment errors"); 799 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 800 &stats->rx_pkts_filtered, 801 "Frames dropped due to address filtering"); 802 803 /* Tx statistics. */ 804 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 805 NULL, "Tx MAC statistics"); 806 child = SYSCTL_CHILDREN(tree); 807 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 808 &stats->tx_frames, "Good frames"); 809 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 810 &stats->tx_bcast_frames, "Good broadcast frames"); 811 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 812 &stats->tx_mcast_frames, "Good multicast frames"); 813 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 814 &stats->tx_pause_frames, "Pause control frames"); 815 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 816 &stats->tx_control_frames, "Control frames"); 817 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 818 &stats->tx_excess_defer, "Frames with excessive derferrals"); 819 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 820 &stats->tx_excess_defer, "Frames with derferrals"); 821 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 822 &stats->tx_bytes, "Good octets"); 823 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 824 &stats->tx_bcast_bytes, "Good broadcast octets"); 825 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 826 &stats->tx_mcast_bytes, "Good multicast octets"); 827 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 828 &stats->tx_pkts_64, "64 bytes frames"); 829 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 830 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 831 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 832 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 833 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 834 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 835 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 836 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 837 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 838 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 839 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 840 &stats->tx_pkts_1519_max, "1519 to max frames"); 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 842 &stats->tx_single_colls, "Single collisions"); 843 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 844 &stats->tx_multi_colls, "Multiple collisions"); 845 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 846 &stats->tx_late_colls, "Late collisions"); 847 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 848 &stats->tx_excess_colls, "Excessive collisions"); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 850 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 851 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 852 &stats->tx_underrun, "FIFO underruns"); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 854 &stats->tx_desc_underrun, "Descriptor write-back errors"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 856 &stats->tx_lenerrs, "Frames with length mismatched"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 858 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 859 } 860 861 #undef ALE_SYSCTL_STAT_ADD32 862 #undef ALE_SYSCTL_STAT_ADD64 863 864 struct ale_dmamap_arg { 865 bus_addr_t ale_busaddr; 866 }; 867 868 static void 869 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 870 { 871 struct ale_dmamap_arg *ctx; 872 873 if (error != 0) 874 return; 875 876 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 877 878 ctx = (struct ale_dmamap_arg *)arg; 879 ctx->ale_busaddr = segs[0].ds_addr; 880 } 881 882 /* 883 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 884 * which specifies high address region of DMA blocks. Therefore these 885 * blocks should have the same high address of given 4GB address 886 * space(i.e. crossing 4GB boundary is not allowed). 887 */ 888 static int 889 ale_check_boundary(struct ale_softc *sc) 890 { 891 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 892 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 893 894 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 895 sc->ale_pagesize; 896 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 897 sc->ale_pagesize; 898 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 899 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 900 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 901 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 902 903 if ((ALE_ADDR_HI(tx_ring_end) != 904 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 905 (ALE_ADDR_HI(rx_page_end[0]) != 906 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 907 (ALE_ADDR_HI(rx_page_end[1]) != 908 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 909 (ALE_ADDR_HI(tx_cmb_end) != 910 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 911 (ALE_ADDR_HI(rx_cmb_end[0]) != 912 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 913 (ALE_ADDR_HI(rx_cmb_end[1]) != 914 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 915 return (EFBIG); 916 917 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 918 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 919 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 920 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 921 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 922 return (EFBIG); 923 924 return (0); 925 } 926 927 static int 928 ale_dma_alloc(struct ale_softc *sc) 929 { 930 struct ale_txdesc *txd; 931 bus_addr_t lowaddr; 932 struct ale_dmamap_arg ctx; 933 int error, guard_size, i; 934 935 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 936 guard_size = ALE_JUMBO_FRAMELEN; 937 else 938 guard_size = ALE_MAX_FRAMELEN; 939 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 940 ALE_RX_PAGE_ALIGN); 941 lowaddr = BUS_SPACE_MAXADDR; 942 again: 943 /* Create parent DMA tag. */ 944 error = bus_dma_tag_create( 945 NULL, /* parent */ 946 1, 0, /* alignment, boundary */ 947 lowaddr, /* lowaddr */ 948 BUS_SPACE_MAXADDR, /* highaddr */ 949 NULL, NULL, /* filter, filterarg */ 950 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 951 0, /* nsegments */ 952 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 953 0, /* flags */ 954 &sc->ale_cdata.ale_parent_tag); 955 if (error != 0) { 956 device_printf(sc->ale_dev, 957 "could not create parent DMA tag.\n"); 958 goto fail; 959 } 960 961 /* Create DMA tag for Tx descriptor ring. */ 962 error = bus_dma_tag_create( 963 sc->ale_cdata.ale_parent_tag, /* parent */ 964 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 965 BUS_SPACE_MAXADDR, /* lowaddr */ 966 BUS_SPACE_MAXADDR, /* highaddr */ 967 NULL, NULL, /* filter, filterarg */ 968 ALE_TX_RING_SZ, /* maxsize */ 969 1, /* nsegments */ 970 ALE_TX_RING_SZ, /* maxsegsize */ 971 0, /* flags */ 972 &sc->ale_cdata.ale_tx_ring_tag); 973 if (error != 0) { 974 device_printf(sc->ale_dev, 975 "could not create Tx ring DMA tag.\n"); 976 goto fail; 977 } 978 979 /* Create DMA tag for Rx pages. */ 980 for (i = 0; i < ALE_RX_PAGES; i++) { 981 error = bus_dma_tag_create( 982 sc->ale_cdata.ale_parent_tag, /* parent */ 983 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 984 BUS_SPACE_MAXADDR, /* lowaddr */ 985 BUS_SPACE_MAXADDR, /* highaddr */ 986 NULL, NULL, /* filter, filterarg */ 987 sc->ale_pagesize, /* maxsize */ 988 1, /* nsegments */ 989 sc->ale_pagesize, /* maxsegsize */ 990 0, /* flags */ 991 &sc->ale_cdata.ale_rx_page[i].page_tag); 992 if (error != 0) { 993 device_printf(sc->ale_dev, 994 "could not create Rx page %d DMA tag.\n", i); 995 goto fail; 996 } 997 } 998 999 /* Create DMA tag for Tx coalescing message block. */ 1000 error = bus_dma_tag_create( 1001 sc->ale_cdata.ale_parent_tag, /* parent */ 1002 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1003 BUS_SPACE_MAXADDR, /* lowaddr */ 1004 BUS_SPACE_MAXADDR, /* highaddr */ 1005 NULL, NULL, /* filter, filterarg */ 1006 ALE_TX_CMB_SZ, /* maxsize */ 1007 1, /* nsegments */ 1008 ALE_TX_CMB_SZ, /* maxsegsize */ 1009 0, /* flags */ 1010 &sc->ale_cdata.ale_tx_cmb_tag); 1011 if (error != 0) { 1012 device_printf(sc->ale_dev, 1013 "could not create Tx CMB DMA tag.\n"); 1014 goto fail; 1015 } 1016 1017 /* Create DMA tag for Rx coalescing message block. */ 1018 for (i = 0; i < ALE_RX_PAGES; i++) { 1019 error = bus_dma_tag_create( 1020 sc->ale_cdata.ale_parent_tag, /* parent */ 1021 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1022 BUS_SPACE_MAXADDR, /* lowaddr */ 1023 BUS_SPACE_MAXADDR, /* highaddr */ 1024 NULL, NULL, /* filter, filterarg */ 1025 ALE_RX_CMB_SZ, /* maxsize */ 1026 1, /* nsegments */ 1027 ALE_RX_CMB_SZ, /* maxsegsize */ 1028 0, /* flags */ 1029 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1030 if (error != 0) { 1031 device_printf(sc->ale_dev, 1032 "could not create Rx page %d CMB DMA tag.\n", i); 1033 goto fail; 1034 } 1035 } 1036 1037 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1038 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1039 (void **)&sc->ale_cdata.ale_tx_ring, 1040 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1041 &sc->ale_cdata.ale_tx_ring_map); 1042 if (error != 0) { 1043 device_printf(sc->ale_dev, 1044 "could not allocate DMA'able memory for Tx ring.\n"); 1045 goto fail; 1046 } 1047 ctx.ale_busaddr = 0; 1048 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1049 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1050 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1051 if (error != 0 || ctx.ale_busaddr == 0) { 1052 device_printf(sc->ale_dev, 1053 "could not load DMA'able memory for Tx ring.\n"); 1054 goto fail; 1055 } 1056 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1057 1058 /* Rx pages. */ 1059 for (i = 0; i < ALE_RX_PAGES; i++) { 1060 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1061 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1062 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1063 &sc->ale_cdata.ale_rx_page[i].page_map); 1064 if (error != 0) { 1065 device_printf(sc->ale_dev, 1066 "could not allocate DMA'able memory for " 1067 "Rx page %d.\n", i); 1068 goto fail; 1069 } 1070 ctx.ale_busaddr = 0; 1071 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1072 sc->ale_cdata.ale_rx_page[i].page_map, 1073 sc->ale_cdata.ale_rx_page[i].page_addr, 1074 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1075 if (error != 0 || ctx.ale_busaddr == 0) { 1076 device_printf(sc->ale_dev, 1077 "could not load DMA'able memory for " 1078 "Rx page %d.\n", i); 1079 goto fail; 1080 } 1081 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1082 } 1083 1084 /* Tx CMB. */ 1085 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1086 (void **)&sc->ale_cdata.ale_tx_cmb, 1087 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1088 &sc->ale_cdata.ale_tx_cmb_map); 1089 if (error != 0) { 1090 device_printf(sc->ale_dev, 1091 "could not allocate DMA'able memory for Tx CMB.\n"); 1092 goto fail; 1093 } 1094 ctx.ale_busaddr = 0; 1095 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1096 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1097 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1098 if (error != 0 || ctx.ale_busaddr == 0) { 1099 device_printf(sc->ale_dev, 1100 "could not load DMA'able memory for Tx CMB.\n"); 1101 goto fail; 1102 } 1103 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1104 1105 /* Rx CMB. */ 1106 for (i = 0; i < ALE_RX_PAGES; i++) { 1107 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1108 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1109 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1110 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1111 if (error != 0) { 1112 device_printf(sc->ale_dev, "could not allocate " 1113 "DMA'able memory for Rx page %d CMB.\n", i); 1114 goto fail; 1115 } 1116 ctx.ale_busaddr = 0; 1117 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1118 sc->ale_cdata.ale_rx_page[i].cmb_map, 1119 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1120 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1121 if (error != 0 || ctx.ale_busaddr == 0) { 1122 device_printf(sc->ale_dev, "could not load DMA'able " 1123 "memory for Rx page %d CMB.\n", i); 1124 goto fail; 1125 } 1126 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1127 } 1128 1129 /* 1130 * Tx descriptors/RXF0/CMB DMA blocks share the same 1131 * high address region of 64bit DMA address space. 1132 */ 1133 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1134 (error = ale_check_boundary(sc)) != 0) { 1135 device_printf(sc->ale_dev, "4GB boundary crossed, " 1136 "switching to 32bit DMA addressing mode.\n"); 1137 ale_dma_free(sc); 1138 /* 1139 * Limit max allowable DMA address space to 32bit 1140 * and try again. 1141 */ 1142 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1143 goto again; 1144 } 1145 1146 /* 1147 * Create Tx buffer parent tag. 1148 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1149 * needs separate parent DMA tag as parent DMA address space 1150 * could be restricted to be within 32bit address space by 1151 * 4GB boundary crossing. 1152 */ 1153 error = bus_dma_tag_create( 1154 NULL, /* parent */ 1155 1, 0, /* alignment, boundary */ 1156 BUS_SPACE_MAXADDR, /* lowaddr */ 1157 BUS_SPACE_MAXADDR, /* highaddr */ 1158 NULL, NULL, /* filter, filterarg */ 1159 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1160 0, /* nsegments */ 1161 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1162 0, /* flags */ 1163 &sc->ale_cdata.ale_buffer_tag); 1164 if (error != 0) { 1165 device_printf(sc->ale_dev, 1166 "could not create parent buffer DMA tag.\n"); 1167 goto fail; 1168 } 1169 1170 /* Create DMA tag for Tx buffers. */ 1171 error = bus_dma_tag_create( 1172 sc->ale_cdata.ale_buffer_tag, /* parent */ 1173 1, 0, /* alignment, boundary */ 1174 BUS_SPACE_MAXADDR, /* lowaddr */ 1175 BUS_SPACE_MAXADDR, /* highaddr */ 1176 NULL, NULL, /* filter, filterarg */ 1177 ALE_TSO_MAXSIZE, /* maxsize */ 1178 ALE_MAXTXSEGS, /* nsegments */ 1179 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1180 0, /* flags */ 1181 &sc->ale_cdata.ale_tx_tag); 1182 if (error != 0) { 1183 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1184 goto fail; 1185 } 1186 1187 /* Create DMA maps for Tx buffers. */ 1188 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1189 txd = &sc->ale_cdata.ale_txdesc[i]; 1190 txd->tx_m = NULL; 1191 txd->tx_dmamap = NULL; 1192 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1193 &txd->tx_dmamap); 1194 if (error != 0) { 1195 device_printf(sc->ale_dev, 1196 "could not create Tx dmamap.\n"); 1197 goto fail; 1198 } 1199 } 1200 fail: 1201 return (error); 1202 } 1203 1204 static void 1205 ale_dma_free(struct ale_softc *sc) 1206 { 1207 struct ale_txdesc *txd; 1208 int i; 1209 1210 /* Tx buffers. */ 1211 if (sc->ale_cdata.ale_tx_tag != NULL) { 1212 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1213 txd = &sc->ale_cdata.ale_txdesc[i]; 1214 if (txd->tx_dmamap != NULL) { 1215 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1216 txd->tx_dmamap); 1217 txd->tx_dmamap = NULL; 1218 } 1219 } 1220 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1221 sc->ale_cdata.ale_tx_tag = NULL; 1222 } 1223 /* Tx descriptor ring. */ 1224 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1225 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1226 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1227 sc->ale_cdata.ale_tx_ring_map); 1228 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1229 sc->ale_cdata.ale_tx_ring != NULL) 1230 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1231 sc->ale_cdata.ale_tx_ring, 1232 sc->ale_cdata.ale_tx_ring_map); 1233 sc->ale_cdata.ale_tx_ring = NULL; 1234 sc->ale_cdata.ale_tx_ring_map = NULL; 1235 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1236 sc->ale_cdata.ale_tx_ring_tag = NULL; 1237 } 1238 /* Rx page block. */ 1239 for (i = 0; i < ALE_RX_PAGES; i++) { 1240 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1241 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1242 bus_dmamap_unload( 1243 sc->ale_cdata.ale_rx_page[i].page_tag, 1244 sc->ale_cdata.ale_rx_page[i].page_map); 1245 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1246 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1247 bus_dmamem_free( 1248 sc->ale_cdata.ale_rx_page[i].page_tag, 1249 sc->ale_cdata.ale_rx_page[i].page_addr, 1250 sc->ale_cdata.ale_rx_page[i].page_map); 1251 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1252 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1253 bus_dma_tag_destroy( 1254 sc->ale_cdata.ale_rx_page[i].page_tag); 1255 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1256 } 1257 } 1258 /* Rx CMB. */ 1259 for (i = 0; i < ALE_RX_PAGES; i++) { 1260 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1261 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1262 bus_dmamap_unload( 1263 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1264 sc->ale_cdata.ale_rx_page[i].cmb_map); 1265 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1266 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1267 bus_dmamem_free( 1268 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1269 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1270 sc->ale_cdata.ale_rx_page[i].cmb_map); 1271 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1272 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1273 bus_dma_tag_destroy( 1274 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1275 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1276 } 1277 } 1278 /* Tx CMB. */ 1279 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1280 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1281 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1282 sc->ale_cdata.ale_tx_cmb_map); 1283 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1284 sc->ale_cdata.ale_tx_cmb != NULL) 1285 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1286 sc->ale_cdata.ale_tx_cmb, 1287 sc->ale_cdata.ale_tx_cmb_map); 1288 sc->ale_cdata.ale_tx_cmb = NULL; 1289 sc->ale_cdata.ale_tx_cmb_map = NULL; 1290 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1291 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1292 } 1293 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1294 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1295 sc->ale_cdata.ale_buffer_tag = NULL; 1296 } 1297 if (sc->ale_cdata.ale_parent_tag != NULL) { 1298 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1299 sc->ale_cdata.ale_parent_tag = NULL; 1300 } 1301 } 1302 1303 static int 1304 ale_shutdown(device_t dev) 1305 { 1306 return (ale_suspend(dev)); 1307 } 1308 1309 #ifdef notyet 1310 1311 /* 1312 * Note, this driver resets the link speed to 10/100Mbps by 1313 * restarting auto-negotiation in suspend/shutdown phase but we 1314 * don't know whether that auto-negotiation would succeed or not 1315 * as driver has no control after powering off/suspend operation. 1316 * If the renegotiation fail WOL may not work. Running at 1Gbps 1317 * will draw more power than 375mA at 3.3V which is specified in 1318 * PCI specification and that would result in complete 1319 * shutdowning power to ethernet controller. 1320 * 1321 * TODO 1322 * Save current negotiated media speed/duplex/flow-control to 1323 * softc and restore the same link again after resuming. PHY 1324 * handling such as power down/resetting to 100Mbps may be better 1325 * handled in suspend method in phy driver. 1326 */ 1327 static void 1328 ale_setlinkspeed(struct ale_softc *sc) 1329 { 1330 struct mii_data *mii; 1331 int aneg, i; 1332 1333 mii = device_get_softc(sc->ale_miibus); 1334 mii_pollstat(mii); 1335 aneg = 0; 1336 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1337 (IFM_ACTIVE | IFM_AVALID)) { 1338 switch IFM_SUBTYPE(mii->mii_media_active) { 1339 case IFM_10_T: 1340 case IFM_100_TX: 1341 return; 1342 case IFM_1000_T: 1343 aneg++; 1344 break; 1345 default: 1346 break; 1347 } 1348 } 1349 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1350 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1351 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1352 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1353 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1354 DELAY(1000); 1355 if (aneg != 0) { 1356 /* 1357 * Poll link state until ale(4) get a 10/100Mbps link. 1358 */ 1359 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1360 mii_pollstat(mii); 1361 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1362 == (IFM_ACTIVE | IFM_AVALID)) { 1363 switch (IFM_SUBTYPE( 1364 mii->mii_media_active)) { 1365 case IFM_10_T: 1366 case IFM_100_TX: 1367 ale_mac_config(sc); 1368 return; 1369 default: 1370 break; 1371 } 1372 } 1373 ALE_UNLOCK(sc); 1374 pause("alelnk", hz); 1375 ALE_LOCK(sc); 1376 } 1377 if (i == MII_ANEGTICKS_GIGE) 1378 device_printf(sc->ale_dev, 1379 "establishing a link failed, WOL may not work!"); 1380 } 1381 /* 1382 * No link, force MAC to have 100Mbps, full-duplex link. 1383 * This is the last resort and may/may not work. 1384 */ 1385 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1386 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1387 ale_mac_config(sc); 1388 } 1389 1390 static void 1391 ale_setwol(struct ale_softc *sc) 1392 { 1393 struct ifnet *ifp; 1394 uint32_t reg, pmcs; 1395 uint16_t pmstat; 1396 int pmc; 1397 1398 ALE_LOCK_ASSERT(sc); 1399 1400 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1401 /* Disable WOL. */ 1402 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1403 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1404 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1405 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1406 /* Force PHY power down. */ 1407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1408 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1409 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1410 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1411 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1412 return; 1413 } 1414 1415 ifp = sc->ale_ifp; 1416 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1417 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1418 ale_setlinkspeed(sc); 1419 } 1420 1421 pmcs = 0; 1422 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1423 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1424 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1425 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1426 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1427 MAC_CFG_BCAST); 1428 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1429 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1430 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1431 reg |= MAC_CFG_RX_ENB; 1432 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1433 1434 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1435 /* WOL disabled, PHY power down. */ 1436 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1437 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1438 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1439 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1440 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1441 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1442 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1443 GPHY_CTRL_PWDOWN_HW); 1444 } 1445 /* Request PME. */ 1446 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1447 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1448 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1449 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1450 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1451 } 1452 1453 #endif /* notyet */ 1454 1455 static int 1456 ale_suspend(device_t dev) 1457 { 1458 struct ale_softc *sc = device_get_softc(dev); 1459 struct ifnet *ifp = &sc->arpcom.ac_if; 1460 1461 lwkt_serialize_enter(ifp->if_serializer); 1462 ale_stop(sc); 1463 #ifdef notyet 1464 ale_setwol(sc); 1465 #endif 1466 lwkt_serialize_exit(ifp->if_serializer); 1467 return (0); 1468 } 1469 1470 static int 1471 ale_resume(device_t dev) 1472 { 1473 struct ale_softc *sc = device_get_softc(dev); 1474 struct ifnet *ifp = &sc->arpcom.ac_if; 1475 uint16_t cmd; 1476 1477 lwkt_serialize_enter(ifp->if_serializer); 1478 1479 /* 1480 * Clear INTx emulation disable for hardwares that 1481 * is set in resume event. From Linux. 1482 */ 1483 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2); 1484 if ((cmd & 0x0400) != 0) { 1485 cmd &= ~0x0400; 1486 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2); 1487 } 1488 1489 #ifdef notyet 1490 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1491 uint16_t pmstat; 1492 int pmc; 1493 1494 /* Disable PME and clear PME status. */ 1495 pmstat = pci_read_config(sc->ale_dev, 1496 pmc + PCIR_POWER_STATUS, 2); 1497 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1498 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1499 pci_write_config(sc->ale_dev, 1500 pmc + PCIR_POWER_STATUS, pmstat, 2); 1501 } 1502 } 1503 #endif 1504 1505 /* Reset PHY. */ 1506 ale_phy_reset(sc); 1507 if ((ifp->if_flags & IFF_UP) != 0) 1508 ale_init(sc); 1509 1510 lwkt_serialize_exit(ifp->if_serializer); 1511 return (0); 1512 } 1513 1514 static int 1515 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1516 { 1517 struct ale_txdesc *txd, *txd_last; 1518 struct tx_desc *desc; 1519 struct mbuf *m; 1520 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1521 struct ale_dmamap_ctx ctx; 1522 bus_dmamap_t map; 1523 uint32_t cflags, poff, vtag; 1524 int error, i, nsegs, prod, si; 1525 1526 M_ASSERTPKTHDR((*m_head)); 1527 1528 m = *m_head; 1529 cflags = vtag = 0; 1530 poff = 0; 1531 1532 si = prod = sc->ale_cdata.ale_tx_prod; 1533 txd = &sc->ale_cdata.ale_txdesc[prod]; 1534 txd_last = txd; 1535 map = txd->tx_dmamap; 1536 1537 ctx.nsegs = ALE_MAXTXSEGS; 1538 ctx.segs = txsegs; 1539 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map, 1540 *m_head, ale_dmamap_buf_cb, &ctx, 1541 BUS_DMA_NOWAIT); 1542 if (error == EFBIG) { 1543 m = m_defrag(*m_head, MB_DONTWAIT); 1544 if (m == NULL) { 1545 m_freem(*m_head); 1546 *m_head = NULL; 1547 return (ENOMEM); 1548 } 1549 *m_head = m; 1550 1551 ctx.nsegs = ALE_MAXTXSEGS; 1552 ctx.segs = txsegs; 1553 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map, 1554 *m_head, ale_dmamap_buf_cb, &ctx, 1555 BUS_DMA_NOWAIT); 1556 if (error != 0) { 1557 m_freem(*m_head); 1558 *m_head = NULL; 1559 return (error); 1560 } 1561 } else if (error != 0) { 1562 return (error); 1563 } 1564 nsegs = ctx.nsegs; 1565 1566 if (nsegs == 0) { 1567 m_freem(*m_head); 1568 *m_head = NULL; 1569 return (EIO); 1570 } 1571 1572 /* Check descriptor overrun. */ 1573 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1574 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1575 return (ENOBUFS); 1576 } 1577 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1578 1579 m = *m_head; 1580 /* Configure Tx checksum offload. */ 1581 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1582 /* 1583 * AR81xx supports Tx custom checksum offload feature 1584 * that offloads single 16bit checksum computation. 1585 * So you can choose one among IP, TCP and UDP. 1586 * Normally driver sets checksum start/insertion 1587 * position from the information of TCP/UDP frame as 1588 * TCP/UDP checksum takes more time than that of IP. 1589 * However it seems that custom checksum offload 1590 * requires 4 bytes aligned Tx buffers due to hardware 1591 * bug. 1592 * AR81xx also supports explicit Tx checksum computation 1593 * if it is told that the size of IP header and TCP 1594 * header(for UDP, the header size does not matter 1595 * because it's fixed length). However with this scheme 1596 * TSO does not work so you have to choose one either 1597 * TSO or explicit Tx checksum offload. I chosen TSO 1598 * plus custom checksum offload with work-around which 1599 * will cover most common usage for this consumer 1600 * ethernet controller. The work-around takes a lot of 1601 * CPU cycles if Tx buffer is not aligned on 4 bytes 1602 * boundary, though. 1603 */ 1604 cflags |= ALE_TD_CXSUM; 1605 /* Set checksum start offset. */ 1606 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1607 /* Set checksum insertion position of TCP/UDP. */ 1608 cflags |= ((poff + m->m_pkthdr.csum_data) << 1609 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1610 } 1611 1612 /* Configure VLAN hardware tag insertion. */ 1613 if ((m->m_flags & M_VLANTAG) != 0) { 1614 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag); 1615 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1616 cflags |= ALE_TD_INSERT_VLAN_TAG; 1617 } 1618 1619 desc = NULL; 1620 for (i = 0; i < nsegs; i++) { 1621 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1622 desc->addr = htole64(txsegs[i].ds_addr); 1623 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1624 desc->flags = htole32(cflags); 1625 sc->ale_cdata.ale_tx_cnt++; 1626 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1627 } 1628 /* Update producer index. */ 1629 sc->ale_cdata.ale_tx_prod = prod; 1630 1631 /* Finally set EOP on the last descriptor. */ 1632 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1633 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1634 desc->flags |= htole32(ALE_TD_EOP); 1635 1636 /* Swap dmamap of the first and the last. */ 1637 txd = &sc->ale_cdata.ale_txdesc[prod]; 1638 map = txd_last->tx_dmamap; 1639 txd_last->tx_dmamap = txd->tx_dmamap; 1640 txd->tx_dmamap = map; 1641 txd->tx_m = m; 1642 1643 /* Sync descriptors. */ 1644 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1645 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE); 1646 1647 return (0); 1648 } 1649 1650 static void 1651 ale_start(struct ifnet *ifp) 1652 { 1653 struct ale_softc *sc = ifp->if_softc; 1654 struct mbuf *m_head; 1655 int enq; 1656 1657 ASSERT_SERIALIZED(ifp->if_serializer); 1658 1659 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1660 ifq_purge(&ifp->if_snd); 1661 return; 1662 } 1663 1664 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1665 return; 1666 1667 /* Reclaim transmitted frames. */ 1668 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1669 ale_txeof(sc); 1670 1671 enq = 0; 1672 while (!ifq_is_empty(&ifp->if_snd)) { 1673 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1674 if (m_head == NULL) 1675 break; 1676 1677 /* 1678 * Pack the data into the transmit ring. If we 1679 * don't have room, set the OACTIVE flag and wait 1680 * for the NIC to drain the ring. 1681 */ 1682 if (ale_encap(sc, &m_head)) { 1683 if (m_head == NULL) 1684 break; 1685 ifq_prepend(&ifp->if_snd, m_head); 1686 ifp->if_flags |= IFF_OACTIVE; 1687 break; 1688 } 1689 enq = 1; 1690 1691 /* 1692 * If there's a BPF listener, bounce a copy of this frame 1693 * to him. 1694 */ 1695 ETHER_BPF_MTAP(ifp, m_head); 1696 } 1697 1698 if (enq) { 1699 /* Kick. */ 1700 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1701 sc->ale_cdata.ale_tx_prod); 1702 1703 /* Set a timeout in case the chip goes out to lunch. */ 1704 ifp->if_timer = ALE_TX_TIMEOUT; 1705 } 1706 } 1707 1708 static void 1709 ale_watchdog(struct ifnet *ifp) 1710 { 1711 struct ale_softc *sc = ifp->if_softc; 1712 1713 ASSERT_SERIALIZED(ifp->if_serializer); 1714 1715 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1716 if_printf(ifp, "watchdog timeout (lost link)\n"); 1717 ifp->if_oerrors++; 1718 ale_init(sc); 1719 return; 1720 } 1721 1722 if_printf(ifp, "watchdog timeout -- resetting\n"); 1723 ifp->if_oerrors++; 1724 ale_init(sc); 1725 1726 if (!ifq_is_empty(&ifp->if_snd)) 1727 if_devstart(ifp); 1728 } 1729 1730 static int 1731 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1732 { 1733 struct ale_softc *sc; 1734 struct ifreq *ifr; 1735 struct mii_data *mii; 1736 int error, mask; 1737 1738 ASSERT_SERIALIZED(ifp->if_serializer); 1739 1740 sc = ifp->if_softc; 1741 ifr = (struct ifreq *)data; 1742 error = 0; 1743 1744 switch (cmd) { 1745 case SIOCSIFMTU: 1746 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1747 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1748 ifr->ifr_mtu > ETHERMTU)) 1749 error = EINVAL; 1750 else if (ifp->if_mtu != ifr->ifr_mtu) { 1751 ifp->if_mtu = ifr->ifr_mtu; 1752 if ((ifp->if_flags & IFF_RUNNING) != 0) 1753 ale_init(sc); 1754 } 1755 break; 1756 1757 case SIOCSIFFLAGS: 1758 if ((ifp->if_flags & IFF_UP) != 0) { 1759 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1760 if (((ifp->if_flags ^ sc->ale_if_flags) 1761 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1762 ale_rxfilter(sc); 1763 } else { 1764 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1765 ale_init(sc); 1766 } 1767 } else { 1768 if ((ifp->if_flags & IFF_RUNNING) != 0) 1769 ale_stop(sc); 1770 } 1771 sc->ale_if_flags = ifp->if_flags; 1772 break; 1773 1774 case SIOCADDMULTI: 1775 case SIOCDELMULTI: 1776 if ((ifp->if_flags & IFF_RUNNING) != 0) 1777 ale_rxfilter(sc); 1778 break; 1779 1780 case SIOCSIFMEDIA: 1781 case SIOCGIFMEDIA: 1782 mii = device_get_softc(sc->ale_miibus); 1783 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1784 break; 1785 1786 case SIOCSIFCAP: 1787 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1788 if ((mask & IFCAP_TXCSUM) != 0 && 1789 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1790 ifp->if_capenable ^= IFCAP_TXCSUM; 1791 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1792 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1793 else 1794 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1795 } 1796 if ((mask & IFCAP_RXCSUM) != 0 && 1797 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1798 ifp->if_capenable ^= IFCAP_RXCSUM; 1799 1800 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1801 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1802 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1803 ale_rxvlan(sc); 1804 } 1805 break; 1806 1807 default: 1808 error = ether_ioctl(ifp, cmd, data); 1809 break; 1810 } 1811 return (error); 1812 } 1813 1814 static void 1815 ale_mac_config(struct ale_softc *sc) 1816 { 1817 struct mii_data *mii; 1818 uint32_t reg; 1819 1820 mii = device_get_softc(sc->ale_miibus); 1821 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1822 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1823 MAC_CFG_SPEED_MASK); 1824 /* Reprogram MAC with resolved speed/duplex. */ 1825 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1826 case IFM_10_T: 1827 case IFM_100_TX: 1828 reg |= MAC_CFG_SPEED_10_100; 1829 break; 1830 case IFM_1000_T: 1831 reg |= MAC_CFG_SPEED_1000; 1832 break; 1833 } 1834 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1835 reg |= MAC_CFG_FULL_DUPLEX; 1836 #ifdef notyet 1837 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1838 reg |= MAC_CFG_TX_FC; 1839 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1840 reg |= MAC_CFG_RX_FC; 1841 #endif 1842 } 1843 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1844 } 1845 1846 static void 1847 ale_stats_clear(struct ale_softc *sc) 1848 { 1849 struct smb sb; 1850 uint32_t *reg; 1851 int i; 1852 1853 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1854 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1855 i += sizeof(uint32_t); 1856 } 1857 /* Read Tx statistics. */ 1858 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1859 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1860 i += sizeof(uint32_t); 1861 } 1862 } 1863 1864 static void 1865 ale_stats_update(struct ale_softc *sc) 1866 { 1867 struct ale_hw_stats *stat; 1868 struct smb sb, *smb; 1869 struct ifnet *ifp; 1870 uint32_t *reg; 1871 int i; 1872 1873 ifp = &sc->arpcom.ac_if; 1874 stat = &sc->ale_stats; 1875 smb = &sb; 1876 1877 /* Read Rx statistics. */ 1878 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1879 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1880 i += sizeof(uint32_t); 1881 } 1882 /* Read Tx statistics. */ 1883 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1884 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1885 i += sizeof(uint32_t); 1886 } 1887 1888 /* Rx stats. */ 1889 stat->rx_frames += smb->rx_frames; 1890 stat->rx_bcast_frames += smb->rx_bcast_frames; 1891 stat->rx_mcast_frames += smb->rx_mcast_frames; 1892 stat->rx_pause_frames += smb->rx_pause_frames; 1893 stat->rx_control_frames += smb->rx_control_frames; 1894 stat->rx_crcerrs += smb->rx_crcerrs; 1895 stat->rx_lenerrs += smb->rx_lenerrs; 1896 stat->rx_bytes += smb->rx_bytes; 1897 stat->rx_runts += smb->rx_runts; 1898 stat->rx_fragments += smb->rx_fragments; 1899 stat->rx_pkts_64 += smb->rx_pkts_64; 1900 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1901 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1902 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1903 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1904 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1905 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1906 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1907 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1908 stat->rx_rrs_errs += smb->rx_rrs_errs; 1909 stat->rx_alignerrs += smb->rx_alignerrs; 1910 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1911 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1912 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1913 1914 /* Tx stats. */ 1915 stat->tx_frames += smb->tx_frames; 1916 stat->tx_bcast_frames += smb->tx_bcast_frames; 1917 stat->tx_mcast_frames += smb->tx_mcast_frames; 1918 stat->tx_pause_frames += smb->tx_pause_frames; 1919 stat->tx_excess_defer += smb->tx_excess_defer; 1920 stat->tx_control_frames += smb->tx_control_frames; 1921 stat->tx_deferred += smb->tx_deferred; 1922 stat->tx_bytes += smb->tx_bytes; 1923 stat->tx_pkts_64 += smb->tx_pkts_64; 1924 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1925 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1926 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1927 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1928 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1929 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1930 stat->tx_single_colls += smb->tx_single_colls; 1931 stat->tx_multi_colls += smb->tx_multi_colls; 1932 stat->tx_late_colls += smb->tx_late_colls; 1933 stat->tx_excess_colls += smb->tx_excess_colls; 1934 stat->tx_abort += smb->tx_abort; 1935 stat->tx_underrun += smb->tx_underrun; 1936 stat->tx_desc_underrun += smb->tx_desc_underrun; 1937 stat->tx_lenerrs += smb->tx_lenerrs; 1938 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1939 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1940 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1941 1942 /* Update counters in ifnet. */ 1943 ifp->if_opackets += smb->tx_frames; 1944 1945 ifp->if_collisions += smb->tx_single_colls + 1946 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1947 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 1948 1949 /* 1950 * XXX 1951 * tx_pkts_truncated counter looks suspicious. It constantly 1952 * increments with no sign of Tx errors. This may indicate 1953 * the counter name is not correct one so I've removed the 1954 * counter in output errors. 1955 */ 1956 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 1957 smb->tx_underrun; 1958 1959 ifp->if_ipackets += smb->rx_frames; 1960 1961 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 1962 smb->rx_runts + smb->rx_pkts_truncated + 1963 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1964 smb->rx_alignerrs; 1965 } 1966 1967 static void 1968 ale_intr(void *xsc) 1969 { 1970 struct ale_softc *sc = xsc; 1971 struct ifnet *ifp = &sc->arpcom.ac_if; 1972 uint32_t status; 1973 1974 ASSERT_SERIALIZED(ifp->if_serializer); 1975 1976 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1977 if ((status & ALE_INTRS) == 0) 1978 return; 1979 1980 /* Acknowledge and disable interrupts. */ 1981 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1982 1983 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1984 int error; 1985 1986 error = ale_rxeof(sc); 1987 if (error) { 1988 sc->ale_stats.reset_brk_seq++; 1989 ale_init(sc); 1990 return; 1991 } 1992 1993 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 1994 if ((status & INTR_DMA_RD_TO_RST) != 0) 1995 device_printf(sc->ale_dev, 1996 "DMA read error! -- resetting\n"); 1997 if ((status & INTR_DMA_WR_TO_RST) != 0) 1998 device_printf(sc->ale_dev, 1999 "DMA write error! -- resetting\n"); 2000 ale_init(sc); 2001 return; 2002 } 2003 2004 ale_txeof(sc); 2005 if (!ifq_is_empty(&ifp->if_snd)) 2006 if_devstart(ifp); 2007 } 2008 2009 /* Re-enable interrupts. */ 2010 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2011 } 2012 2013 static void 2014 ale_txeof(struct ale_softc *sc) 2015 { 2016 struct ifnet *ifp = &sc->arpcom.ac_if; 2017 struct ale_txdesc *txd; 2018 uint32_t cons, prod; 2019 int prog; 2020 2021 if (sc->ale_cdata.ale_tx_cnt == 0) 2022 return; 2023 2024 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2025 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD); 2026 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2027 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2028 sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD); 2029 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2030 } else 2031 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2032 cons = sc->ale_cdata.ale_tx_cons; 2033 /* 2034 * Go through our Tx list and free mbufs for those 2035 * frames which have been transmitted. 2036 */ 2037 for (prog = 0; cons != prod; prog++, 2038 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2039 if (sc->ale_cdata.ale_tx_cnt <= 0) 2040 break; 2041 prog++; 2042 ifp->if_flags &= ~IFF_OACTIVE; 2043 sc->ale_cdata.ale_tx_cnt--; 2044 txd = &sc->ale_cdata.ale_txdesc[cons]; 2045 if (txd->tx_m != NULL) { 2046 /* Reclaim transmitted mbufs. */ 2047 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2048 txd->tx_dmamap); 2049 m_freem(txd->tx_m); 2050 txd->tx_m = NULL; 2051 } 2052 } 2053 2054 if (prog > 0) { 2055 sc->ale_cdata.ale_tx_cons = cons; 2056 /* 2057 * Unarm watchdog timer only when there is no pending 2058 * Tx descriptors in queue. 2059 */ 2060 if (sc->ale_cdata.ale_tx_cnt == 0) 2061 ifp->if_timer = 0; 2062 } 2063 } 2064 2065 static void 2066 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2067 uint32_t length, uint32_t *prod) 2068 { 2069 struct ale_rx_page *rx_page; 2070 2071 rx_page = *page; 2072 /* Update consumer position. */ 2073 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2074 ALE_RX_PAGE_ALIGN); 2075 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2076 /* 2077 * End of Rx page reached, let hardware reuse 2078 * this page. 2079 */ 2080 rx_page->cons = 0; 2081 *rx_page->cmb_addr = 0; 2082 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2083 BUS_DMASYNC_PREWRITE); 2084 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2085 RXF_VALID); 2086 /* Switch to alternate Rx page. */ 2087 sc->ale_cdata.ale_rx_curp ^= 1; 2088 rx_page = *page = 2089 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2090 /* Page flipped, sync CMB and Rx page. */ 2091 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2092 BUS_DMASYNC_POSTREAD); 2093 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2094 BUS_DMASYNC_POSTREAD); 2095 /* Sync completed, cache updated producer index. */ 2096 *prod = *rx_page->cmb_addr; 2097 } 2098 } 2099 2100 2101 /* 2102 * It seems that AR81xx controller can compute partial checksum. 2103 * The partial checksum value can be used to accelerate checksum 2104 * computation for fragmented TCP/UDP packets. Upper network stack 2105 * already takes advantage of the partial checksum value in IP 2106 * reassembly stage. But I'm not sure the correctness of the 2107 * partial hardware checksum assistance due to lack of data sheet. 2108 * In addition, the Rx feature of controller that requires copying 2109 * for every frames effectively nullifies one of most nice offload 2110 * capability of controller. 2111 */ 2112 static void 2113 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2114 { 2115 struct ifnet *ifp = &sc->arpcom.ac_if; 2116 struct ip *ip; 2117 char *p; 2118 2119 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2120 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2121 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2122 2123 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2124 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2125 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2126 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2127 m->m_pkthdr.csum_flags |= 2128 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2129 m->m_pkthdr.csum_data = 0xffff; 2130 } 2131 } else { 2132 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2133 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2134 p = mtod(m, char *); 2135 p += ETHER_HDR_LEN; 2136 if ((status & ALE_RD_802_3) != 0) 2137 p += LLC_SNAPFRAMELEN; 2138 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2139 (status & ALE_RD_VLAN) != 0) 2140 p += EVL_ENCAPLEN; 2141 ip = (struct ip *)p; 2142 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2143 return; 2144 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2145 CSUM_PSEUDO_HDR; 2146 m->m_pkthdr.csum_data = 0xffff; 2147 } 2148 } 2149 /* 2150 * Don't mark bad checksum for TCP/UDP frames 2151 * as fragmented frames may always have set 2152 * bad checksummed bit of frame status. 2153 */ 2154 } 2155 2156 /* Process received frames. */ 2157 static int 2158 ale_rxeof(struct ale_softc *sc) 2159 { 2160 struct ifnet *ifp = &sc->arpcom.ac_if; 2161 struct ale_rx_page *rx_page; 2162 struct rx_rs *rs; 2163 struct mbuf *m; 2164 uint32_t length, prod, seqno, status, vtags; 2165 int prog; 2166 2167 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2168 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2169 BUS_DMASYNC_POSTREAD); 2170 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2171 BUS_DMASYNC_POSTREAD); 2172 /* 2173 * Don't directly access producer index as hardware may 2174 * update it while Rx handler is in progress. It would 2175 * be even better if there is a way to let hardware 2176 * know how far driver processed its received frames. 2177 * Alternatively, hardware could provide a way to disable 2178 * CMB updates until driver acknowledges the end of CMB 2179 * access. 2180 */ 2181 prod = *rx_page->cmb_addr; 2182 for (prog = 0; ; prog++) { 2183 if (rx_page->cons >= prod) 2184 break; 2185 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2186 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2187 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2188 /* 2189 * Normally I believe this should not happen unless 2190 * severe driver bug or corrupted memory. However 2191 * it seems to happen under certain conditions which 2192 * is triggered by abrupt Rx events such as initiation 2193 * of bulk transfer of remote host. It's not easy to 2194 * reproduce this and I doubt it could be related 2195 * with FIFO overflow of hardware or activity of Tx 2196 * CMB updates. I also remember similar behaviour 2197 * seen on RealTek 8139 which uses resembling Rx 2198 * scheme. 2199 */ 2200 if (bootverbose) 2201 device_printf(sc->ale_dev, 2202 "garbled seq: %u, expected: %u -- " 2203 "resetting!\n", seqno, 2204 sc->ale_cdata.ale_rx_seqno); 2205 return (EIO); 2206 } 2207 /* Frame received. */ 2208 sc->ale_cdata.ale_rx_seqno++; 2209 length = ALE_RX_BYTES(le32toh(rs->length)); 2210 status = le32toh(rs->flags); 2211 if ((status & ALE_RD_ERROR) != 0) { 2212 /* 2213 * We want to pass the following frames to upper 2214 * layer regardless of error status of Rx return 2215 * status. 2216 * 2217 * o IP/TCP/UDP checksum is bad. 2218 * o frame length and protocol specific length 2219 * does not match. 2220 */ 2221 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2222 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2223 ALE_RD_TRUNC)) != 0) { 2224 ale_rx_update_page(sc, &rx_page, length, &prod); 2225 continue; 2226 } 2227 } 2228 /* 2229 * m_devget(9) is major bottle-neck of ale(4)(It comes 2230 * from hardware limitation). For jumbo frames we could 2231 * get a slightly better performance if driver use 2232 * m_getjcl(9) with proper buffer size argument. However 2233 * that would make code more complicated and I don't 2234 * think users would expect good Rx performance numbers 2235 * on these low-end consumer ethernet controller. 2236 */ 2237 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2238 ETHER_ALIGN, ifp, NULL); 2239 if (m == NULL) { 2240 ifp->if_iqdrops++; 2241 ale_rx_update_page(sc, &rx_page, length, &prod); 2242 continue; 2243 } 2244 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2245 (status & ALE_RD_IPV4) != 0) 2246 ale_rxcsum(sc, m, status); 2247 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2248 (status & ALE_RD_VLAN) != 0) { 2249 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2250 m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags); 2251 m->m_flags |= M_VLANTAG; 2252 } 2253 2254 /* Pass it to upper layer. */ 2255 ifp->if_input(ifp, m); 2256 2257 ale_rx_update_page(sc, &rx_page, length, &prod); 2258 } 2259 return 0; 2260 } 2261 2262 static void 2263 ale_tick(void *xsc) 2264 { 2265 struct ale_softc *sc = xsc; 2266 struct ifnet *ifp = &sc->arpcom.ac_if; 2267 struct mii_data *mii; 2268 2269 lwkt_serialize_enter(ifp->if_serializer); 2270 2271 mii = device_get_softc(sc->ale_miibus); 2272 mii_tick(mii); 2273 ale_stats_update(sc); 2274 2275 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2276 2277 lwkt_serialize_exit(ifp->if_serializer); 2278 } 2279 2280 static void 2281 ale_reset(struct ale_softc *sc) 2282 { 2283 uint32_t reg; 2284 int i; 2285 2286 /* Initialize PCIe module. From Linux. */ 2287 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2288 2289 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2290 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2291 DELAY(10); 2292 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2293 break; 2294 } 2295 if (i == 0) 2296 device_printf(sc->ale_dev, "master reset timeout!\n"); 2297 2298 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2299 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2300 break; 2301 DELAY(10); 2302 } 2303 2304 if (i == 0) 2305 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2306 } 2307 2308 static void 2309 ale_init(void *xsc) 2310 { 2311 struct ale_softc *sc = xsc; 2312 struct ifnet *ifp = &sc->arpcom.ac_if; 2313 struct mii_data *mii; 2314 uint8_t eaddr[ETHER_ADDR_LEN]; 2315 bus_addr_t paddr; 2316 uint32_t reg, rxf_hi, rxf_lo; 2317 2318 ASSERT_SERIALIZED(ifp->if_serializer); 2319 2320 mii = device_get_softc(sc->ale_miibus); 2321 2322 /* 2323 * Cancel any pending I/O. 2324 */ 2325 ale_stop(sc); 2326 2327 /* 2328 * Reset the chip to a known state. 2329 */ 2330 ale_reset(sc); 2331 2332 /* Initialize Tx descriptors, DMA memory blocks. */ 2333 ale_init_rx_pages(sc); 2334 ale_init_tx_ring(sc); 2335 2336 /* Reprogram the station address. */ 2337 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2338 CSR_WRITE_4(sc, ALE_PAR0, 2339 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2340 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2341 2342 /* 2343 * Clear WOL status and disable all WOL feature as WOL 2344 * would interfere Rx operation under normal environments. 2345 */ 2346 CSR_READ_4(sc, ALE_WOL_CFG); 2347 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2348 2349 /* 2350 * Set Tx descriptor/RXF0/CMB base addresses. They share 2351 * the same high address part of DMAable region. 2352 */ 2353 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2354 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2355 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2356 CSR_WRITE_4(sc, ALE_TPD_CNT, 2357 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2358 2359 /* Set Rx page base address, note we use single queue. */ 2360 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2361 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2362 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2363 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2364 2365 /* Set Tx/Rx CMB addresses. */ 2366 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2367 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2368 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2369 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2370 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2371 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2372 2373 /* Mark RXF0 is valid. */ 2374 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2375 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2376 /* 2377 * No need to initialize RFX1/RXF2/RXF3. We don't use 2378 * multi-queue yet. 2379 */ 2380 2381 /* Set Rx page size, excluding guard frame size. */ 2382 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2383 2384 /* Tell hardware that we're ready to load DMA blocks. */ 2385 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2386 2387 /* Set Rx/Tx interrupt trigger threshold. */ 2388 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2389 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2390 /* 2391 * XXX 2392 * Set interrupt trigger timer, its purpose and relation 2393 * with interrupt moderation mechanism is not clear yet. 2394 */ 2395 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2396 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2397 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2398 2399 /* Configure interrupt moderation timer. */ 2400 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2401 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2402 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2403 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2404 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2405 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2406 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2407 reg |= MASTER_IM_RX_TIMER_ENB; 2408 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2409 reg |= MASTER_IM_TX_TIMER_ENB; 2410 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2411 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2412 2413 /* Set Maximum frame size of controller. */ 2414 if (ifp->if_mtu < ETHERMTU) 2415 sc->ale_max_frame_size = ETHERMTU; 2416 else 2417 sc->ale_max_frame_size = ifp->if_mtu; 2418 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 2419 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2420 2421 /* Configure IPG/IFG parameters. */ 2422 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2423 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2424 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2425 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2426 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2427 2428 /* Set parameters for half-duplex media. */ 2429 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2430 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2431 HDPX_CFG_LCOL_MASK) | 2432 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2433 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2434 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2435 HDPX_CFG_ABEBT_MASK) | 2436 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2437 HDPX_CFG_JAMIPG_MASK)); 2438 2439 /* Configure Tx jumbo frame parameters. */ 2440 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2441 if (ifp->if_mtu < ETHERMTU) 2442 reg = sc->ale_max_frame_size; 2443 else if (ifp->if_mtu < 6 * 1024) 2444 reg = (sc->ale_max_frame_size * 2) / 3; 2445 else 2446 reg = sc->ale_max_frame_size / 2; 2447 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2448 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2449 TX_JUMBO_THRESH_UNIT_SHIFT); 2450 } 2451 2452 /* Configure TxQ. */ 2453 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2454 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2455 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2456 TXQ_CFG_TPD_BURST_MASK; 2457 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2458 2459 /* Configure Rx jumbo frame & flow control parameters. */ 2460 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2461 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2462 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2463 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2464 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2465 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2466 RX_JUMBO_LKAH_MASK)); 2467 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2468 rxf_hi = (reg * 7) / 10; 2469 rxf_lo = (reg * 3)/ 10; 2470 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2471 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2472 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2473 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2474 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2475 } 2476 2477 /* Disable RSS. */ 2478 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2479 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2480 2481 /* Configure RxQ. */ 2482 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2483 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2484 2485 /* Configure DMA parameters. */ 2486 reg = 0; 2487 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2488 reg |= DMA_CFG_TXCMB_ENB; 2489 CSR_WRITE_4(sc, ALE_DMA_CFG, 2490 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2491 sc->ale_dma_rd_burst | reg | 2492 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2493 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2494 DMA_CFG_RD_DELAY_CNT_MASK) | 2495 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2496 DMA_CFG_WR_DELAY_CNT_MASK)); 2497 2498 /* 2499 * Hardware can be configured to issue SMB interrupt based 2500 * on programmed interval. Since there is a callout that is 2501 * invoked for every hz in driver we use that instead of 2502 * relying on periodic SMB interrupt. 2503 */ 2504 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2505 2506 /* Clear MAC statistics. */ 2507 ale_stats_clear(sc); 2508 2509 /* 2510 * Configure Tx/Rx MACs. 2511 * - Auto-padding for short frames. 2512 * - Enable CRC generation. 2513 * Actual reconfiguration of MAC for resolved speed/duplex 2514 * is followed after detection of link establishment. 2515 * AR81xx always does checksum computation regardless of 2516 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2517 * cause Rx handling issue for fragmented IP datagrams due 2518 * to silicon bug. 2519 */ 2520 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2521 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2522 MAC_CFG_PREAMBLE_MASK); 2523 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2524 reg |= MAC_CFG_SPEED_10_100; 2525 else 2526 reg |= MAC_CFG_SPEED_1000; 2527 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2528 2529 /* Set up the receive filter. */ 2530 ale_rxfilter(sc); 2531 ale_rxvlan(sc); 2532 2533 /* Acknowledge all pending interrupts and clear it. */ 2534 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2535 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2536 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2537 2538 sc->ale_flags &= ~ALE_FLAG_LINK; 2539 2540 /* Switch to the current media. */ 2541 mii_mediachg(mii); 2542 2543 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2544 2545 ifp->if_flags |= IFF_RUNNING; 2546 ifp->if_flags &= ~IFF_OACTIVE; 2547 } 2548 2549 static void 2550 ale_stop(struct ale_softc *sc) 2551 { 2552 struct ifnet *ifp = &sc->arpcom.ac_if; 2553 struct ale_txdesc *txd; 2554 uint32_t reg; 2555 int i; 2556 2557 ASSERT_SERIALIZED(ifp->if_serializer); 2558 2559 /* 2560 * Mark the interface down and cancel the watchdog timer. 2561 */ 2562 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2563 ifp->if_timer = 0; 2564 2565 callout_stop(&sc->ale_tick_ch); 2566 sc->ale_flags &= ~ALE_FLAG_LINK; 2567 2568 ale_stats_update(sc); 2569 2570 /* Disable interrupts. */ 2571 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2572 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2573 2574 /* Disable queue processing and DMA. */ 2575 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2576 reg &= ~TXQ_CFG_ENB; 2577 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2578 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2579 reg &= ~RXQ_CFG_ENB; 2580 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2581 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2582 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2583 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2584 DELAY(1000); 2585 2586 /* Stop Rx/Tx MACs. */ 2587 ale_stop_mac(sc); 2588 2589 /* Disable interrupts again? XXX */ 2590 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2591 2592 /* 2593 * Free TX mbufs still in the queues. 2594 */ 2595 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2596 txd = &sc->ale_cdata.ale_txdesc[i]; 2597 if (txd->tx_m != NULL) { 2598 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2599 txd->tx_dmamap); 2600 m_freem(txd->tx_m); 2601 txd->tx_m = NULL; 2602 } 2603 } 2604 } 2605 2606 static void 2607 ale_stop_mac(struct ale_softc *sc) 2608 { 2609 uint32_t reg; 2610 int i; 2611 2612 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2613 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2614 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2615 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2616 } 2617 2618 for (i = ALE_TIMEOUT; i > 0; i--) { 2619 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2620 if (reg == 0) 2621 break; 2622 DELAY(10); 2623 } 2624 if (i == 0) 2625 device_printf(sc->ale_dev, 2626 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2627 } 2628 2629 static void 2630 ale_init_tx_ring(struct ale_softc *sc) 2631 { 2632 struct ale_txdesc *txd; 2633 int i; 2634 2635 sc->ale_cdata.ale_tx_prod = 0; 2636 sc->ale_cdata.ale_tx_cons = 0; 2637 sc->ale_cdata.ale_tx_cnt = 0; 2638 2639 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2640 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2641 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2642 txd = &sc->ale_cdata.ale_txdesc[i]; 2643 txd->tx_m = NULL; 2644 } 2645 *sc->ale_cdata.ale_tx_cmb = 0; 2646 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2647 sc->ale_cdata.ale_tx_cmb_map, 2648 BUS_DMASYNC_PREWRITE); 2649 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2650 sc->ale_cdata.ale_tx_ring_map, 2651 BUS_DMASYNC_PREWRITE); 2652 } 2653 2654 static void 2655 ale_init_rx_pages(struct ale_softc *sc) 2656 { 2657 struct ale_rx_page *rx_page; 2658 int i; 2659 2660 sc->ale_cdata.ale_rx_seqno = 0; 2661 sc->ale_cdata.ale_rx_curp = 0; 2662 2663 for (i = 0; i < ALE_RX_PAGES; i++) { 2664 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2665 bzero(rx_page->page_addr, sc->ale_pagesize); 2666 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2667 rx_page->cons = 0; 2668 *rx_page->cmb_addr = 0; 2669 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2670 BUS_DMASYNC_PREWRITE); 2671 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2672 BUS_DMASYNC_PREWRITE); 2673 } 2674 } 2675 2676 static void 2677 ale_rxvlan(struct ale_softc *sc) 2678 { 2679 struct ifnet *ifp; 2680 uint32_t reg; 2681 2682 ifp = &sc->arpcom.ac_if; 2683 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2684 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2685 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2686 reg |= MAC_CFG_VLAN_TAG_STRIP; 2687 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2688 } 2689 2690 static void 2691 ale_rxfilter(struct ale_softc *sc) 2692 { 2693 struct ifnet *ifp; 2694 struct ifmultiaddr *ifma; 2695 uint32_t crc; 2696 uint32_t mchash[2]; 2697 uint32_t rxcfg; 2698 2699 ifp = &sc->arpcom.ac_if; 2700 2701 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2702 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2703 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2704 rxcfg |= MAC_CFG_BCAST; 2705 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2706 if ((ifp->if_flags & IFF_PROMISC) != 0) 2707 rxcfg |= MAC_CFG_PROMISC; 2708 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2709 rxcfg |= MAC_CFG_ALLMULTI; 2710 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 2711 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 2712 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2713 return; 2714 } 2715 2716 /* Program new filter. */ 2717 bzero(mchash, sizeof(mchash)); 2718 2719 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2720 if (ifma->ifma_addr->sa_family != AF_LINK) 2721 continue; 2722 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2723 ifma->ifma_addr), ETHER_ADDR_LEN); 2724 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2725 } 2726 2727 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2728 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2729 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2730 } 2731 2732 static int 2733 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 2734 { 2735 return (sysctl_int_range(oidp, arg1, arg2, req, 2736 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 2737 } 2738 2739 static void 2740 ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs, 2741 bus_size_t mapsz __unused, int error) 2742 { 2743 struct ale_dmamap_ctx *ctx = xctx; 2744 int i; 2745 2746 if (error) 2747 return; 2748 2749 if (nsegs > ctx->nsegs) { 2750 ctx->nsegs = 0; 2751 return; 2752 } 2753 2754 ctx->nsegs = nsegs; 2755 for (i = 0; i < nsegs; ++i) 2756 ctx->segs[i] = segs[i]; 2757 } 2758