1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_ath.c 203751 2010-02-10 11:12:39Z rpaulo $"); 30 */ 31 32 /* 33 * Driver for the Atheros Wireless LAN controller. 34 * 35 * This software is derived from work of Atsushi Onoe; his contribution 36 * is greatly appreciated. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ath.h" 41 #include "opt_wlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sysctl.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/errno.h> 54 #include <sys/callout.h> 55 #include <sys/bus.h> 56 #include <sys/endian.h> 57 #include <sys/kthread.h> 58 #include <sys/taskqueue.h> 59 #include <sys/priv.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_arp.h> 66 #include <net/if_llc.h> 67 #include <net/ifq_var.h> 68 69 #include <netproto/802_11/ieee80211_var.h> 70 #include <netproto/802_11/ieee80211_regdomain.h> 71 #ifdef IEEE80211_SUPPORT_SUPERG 72 #include <netproto/802_11/ieee80211_superg.h> 73 #endif 74 #ifdef IEEE80211_SUPPORT_TDMA 75 #include <netproto/802_11/ieee80211_tdma.h> 76 #endif 77 78 #include <net/bpf.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/if_ether.h> 83 #endif 84 85 #include <dev/netif/ath/ath/if_athvar.h> 86 #include <dev/netif/ath/hal/ath_hal/ah_devid.h> /* XXX for softled */ 87 88 #ifdef ATH_TX99_DIAG 89 #include <dev/netif/ath_tx99/ath_tx99.h> 90 #endif 91 92 /* 93 * ATH_BCBUF determines the number of vap's that can transmit 94 * beacons and also (currently) the number of vap's that can 95 * have unique mac addresses/bssid. When staggering beacons 96 * 4 is probably a good max as otherwise the beacons become 97 * very closely spaced and there is limited time for cab q traffic 98 * to go out. You can burst beacons instead but that is not good 99 * for stations in power save and at some point you really want 100 * another radio (and channel). 101 * 102 * The limit on the number of mac addresses is tied to our use of 103 * the U/L bit and tracking addresses in a byte; it would be 104 * worthwhile to allow more for applications like proxy sta. 105 */ 106 CTASSERT(ATH_BCBUF <= 8); 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 118 const char name[IFNAMSIZ], int unit, int opmode, 119 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 120 const uint8_t mac[IEEE80211_ADDR_LEN]); 121 static void ath_vap_delete(struct ieee80211vap *); 122 static void ath_init(void *); 123 static void ath_stop_locked(struct ifnet *); 124 static void ath_stop(struct ifnet *); 125 static void ath_start(struct ifnet *); 126 static int ath_reset(struct ifnet *); 127 static int ath_reset_vap(struct ieee80211vap *, u_long); 128 static int ath_media_change(struct ifnet *); 129 static void ath_watchdog_callout(void *); 130 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 131 static void ath_fatal_proc(void *, int); 132 static void ath_bmiss_vap(struct ieee80211vap *); 133 static void ath_bmiss_task(void *, int); 134 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 135 struct ieee80211_node *); 136 static int ath_key_alloc(struct ieee80211vap *, 137 struct ieee80211_key *, 138 ieee80211_keyix *, ieee80211_keyix *); 139 static int ath_key_delete(struct ieee80211vap *, 140 const struct ieee80211_key *); 141 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 142 const u_int8_t mac[IEEE80211_ADDR_LEN]); 143 static void ath_key_update_begin(struct ieee80211vap *); 144 static void ath_key_update_end(struct ieee80211vap *); 145 static void ath_update_mcast(struct ifnet *); 146 static void ath_update_promisc(struct ifnet *); 147 static void ath_mode_init(struct ath_softc *); 148 static void ath_setslottime(struct ath_softc *); 149 static void ath_updateslot(struct ifnet *); 150 static int ath_beaconq_setup(struct ath_hal *); 151 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 152 static void ath_beacon_update(struct ieee80211vap *, int item); 153 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 154 static void ath_beacon_proc(void *, int); 155 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 156 struct ieee80211vap *); 157 static void ath_bstuck_task(void *, int); 158 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 159 static void ath_beacon_free(struct ath_softc *); 160 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 161 static void ath_descdma_cleanup(struct ath_softc *sc, 162 struct ath_descdma *, ath_bufhead *); 163 static int ath_desc_alloc(struct ath_softc *); 164 static void ath_desc_free(struct ath_softc *); 165 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 166 const uint8_t [IEEE80211_ADDR_LEN]); 167 static void ath_node_free(struct ieee80211_node *); 168 static void ath_node_getsignal(const struct ieee80211_node *, 169 int8_t *, int8_t *); 170 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 171 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 172 int subtype, int rssi, int nf); 173 static void ath_setdefantenna(struct ath_softc *, u_int); 174 static void ath_rx_task(void *, int); 175 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 176 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 177 static int ath_tx_setup(struct ath_softc *, int, int); 178 static int ath_wme_update(struct ieee80211com *); 179 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 180 static void ath_tx_cleanup(struct ath_softc *); 181 static void ath_freetx(struct mbuf *); 182 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 183 struct ath_buf *, struct mbuf *); 184 static void ath_tx_task_q0(void *, int); 185 static void ath_tx_task_q0123(void *, int); 186 static void ath_tx_task(void *, int); 187 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 188 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 189 static void ath_draintxq(struct ath_softc *); 190 static void ath_stoprecv(struct ath_softc *); 191 static int ath_startrecv(struct ath_softc *); 192 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 193 static void ath_scan_start(struct ieee80211com *); 194 static void ath_scan_end(struct ieee80211com *); 195 static void ath_set_channel(struct ieee80211com *); 196 static void ath_calibrate_callout(void *); 197 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 198 static void ath_setup_stationkey(struct ieee80211_node *); 199 static void ath_newassoc(struct ieee80211_node *, int); 200 static int ath_setregdomain(struct ieee80211com *, 201 struct ieee80211_regdomain *, int, 202 struct ieee80211_channel []); 203 static void ath_getradiocaps(struct ieee80211com *, int, int *, 204 struct ieee80211_channel []); 205 static int ath_getchannels(struct ath_softc *); 206 static void ath_led_event(struct ath_softc *, int); 207 208 static int ath_rate_setup(struct ath_softc *, u_int mode); 209 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 210 211 static void ath_sysctlattach(struct ath_softc *); 212 static int ath_raw_xmit(struct ieee80211_node *, 213 struct mbuf *, const struct ieee80211_bpf_params *); 214 static void ath_announce(struct ath_softc *); 215 static void ath_sysctl_stats_attach(struct ath_softc *sc); 216 217 #ifdef IEEE80211_SUPPORT_TDMA 218 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 219 u_int32_t bintval); 220 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 221 const struct ieee80211_tdma_state *tdma); 222 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 223 static void ath_tdma_update(struct ieee80211_node *ni, 224 const struct ieee80211_tdma_param *tdma, int); 225 static void ath_tdma_beacon_send(struct ath_softc *sc, 226 struct ieee80211vap *vap); 227 228 static __inline void 229 ath_hal_setcca(struct ath_hal *ah, int ena) 230 { 231 /* 232 * NB: fill me in; this is not provided by default because disabling 233 * CCA in most locales violates regulatory. 234 */ 235 } 236 237 static __inline int 238 ath_hal_getcca(struct ath_hal *ah) 239 { 240 u_int32_t diag; 241 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 242 return 1; 243 return ((diag & 0x500000) == 0); 244 } 245 246 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 247 #define TDMA_LPF_LEN 6 248 #define TDMA_DUMMY_MARKER 0x127 249 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 250 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 251 #define TDMA_LPF(x, y, len) \ 252 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 253 #define TDMA_SAMPLE(x, y) do { \ 254 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 255 } while (0) 256 #define TDMA_EP_RND(x,mul) \ 257 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 258 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 259 #endif /* IEEE80211_SUPPORT_TDMA */ 260 261 SYSCTL_DECL(_hw_ath); 262 263 /* XXX validate sysctl values */ 264 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 265 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 266 0, "long chip calibration interval (secs)"); 267 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 268 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 269 0, "short chip calibration interval (msecs)"); 270 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 271 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 272 0, "reset chip calibration results (secs)"); 273 274 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 275 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 276 0, "rx buffers allocated"); 277 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 278 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 279 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 280 0, "tx buffers allocated"); 281 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 282 283 static int ath_bstuck_threshold = 4; /* max missed beacons */ 284 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 285 0, "max missed beacon xmits before chip reset"); 286 287 #ifdef ATH_DEBUG 288 enum { 289 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 290 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 291 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 292 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 293 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 294 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 295 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 296 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 297 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 298 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 299 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 300 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 301 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 302 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 303 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 304 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 305 ATH_DEBUG_NODE = 0x00080000, /* node management */ 306 ATH_DEBUG_LED = 0x00100000, /* led management */ 307 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 308 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 309 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */ 310 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */ 311 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 312 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 313 ATH_DEBUG_ANY = 0xffffffff 314 }; 315 static int ath_debug = 0; 316 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 317 0, "control debugging printfs"); 318 TUNABLE_INT("hw.ath.debug", &ath_debug); 319 320 #define IFF_DUMPPKTS(sc, m) \ 321 ((sc->sc_debug & (m)) || \ 322 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 323 #define DPRINTF(sc, m, fmt, ...) do { \ 324 if (sc->sc_debug & (m)) \ 325 kprintf(fmt, __VA_ARGS__); \ 326 } while (0) 327 #define KEYPRINTF(sc, ix, hk, mac) do { \ 328 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 329 ath_keyprint(sc, __func__, ix, hk, mac); \ 330 } while (0) 331 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 332 u_int ix, int); 333 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 334 u_int qnum, u_int ix, int done); 335 #else 336 #define IFF_DUMPPKTS(sc, m) \ 337 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 338 #define DPRINTF(sc, m, fmt, ...) do { \ 339 (void) sc; \ 340 } while (0) 341 #define KEYPRINTF(sc, k, ix, mac) do { \ 342 (void) sc; \ 343 } while (0) 344 #endif 345 346 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 347 348 int 349 ath_attach(u_int16_t devid, struct ath_softc *sc) 350 { 351 struct ifnet *ifp; 352 struct ieee80211com *ic; 353 struct ath_hal *ah = NULL; 354 HAL_STATUS status; 355 int error = 0, i; 356 u_int wmodes; 357 uint8_t macaddr[IEEE80211_ADDR_LEN]; 358 359 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 360 361 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 362 if (ifp == NULL) { 363 device_printf(sc->sc_dev, "can not if_alloc()\n"); 364 error = ENOSPC; 365 goto bad; 366 } 367 ic = ifp->if_l2com; 368 369 /* set these up early for if_printf use */ 370 if_initname(ifp, device_get_name(sc->sc_dev), 371 device_get_unit(sc->sc_dev)); 372 373 /* prepare sysctl tree for use in sub modules */ 374 sysctl_ctx_init(&sc->sc_sysctl_ctx); 375 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 376 SYSCTL_STATIC_CHILDREN(_hw), 377 OID_AUTO, 378 device_get_nameunit(sc->sc_dev), 379 CTLFLAG_RD, 0, ""); 380 381 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 382 if (ah == NULL) { 383 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 384 status); 385 error = ENXIO; 386 goto bad; 387 } 388 sc->sc_ah = ah; 389 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 390 #ifdef ATH_DEBUG 391 sc->sc_debug = ath_debug; 392 #endif 393 394 /* 395 * Check if the MAC has multi-rate retry support. 396 * We do this by trying to setup a fake extended 397 * descriptor. MAC's that don't have support will 398 * return false w/o doing anything. MAC's that do 399 * support it will return true w/o doing anything. 400 */ 401 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 402 403 /* 404 * Check if the device has hardware counters for PHY 405 * errors. If so we need to enable the MIB interrupt 406 * so we can act on stat triggers. 407 */ 408 if (ath_hal_hwphycounters(ah)) 409 sc->sc_needmib = 1; 410 411 /* 412 * Get the hardware key cache size. 413 */ 414 sc->sc_keymax = ath_hal_keycachesize(ah); 415 if (sc->sc_keymax > ATH_KEYMAX) { 416 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 417 ATH_KEYMAX, sc->sc_keymax); 418 sc->sc_keymax = ATH_KEYMAX; 419 } 420 /* 421 * Reset the key cache since some parts do not 422 * reset the contents on initial power up. 423 */ 424 for (i = 0; i < sc->sc_keymax; i++) 425 ath_hal_keyreset(ah, i); 426 427 /* 428 * Collect the default channel list. 429 */ 430 error = ath_getchannels(sc); 431 if (error != 0) 432 goto bad; 433 434 /* 435 * Setup rate tables for all potential media types. 436 */ 437 ath_rate_setup(sc, IEEE80211_MODE_11A); 438 ath_rate_setup(sc, IEEE80211_MODE_11B); 439 ath_rate_setup(sc, IEEE80211_MODE_11G); 440 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 441 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 442 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 443 ath_rate_setup(sc, IEEE80211_MODE_11NA); 444 ath_rate_setup(sc, IEEE80211_MODE_11NG); 445 ath_rate_setup(sc, IEEE80211_MODE_HALF); 446 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 447 448 /* NB: setup here so ath_rate_update is happy */ 449 ath_setcurmode(sc, IEEE80211_MODE_11A); 450 451 /* 452 * Allocate tx+rx descriptors and populate the lists. 453 */ 454 wlan_assert_serialized(); 455 wlan_serialize_exit(); 456 error = ath_desc_alloc(sc); 457 wlan_serialize_enter(); 458 if (error != 0) { 459 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 460 goto bad; 461 } 462 callout_init(&sc->sc_cal_ch); 463 callout_init(&sc->sc_wd_ch); 464 465 sc->sc_tq = taskqueue_create("ath_taskq", M_INTWAIT, 466 taskqueue_thread_enqueue, &sc->sc_tq); 467 taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1, 468 "%s taskq", ifp->if_xname); 469 470 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_task, sc); 471 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_task, sc); 472 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_task, sc); 473 474 /* 475 * Allocate hardware transmit queues: one queue for 476 * beacon frames and one data queue for each QoS 477 * priority. Note that the hal handles reseting 478 * these queues at the needed time. 479 * 480 * XXX PS-Poll 481 */ 482 sc->sc_bhalq = ath_beaconq_setup(ah); 483 if (sc->sc_bhalq == (u_int) -1) { 484 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 485 error = EIO; 486 goto bad2; 487 } 488 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 489 if (sc->sc_cabq == NULL) { 490 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 491 error = EIO; 492 goto bad2; 493 } 494 /* NB: insure BK queue is the lowest priority h/w queue */ 495 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 496 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 497 ieee80211_wme_acnames[WME_AC_BK]); 498 error = EIO; 499 goto bad2; 500 } 501 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 502 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 503 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 504 /* 505 * Not enough hardware tx queues to properly do WME; 506 * just punt and assign them all to the same h/w queue. 507 * We could do a better job of this if, for example, 508 * we allocate queues when we switch from station to 509 * AP mode. 510 */ 511 if (sc->sc_ac2q[WME_AC_VI] != NULL) 512 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 513 if (sc->sc_ac2q[WME_AC_BE] != NULL) 514 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 515 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 516 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 517 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 518 } 519 520 /* 521 * Special case certain configurations. Note the 522 * CAB queue is handled by these specially so don't 523 * include them when checking the txq setup mask. 524 */ 525 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 526 case 0x01: 527 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0, sc); 528 break; 529 case 0x0f: 530 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0123, sc); 531 break; 532 default: 533 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task, sc); 534 break; 535 } 536 537 /* 538 * Setup rate control. Some rate control modules 539 * call back to change the anntena state so expose 540 * the necessary entry points. 541 * XXX maybe belongs in struct ath_ratectrl? 542 */ 543 sc->sc_setdefantenna = ath_setdefantenna; 544 sc->sc_rc = ath_rate_attach(sc); 545 if (sc->sc_rc == NULL) { 546 error = EIO; 547 goto bad2; 548 } 549 550 sc->sc_blinking = 0; 551 sc->sc_ledstate = 1; 552 sc->sc_ledon = 0; /* low true */ 553 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 554 callout_init_mp(&sc->sc_ledtimer); 555 /* 556 * Auto-enable soft led processing for IBM cards and for 557 * 5211 minipci cards. Users can also manually enable/disable 558 * support with a sysctl. 559 */ 560 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 561 if (sc->sc_softled) { 562 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 563 HAL_GPIO_MUX_MAC_NETWORK_LED); 564 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 565 } 566 567 ifp->if_softc = sc; 568 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 569 ifp->if_start = ath_start; 570 ifp->if_ioctl = ath_ioctl; 571 ifp->if_init = ath_init; 572 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 573 ifq_set_ready(&ifp->if_snd); 574 575 ic->ic_ifp = ifp; 576 /* XXX not right but it's not used anywhere important */ 577 ic->ic_phytype = IEEE80211_T_OFDM; 578 ic->ic_opmode = IEEE80211_M_STA; 579 ic->ic_caps = 580 IEEE80211_C_STA /* station mode */ 581 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 582 | IEEE80211_C_HOSTAP /* hostap mode */ 583 | IEEE80211_C_MONITOR /* monitor mode */ 584 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 585 | IEEE80211_C_WDS /* 4-address traffic works */ 586 | IEEE80211_C_MBSS /* mesh point link mode */ 587 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 588 | IEEE80211_C_SHSLOT /* short slot time supported */ 589 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 590 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 591 | IEEE80211_C_TXFRAG /* handle tx frags */ 592 ; 593 /* 594 * Query the hal to figure out h/w crypto support. 595 */ 596 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 597 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 598 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 599 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 600 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 601 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 602 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 603 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 604 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 605 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 606 /* 607 * Check if h/w does the MIC and/or whether the 608 * separate key cache entries are required to 609 * handle both tx+rx MIC keys. 610 */ 611 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 612 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 613 /* 614 * If the h/w supports storing tx+rx MIC keys 615 * in one cache slot automatically enable use. 616 */ 617 if (ath_hal_hastkipsplit(ah) || 618 !ath_hal_settkipsplit(ah, AH_FALSE)) 619 sc->sc_splitmic = 1; 620 /* 621 * If the h/w can do TKIP MIC together with WME then 622 * we use it; otherwise we force the MIC to be done 623 * in software by the net80211 layer. 624 */ 625 if (ath_hal_haswmetkipmic(ah)) 626 sc->sc_wmetkipmic = 1; 627 } 628 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 629 /* 630 * Check for multicast key search support. 631 */ 632 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 633 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 634 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 635 } 636 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 637 /* 638 * Mark key cache slots associated with global keys 639 * as in use. If we knew TKIP was not to be used we 640 * could leave the +32, +64, and +32+64 slots free. 641 */ 642 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 643 setbit(sc->sc_keymap, i); 644 setbit(sc->sc_keymap, i+64); 645 if (sc->sc_splitmic) { 646 setbit(sc->sc_keymap, i+32); 647 setbit(sc->sc_keymap, i+32+64); 648 } 649 } 650 /* 651 * TPC support can be done either with a global cap or 652 * per-packet support. The latter is not available on 653 * all parts. We're a bit pedantic here as all parts 654 * support a global cap. 655 */ 656 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 657 ic->ic_caps |= IEEE80211_C_TXPMGT; 658 659 /* 660 * Mark WME capability only if we have sufficient 661 * hardware queues to do proper priority scheduling. 662 */ 663 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 664 ic->ic_caps |= IEEE80211_C_WME; 665 /* 666 * Check for misc other capabilities. 667 */ 668 if (ath_hal_hasbursting(ah)) 669 ic->ic_caps |= IEEE80211_C_BURST; 670 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 671 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 672 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 673 if (ath_hal_hasfastframes(ah)) 674 ic->ic_caps |= IEEE80211_C_FF; 675 wmodes = ath_hal_getwirelessmodes(ah); 676 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 677 ic->ic_caps |= IEEE80211_C_TURBOP; 678 #ifdef IEEE80211_SUPPORT_TDMA 679 if (ath_hal_macversion(ah) > 0x78) { 680 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 681 ic->ic_tdma_update = ath_tdma_update; 682 } 683 #endif 684 /* 685 * Indicate we need the 802.11 header padded to a 686 * 32-bit boundary for 4-address and QoS frames. 687 */ 688 ic->ic_flags |= IEEE80211_F_DATAPAD; 689 690 /* 691 * Query the hal about antenna support. 692 */ 693 sc->sc_defant = ath_hal_getdefantenna(ah); 694 695 /* 696 * Not all chips have the VEOL support we want to 697 * use with IBSS beacons; check here for it. 698 */ 699 sc->sc_hasveol = ath_hal_hasveol(ah); 700 701 /* get mac address from hardware */ 702 ath_hal_getmac(ah, macaddr); 703 if (sc->sc_hasbmask) 704 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 705 706 /* NB: used to size node table key mapping array */ 707 ic->ic_max_keyix = sc->sc_keymax; 708 /* call MI attach routine. */ 709 ieee80211_ifattach(ic, macaddr); 710 ic->ic_setregdomain = ath_setregdomain; 711 ic->ic_getradiocaps = ath_getradiocaps; 712 sc->sc_opmode = HAL_M_STA; 713 714 /* override default methods */ 715 ic->ic_newassoc = ath_newassoc; 716 ic->ic_updateslot = ath_updateslot; 717 ic->ic_wme.wme_update = ath_wme_update; 718 ic->ic_vap_create = ath_vap_create; 719 ic->ic_vap_delete = ath_vap_delete; 720 ic->ic_raw_xmit = ath_raw_xmit; 721 ic->ic_update_mcast = ath_update_mcast; 722 ic->ic_update_promisc = ath_update_promisc; 723 ic->ic_node_alloc = ath_node_alloc; 724 sc->sc_node_free = ic->ic_node_free; 725 ic->ic_node_free = ath_node_free; 726 ic->ic_node_getsignal = ath_node_getsignal; 727 ic->ic_scan_start = ath_scan_start; 728 ic->ic_scan_end = ath_scan_end; 729 ic->ic_set_channel = ath_set_channel; 730 731 ieee80211_radiotap_attach(ic, 732 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 733 ATH_TX_RADIOTAP_PRESENT, 734 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 735 ATH_RX_RADIOTAP_PRESENT); 736 737 /* 738 * Setup dynamic sysctl's now that country code and 739 * regdomain are available from the hal. 740 */ 741 ath_sysctlattach(sc); 742 ath_sysctl_stats_attach(sc); 743 744 if (bootverbose) 745 ieee80211_announce(ic); 746 ath_announce(sc); 747 return 0; 748 bad2: 749 ath_tx_cleanup(sc); 750 ath_desc_free(sc); 751 bad: 752 if (ah) 753 ath_hal_detach(ah); 754 if (ifp != NULL) 755 if_free(ifp); 756 sc->sc_invalid = 1; 757 return error; 758 } 759 760 int 761 ath_detach(struct ath_softc *sc) 762 { 763 struct ifnet *ifp = sc->sc_ifp; 764 765 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 766 __func__, ifp->if_flags); 767 768 /* 769 * NB: the order of these is important: 770 * o stop the chip so no more interrupts will fire 771 * o call the 802.11 layer before detaching the hal to 772 * insure callbacks into the driver to delete global 773 * key cache entries can be handled 774 * o free the taskqueue which drains any pending tasks 775 * o reclaim the tx queue data structures after calling 776 * the 802.11 layer as we'll get called back to reclaim 777 * node state and potentially want to use them 778 * o to cleanup the tx queues the hal is called, so detach 779 * it last 780 * Other than that, it's straightforward... 781 */ 782 ath_stop(ifp); 783 ieee80211_ifdetach(ifp->if_l2com); 784 taskqueue_free(sc->sc_tq); 785 #ifdef ATH_TX99_DIAG 786 if (sc->sc_tx99 != NULL) 787 sc->sc_tx99->detach(sc->sc_tx99); 788 #endif 789 ath_rate_detach(sc->sc_rc); 790 ath_desc_free(sc); 791 ath_tx_cleanup(sc); 792 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 793 if (sc->sc_sysctl_tree) { 794 sysctl_ctx_free(&sc->sc_sysctl_ctx); 795 sc->sc_sysctl_tree = NULL; 796 } 797 if_free(ifp); 798 799 return 0; 800 } 801 802 /* 803 * MAC address handling for multiple BSS on the same radio. 804 * The first vap uses the MAC address from the EEPROM. For 805 * subsequent vap's we set the U/L bit (bit 1) in the MAC 806 * address and use the next six bits as an index. 807 */ 808 static void 809 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 810 { 811 int i; 812 813 if (clone && sc->sc_hasbmask) { 814 /* NB: we only do this if h/w supports multiple bssid */ 815 for (i = 0; i < 8; i++) 816 if ((sc->sc_bssidmask & (1<<i)) == 0) 817 break; 818 if (i != 0) 819 mac[0] |= (i << 2)|0x2; 820 } else 821 i = 0; 822 sc->sc_bssidmask |= 1<<i; 823 sc->sc_hwbssidmask[0] &= ~mac[0]; 824 if (i == 0) 825 sc->sc_nbssid0++; 826 } 827 828 static void 829 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 830 { 831 int i = mac[0] >> 2; 832 uint8_t mask; 833 834 if (i != 0 || --sc->sc_nbssid0 == 0) { 835 sc->sc_bssidmask &= ~(1<<i); 836 /* recalculate bssid mask from remaining addresses */ 837 mask = 0xff; 838 for (i = 1; i < 8; i++) 839 if (sc->sc_bssidmask & (1<<i)) 840 mask &= ~((i<<2)|0x2); 841 sc->sc_hwbssidmask[0] |= mask; 842 } 843 } 844 845 /* 846 * Assign a beacon xmit slot. We try to space out 847 * assignments so when beacons are staggered the 848 * traffic coming out of the cab q has maximal time 849 * to go out before the next beacon is scheduled. 850 */ 851 static int 852 assign_bslot(struct ath_softc *sc) 853 { 854 u_int slot, free; 855 856 free = 0; 857 for (slot = 0; slot < ATH_BCBUF; slot++) 858 if (sc->sc_bslot[slot] == NULL) { 859 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 860 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 861 return slot; 862 free = slot; 863 /* NB: keep looking for a double slot */ 864 } 865 return free; 866 } 867 868 static struct ieee80211vap * 869 ath_vap_create(struct ieee80211com *ic, 870 const char name[IFNAMSIZ], int unit, int opmode, int flags, 871 const uint8_t bssid[IEEE80211_ADDR_LEN], 872 const uint8_t mac0[IEEE80211_ADDR_LEN]) 873 { 874 struct ath_softc *sc = ic->ic_ifp->if_softc; 875 struct ath_vap *avp; 876 struct ieee80211vap *vap; 877 uint8_t mac[IEEE80211_ADDR_LEN]; 878 int ic_opmode, needbeacon, error; 879 880 avp = (struct ath_vap *) kmalloc(sizeof(struct ath_vap), 881 M_80211_VAP, M_WAITOK | M_ZERO); 882 needbeacon = 0; 883 IEEE80211_ADDR_COPY(mac, mac0); 884 885 ic_opmode = opmode; /* default to opmode of new vap */ 886 switch (opmode) { 887 case IEEE80211_M_STA: 888 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 889 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 890 goto bad; 891 } 892 if (sc->sc_nvaps) { 893 /* 894 * With multiple vaps we must fall back 895 * to s/w beacon miss handling. 896 */ 897 flags |= IEEE80211_CLONE_NOBEACONS; 898 } 899 if (flags & IEEE80211_CLONE_NOBEACONS) { 900 /* 901 * Station mode w/o beacons are implemented w/ AP mode. 902 */ 903 ic_opmode = IEEE80211_M_HOSTAP; 904 } 905 break; 906 case IEEE80211_M_IBSS: 907 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 908 device_printf(sc->sc_dev, 909 "only 1 ibss vap supported\n"); 910 goto bad; 911 } 912 needbeacon = 1; 913 break; 914 case IEEE80211_M_AHDEMO: 915 #ifdef IEEE80211_SUPPORT_TDMA 916 if (flags & IEEE80211_CLONE_TDMA) { 917 if (sc->sc_nvaps != 0) { 918 device_printf(sc->sc_dev, 919 "only 1 tdma vap supported\n"); 920 goto bad; 921 } 922 needbeacon = 1; 923 flags |= IEEE80211_CLONE_NOBEACONS; 924 } 925 /* fall thru... */ 926 #endif 927 case IEEE80211_M_MONITOR: 928 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 929 /* 930 * Adopt existing mode. Adding a monitor or ahdemo 931 * vap to an existing configuration is of dubious 932 * value but should be ok. 933 */ 934 /* XXX not right for monitor mode */ 935 ic_opmode = ic->ic_opmode; 936 } 937 break; 938 case IEEE80211_M_HOSTAP: 939 case IEEE80211_M_MBSS: 940 needbeacon = 1; 941 break; 942 case IEEE80211_M_WDS: 943 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 944 device_printf(sc->sc_dev, 945 "wds not supported in sta mode\n"); 946 goto bad; 947 } 948 /* 949 * Silently remove any request for a unique 950 * bssid; WDS vap's always share the local 951 * mac address. 952 */ 953 flags &= ~IEEE80211_CLONE_BSSID; 954 if (sc->sc_nvaps == 0) 955 ic_opmode = IEEE80211_M_HOSTAP; 956 else 957 ic_opmode = ic->ic_opmode; 958 break; 959 default: 960 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 961 goto bad; 962 } 963 /* 964 * Check that a beacon buffer is available; the code below assumes it. 965 */ 966 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 967 device_printf(sc->sc_dev, "no beacon buffer available\n"); 968 goto bad; 969 } 970 971 /* STA, AHDEMO? */ 972 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 973 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 974 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 975 } 976 977 vap = &avp->av_vap; 978 /* XXX can't hold mutex across if_alloc */ 979 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 980 bssid, mac); 981 if (error != 0) { 982 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 983 __func__, error); 984 goto bad2; 985 } 986 987 /* h/w crypto support */ 988 vap->iv_key_alloc = ath_key_alloc; 989 vap->iv_key_delete = ath_key_delete; 990 vap->iv_key_set = ath_key_set; 991 vap->iv_key_update_begin = ath_key_update_begin; 992 vap->iv_key_update_end = ath_key_update_end; 993 994 /* override various methods */ 995 avp->av_recv_mgmt = vap->iv_recv_mgmt; 996 vap->iv_recv_mgmt = ath_recv_mgmt; 997 vap->iv_reset = ath_reset_vap; 998 vap->iv_update_beacon = ath_beacon_update; 999 avp->av_newstate = vap->iv_newstate; 1000 vap->iv_newstate = ath_newstate; 1001 avp->av_bmiss = vap->iv_bmiss; 1002 vap->iv_bmiss = ath_bmiss_vap; 1003 1004 avp->av_bslot = -1; 1005 if (needbeacon) { 1006 /* 1007 * Allocate beacon state and setup the q for buffered 1008 * multicast frames. We know a beacon buffer is 1009 * available because we checked above. 1010 */ 1011 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 1012 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 1013 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1014 /* 1015 * Assign the vap to a beacon xmit slot. As above 1016 * this cannot fail to find a free one. 1017 */ 1018 avp->av_bslot = assign_bslot(sc); 1019 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1020 ("beacon slot %u not empty", avp->av_bslot)); 1021 sc->sc_bslot[avp->av_bslot] = vap; 1022 sc->sc_nbcnvaps++; 1023 } 1024 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1025 /* 1026 * Multple vaps are to transmit beacons and we 1027 * have h/w support for TSF adjusting; enable 1028 * use of staggered beacons. 1029 */ 1030 sc->sc_stagbeacons = 1; 1031 } 1032 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1033 } 1034 1035 ic->ic_opmode = ic_opmode; 1036 if (opmode != IEEE80211_M_WDS) { 1037 sc->sc_nvaps++; 1038 if (opmode == IEEE80211_M_STA) 1039 sc->sc_nstavaps++; 1040 if (opmode == IEEE80211_M_MBSS) 1041 sc->sc_nmeshvaps++; 1042 } 1043 switch (ic_opmode) { 1044 case IEEE80211_M_IBSS: 1045 sc->sc_opmode = HAL_M_IBSS; 1046 break; 1047 case IEEE80211_M_STA: 1048 sc->sc_opmode = HAL_M_STA; 1049 break; 1050 case IEEE80211_M_AHDEMO: 1051 #ifdef IEEE80211_SUPPORT_TDMA 1052 if (vap->iv_caps & IEEE80211_C_TDMA) { 1053 sc->sc_tdma = 1; 1054 /* NB: disable tsf adjust */ 1055 sc->sc_stagbeacons = 0; 1056 } 1057 /* 1058 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1059 * just ap mode. 1060 */ 1061 /* fall thru... */ 1062 #endif 1063 case IEEE80211_M_HOSTAP: 1064 case IEEE80211_M_MBSS: 1065 sc->sc_opmode = HAL_M_HOSTAP; 1066 break; 1067 case IEEE80211_M_MONITOR: 1068 sc->sc_opmode = HAL_M_MONITOR; 1069 break; 1070 default: 1071 /* XXX should not happen */ 1072 break; 1073 } 1074 if (sc->sc_hastsfadd) { 1075 /* 1076 * Configure whether or not TSF adjust should be done. 1077 */ 1078 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1079 } 1080 if (flags & IEEE80211_CLONE_NOBEACONS) { 1081 /* 1082 * Enable s/w beacon miss handling. 1083 */ 1084 sc->sc_swbmiss = 1; 1085 } 1086 1087 /* complete setup */ 1088 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1089 return vap; 1090 bad2: 1091 reclaim_address(sc, mac); 1092 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1093 bad: 1094 kfree(avp, M_80211_VAP); 1095 return NULL; 1096 } 1097 1098 static void 1099 ath_vap_delete(struct ieee80211vap *vap) 1100 { 1101 struct ieee80211com *ic = vap->iv_ic; 1102 struct ifnet *ifp = ic->ic_ifp; 1103 struct ath_softc *sc = ifp->if_softc; 1104 struct ath_hal *ah = sc->sc_ah; 1105 struct ath_vap *avp = ATH_VAP(vap); 1106 1107 if (ifp->if_flags & IFF_RUNNING) { 1108 /* 1109 * Quiesce the hardware while we remove the vap. In 1110 * particular we need to reclaim all references to 1111 * the vap state by any frames pending on the tx queues. 1112 */ 1113 ath_hal_intrset(ah, 0); /* disable interrupts */ 1114 ath_draintxq(sc); /* stop xmit side */ 1115 ath_stoprecv(sc); /* stop recv side */ 1116 } 1117 1118 ieee80211_vap_detach(vap); 1119 /* 1120 * Reclaim beacon state. Note this must be done before 1121 * the vap instance is reclaimed as we may have a reference 1122 * to it in the buffer for the beacon frame. 1123 */ 1124 if (avp->av_bcbuf != NULL) { 1125 if (avp->av_bslot != -1) { 1126 sc->sc_bslot[avp->av_bslot] = NULL; 1127 sc->sc_nbcnvaps--; 1128 } 1129 ath_beacon_return(sc, avp->av_bcbuf); 1130 avp->av_bcbuf = NULL; 1131 if (sc->sc_nbcnvaps == 0) { 1132 sc->sc_stagbeacons = 0; 1133 if (sc->sc_hastsfadd) 1134 ath_hal_settsfadjust(sc->sc_ah, 0); 1135 } 1136 /* 1137 * Reclaim any pending mcast frames for the vap. 1138 */ 1139 ath_tx_draintxq(sc, &avp->av_mcastq); 1140 } 1141 /* 1142 * Update bookkeeping. 1143 */ 1144 if (vap->iv_opmode == IEEE80211_M_STA) { 1145 sc->sc_nstavaps--; 1146 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1147 sc->sc_swbmiss = 0; 1148 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1149 vap->iv_opmode == IEEE80211_M_MBSS) { 1150 reclaim_address(sc, vap->iv_myaddr); 1151 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1152 if (vap->iv_opmode == IEEE80211_M_MBSS) 1153 sc->sc_nmeshvaps--; 1154 } 1155 if (vap->iv_opmode != IEEE80211_M_WDS) 1156 sc->sc_nvaps--; 1157 #ifdef IEEE80211_SUPPORT_TDMA 1158 /* TDMA operation ceases when the last vap is destroyed */ 1159 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1160 sc->sc_tdma = 0; 1161 sc->sc_swbmiss = 0; 1162 } 1163 #endif 1164 kfree(avp, M_80211_VAP); 1165 1166 if (ifp->if_flags & IFF_RUNNING) { 1167 /* 1168 * Restart rx+tx machines if still running (RUNNING will 1169 * be reset if we just destroyed the last vap). 1170 */ 1171 if (ath_startrecv(sc) != 0) 1172 if_printf(ifp, "%s: unable to restart recv logic\n", 1173 __func__); 1174 if (sc->sc_beacons) { /* restart beacons */ 1175 #ifdef IEEE80211_SUPPORT_TDMA 1176 if (sc->sc_tdma) 1177 ath_tdma_config(sc, NULL); 1178 else 1179 #endif 1180 ath_beacon_config(sc, NULL); 1181 } 1182 ath_hal_intrset(ah, sc->sc_imask); 1183 } 1184 } 1185 1186 void 1187 ath_suspend(struct ath_softc *sc) 1188 { 1189 struct ifnet *ifp = sc->sc_ifp; 1190 struct ieee80211com *ic = ifp->if_l2com; 1191 1192 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1193 __func__, ifp->if_flags); 1194 1195 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1196 if (ic->ic_opmode == IEEE80211_M_STA) 1197 ath_stop(ifp); 1198 else 1199 ieee80211_suspend_all(ic); 1200 /* 1201 * NB: don't worry about putting the chip in low power 1202 * mode; pci will power off our socket on suspend and 1203 * CardBus detaches the device. 1204 */ 1205 } 1206 1207 /* 1208 * Reset the key cache since some parts do not reset the 1209 * contents on resume. First we clear all entries, then 1210 * re-load keys that the 802.11 layer assumes are setup 1211 * in h/w. 1212 */ 1213 static void 1214 ath_reset_keycache(struct ath_softc *sc) 1215 { 1216 struct ifnet *ifp = sc->sc_ifp; 1217 struct ieee80211com *ic = ifp->if_l2com; 1218 struct ath_hal *ah = sc->sc_ah; 1219 int i; 1220 1221 for (i = 0; i < sc->sc_keymax; i++) 1222 ath_hal_keyreset(ah, i); 1223 ieee80211_crypto_reload_keys(ic); 1224 } 1225 1226 void 1227 ath_resume(struct ath_softc *sc) 1228 { 1229 struct ifnet *ifp = sc->sc_ifp; 1230 struct ieee80211com *ic = ifp->if_l2com; 1231 struct ath_hal *ah = sc->sc_ah; 1232 HAL_STATUS status; 1233 1234 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1235 __func__, ifp->if_flags); 1236 1237 /* 1238 * Must reset the chip before we reload the 1239 * keycache as we were powered down on suspend. 1240 */ 1241 ath_hal_reset(ah, sc->sc_opmode, 1242 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1243 AH_FALSE, &status); 1244 ath_reset_keycache(sc); 1245 if (sc->sc_resume_up) { 1246 if (ic->ic_opmode == IEEE80211_M_STA) { 1247 ath_init(sc); 1248 /* 1249 * Program the beacon registers using the last rx'd 1250 * beacon frame and enable sync on the next beacon 1251 * we see. This should handle the case where we 1252 * wakeup and find the same AP and also the case where 1253 * we wakeup and need to roam. For the latter we 1254 * should get bmiss events that trigger a roam. 1255 */ 1256 ath_beacon_config(sc, NULL); 1257 sc->sc_syncbeacon = 1; 1258 } else 1259 ieee80211_resume_all(ic); 1260 } 1261 if (sc->sc_softled) { 1262 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1263 HAL_GPIO_MUX_MAC_NETWORK_LED); 1264 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1265 } 1266 } 1267 1268 void 1269 ath_shutdown(struct ath_softc *sc) 1270 { 1271 struct ifnet *ifp = sc->sc_ifp; 1272 1273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1274 __func__, ifp->if_flags); 1275 1276 ath_stop(ifp); 1277 /* NB: no point powering down chip as we're about to reboot */ 1278 } 1279 1280 /* 1281 * Interrupt handler. Most of the actual processing is deferred. 1282 */ 1283 void 1284 ath_intr(void *arg) 1285 { 1286 struct ath_softc *sc = arg; 1287 struct ifnet *ifp = sc->sc_ifp; 1288 struct ath_hal *ah = sc->sc_ah; 1289 HAL_INT status; 1290 HAL_INT ostatus; 1291 1292 if (sc->sc_invalid) { 1293 /* 1294 * The hardware is not ready/present, don't touch anything. 1295 * Note this can happen early on if the IRQ is shared. 1296 */ 1297 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1298 return; 1299 } 1300 1301 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1302 return; 1303 if ((ifp->if_flags & IFF_UP) == 0 || 1304 (ifp->if_flags & IFF_RUNNING) == 0) { 1305 HAL_INT status; 1306 1307 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1308 __func__, ifp->if_flags); 1309 ath_hal_getisr(ah, &status); /* clear ISR */ 1310 ath_hal_intrset(ah, 0); /* disable further intr's */ 1311 return; 1312 } 1313 /* 1314 * Figure out the reason(s) for the interrupt. Note 1315 * that the hal returns a pseudo-ISR that may include 1316 * bits we haven't explicitly enabled so we mask the 1317 * value to insure we only process bits we requested. 1318 */ 1319 ath_hal_getisr(ah, &ostatus); /* NB: clears ISR too */ 1320 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, ostatus); 1321 status = ostatus & sc->sc_imask; /* discard unasked for bits */ 1322 if (status & HAL_INT_FATAL) { 1323 sc->sc_stats.ast_hardware++; 1324 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1325 ath_fatal_proc(sc, 0); 1326 } else { 1327 if (status & HAL_INT_SWBA) { 1328 /* 1329 * Software beacon alert--time to send a beacon. 1330 * Handle beacon transmission directly; deferring 1331 * this is too slow to meet timing constraints 1332 * under load. 1333 */ 1334 #ifdef IEEE80211_SUPPORT_TDMA 1335 if (sc->sc_tdma) { 1336 if (sc->sc_tdmaswba == 0) { 1337 struct ieee80211com *ic = ifp->if_l2com; 1338 struct ieee80211vap *vap = 1339 TAILQ_FIRST(&ic->ic_vaps); 1340 ath_tdma_beacon_send(sc, vap); 1341 sc->sc_tdmaswba = 1342 vap->iv_tdma->tdma_bintval; 1343 } else 1344 sc->sc_tdmaswba--; 1345 } else 1346 #endif 1347 { 1348 ath_beacon_proc(sc, 0); 1349 #ifdef IEEE80211_SUPPORT_SUPERG 1350 /* 1351 * Schedule the rx taskq in case there's no 1352 * traffic so any frames held on the staging 1353 * queue are aged and potentially flushed. 1354 */ 1355 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1356 #endif 1357 } 1358 } 1359 1360 /* 1361 * NB: The hardware should re-read the link when the RXE 1362 * bit is written, but it doesn't work at least on 1363 * older chipsets. 1364 */ 1365 if (status & HAL_INT_RXEOL) { 1366 sc->sc_stats.ast_rxeol++; 1367 sc->sc_rxlink = NULL; 1368 } 1369 1370 if (status & HAL_INT_TXURN) { 1371 sc->sc_stats.ast_txurn++; 1372 /* bump tx trigger level */ 1373 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1374 } 1375 1376 if (status & HAL_INT_RX) 1377 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1378 1379 if (status & HAL_INT_TX) 1380 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1381 1382 if (status & HAL_INT_BMISS) { 1383 sc->sc_stats.ast_bmiss++; 1384 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1385 } 1386 1387 if (status & HAL_INT_MIB) { 1388 sc->sc_stats.ast_mib++; 1389 /* 1390 * Disable interrupts until we service the MIB 1391 * interrupt; otherwise it will continue to fire. 1392 */ 1393 ath_hal_intrset(ah, 0); 1394 /* 1395 * Let the hal handle the event. We assume it will 1396 * clear whatever condition caused the interrupt. 1397 */ 1398 ath_hal_mibevent(ah, &sc->sc_halstats); 1399 ath_hal_intrset(ah, sc->sc_imask); 1400 } 1401 1402 if (status & HAL_INT_RXORN) { 1403 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1404 sc->sc_stats.ast_rxorn++; 1405 } 1406 } 1407 } 1408 1409 static void 1410 ath_fatal_proc(void *arg, int pending) 1411 { 1412 struct ath_softc *sc = arg; 1413 struct ifnet *ifp = sc->sc_ifp; 1414 u_int32_t *state; 1415 u_int32_t len; 1416 void *sp; 1417 1418 if_printf(ifp, "hardware error; resetting\n"); 1419 /* 1420 * Fatal errors are unrecoverable. Typically these 1421 * are caused by DMA errors. Collect h/w state from 1422 * the hal so we can diagnose what's going on. 1423 */ 1424 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1425 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1426 state = sp; 1427 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1428 state[0], state[1] , state[2], state[3], 1429 state[4], state[5]); 1430 } 1431 ath_reset(ifp); 1432 } 1433 1434 static void 1435 ath_bmiss_vap(struct ieee80211vap *vap) 1436 { 1437 /* 1438 * Workaround phantom bmiss interrupts by sanity-checking 1439 * the time of our last rx'd frame. If it is within the 1440 * beacon miss interval then ignore the interrupt. If it's 1441 * truly a bmiss we'll get another interrupt soon and that'll 1442 * be dispatched up for processing. Note this applies only 1443 * for h/w beacon miss events. 1444 */ 1445 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1446 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1447 struct ath_softc *sc = ifp->if_softc; 1448 u_int64_t lastrx = sc->sc_lastrx; 1449 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1450 u_int bmisstimeout = 1451 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1452 1453 DPRINTF(sc, ATH_DEBUG_BEACON, 1454 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1455 __func__, (unsigned long long) tsf, 1456 (unsigned long long)(tsf - lastrx), 1457 (unsigned long long) lastrx, bmisstimeout); 1458 1459 if (tsf - lastrx <= bmisstimeout) { 1460 sc->sc_stats.ast_bmiss_phantom++; 1461 return; 1462 } 1463 } 1464 ATH_VAP(vap)->av_bmiss(vap); 1465 } 1466 1467 static int 1468 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1469 { 1470 uint32_t rsize; 1471 void *sp; 1472 1473 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(mask), &sp, &rsize)) 1474 return 0; 1475 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1476 *hangs = *(uint32_t *)sp; 1477 return 1; 1478 } 1479 1480 static void 1481 ath_bmiss_task(void *arg, int pending) 1482 { 1483 struct ath_softc *sc = arg; 1484 struct ifnet *ifp = sc->sc_ifp; 1485 uint32_t hangs; 1486 1487 wlan_serialize_enter(); 1488 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1489 1490 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1491 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs); 1492 ath_reset(ifp); 1493 } else { 1494 ieee80211_beacon_miss(ifp->if_l2com); 1495 } 1496 wlan_serialize_exit(); 1497 } 1498 1499 /* 1500 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1501 * calcs together with WME. If necessary disable the crypto 1502 * hardware and mark the 802.11 state so keys will be setup 1503 * with the MIC work done in software. 1504 */ 1505 static void 1506 ath_settkipmic(struct ath_softc *sc) 1507 { 1508 struct ifnet *ifp = sc->sc_ifp; 1509 struct ieee80211com *ic = ifp->if_l2com; 1510 1511 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1512 if (ic->ic_flags & IEEE80211_F_WME) { 1513 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1514 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1515 } else { 1516 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1517 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1518 } 1519 } 1520 } 1521 1522 static void 1523 ath_init(void *arg) 1524 { 1525 struct ath_softc *sc = (struct ath_softc *) arg; 1526 struct ifnet *ifp = sc->sc_ifp; 1527 struct ieee80211com *ic = ifp->if_l2com; 1528 struct ath_hal *ah = sc->sc_ah; 1529 HAL_STATUS status; 1530 1531 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1532 __func__, ifp->if_flags); 1533 1534 /* 1535 * Stop anything previously setup. This is safe 1536 * whether this is the first time through or not. 1537 */ 1538 ath_stop_locked(ifp); 1539 1540 /* 1541 * The basic interface to setting the hardware in a good 1542 * state is ``reset''. On return the hardware is known to 1543 * be powered up and with interrupts disabled. This must 1544 * be followed by initialization of the appropriate bits 1545 * and then setup of the interrupt mask. 1546 */ 1547 ath_settkipmic(sc); 1548 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1549 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1550 status); 1551 return; 1552 } 1553 ath_chan_change(sc, ic->ic_curchan); 1554 1555 /* 1556 * Likewise this is set during reset so update 1557 * state cached in the driver. 1558 */ 1559 sc->sc_diversity = ath_hal_getdiversity(ah); 1560 sc->sc_lastlongcal = 0; 1561 sc->sc_resetcal = 1; 1562 sc->sc_lastcalreset = 0; 1563 1564 /* 1565 * Setup the hardware after reset: the key cache 1566 * is filled as needed and the receive engine is 1567 * set going. Frame transmit is handled entirely 1568 * in the frame output path; there's nothing to do 1569 * here except setup the interrupt mask. 1570 */ 1571 if (ath_startrecv(sc) != 0) { 1572 if_printf(ifp, "unable to start recv logic\n"); 1573 return; 1574 } 1575 1576 /* 1577 * Enable interrupts. 1578 */ 1579 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1580 | HAL_INT_RXEOL | HAL_INT_RXORN 1581 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1582 /* 1583 * Enable MIB interrupts when there are hardware phy counters. 1584 * Note we only do this (at the moment) for station mode. 1585 */ 1586 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1587 sc->sc_imask |= HAL_INT_MIB; 1588 1589 ifp->if_flags |= IFF_RUNNING; 1590 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 1591 ath_hal_intrset(ah, sc->sc_imask); 1592 1593 1594 #ifdef ATH_TX99_DIAG 1595 if (sc->sc_tx99 != NULL) 1596 sc->sc_tx99->start(sc->sc_tx99); 1597 else 1598 #endif 1599 ieee80211_start_all(ic); /* start all vap's */ 1600 } 1601 1602 static void 1603 ath_stop_locked(struct ifnet *ifp) 1604 { 1605 struct ath_softc *sc = ifp->if_softc; 1606 struct ath_hal *ah = sc->sc_ah; 1607 1608 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1609 __func__, sc->sc_invalid, ifp->if_flags); 1610 1611 if (ifp->if_flags & IFF_RUNNING) { 1612 /* 1613 * Shutdown the hardware and driver: 1614 * reset 802.11 state machine 1615 * turn off timers 1616 * disable interrupts 1617 * turn off the radio 1618 * clear transmit machinery 1619 * clear receive machinery 1620 * drain and release tx queues 1621 * reclaim beacon resources 1622 * power down hardware 1623 * 1624 * Note that some of this work is not possible if the 1625 * hardware is gone (invalid). 1626 */ 1627 #ifdef ATH_TX99_DIAG 1628 if (sc->sc_tx99 != NULL) 1629 sc->sc_tx99->stop(sc->sc_tx99); 1630 #endif 1631 callout_stop(&sc->sc_wd_ch); 1632 sc->sc_wd_timer = 0; 1633 ifp->if_flags &= ~IFF_RUNNING; 1634 if (!sc->sc_invalid) { 1635 if (sc->sc_softled) { 1636 callout_stop(&sc->sc_ledtimer); 1637 ath_hal_gpioset(ah, sc->sc_ledpin, 1638 !sc->sc_ledon); 1639 sc->sc_blinking = 0; 1640 } 1641 ath_hal_intrset(ah, 0); 1642 } 1643 ath_draintxq(sc); 1644 if (!sc->sc_invalid) { 1645 ath_stoprecv(sc); 1646 ath_hal_phydisable(ah); 1647 } else 1648 sc->sc_rxlink = NULL; 1649 ath_beacon_free(sc); /* XXX not needed */ 1650 } 1651 } 1652 1653 static void 1654 ath_stop(struct ifnet *ifp) 1655 { 1656 struct ath_softc *sc __unused = ifp->if_softc; 1657 1658 ath_stop_locked(ifp); 1659 } 1660 1661 /* 1662 * Reset the hardware w/o losing operational state. This is 1663 * basically a more efficient way of doing ath_stop, ath_init, 1664 * followed by state transitions to the current 802.11 1665 * operational state. Used to recover from various errors and 1666 * to reset or reload hardware state. 1667 */ 1668 static int 1669 ath_reset(struct ifnet *ifp) 1670 { 1671 struct ath_softc *sc = ifp->if_softc; 1672 struct ieee80211com *ic = ifp->if_l2com; 1673 struct ath_hal *ah = sc->sc_ah; 1674 HAL_STATUS status; 1675 1676 kprintf("ath_reset\n"); 1677 ath_hal_intrset(ah, 0); /* disable interrupts */ 1678 ath_draintxq(sc); /* stop xmit side */ 1679 ath_stoprecv(sc); /* stop recv side */ 1680 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1681 /* NB: indicate channel change so we do a full reset */ 1682 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1683 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1684 __func__, status); 1685 sc->sc_diversity = ath_hal_getdiversity(ah); 1686 if (ath_startrecv(sc) != 0) /* restart recv */ 1687 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1688 /* 1689 * We may be doing a reset in response to an ioctl 1690 * that changes the channel so update any state that 1691 * might change as a result. 1692 */ 1693 ath_chan_change(sc, ic->ic_curchan); 1694 if (sc->sc_beacons) { /* restart beacons */ 1695 #ifdef IEEE80211_SUPPORT_TDMA 1696 if (sc->sc_tdma) 1697 ath_tdma_config(sc, NULL); 1698 else 1699 #endif 1700 ath_beacon_config(sc, NULL); 1701 } 1702 ath_hal_intrset(ah, sc->sc_imask); 1703 1704 ath_start(ifp); /* restart xmit */ 1705 return 0; 1706 } 1707 1708 static int 1709 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1710 { 1711 struct ieee80211com *ic = vap->iv_ic; 1712 struct ifnet *ifp = ic->ic_ifp; 1713 struct ath_softc *sc = ifp->if_softc; 1714 struct ath_hal *ah = sc->sc_ah; 1715 1716 switch (cmd) { 1717 case IEEE80211_IOC_TXPOWER: 1718 /* 1719 * If per-packet TPC is enabled, then we have nothing 1720 * to do; otherwise we need to force the global limit. 1721 * All this can happen directly; no need to reset. 1722 */ 1723 if (!ath_hal_gettpc(ah)) 1724 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1725 return 0; 1726 } 1727 return ath_reset(ifp); 1728 } 1729 1730 static struct ath_buf * 1731 _ath_getbuf_locked(struct ath_softc *sc) 1732 { 1733 struct ath_buf *bf; 1734 1735 bf = STAILQ_FIRST(&sc->sc_txbuf); 1736 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1737 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1738 else 1739 bf = NULL; 1740 if (bf == NULL) { 1741 kprintf("ath: ran out of descriptors\n"); 1742 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 1743 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 1744 "out of xmit buffers" : "xmit buffer busy"); 1745 } 1746 return bf; 1747 } 1748 1749 static struct ath_buf * 1750 ath_getbuf(struct ath_softc *sc) 1751 { 1752 struct ath_buf *bf; 1753 1754 bf = _ath_getbuf_locked(sc); 1755 if (bf == NULL) { 1756 struct ifnet *ifp = sc->sc_ifp; 1757 1758 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1759 sc->sc_stats.ast_tx_qstop++; 1760 ifp->if_flags |= IFF_OACTIVE; 1761 } 1762 return bf; 1763 } 1764 1765 /* 1766 * Cleanup driver resources when we run out of buffers 1767 * while processing fragments; return the tx buffers 1768 * allocated and drop node references. 1769 */ 1770 static void 1771 ath_txfrag_cleanup(struct ath_softc *sc, 1772 ath_bufhead *frags, struct ieee80211_node *ni) 1773 { 1774 struct ath_buf *bf, *next; 1775 1776 STAILQ_FOREACH_MUTABLE(bf, frags, bf_list, next) { 1777 /* NB: bf assumed clean */ 1778 STAILQ_REMOVE_HEAD(frags, bf_list); 1779 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1780 ieee80211_node_decref(ni); 1781 } 1782 } 1783 1784 /* 1785 * Setup xmit of a fragmented frame. Allocate a buffer 1786 * for each frag and bump the node reference count to 1787 * reflect the held reference to be setup by ath_tx_start. 1788 */ 1789 static int 1790 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1791 struct mbuf *m0, struct ieee80211_node *ni) 1792 { 1793 struct mbuf *m; 1794 struct ath_buf *bf; 1795 1796 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1797 bf = _ath_getbuf_locked(sc); 1798 if (bf == NULL) { /* out of buffers, cleanup */ 1799 ath_txfrag_cleanup(sc, frags, ni); 1800 break; 1801 } 1802 ieee80211_node_incref(ni); 1803 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1804 } 1805 1806 return !STAILQ_EMPTY(frags); 1807 } 1808 1809 static void 1810 ath_start(struct ifnet *ifp) 1811 { 1812 struct ath_softc *sc = ifp->if_softc; 1813 struct ieee80211_node *ni; 1814 struct ath_buf *bf; 1815 struct mbuf *m, *next; 1816 ath_bufhead frags; 1817 1818 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 1819 ifq_purge(&ifp->if_snd); 1820 return; 1821 } 1822 for (;;) { 1823 /* 1824 * Grab a TX buffer and associated resources. 1825 */ 1826 bf = ath_getbuf(sc); 1827 if (bf == NULL) 1828 break; 1829 1830 IF_DEQUEUE(&ifp->if_snd, m); 1831 if (m == NULL) { 1832 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1833 break; 1834 } 1835 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1836 /* 1837 * Check for fragmentation. If this frame 1838 * has been broken up verify we have enough 1839 * buffers to send all the fragments so all 1840 * go out or none... 1841 */ 1842 STAILQ_INIT(&frags); 1843 if ((m->m_flags & M_FRAG) && 1844 !ath_txfrag_setup(sc, &frags, m, ni)) { 1845 DPRINTF(sc, ATH_DEBUG_XMIT, 1846 "%s: out of txfrag buffers\n", __func__); 1847 sc->sc_stats.ast_tx_nofrag++; 1848 ifp->if_oerrors++; 1849 ath_freetx(m); 1850 goto bad; 1851 } 1852 ifp->if_opackets++; 1853 nextfrag: 1854 /* 1855 * Pass the frame to the h/w for transmission. 1856 * Fragmented frames have each frag chained together 1857 * with m_nextpkt. We know there are sufficient ath_buf's 1858 * to send all the frags because of work done by 1859 * ath_txfrag_setup. We leave m_nextpkt set while 1860 * calling ath_tx_start so it can use it to extend the 1861 * the tx duration to cover the subsequent frag and 1862 * so it can reclaim all the mbufs in case of an error; 1863 * ath_tx_start clears m_nextpkt once it commits to 1864 * handing the frame to the hardware. 1865 */ 1866 next = m->m_nextpkt; 1867 if (ath_tx_start(sc, ni, bf, m)) { 1868 bad: 1869 ifp->if_oerrors++; 1870 reclaim: 1871 bf->bf_m = NULL; 1872 bf->bf_node = NULL; 1873 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1874 ath_txfrag_cleanup(sc, &frags, ni); 1875 if (ni != NULL) 1876 ieee80211_free_node(ni); 1877 continue; 1878 } 1879 if (next != NULL) { 1880 /* 1881 * Beware of state changing between frags. 1882 * XXX check sta power-save state? 1883 */ 1884 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1885 DPRINTF(sc, ATH_DEBUG_XMIT, 1886 "%s: flush fragmented packet, state %s\n", 1887 __func__, 1888 ieee80211_state_name[ni->ni_vap->iv_state]); 1889 ath_freetx(next); 1890 goto reclaim; 1891 } 1892 m = next; 1893 bf = STAILQ_FIRST(&frags); 1894 KASSERT(bf != NULL, ("no buf for txfrag")); 1895 STAILQ_REMOVE_HEAD(&frags, bf_list); 1896 goto nextfrag; 1897 } 1898 1899 sc->sc_wd_timer = 5; 1900 } 1901 } 1902 1903 static int 1904 ath_media_change(struct ifnet *ifp) 1905 { 1906 int error = ieee80211_media_change(ifp); 1907 /* NB: only the fixed rate can change and that doesn't need a reset */ 1908 return (error == ENETRESET ? 0 : error); 1909 } 1910 1911 #ifdef ATH_DEBUG 1912 static void 1913 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1914 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1915 { 1916 static const char *ciphers[] = { 1917 "WEP", 1918 "AES-OCB", 1919 "AES-CCM", 1920 "CKIP", 1921 "TKIP", 1922 "CLR", 1923 }; 1924 int i, n; 1925 1926 kprintf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1927 for (i = 0, n = hk->kv_len; i < n; i++) 1928 kprintf("%02x", hk->kv_val[i]); 1929 kprintf(" mac %6D", mac, ":"); 1930 if (hk->kv_type == HAL_CIPHER_TKIP) { 1931 kprintf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1932 for (i = 0; i < sizeof(hk->kv_mic); i++) 1933 kprintf("%02x", hk->kv_mic[i]); 1934 if (!sc->sc_splitmic) { 1935 kprintf(" txmic "); 1936 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1937 kprintf("%02x", hk->kv_txmic[i]); 1938 } 1939 } 1940 kprintf("\n"); 1941 } 1942 #endif 1943 1944 /* 1945 * Set a TKIP key into the hardware. This handles the 1946 * potential distribution of key state to multiple key 1947 * cache slots for TKIP. 1948 */ 1949 static int 1950 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1951 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1952 { 1953 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1954 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1955 struct ath_hal *ah = sc->sc_ah; 1956 1957 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1958 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1959 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1960 if (sc->sc_splitmic) { 1961 /* 1962 * TX key goes at first index, RX key at the rx index. 1963 * The hal handles the MIC keys at index+64. 1964 */ 1965 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1966 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1967 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1968 return 0; 1969 1970 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1971 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1972 /* XXX delete tx key on failure? */ 1973 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1974 } else { 1975 /* 1976 * Room for both TX+RX MIC keys in one key cache 1977 * slot, just set key at the first index; the hal 1978 * will handle the rest. 1979 */ 1980 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1981 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1982 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1983 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1984 } 1985 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1986 if (sc->sc_splitmic) { 1987 /* 1988 * NB: must pass MIC key in expected location when 1989 * the keycache only holds one MIC key per entry. 1990 */ 1991 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1992 } else 1993 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1994 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1995 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1996 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1997 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1998 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1999 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2000 } 2001 return 0; 2002 #undef IEEE80211_KEY_XR 2003 } 2004 2005 /* 2006 * Set a net80211 key into the hardware. This handles the 2007 * potential distribution of key state to multiple key 2008 * cache slots for TKIP with hardware MIC support. 2009 */ 2010 static int 2011 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2012 struct ieee80211_node *bss) 2013 { 2014 #define N(a) (sizeof(a)/sizeof(a[0])) 2015 static const u_int8_t ciphermap[] = { 2016 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2017 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2018 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2019 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2020 (u_int8_t) -1, /* 4 is not allocated */ 2021 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2022 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2023 }; 2024 struct ath_hal *ah = sc->sc_ah; 2025 const struct ieee80211_cipher *cip = k->wk_cipher; 2026 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2027 const u_int8_t *mac; 2028 HAL_KEYVAL hk; 2029 2030 memset(&hk, 0, sizeof(hk)); 2031 /* 2032 * Software crypto uses a "clear key" so non-crypto 2033 * state kept in the key cache are maintained and 2034 * so that rx frames have an entry to match. 2035 */ 2036 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2037 KASSERT(cip->ic_cipher < N(ciphermap), 2038 ("invalid cipher type %u", cip->ic_cipher)); 2039 hk.kv_type = ciphermap[cip->ic_cipher]; 2040 hk.kv_len = k->wk_keylen; 2041 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2042 } else 2043 hk.kv_type = HAL_CIPHER_CLR; 2044 2045 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2046 /* 2047 * Group keys on hardware that supports multicast frame 2048 * key search use a MAC that is the sender's address with 2049 * the high bit set instead of the app-specified address. 2050 */ 2051 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2052 gmac[0] |= 0x80; 2053 mac = gmac; 2054 } else 2055 mac = k->wk_macaddr; 2056 2057 if (hk.kv_type == HAL_CIPHER_TKIP && 2058 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2059 return ath_keyset_tkip(sc, k, &hk, mac); 2060 } else { 2061 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2062 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2063 } 2064 #undef N 2065 } 2066 2067 /* 2068 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2069 * each key, one for decrypt/encrypt and the other for the MIC. 2070 */ 2071 static u_int16_t 2072 key_alloc_2pair(struct ath_softc *sc, 2073 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2074 { 2075 #define N(a) (sizeof(a)/sizeof(a[0])) 2076 u_int i, keyix; 2077 2078 KASSERT(sc->sc_splitmic, ("key cache !split")); 2079 /* XXX could optimize */ 2080 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2081 u_int8_t b = sc->sc_keymap[i]; 2082 if (b != 0xff) { 2083 /* 2084 * One or more slots in this byte are free. 2085 */ 2086 keyix = i*NBBY; 2087 while (b & 1) { 2088 again: 2089 keyix++; 2090 b >>= 1; 2091 } 2092 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2093 if (isset(sc->sc_keymap, keyix+32) || 2094 isset(sc->sc_keymap, keyix+64) || 2095 isset(sc->sc_keymap, keyix+32+64)) { 2096 /* full pair unavailable */ 2097 /* XXX statistic */ 2098 if (keyix == (i+1)*NBBY) { 2099 /* no slots were appropriate, advance */ 2100 continue; 2101 } 2102 goto again; 2103 } 2104 setbit(sc->sc_keymap, keyix); 2105 setbit(sc->sc_keymap, keyix+64); 2106 setbit(sc->sc_keymap, keyix+32); 2107 setbit(sc->sc_keymap, keyix+32+64); 2108 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2109 "%s: key pair %u,%u %u,%u\n", 2110 __func__, keyix, keyix+64, 2111 keyix+32, keyix+32+64); 2112 *txkeyix = keyix; 2113 *rxkeyix = keyix+32; 2114 return 1; 2115 } 2116 } 2117 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2118 return 0; 2119 #undef N 2120 } 2121 2122 /* 2123 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2124 * each key, one for decrypt/encrypt and the other for the MIC. 2125 */ 2126 static u_int16_t 2127 key_alloc_pair(struct ath_softc *sc, 2128 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2129 { 2130 #define N(a) (sizeof(a)/sizeof(a[0])) 2131 u_int i, keyix; 2132 2133 KASSERT(!sc->sc_splitmic, ("key cache split")); 2134 /* XXX could optimize */ 2135 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 2136 u_int8_t b = sc->sc_keymap[i]; 2137 if (b != 0xff) { 2138 /* 2139 * One or more slots in this byte are free. 2140 */ 2141 keyix = i*NBBY; 2142 while (b & 1) { 2143 again: 2144 keyix++; 2145 b >>= 1; 2146 } 2147 if (isset(sc->sc_keymap, keyix+64)) { 2148 /* full pair unavailable */ 2149 /* XXX statistic */ 2150 if (keyix == (i+1)*NBBY) { 2151 /* no slots were appropriate, advance */ 2152 continue; 2153 } 2154 goto again; 2155 } 2156 setbit(sc->sc_keymap, keyix); 2157 setbit(sc->sc_keymap, keyix+64); 2158 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2159 "%s: key pair %u,%u\n", 2160 __func__, keyix, keyix+64); 2161 *txkeyix = *rxkeyix = keyix; 2162 return 1; 2163 } 2164 } 2165 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2166 return 0; 2167 #undef N 2168 } 2169 2170 /* 2171 * Allocate a single key cache slot. 2172 */ 2173 static int 2174 key_alloc_single(struct ath_softc *sc, 2175 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2176 { 2177 #define N(a) (sizeof(a)/sizeof(a[0])) 2178 u_int i, keyix; 2179 2180 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2181 for (i = 0; i < N(sc->sc_keymap); i++) { 2182 u_int8_t b = sc->sc_keymap[i]; 2183 if (b != 0xff) { 2184 /* 2185 * One or more slots are free. 2186 */ 2187 keyix = i*NBBY; 2188 while (b & 1) 2189 keyix++, b >>= 1; 2190 setbit(sc->sc_keymap, keyix); 2191 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2192 __func__, keyix); 2193 *txkeyix = *rxkeyix = keyix; 2194 return 1; 2195 } 2196 } 2197 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2198 return 0; 2199 #undef N 2200 } 2201 2202 /* 2203 * Allocate one or more key cache slots for a uniacst key. The 2204 * key itself is needed only to identify the cipher. For hardware 2205 * TKIP with split cipher+MIC keys we allocate two key cache slot 2206 * pairs so that we can setup separate TX and RX MIC keys. Note 2207 * that the MIC key for a TKIP key at slot i is assumed by the 2208 * hardware to be at slot i+64. This limits TKIP keys to the first 2209 * 64 entries. 2210 */ 2211 static int 2212 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2213 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2214 { 2215 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2216 2217 /* 2218 * Group key allocation must be handled specially for 2219 * parts that do not support multicast key cache search 2220 * functionality. For those parts the key id must match 2221 * the h/w key index so lookups find the right key. On 2222 * parts w/ the key search facility we install the sender's 2223 * mac address (with the high bit set) and let the hardware 2224 * find the key w/o using the key id. This is preferred as 2225 * it permits us to support multiple users for adhoc and/or 2226 * multi-station operation. 2227 */ 2228 if (k->wk_keyix != IEEE80211_KEYIX_NONE) { 2229 /* 2230 * Only global keys should have key index assigned. 2231 */ 2232 if (!(&vap->iv_nw_keys[0] <= k && 2233 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2234 /* should not happen */ 2235 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2236 "%s: bogus group key\n", __func__); 2237 return 0; 2238 } 2239 if (vap->iv_opmode != IEEE80211_M_HOSTAP || 2240 !(k->wk_flags & IEEE80211_KEY_GROUP) || 2241 !sc->sc_mcastkey) { 2242 /* 2243 * XXX we pre-allocate the global keys so 2244 * have no way to check if they've already 2245 * been allocated. 2246 */ 2247 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2248 return 1; 2249 } 2250 /* 2251 * Group key and device supports multicast key search. 2252 */ 2253 k->wk_keyix = IEEE80211_KEYIX_NONE; 2254 } 2255 2256 /* 2257 * We allocate two pair for TKIP when using the h/w to do 2258 * the MIC. For everything else, including software crypto, 2259 * we allocate a single entry. Note that s/w crypto requires 2260 * a pass-through slot on the 5211 and 5212. The 5210 does 2261 * not support pass-through cache entries and we map all 2262 * those requests to slot 0. 2263 */ 2264 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2265 return key_alloc_single(sc, keyix, rxkeyix); 2266 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2267 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2268 if (sc->sc_splitmic) 2269 return key_alloc_2pair(sc, keyix, rxkeyix); 2270 else 2271 return key_alloc_pair(sc, keyix, rxkeyix); 2272 } else { 2273 return key_alloc_single(sc, keyix, rxkeyix); 2274 } 2275 } 2276 2277 /* 2278 * Delete an entry in the key cache allocated by ath_key_alloc. 2279 */ 2280 static int 2281 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2282 { 2283 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2284 struct ath_hal *ah = sc->sc_ah; 2285 const struct ieee80211_cipher *cip = k->wk_cipher; 2286 u_int keyix = k->wk_keyix; 2287 2288 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2289 2290 ath_hal_keyreset(ah, keyix); 2291 /* 2292 * Handle split tx/rx keying required for TKIP with h/w MIC. 2293 */ 2294 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2295 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2296 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2297 if (keyix >= IEEE80211_WEP_NKID) { 2298 /* 2299 * Don't touch keymap entries for global keys so 2300 * they are never considered for dynamic allocation. 2301 */ 2302 clrbit(sc->sc_keymap, keyix); 2303 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2304 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2305 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2306 if (sc->sc_splitmic) { 2307 /* +32 for RX key, +32+64 for RX key MIC */ 2308 clrbit(sc->sc_keymap, keyix+32); 2309 clrbit(sc->sc_keymap, keyix+32+64); 2310 } 2311 } 2312 } 2313 return 1; 2314 } 2315 2316 /* 2317 * Set the key cache contents for the specified key. Key cache 2318 * slot(s) must already have been allocated by ath_key_alloc. 2319 */ 2320 static int 2321 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2322 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2323 { 2324 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2325 2326 return ath_keyset(sc, k, vap->iv_bss); 2327 } 2328 2329 /* 2330 * Block/unblock tx+rx processing while a key change is done. 2331 * We assume the caller serializes key management operations 2332 * so we only need to worry about synchronization with other 2333 * uses that originate in the driver. 2334 */ 2335 static void 2336 ath_key_update_begin(struct ieee80211vap *vap) 2337 { 2338 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2339 struct ath_softc *sc = ifp->if_softc; 2340 2341 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2342 taskqueue_block(sc->sc_tq); 2343 } 2344 2345 static void 2346 ath_key_update_end(struct ieee80211vap *vap) 2347 { 2348 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2349 struct ath_softc *sc = ifp->if_softc; 2350 2351 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2352 taskqueue_unblock(sc->sc_tq); 2353 } 2354 2355 /* 2356 * Calculate the receive filter according to the 2357 * operating mode and state: 2358 * 2359 * o always accept unicast, broadcast, and multicast traffic 2360 * o accept PHY error frames when hardware doesn't have MIB support 2361 * to count and we need them for ANI (sta mode only until recently) 2362 * and we are not scanning (ANI is disabled) 2363 * NB: older hal's add rx filter bits out of sight and we need to 2364 * blindly preserve them 2365 * o probe request frames are accepted only when operating in 2366 * hostap, adhoc, mesh, or monitor modes 2367 * o enable promiscuous mode 2368 * - when in monitor mode 2369 * - if interface marked PROMISC (assumes bridge setting is filtered) 2370 * o accept beacons: 2371 * - when operating in station mode for collecting rssi data when 2372 * the station is otherwise quiet, or 2373 * - when operating in adhoc mode so the 802.11 layer creates 2374 * node table entries for peers, 2375 * - when scanning 2376 * - when doing s/w beacon miss (e.g. for ap+sta) 2377 * - when operating in ap mode in 11g to detect overlapping bss that 2378 * require protection 2379 * - when operating in mesh mode to detect neighbors 2380 * o accept control frames: 2381 * - when in monitor mode 2382 * XXX BAR frames for 11n 2383 * XXX HT protection for 11n 2384 */ 2385 static u_int32_t 2386 ath_calcrxfilter(struct ath_softc *sc) 2387 { 2388 struct ifnet *ifp = sc->sc_ifp; 2389 struct ieee80211com *ic = ifp->if_l2com; 2390 u_int32_t rfilt; 2391 2392 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2393 if (!sc->sc_needmib && !sc->sc_scanning) 2394 rfilt |= HAL_RX_FILTER_PHYERR; 2395 if (ic->ic_opmode != IEEE80211_M_STA) 2396 rfilt |= HAL_RX_FILTER_PROBEREQ; 2397 /* XXX ic->ic_monvaps != 0? */ 2398 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2399 rfilt |= HAL_RX_FILTER_PROM; 2400 if (ic->ic_opmode == IEEE80211_M_STA || 2401 ic->ic_opmode == IEEE80211_M_IBSS || 2402 sc->sc_swbmiss || sc->sc_scanning) 2403 rfilt |= HAL_RX_FILTER_BEACON; 2404 /* 2405 * NB: We don't recalculate the rx filter when 2406 * ic_protmode changes; otherwise we could do 2407 * this only when ic_protmode != NONE. 2408 */ 2409 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2410 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2411 rfilt |= HAL_RX_FILTER_BEACON; 2412 if (sc->sc_nmeshvaps) { 2413 rfilt |= HAL_RX_FILTER_BEACON; 2414 if (sc->sc_hasbmatch) 2415 rfilt |= HAL_RX_FILTER_BSSID; 2416 else 2417 rfilt |= HAL_RX_FILTER_PROM; 2418 } 2419 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2420 rfilt |= HAL_RX_FILTER_CONTROL; 2421 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2422 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2423 return rfilt; 2424 } 2425 2426 static void 2427 ath_update_promisc(struct ifnet *ifp) 2428 { 2429 struct ath_softc *sc = ifp->if_softc; 2430 u_int32_t rfilt; 2431 2432 /* configure rx filter */ 2433 rfilt = ath_calcrxfilter(sc); 2434 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2435 2436 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2437 } 2438 2439 static void 2440 ath_update_mcast(struct ifnet *ifp) 2441 { 2442 struct ath_softc *sc = ifp->if_softc; 2443 u_int32_t mfilt[2]; 2444 2445 /* calculate and install multicast filter */ 2446 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2447 struct ifmultiaddr *ifma; 2448 /* 2449 * Merge multicast addresses to form the hardware filter. 2450 */ 2451 mfilt[0] = mfilt[1] = 0; 2452 #ifdef __FreeBSD__ 2453 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2454 #endif 2455 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2456 caddr_t dl; 2457 u_int32_t val; 2458 u_int8_t pos; 2459 2460 /* calculate XOR of eight 6bit values */ 2461 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2462 val = LE_READ_4(dl + 0); 2463 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2464 val = LE_READ_4(dl + 3); 2465 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2466 pos &= 0x3f; 2467 mfilt[pos / 32] |= (1 << (pos % 32)); 2468 } 2469 #ifdef __FreeBSD__ 2470 if_maddr_runlock(ifp); 2471 #endif 2472 } else 2473 mfilt[0] = mfilt[1] = ~0; 2474 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2475 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2476 __func__, mfilt[0], mfilt[1]); 2477 } 2478 2479 static void 2480 ath_mode_init(struct ath_softc *sc) 2481 { 2482 struct ifnet *ifp = sc->sc_ifp; 2483 struct ath_hal *ah = sc->sc_ah; 2484 u_int32_t rfilt; 2485 2486 /* configure rx filter */ 2487 rfilt = ath_calcrxfilter(sc); 2488 ath_hal_setrxfilter(ah, rfilt); 2489 2490 /* configure operational mode */ 2491 ath_hal_setopmode(ah); 2492 2493 /* handle any link-level address change */ 2494 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2495 2496 /* calculate and install multicast filter */ 2497 ath_update_mcast(ifp); 2498 } 2499 2500 /* 2501 * Set the slot time based on the current setting. 2502 */ 2503 static void 2504 ath_setslottime(struct ath_softc *sc) 2505 { 2506 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2507 struct ath_hal *ah = sc->sc_ah; 2508 u_int usec; 2509 2510 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2511 usec = 13; 2512 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2513 usec = 21; 2514 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2515 /* honor short/long slot time only in 11g */ 2516 /* XXX shouldn't honor on pure g or turbo g channel */ 2517 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2518 usec = HAL_SLOT_TIME_9; 2519 else 2520 usec = HAL_SLOT_TIME_20; 2521 } else 2522 usec = HAL_SLOT_TIME_9; 2523 2524 DPRINTF(sc, ATH_DEBUG_RESET, 2525 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2526 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2527 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2528 2529 ath_hal_setslottime(ah, usec); 2530 sc->sc_updateslot = OK; 2531 } 2532 2533 /* 2534 * Callback from the 802.11 layer to update the 2535 * slot time based on the current setting. 2536 */ 2537 static void 2538 ath_updateslot(struct ifnet *ifp) 2539 { 2540 struct ath_softc *sc = ifp->if_softc; 2541 struct ieee80211com *ic = ifp->if_l2com; 2542 2543 /* 2544 * When not coordinating the BSS, change the hardware 2545 * immediately. For other operation we defer the change 2546 * until beacon updates have propagated to the stations. 2547 */ 2548 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2549 ic->ic_opmode == IEEE80211_M_MBSS) 2550 sc->sc_updateslot = UPDATE; 2551 else 2552 ath_setslottime(sc); 2553 } 2554 2555 /* 2556 * Setup a h/w transmit queue for beacons. 2557 */ 2558 static int 2559 ath_beaconq_setup(struct ath_hal *ah) 2560 { 2561 HAL_TXQ_INFO qi; 2562 2563 memset(&qi, 0, sizeof(qi)); 2564 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2565 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2566 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2567 /* NB: for dynamic turbo, don't enable any other interrupts */ 2568 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2569 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2570 } 2571 2572 /* 2573 * Setup the transmit queue parameters for the beacon queue. 2574 */ 2575 static int 2576 ath_beaconq_config(struct ath_softc *sc) 2577 { 2578 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2579 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2580 struct ath_hal *ah = sc->sc_ah; 2581 HAL_TXQ_INFO qi; 2582 2583 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2584 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2585 ic->ic_opmode == IEEE80211_M_MBSS) { 2586 /* 2587 * Always burst out beacon and CAB traffic. 2588 */ 2589 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2590 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2591 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2592 } else { 2593 struct wmeParams *wmep = 2594 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2595 /* 2596 * Adhoc mode; important thing is to use 2x cwmin. 2597 */ 2598 qi.tqi_aifs = wmep->wmep_aifsn; 2599 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2600 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2601 } 2602 2603 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2604 device_printf(sc->sc_dev, "unable to update parameters for " 2605 "beacon hardware queue!\n"); 2606 return 0; 2607 } else { 2608 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2609 return 1; 2610 } 2611 #undef ATH_EXPONENT_TO_VALUE 2612 } 2613 2614 /* 2615 * Allocate and setup an initial beacon frame. 2616 */ 2617 static int 2618 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2619 { 2620 struct ieee80211vap *vap = ni->ni_vap; 2621 struct ath_vap *avp = ATH_VAP(vap); 2622 struct ath_buf *bf; 2623 struct mbuf *m; 2624 int error; 2625 2626 bf = avp->av_bcbuf; 2627 if (bf->bf_m != NULL) { 2628 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2629 m_freem(bf->bf_m); 2630 bf->bf_m = NULL; 2631 } 2632 if (bf->bf_node != NULL) { 2633 ieee80211_free_node(bf->bf_node); 2634 bf->bf_node = NULL; 2635 } 2636 2637 /* 2638 * NB: the beacon data buffer must be 32-bit aligned; 2639 * we assume the mbuf routines will return us something 2640 * with this alignment (perhaps should assert). 2641 */ 2642 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2643 if (m == NULL) { 2644 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2645 sc->sc_stats.ast_be_nombuf++; 2646 return ENOMEM; 2647 } 2648 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2649 bf->bf_segs, 1, &bf->bf_nseg, 2650 BUS_DMA_NOWAIT); 2651 if (error != 0) { 2652 device_printf(sc->sc_dev, 2653 "%s: cannot map mbuf, bus_dmamap_load_mbuf_segment returns %d\n", 2654 __func__, error); 2655 m_freem(m); 2656 return error; 2657 } 2658 2659 /* 2660 * Calculate a TSF adjustment factor required for staggered 2661 * beacons. Note that we assume the format of the beacon 2662 * frame leaves the tstamp field immediately following the 2663 * header. 2664 */ 2665 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2666 uint64_t tsfadjust; 2667 struct ieee80211_frame *wh; 2668 2669 /* 2670 * The beacon interval is in TU's; the TSF is in usecs. 2671 * We figure out how many TU's to add to align the timestamp 2672 * then convert to TSF units and handle byte swapping before 2673 * inserting it in the frame. The hardware will then add this 2674 * each time a beacon frame is sent. Note that we align vap's 2675 * 1..N and leave vap 0 untouched. This means vap 0 has a 2676 * timestamp in one beacon interval while the others get a 2677 * timstamp aligned to the next interval. 2678 */ 2679 tsfadjust = ni->ni_intval * 2680 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2681 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2682 2683 DPRINTF(sc, ATH_DEBUG_BEACON, 2684 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2685 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2686 avp->av_bslot, ni->ni_intval, 2687 (long long unsigned) le64toh(tsfadjust)); 2688 2689 wh = mtod(m, struct ieee80211_frame *); 2690 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2691 } 2692 bf->bf_m = m; 2693 bf->bf_node = ieee80211_ref_node(ni); 2694 2695 return 0; 2696 } 2697 2698 /* 2699 * Setup the beacon frame for transmit. 2700 */ 2701 static void 2702 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2703 { 2704 #define USE_SHPREAMBLE(_ic) \ 2705 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2706 == IEEE80211_F_SHPREAMBLE) 2707 struct ieee80211_node *ni = bf->bf_node; 2708 struct ieee80211com *ic = ni->ni_ic; 2709 struct mbuf *m = bf->bf_m; 2710 struct ath_hal *ah = sc->sc_ah; 2711 struct ath_desc *ds; 2712 int flags, antenna; 2713 const HAL_RATE_TABLE *rt; 2714 u_int8_t rix, rate; 2715 2716 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2717 __func__, m, m->m_len); 2718 2719 /* setup descriptors */ 2720 ds = bf->bf_desc; 2721 2722 flags = HAL_TXDESC_NOACK; 2723 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2724 ds->ds_link = bf->bf_daddr; /* self-linked */ 2725 flags |= HAL_TXDESC_VEOL; 2726 /* 2727 * Let hardware handle antenna switching. 2728 */ 2729 antenna = sc->sc_txantenna; 2730 } else { 2731 ds->ds_link = 0; 2732 /* 2733 * Switch antenna every 4 beacons. 2734 * XXX assumes two antenna 2735 */ 2736 if (sc->sc_txantenna != 0) 2737 antenna = sc->sc_txantenna; 2738 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2739 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2740 else 2741 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2742 } 2743 2744 KASSERT(bf->bf_nseg == 1, 2745 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2746 ds->ds_data = bf->bf_segs[0].ds_addr; 2747 /* 2748 * Calculate rate code. 2749 * XXX everything at min xmit rate 2750 */ 2751 rix = 0; 2752 rt = sc->sc_currates; 2753 rate = rt->info[rix].rateCode; 2754 if (USE_SHPREAMBLE(ic)) 2755 rate |= rt->info[rix].shortPreamble; 2756 ath_hal_setuptxdesc(ah, ds 2757 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2758 , sizeof(struct ieee80211_frame)/* header length */ 2759 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2760 , ni->ni_txpower /* txpower XXX */ 2761 , rate, 1 /* series 0 rate/tries */ 2762 , HAL_TXKEYIX_INVALID /* no encryption */ 2763 , antenna /* antenna mode */ 2764 , flags /* no ack, veol for beacons */ 2765 , 0 /* rts/cts rate */ 2766 , 0 /* rts/cts duration */ 2767 ); 2768 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2769 ath_hal_filltxdesc(ah, ds 2770 , roundup(m->m_len, 4) /* buffer length */ 2771 , AH_TRUE /* first segment */ 2772 , AH_TRUE /* last segment */ 2773 , ds /* first descriptor */ 2774 ); 2775 #if 0 2776 ath_desc_swap(ds); 2777 #endif 2778 #undef USE_SHPREAMBLE 2779 } 2780 2781 static void 2782 ath_beacon_update(struct ieee80211vap *vap, int item) 2783 { 2784 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2785 2786 setbit(bo->bo_flags, item); 2787 } 2788 2789 /* 2790 * Append the contents of src to dst; both queues 2791 * are assumed to be locked. 2792 */ 2793 static void 2794 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2795 { 2796 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2797 if (src->axq_depth) 2798 dst->axq_link = src->axq_link; 2799 src->axq_link = NULL; 2800 dst->axq_depth += src->axq_depth; 2801 src->axq_depth = 0; 2802 } 2803 2804 /* 2805 * Transmit a beacon frame at SWBA. Dynamic updates to the 2806 * frame contents are done as needed and the slot time is 2807 * also adjusted based on current state. 2808 */ 2809 static void 2810 ath_beacon_proc(void *arg, int pending) 2811 { 2812 struct ath_softc *sc = arg; 2813 struct ath_hal *ah = sc->sc_ah; 2814 struct ieee80211vap *vap; 2815 struct ath_buf *bf; 2816 int slot, otherant; 2817 uint32_t bfaddr; 2818 2819 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2820 __func__, pending); 2821 /* 2822 * Check if the previous beacon has gone out. If 2823 * not don't try to post another, skip this period 2824 * and wait for the next. Missed beacons indicate 2825 * a problem and should not occur. If we miss too 2826 * many consecutive beacons reset the device. 2827 */ 2828 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2829 sc->sc_bmisscount++; 2830 DPRINTF(sc, ATH_DEBUG_BEACON, 2831 "%s: missed %u consecutive beacons\n", 2832 __func__, sc->sc_bmisscount); 2833 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2834 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2835 return; 2836 } 2837 if (sc->sc_bmisscount != 0) { 2838 DPRINTF(sc, ATH_DEBUG_BEACON, 2839 "%s: resume beacon xmit after %u misses\n", 2840 __func__, sc->sc_bmisscount); 2841 sc->sc_bmisscount = 0; 2842 } 2843 2844 /* 2845 * Stop any current dma before messing with the beacon linkages. 2846 */ 2847 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2848 DPRINTF(sc, ATH_DEBUG_ANY, 2849 "%s: beacon queue %u did not stop?\n", 2850 __func__, sc->sc_bhalq); 2851 } 2852 2853 if (sc->sc_stagbeacons) { /* staggered beacons */ 2854 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2855 uint32_t tsftu; 2856 2857 tsftu = ath_hal_gettsf32(ah) >> 10; 2858 /* XXX lintval */ 2859 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2860 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2861 bfaddr = 0; 2862 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2863 bf = ath_beacon_generate(sc, vap); 2864 if (bf != NULL) 2865 bfaddr = bf->bf_daddr; 2866 } 2867 } else { /* burst'd beacons */ 2868 uint32_t *bflink = &bfaddr; 2869 2870 for (slot = 0; slot < ATH_BCBUF; slot++) { 2871 vap = sc->sc_bslot[slot]; 2872 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2873 bf = ath_beacon_generate(sc, vap); 2874 if (bf != NULL) { 2875 *bflink = bf->bf_daddr; 2876 bflink = &bf->bf_desc->ds_link; 2877 } 2878 } 2879 } 2880 *bflink = 0; /* terminate list */ 2881 } 2882 2883 /* 2884 * Handle slot time change when a non-ERP station joins/leaves 2885 * an 11g network. The 802.11 layer notifies us via callback, 2886 * we mark updateslot, then wait one beacon before effecting 2887 * the change. This gives associated stations at least one 2888 * beacon interval to note the state change. 2889 */ 2890 /* XXX locking */ 2891 if (sc->sc_updateslot == UPDATE) { 2892 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2893 sc->sc_slotupdate = slot; 2894 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2895 ath_setslottime(sc); /* commit change to h/w */ 2896 2897 /* 2898 * Check recent per-antenna transmit statistics and flip 2899 * the default antenna if noticeably more frames went out 2900 * on the non-default antenna. 2901 * XXX assumes 2 anntenae 2902 */ 2903 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2904 otherant = sc->sc_defant & 1 ? 2 : 1; 2905 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2906 ath_setdefantenna(sc, otherant); 2907 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2908 } 2909 2910 if (bfaddr != 0) { 2911 /* NB: cabq traffic should already be queued and primed */ 2912 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2913 sc->sc_stats.ast_be_xmit++; 2914 ath_hal_txstart(ah, sc->sc_bhalq); 2915 } 2916 /* else no beacon will be generated */ 2917 } 2918 2919 static struct ath_buf * 2920 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2921 { 2922 struct ath_vap *avp = ATH_VAP(vap); 2923 struct ath_txq *cabq = sc->sc_cabq; 2924 struct ath_buf *bf; 2925 struct mbuf *m; 2926 int nmcastq, error; 2927 2928 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2929 ("not running, state %d", vap->iv_state)); 2930 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2931 2932 /* 2933 * Update dynamic beacon contents. If this returns 2934 * non-zero then we need to remap the memory because 2935 * the beacon frame changed size (probably because 2936 * of the TIM bitmap). 2937 */ 2938 bf = avp->av_bcbuf; 2939 m = bf->bf_m; 2940 nmcastq = avp->av_mcastq.axq_depth; 2941 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2942 /* XXX too conservative? */ 2943 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2944 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2945 bf->bf_segs, 1, &bf->bf_nseg, 2946 BUS_DMA_NOWAIT); 2947 if (error != 0) { 2948 if_printf(vap->iv_ifp, 2949 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 2950 __func__, error); 2951 return NULL; 2952 } 2953 } 2954 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2955 DPRINTF(sc, ATH_DEBUG_BEACON, 2956 "%s: cabq did not drain, mcastq %u cabq %u\n", 2957 __func__, nmcastq, cabq->axq_depth); 2958 sc->sc_stats.ast_cabq_busy++; 2959 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2960 /* 2961 * CABQ traffic from a previous vap is still pending. 2962 * We must drain the q before this beacon frame goes 2963 * out as otherwise this vap's stations will get cab 2964 * frames from a different vap. 2965 * XXX could be slow causing us to miss DBA 2966 */ 2967 ath_tx_draintxq(sc, cabq); 2968 } 2969 } 2970 ath_beacon_setup(sc, bf); 2971 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2972 2973 /* 2974 * Enable the CAB queue before the beacon queue to 2975 * insure cab frames are triggered by this beacon. 2976 */ 2977 if (avp->av_boff.bo_tim[4] & 1) { 2978 struct ath_hal *ah = sc->sc_ah; 2979 2980 /* NB: only at DTIM */ 2981 if (nmcastq) { 2982 struct ath_buf *bfm; 2983 int qbusy; 2984 2985 /* 2986 * Move frames from the s/w mcast q to the h/w cab q. 2987 * XXX MORE_DATA bit 2988 */ 2989 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 2990 qbusy = ath_hal_txqenabled(ah, cabq->axq_qnum); 2991 if (qbusy == 0) { 2992 if (cabq->axq_link != NULL) { 2993 cpu_sfence(); 2994 *cabq->axq_link = bfm->bf_daddr; 2995 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 2996 } else { 2997 cpu_sfence(); 2998 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2999 bfm->bf_daddr); 3000 } 3001 } else { 3002 if (cabq->axq_link != NULL) { 3003 cpu_sfence(); 3004 *cabq->axq_link = bfm->bf_daddr; 3005 } 3006 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 3007 } 3008 ath_txqmove(cabq, &avp->av_mcastq); 3009 3010 sc->sc_stats.ast_cabq_xmit += nmcastq; 3011 } 3012 /* NB: gated by beacon so safe to start here */ 3013 ath_hal_txstart(ah, cabq->axq_qnum); 3014 } 3015 return bf; 3016 } 3017 3018 static void 3019 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3020 { 3021 struct ath_vap *avp = ATH_VAP(vap); 3022 struct ath_hal *ah = sc->sc_ah; 3023 struct ath_buf *bf; 3024 struct mbuf *m; 3025 int error; 3026 3027 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3028 3029 /* 3030 * Update dynamic beacon contents. If this returns 3031 * non-zero then we need to remap the memory because 3032 * the beacon frame changed size (probably because 3033 * of the TIM bitmap). 3034 */ 3035 bf = avp->av_bcbuf; 3036 m = bf->bf_m; 3037 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3038 /* XXX too conservative? */ 3039 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3040 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 3041 bf->bf_segs, 1, &bf->bf_nseg, 3042 BUS_DMA_NOWAIT); 3043 if (error != 0) { 3044 if_printf(vap->iv_ifp, 3045 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 3046 __func__, error); 3047 return; 3048 } 3049 } 3050 ath_beacon_setup(sc, bf); 3051 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3052 3053 /* NB: caller is known to have already stopped tx dma */ 3054 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3055 ath_hal_txstart(ah, sc->sc_bhalq); 3056 } 3057 3058 /* 3059 * Reset the hardware after detecting beacons have stopped. 3060 */ 3061 static void 3062 ath_bstuck_task(void *arg, int pending) 3063 { 3064 struct ath_softc *sc = arg; 3065 struct ifnet *ifp = sc->sc_ifp; 3066 3067 wlan_serialize_enter(); 3068 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3069 sc->sc_bmisscount); 3070 sc->sc_stats.ast_bstuck++; 3071 ath_reset(ifp); 3072 wlan_serialize_exit(); 3073 } 3074 3075 /* 3076 * Reclaim beacon resources and return buffer to the pool. 3077 */ 3078 static void 3079 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3080 { 3081 3082 if (bf->bf_m != NULL) { 3083 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3084 m_freem(bf->bf_m); 3085 bf->bf_m = NULL; 3086 } 3087 if (bf->bf_node != NULL) { 3088 ieee80211_free_node(bf->bf_node); 3089 bf->bf_node = NULL; 3090 } 3091 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3092 } 3093 3094 /* 3095 * Reclaim beacon resources. 3096 */ 3097 static void 3098 ath_beacon_free(struct ath_softc *sc) 3099 { 3100 struct ath_buf *bf; 3101 3102 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3103 if (bf->bf_m != NULL) { 3104 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3105 m_freem(bf->bf_m); 3106 bf->bf_m = NULL; 3107 } 3108 if (bf->bf_node != NULL) { 3109 ieee80211_free_node(bf->bf_node); 3110 bf->bf_node = NULL; 3111 } 3112 } 3113 } 3114 3115 /* 3116 * Configure the beacon and sleep timers. 3117 * 3118 * When operating as an AP this resets the TSF and sets 3119 * up the hardware to notify us when we need to issue beacons. 3120 * 3121 * When operating in station mode this sets up the beacon 3122 * timers according to the timestamp of the last received 3123 * beacon and the current TSF, configures PCF and DTIM 3124 * handling, programs the sleep registers so the hardware 3125 * will wakeup in time to receive beacons, and configures 3126 * the beacon miss handling so we'll receive a BMISS 3127 * interrupt when we stop seeing beacons from the AP 3128 * we've associated with. 3129 */ 3130 static void 3131 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3132 { 3133 #define TSF_TO_TU(_h,_l) \ 3134 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3135 #define FUDGE 2 3136 struct ath_hal *ah = sc->sc_ah; 3137 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3138 struct ieee80211_node *ni; 3139 u_int32_t nexttbtt, intval, tsftu; 3140 u_int64_t tsf; 3141 3142 if (vap == NULL) 3143 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3144 ni = vap->iv_bss; 3145 3146 /* extract tstamp from last beacon and convert to TU */ 3147 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3148 LE_READ_4(ni->ni_tstamp.data)); 3149 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3150 ic->ic_opmode == IEEE80211_M_MBSS) { 3151 /* 3152 * For multi-bss ap/mesh support beacons are either staggered 3153 * evenly over N slots or burst together. For the former 3154 * arrange for the SWBA to be delivered for each slot. 3155 * Slots that are not occupied will generate nothing. 3156 */ 3157 /* NB: the beacon interval is kept internally in TU's */ 3158 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3159 if (sc->sc_stagbeacons) 3160 intval /= ATH_BCBUF; 3161 } else { 3162 /* NB: the beacon interval is kept internally in TU's */ 3163 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3164 } 3165 if (nexttbtt == 0) /* e.g. for ap mode */ 3166 nexttbtt = intval; 3167 else if (intval) /* NB: can be 0 for monitor mode */ 3168 nexttbtt = roundup(nexttbtt, intval); 3169 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3170 __func__, nexttbtt, intval, ni->ni_intval); 3171 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3172 HAL_BEACON_STATE bs; 3173 int dtimperiod, dtimcount; 3174 int cfpperiod, cfpcount; 3175 3176 /* 3177 * Setup dtim and cfp parameters according to 3178 * last beacon we received (which may be none). 3179 */ 3180 dtimperiod = ni->ni_dtim_period; 3181 if (dtimperiod <= 0) /* NB: 0 if not known */ 3182 dtimperiod = 1; 3183 dtimcount = ni->ni_dtim_count; 3184 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3185 dtimcount = 0; /* XXX? */ 3186 cfpperiod = 1; /* NB: no PCF support yet */ 3187 cfpcount = 0; 3188 /* 3189 * Pull nexttbtt forward to reflect the current 3190 * TSF and calculate dtim+cfp state for the result. 3191 */ 3192 tsf = ath_hal_gettsf64(ah); 3193 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3194 do { 3195 nexttbtt += intval; 3196 if (--dtimcount < 0) { 3197 dtimcount = dtimperiod - 1; 3198 if (--cfpcount < 0) 3199 cfpcount = cfpperiod - 1; 3200 } 3201 } while (nexttbtt < tsftu); 3202 memset(&bs, 0, sizeof(bs)); 3203 bs.bs_intval = intval; 3204 bs.bs_nexttbtt = nexttbtt; 3205 bs.bs_dtimperiod = dtimperiod*intval; 3206 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3207 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3208 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3209 bs.bs_cfpmaxduration = 0; 3210 #if 0 3211 /* 3212 * The 802.11 layer records the offset to the DTIM 3213 * bitmap while receiving beacons; use it here to 3214 * enable h/w detection of our AID being marked in 3215 * the bitmap vector (to indicate frames for us are 3216 * pending at the AP). 3217 * XXX do DTIM handling in s/w to WAR old h/w bugs 3218 * XXX enable based on h/w rev for newer chips 3219 */ 3220 bs.bs_timoffset = ni->ni_timoff; 3221 #endif 3222 /* 3223 * Calculate the number of consecutive beacons to miss 3224 * before taking a BMISS interrupt. 3225 * Note that we clamp the result to at most 10 beacons. 3226 */ 3227 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3228 if (bs.bs_bmissthreshold > 10) 3229 bs.bs_bmissthreshold = 10; 3230 else if (bs.bs_bmissthreshold <= 0) 3231 bs.bs_bmissthreshold = 1; 3232 3233 /* 3234 * Calculate sleep duration. The configuration is 3235 * given in ms. We insure a multiple of the beacon 3236 * period is used. Also, if the sleep duration is 3237 * greater than the DTIM period then it makes senses 3238 * to make it a multiple of that. 3239 * 3240 * XXX fixed at 100ms 3241 */ 3242 bs.bs_sleepduration = 3243 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3244 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3245 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3246 3247 DPRINTF(sc, ATH_DEBUG_BEACON, 3248 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3249 , __func__ 3250 , tsf, tsftu 3251 , bs.bs_intval 3252 , bs.bs_nexttbtt 3253 , bs.bs_dtimperiod 3254 , bs.bs_nextdtim 3255 , bs.bs_bmissthreshold 3256 , bs.bs_sleepduration 3257 , bs.bs_cfpperiod 3258 , bs.bs_cfpmaxduration 3259 , bs.bs_cfpnext 3260 , bs.bs_timoffset 3261 ); 3262 ath_hal_intrset(ah, 0); 3263 ath_hal_beacontimers(ah, &bs); 3264 sc->sc_imask |= HAL_INT_BMISS; 3265 ath_hal_intrset(ah, sc->sc_imask); 3266 } else { 3267 ath_hal_intrset(ah, 0); 3268 if (nexttbtt == intval) 3269 intval |= HAL_BEACON_RESET_TSF; 3270 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3271 /* 3272 * In IBSS mode enable the beacon timers but only 3273 * enable SWBA interrupts if we need to manually 3274 * prepare beacon frames. Otherwise we use a 3275 * self-linked tx descriptor and let the hardware 3276 * deal with things. 3277 */ 3278 intval |= HAL_BEACON_ENA; 3279 if (!sc->sc_hasveol) 3280 sc->sc_imask |= HAL_INT_SWBA; 3281 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3282 /* 3283 * Pull nexttbtt forward to reflect 3284 * the current TSF. 3285 */ 3286 tsf = ath_hal_gettsf64(ah); 3287 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3288 do { 3289 nexttbtt += intval; 3290 } while (nexttbtt < tsftu); 3291 } 3292 ath_beaconq_config(sc); 3293 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3294 ic->ic_opmode == IEEE80211_M_MBSS) { 3295 /* 3296 * In AP/mesh mode we enable the beacon timers 3297 * and SWBA interrupts to prepare beacon frames. 3298 */ 3299 intval |= HAL_BEACON_ENA; 3300 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3301 ath_beaconq_config(sc); 3302 } 3303 ath_hal_beaconinit(ah, nexttbtt, intval); 3304 sc->sc_bmisscount = 0; 3305 ath_hal_intrset(ah, sc->sc_imask); 3306 /* 3307 * When using a self-linked beacon descriptor in 3308 * ibss mode load it once here. 3309 */ 3310 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3311 ath_beacon_start_adhoc(sc, vap); 3312 } 3313 sc->sc_syncbeacon = 0; 3314 #undef FUDGE 3315 #undef TSF_TO_TU 3316 } 3317 3318 static void 3319 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3320 { 3321 bus_addr_t *paddr = (bus_addr_t*) arg; 3322 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3323 *paddr = segs->ds_addr; 3324 } 3325 3326 static int 3327 ath_descdma_setup(struct ath_softc *sc, 3328 struct ath_descdma *dd, ath_bufhead *head, 3329 const char *name, int nbuf, int ndesc) 3330 { 3331 #define DS2PHYS(_dd, _ds) \ 3332 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3333 struct ifnet *ifp = sc->sc_ifp; 3334 struct ath_desc *ds; 3335 struct ath_buf *bf; 3336 int i, bsize, error; 3337 3338 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3339 __func__, name, nbuf, ndesc); 3340 3341 dd->dd_name = name; 3342 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3343 3344 /* 3345 * Setup DMA descriptor area. 3346 */ 3347 error = bus_dma_tag_create(dd->dd_dmat, /* parent */ 3348 PAGE_SIZE, 0, /* alignment, bounds */ 3349 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3350 BUS_SPACE_MAXADDR, /* highaddr */ 3351 NULL, NULL, /* filter, filterarg */ 3352 dd->dd_desc_len, /* maxsize */ 3353 1, /* nsegments */ 3354 dd->dd_desc_len, /* maxsegsize */ 3355 BUS_DMA_ALLOCNOW, /* flags */ 3356 &dd->dd_dmat); 3357 if (error != 0) { 3358 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3359 return error; 3360 } 3361 3362 /* allocate descriptors */ 3363 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3364 if (error != 0) { 3365 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3366 "error %u\n", dd->dd_name, error); 3367 goto fail0; 3368 } 3369 3370 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3371 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3372 &dd->dd_dmamap); 3373 if (error != 0) { 3374 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3375 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3376 goto fail1; 3377 } 3378 3379 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3380 dd->dd_desc, dd->dd_desc_len, 3381 ath_load_cb, &dd->dd_desc_paddr, 3382 BUS_DMA_NOWAIT); 3383 if (error != 0) { 3384 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3385 dd->dd_name, error); 3386 goto fail2; 3387 } 3388 3389 ds = dd->dd_desc; 3390 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3391 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3392 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3393 3394 /* allocate rx buffers */ 3395 bsize = sizeof(struct ath_buf) * nbuf; 3396 bf = kmalloc(bsize, M_ATHDEV, M_INTWAIT | M_ZERO); 3397 if (bf == NULL) { 3398 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3399 dd->dd_name, bsize); 3400 goto fail3; 3401 } 3402 dd->dd_bufptr = bf; 3403 3404 STAILQ_INIT(head); 3405 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3406 bf->bf_desc = ds; 3407 bf->bf_daddr = DS2PHYS(dd, ds); 3408 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3409 &bf->bf_dmamap); 3410 if (error != 0) { 3411 if_printf(ifp, "unable to create dmamap for %s " 3412 "buffer %u, error %u\n", dd->dd_name, i, error); 3413 ath_descdma_cleanup(sc, dd, head); 3414 return error; 3415 } 3416 STAILQ_INSERT_TAIL(head, bf, bf_list); 3417 } 3418 return 0; 3419 fail3: 3420 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3421 fail2: 3422 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3423 fail1: 3424 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3425 fail0: 3426 bus_dma_tag_destroy(dd->dd_dmat); 3427 memset(dd, 0, sizeof(*dd)); 3428 return error; 3429 #undef DS2PHYS 3430 } 3431 3432 static void 3433 ath_descdma_cleanup(struct ath_softc *sc, 3434 struct ath_descdma *dd, ath_bufhead *head) 3435 { 3436 struct ath_buf *bf; 3437 struct ieee80211_node *ni; 3438 3439 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3440 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3441 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3442 bus_dma_tag_destroy(dd->dd_dmat); 3443 3444 STAILQ_FOREACH(bf, head, bf_list) { 3445 if (bf->bf_m) { 3446 m_freem(bf->bf_m); 3447 bf->bf_m = NULL; 3448 } 3449 if (bf->bf_dmamap != NULL) { 3450 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3451 bf->bf_dmamap = NULL; 3452 } 3453 ni = bf->bf_node; 3454 bf->bf_node = NULL; 3455 if (ni != NULL) { 3456 /* 3457 * Reclaim node reference. 3458 */ 3459 ieee80211_free_node(ni); 3460 } 3461 } 3462 3463 STAILQ_INIT(head); 3464 kfree(dd->dd_bufptr, M_ATHDEV); 3465 memset(dd, 0, sizeof(*dd)); 3466 } 3467 3468 static int 3469 ath_desc_alloc(struct ath_softc *sc) 3470 { 3471 int error; 3472 3473 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3474 "rx", ath_rxbuf, 1); 3475 if (error != 0) 3476 return error; 3477 3478 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3479 "tx", ath_txbuf, ATH_TXDESC); 3480 if (error != 0) { 3481 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3482 return error; 3483 } 3484 3485 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3486 "beacon", ATH_BCBUF, 1); 3487 if (error != 0) { 3488 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3489 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3490 return error; 3491 } 3492 return 0; 3493 } 3494 3495 static void 3496 ath_desc_free(struct ath_softc *sc) 3497 { 3498 3499 if (sc->sc_bdma.dd_desc_len != 0) 3500 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3501 if (sc->sc_txdma.dd_desc_len != 0) 3502 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3503 if (sc->sc_rxdma.dd_desc_len != 0) 3504 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3505 } 3506 3507 static struct ieee80211_node * 3508 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3509 { 3510 struct ieee80211com *ic = vap->iv_ic; 3511 struct ath_softc *sc = ic->ic_ifp->if_softc; 3512 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3513 struct ath_node *an; 3514 3515 an = kmalloc(space, M_80211_NODE, M_INTWAIT|M_ZERO); 3516 if (an == NULL) { 3517 /* XXX stat+msg */ 3518 return NULL; 3519 } 3520 ath_rate_node_init(sc, an); 3521 3522 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3523 return &an->an_node; 3524 } 3525 3526 static void 3527 ath_node_free(struct ieee80211_node *ni) 3528 { 3529 struct ieee80211com *ic = ni->ni_ic; 3530 struct ath_softc *sc = ic->ic_ifp->if_softc; 3531 3532 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3533 3534 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3535 sc->sc_node_free(ni); 3536 } 3537 3538 static void 3539 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3540 { 3541 struct ieee80211com *ic = ni->ni_ic; 3542 struct ath_softc *sc = ic->ic_ifp->if_softc; 3543 struct ath_hal *ah = sc->sc_ah; 3544 3545 *rssi = ic->ic_node_getrssi(ni); 3546 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3547 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3548 else 3549 *noise = -95; /* nominally correct */ 3550 } 3551 3552 static int 3553 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3554 { 3555 struct ath_hal *ah = sc->sc_ah; 3556 int error; 3557 struct mbuf *m; 3558 struct ath_desc *ds; 3559 3560 m = bf->bf_m; 3561 if (m == NULL) { 3562 /* 3563 * NB: by assigning a page to the rx dma buffer we 3564 * implicitly satisfy the Atheros requirement that 3565 * this buffer be cache-line-aligned and sized to be 3566 * multiple of the cache line size. Not doing this 3567 * causes weird stuff to happen (for the 5210 at least). 3568 */ 3569 m = m_getcl(MB_WAIT, MT_DATA, M_PKTHDR); 3570 if (m == NULL) { 3571 kprintf("ath_rxbuf_init: no mbuf\n"); 3572 DPRINTF(sc, ATH_DEBUG_ANY, 3573 "%s: no mbuf/cluster\n", __func__); 3574 sc->sc_stats.ast_rx_nombuf++; 3575 return ENOMEM; 3576 } 3577 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3578 3579 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 3580 bf->bf_dmamap, m, 3581 bf->bf_segs, 1, &bf->bf_nseg, 3582 BUS_DMA_NOWAIT); 3583 if (error != 0) { 3584 DPRINTF(sc, ATH_DEBUG_ANY, 3585 "%s: bus_dmamap_load_mbuf_segment failed; error %d\n", 3586 __func__, error); 3587 sc->sc_stats.ast_rx_busdma++; 3588 m_freem(m); 3589 return error; 3590 } 3591 KASSERT(bf->bf_nseg == 1, 3592 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3593 bf->bf_m = m; 3594 } 3595 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3596 3597 /* 3598 * Setup descriptors. For receive we always terminate 3599 * the descriptor list with a self-linked entry so we'll 3600 * not get overrun under high load (as can happen with a 3601 * 5212 when ANI processing enables PHY error frames). 3602 * 3603 * To insure the last descriptor is self-linked we create 3604 * each descriptor as self-linked and add it to the end. As 3605 * each additional descriptor is added the previous self-linked 3606 * entry is ``fixed'' naturally. This should be safe even 3607 * if DMA is happening. When processing RX interrupts we 3608 * never remove/process the last, self-linked, entry on the 3609 * descriptor list. This insures the hardware always has 3610 * someplace to write a new frame. 3611 */ 3612 ds = bf->bf_desc; 3613 ds->ds_link = bf->bf_daddr; /* link to self */ 3614 ds->ds_data = bf->bf_segs[0].ds_addr; 3615 ath_hal_setuprxdesc(ah, ds 3616 , m->m_len /* buffer size */ 3617 , 0 3618 ); 3619 3620 if (sc->sc_rxlink != NULL) 3621 *sc->sc_rxlink = bf->bf_daddr; 3622 sc->sc_rxlink = &ds->ds_link; 3623 return 0; 3624 } 3625 3626 /* 3627 * Extend 15-bit time stamp from rx descriptor to 3628 * a full 64-bit TSF using the specified TSF. 3629 */ 3630 static __inline u_int64_t 3631 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3632 { 3633 if ((tsf & 0x7fff) < rstamp) 3634 tsf -= 0x8000; 3635 return ((tsf &~ 0x7fff) | rstamp); 3636 } 3637 3638 /* 3639 * Intercept management frames to collect beacon rssi data 3640 * and to do ibss merges. 3641 */ 3642 static void 3643 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3644 int subtype, int rssi, int nf) 3645 { 3646 struct ieee80211vap *vap = ni->ni_vap; 3647 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3648 3649 /* 3650 * Call up first so subsequent work can use information 3651 * potentially stored in the node (e.g. for ibss merge). 3652 */ 3653 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3654 switch (subtype) { 3655 case IEEE80211_FC0_SUBTYPE_BEACON: 3656 /* update rssi statistics for use by the hal */ 3657 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3658 if (sc->sc_syncbeacon && 3659 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3660 /* 3661 * Resync beacon timers using the tsf of the beacon 3662 * frame we just received. 3663 */ 3664 ath_beacon_config(sc, vap); 3665 } 3666 /* fall thru... */ 3667 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3668 if (vap->iv_opmode == IEEE80211_M_IBSS && 3669 vap->iv_state == IEEE80211_S_RUN) { 3670 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3671 u_int64_t tsf = ath_extend_tsf(rstamp, 3672 ath_hal_gettsf64(sc->sc_ah)); 3673 /* 3674 * Handle ibss merge as needed; check the tsf on the 3675 * frame before attempting the merge. The 802.11 spec 3676 * says the station should change it's bssid to match 3677 * the oldest station with the same ssid, where oldest 3678 * is determined by the tsf. Note that hardware 3679 * reconfiguration happens through callback to 3680 * ath_newstate as the state machine will go from 3681 * RUN -> RUN when this happens. 3682 */ 3683 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3684 DPRINTF(sc, ATH_DEBUG_STATE, 3685 "ibss merge, rstamp %u tsf %ju " 3686 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3687 (uintmax_t)ni->ni_tstamp.tsf); 3688 (void) ieee80211_ibss_merge(ni); 3689 } 3690 } 3691 break; 3692 } 3693 } 3694 3695 /* 3696 * Set the default antenna. 3697 */ 3698 static void 3699 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3700 { 3701 struct ath_hal *ah = sc->sc_ah; 3702 3703 /* XXX block beacon interrupts */ 3704 ath_hal_setdefantenna(ah, antenna); 3705 if (sc->sc_defant != antenna) 3706 sc->sc_stats.ast_ant_defswitch++; 3707 sc->sc_defant = antenna; 3708 sc->sc_rxotherant = 0; 3709 } 3710 3711 static void 3712 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3713 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3714 { 3715 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3716 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3717 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3718 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3719 struct ath_softc *sc = ifp->if_softc; 3720 const HAL_RATE_TABLE *rt; 3721 uint8_t rix; 3722 3723 rt = sc->sc_currates; 3724 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3725 rix = rt->rateCodeToIndex[rs->rs_rate]; 3726 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3727 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3728 #ifdef AH_SUPPORT_AR5416 3729 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3730 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3731 struct ieee80211com *ic = ifp->if_l2com; 3732 3733 if ((rs->rs_flags & HAL_RX_2040) == 0) 3734 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3735 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3736 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3737 else 3738 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3739 if ((rs->rs_flags & HAL_RX_GI) == 0) 3740 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3741 } 3742 #endif 3743 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3744 if (rs->rs_status & HAL_RXERR_CRC) 3745 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3746 /* XXX propagate other error flags from descriptor */ 3747 sc->sc_rx_th.wr_antnoise = nf; 3748 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3749 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3750 #undef CHAN_HT 3751 #undef CHAN_HT20 3752 #undef CHAN_HT40U 3753 #undef CHAN_HT40D 3754 } 3755 3756 static void 3757 ath_handle_micerror(struct ieee80211com *ic, 3758 struct ieee80211_frame *wh, int keyix) 3759 { 3760 struct ieee80211_node *ni; 3761 3762 /* XXX recheck MIC to deal w/ chips that lie */ 3763 /* XXX discard MIC errors on !data frames */ 3764 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3765 if (ni != NULL) { 3766 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3767 ieee80211_free_node(ni); 3768 } 3769 } 3770 3771 static void 3772 ath_rx_task(void *arg, int npending) 3773 { 3774 #define PA2DESC(_sc, _pa) \ 3775 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3776 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3777 struct ath_softc *sc = arg; 3778 struct ath_buf *bf; 3779 struct ifnet *ifp; 3780 struct ieee80211com *ic; 3781 struct ath_hal *ah; 3782 struct ath_desc *ds; 3783 struct ath_rx_status *rs; 3784 struct mbuf *m; 3785 struct ieee80211_node *ni; 3786 int len, type, ngood; 3787 u_int phyerr; 3788 HAL_STATUS status; 3789 int16_t nf; 3790 u_int64_t tsf; 3791 3792 wlan_serialize_enter(); 3793 ifp = sc->sc_ifp; 3794 ic = ifp->if_l2com; 3795 ah = sc->sc_ah; 3796 3797 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3798 ngood = 0; 3799 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3800 sc->sc_stats.ast_rx_noise = nf; 3801 tsf = ath_hal_gettsf64(ah); 3802 do { 3803 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3804 if (bf == NULL) { /* NB: shouldn't happen */ 3805 if_printf(ifp, "%s: no buffer!\n", __func__); 3806 break; 3807 } 3808 m = bf->bf_m; 3809 if (m == NULL) { /* NB: shouldn't happen */ 3810 /* 3811 * If mbuf allocation failed previously there 3812 * will be no mbuf; try again to re-populate it. 3813 */ 3814 /* XXX make debug msg */ 3815 if_printf(ifp, "%s: no mbuf!\n", __func__); 3816 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3817 goto rx_next; 3818 } 3819 ds = bf->bf_desc; 3820 if (ds->ds_link == bf->bf_daddr) { 3821 /* NB: never process the self-linked entry at the end */ 3822 break; 3823 } 3824 /* XXX sync descriptor memory */ 3825 /* 3826 * Must provide the virtual address of the current 3827 * descriptor, the physical address, and the virtual 3828 * address of the next descriptor in the h/w chain. 3829 * This allows the HAL to look ahead to see if the 3830 * hardware is done with a descriptor by checking the 3831 * done bit in the following descriptor and the address 3832 * of the current descriptor the DMA engine is working 3833 * on. All this is necessary because of our use of 3834 * a self-linked list to avoid rx overruns. 3835 */ 3836 rs = &bf->bf_status.ds_rxstat; 3837 status = ath_hal_rxprocdesc(ah, ds, 3838 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3839 #ifdef ATH_DEBUG 3840 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3841 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3842 #endif 3843 if (status == HAL_EINPROGRESS) 3844 break; 3845 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3846 if (rs->rs_status != 0) { 3847 if (rs->rs_status & HAL_RXERR_CRC) 3848 sc->sc_stats.ast_rx_crcerr++; 3849 if (rs->rs_status & HAL_RXERR_FIFO) 3850 sc->sc_stats.ast_rx_fifoerr++; 3851 if (rs->rs_status & HAL_RXERR_PHY) { 3852 sc->sc_stats.ast_rx_phyerr++; 3853 phyerr = rs->rs_phyerr & 0x1f; 3854 sc->sc_stats.ast_rx_phy[phyerr]++; 3855 goto rx_error; /* NB: don't count in ierrors */ 3856 } 3857 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3858 /* 3859 * Decrypt error. If the error occurred 3860 * because there was no hardware key, then 3861 * let the frame through so the upper layers 3862 * can process it. This is necessary for 5210 3863 * parts which have no way to setup a ``clear'' 3864 * key cache entry. 3865 * 3866 * XXX do key cache faulting 3867 */ 3868 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3869 goto rx_accept; 3870 sc->sc_stats.ast_rx_badcrypt++; 3871 } 3872 if (rs->rs_status & HAL_RXERR_MIC) { 3873 sc->sc_stats.ast_rx_badmic++; 3874 /* 3875 * Do minimal work required to hand off 3876 * the 802.11 header for notification. 3877 */ 3878 /* XXX frag's and qos frames */ 3879 len = rs->rs_datalen; 3880 if (len >= sizeof (struct ieee80211_frame)) { 3881 bus_dmamap_sync(sc->sc_dmat, 3882 bf->bf_dmamap, 3883 BUS_DMASYNC_POSTREAD); 3884 ath_handle_micerror(ic, 3885 mtod(m, struct ieee80211_frame *), 3886 sc->sc_splitmic ? 3887 rs->rs_keyix-32 : rs->rs_keyix); 3888 } 3889 } 3890 ifp->if_ierrors++; 3891 rx_error: 3892 /* 3893 * Cleanup any pending partial frame. 3894 */ 3895 if (sc->sc_rxpending != NULL) { 3896 m_freem(sc->sc_rxpending); 3897 sc->sc_rxpending = NULL; 3898 } 3899 /* 3900 * When a tap is present pass error frames 3901 * that have been requested. By default we 3902 * pass decrypt+mic errors but others may be 3903 * interesting (e.g. crc). 3904 */ 3905 if (ieee80211_radiotap_active(ic) && 3906 (rs->rs_status & sc->sc_monpass)) { 3907 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3908 BUS_DMASYNC_POSTREAD); 3909 /* NB: bpf needs the mbuf length setup */ 3910 len = rs->rs_datalen; 3911 m->m_pkthdr.len = m->m_len = len; 3912 ath_rx_tap(ifp, m, rs, tsf, nf); 3913 ieee80211_radiotap_rx_all(ic, m); 3914 } 3915 /* XXX pass MIC errors up for s/w reclaculation */ 3916 goto rx_next; 3917 } 3918 rx_accept: 3919 /* 3920 * Sync and unmap the frame. At this point we're 3921 * committed to passing the mbuf somewhere so clear 3922 * bf_m; this means a new mbuf must be allocated 3923 * when the rx descriptor is setup again to receive 3924 * another frame. 3925 */ 3926 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3927 BUS_DMASYNC_POSTREAD); 3928 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3929 bf->bf_m = NULL; 3930 3931 len = rs->rs_datalen; 3932 m->m_len = len; 3933 3934 if (rs->rs_more) { 3935 /* 3936 * Frame spans multiple descriptors; save 3937 * it for the next completed descriptor, it 3938 * will be used to construct a jumbogram. 3939 */ 3940 if (sc->sc_rxpending != NULL) { 3941 /* NB: max frame size is currently 2 clusters */ 3942 sc->sc_stats.ast_rx_toobig++; 3943 m_freem(sc->sc_rxpending); 3944 } 3945 m->m_pkthdr.rcvif = ifp; 3946 m->m_pkthdr.len = len; 3947 sc->sc_rxpending = m; 3948 goto rx_next; 3949 } else if (sc->sc_rxpending != NULL) { 3950 /* 3951 * This is the second part of a jumbogram, 3952 * chain it to the first mbuf, adjust the 3953 * frame length, and clear the rxpending state. 3954 */ 3955 sc->sc_rxpending->m_next = m; 3956 sc->sc_rxpending->m_pkthdr.len += len; 3957 m = sc->sc_rxpending; 3958 sc->sc_rxpending = NULL; 3959 } else { 3960 /* 3961 * Normal single-descriptor receive; setup 3962 * the rcvif and packet length. 3963 */ 3964 m->m_pkthdr.rcvif = ifp; 3965 m->m_pkthdr.len = len; 3966 } 3967 3968 ifp->if_ipackets++; 3969 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3970 3971 /* 3972 * Populate the rx status block. When there are bpf 3973 * listeners we do the additional work to provide 3974 * complete status. Otherwise we fill in only the 3975 * material required by ieee80211_input. Note that 3976 * noise setting is filled in above. 3977 */ 3978 if (ieee80211_radiotap_active(ic)) 3979 ath_rx_tap(ifp, m, rs, tsf, nf); 3980 3981 /* 3982 * From this point on we assume the frame is at least 3983 * as large as ieee80211_frame_min; verify that. 3984 */ 3985 if (len < IEEE80211_MIN_LEN) { 3986 if (!ieee80211_radiotap_active(ic)) { 3987 DPRINTF(sc, ATH_DEBUG_RECV, 3988 "%s: short packet %d\n", __func__, len); 3989 sc->sc_stats.ast_rx_tooshort++; 3990 } else { 3991 /* NB: in particular this captures ack's */ 3992 ieee80211_radiotap_rx_all(ic, m); 3993 } 3994 m_freem(m); 3995 goto rx_next; 3996 } 3997 3998 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3999 const HAL_RATE_TABLE *rt = sc->sc_currates; 4000 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 4001 4002 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 4003 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 4004 } 4005 4006 m_adj(m, -IEEE80211_CRC_LEN); 4007 4008 /* 4009 * Locate the node for sender, track state, and then 4010 * pass the (referenced) node up to the 802.11 layer 4011 * for its use. 4012 */ 4013 ni = ieee80211_find_rxnode_withkey(ic, 4014 mtod(m, const struct ieee80211_frame_min *), 4015 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4016 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4017 if (ni != NULL) { 4018 /* 4019 * Sending station is known, dispatch directly. 4020 */ 4021 sc->sc_lastrs = rs; 4022 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 4023 ieee80211_free_node(ni); 4024 /* 4025 * Arrange to update the last rx timestamp only for 4026 * frames from our ap when operating in station mode. 4027 * This assumes the rx key is always setup when 4028 * associated. 4029 */ 4030 if (ic->ic_opmode == IEEE80211_M_STA && 4031 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4032 ngood++; 4033 } else { 4034 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 4035 } 4036 /* 4037 * Track rx rssi and do any rx antenna management. 4038 */ 4039 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4040 if (sc->sc_diversity) { 4041 /* 4042 * When using fast diversity, change the default rx 4043 * antenna if diversity chooses the other antenna 3 4044 * times in a row. 4045 */ 4046 if (sc->sc_defant != rs->rs_antenna) { 4047 if (++sc->sc_rxotherant >= 3) 4048 ath_setdefantenna(sc, rs->rs_antenna); 4049 } else 4050 sc->sc_rxotherant = 0; 4051 } 4052 if (sc->sc_softled) { 4053 /* 4054 * Blink for any data frame. Otherwise do a 4055 * heartbeat-style blink when idle. The latter 4056 * is mainly for station mode where we depend on 4057 * periodic beacon frames to trigger the poll event. 4058 */ 4059 if (type == IEEE80211_FC0_TYPE_DATA) { 4060 const HAL_RATE_TABLE *rt = sc->sc_currates; 4061 ath_led_event(sc, 4062 rt->rateCodeToIndex[rs->rs_rate]); 4063 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4064 ath_led_event(sc, 0); 4065 } 4066 rx_next: 4067 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4068 } while (ath_rxbuf_init(sc, bf) == 0); 4069 4070 /* rx signal state monitoring */ 4071 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4072 if (ngood) 4073 sc->sc_lastrx = tsf; 4074 4075 if ((ifp->if_flags & IFF_OACTIVE) == 0) { 4076 #ifdef IEEE80211_SUPPORT_SUPERG 4077 ieee80211_ff_age_all(ic, 100); 4078 #endif 4079 if (!ifq_is_empty(&ifp->if_snd)) 4080 ath_start(ifp); 4081 } 4082 wlan_serialize_exit(); 4083 #undef PA2DESC 4084 } 4085 4086 static void 4087 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4088 { 4089 txq->axq_qnum = qnum; 4090 txq->axq_ac = 0; 4091 txq->axq_depth = 0; 4092 txq->axq_intrcnt = 0; 4093 txq->axq_link = NULL; 4094 STAILQ_INIT(&txq->axq_q); 4095 } 4096 4097 /* 4098 * Setup a h/w transmit queue. 4099 */ 4100 static struct ath_txq * 4101 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4102 { 4103 #define N(a) (sizeof(a)/sizeof(a[0])) 4104 struct ath_hal *ah = sc->sc_ah; 4105 HAL_TXQ_INFO qi; 4106 int qnum; 4107 4108 memset(&qi, 0, sizeof(qi)); 4109 qi.tqi_subtype = subtype; 4110 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4111 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4112 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4113 /* 4114 * Enable interrupts only for EOL and DESC conditions. 4115 * We mark tx descriptors to receive a DESC interrupt 4116 * when a tx queue gets deep; otherwise waiting for the 4117 * EOL to reap descriptors. Note that this is done to 4118 * reduce interrupt load and this only defers reaping 4119 * descriptors, never transmitting frames. Aside from 4120 * reducing interrupts this also permits more concurrency. 4121 * The only potential downside is if the tx queue backs 4122 * up in which case the top half of the kernel may backup 4123 * due to a lack of tx descriptors. 4124 */ 4125 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4126 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4127 if (qnum == -1) { 4128 /* 4129 * NB: don't print a message, this happens 4130 * normally on parts with too few tx queues 4131 */ 4132 return NULL; 4133 } 4134 if (qnum >= N(sc->sc_txq)) { 4135 device_printf(sc->sc_dev, 4136 "hal qnum %u out of range, max %zu!\n", 4137 qnum, N(sc->sc_txq)); 4138 ath_hal_releasetxqueue(ah, qnum); 4139 return NULL; 4140 } 4141 if (!ATH_TXQ_SETUP(sc, qnum)) { 4142 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4143 sc->sc_txqsetup |= 1<<qnum; 4144 } 4145 return &sc->sc_txq[qnum]; 4146 #undef N 4147 } 4148 4149 /* 4150 * Setup a hardware data transmit queue for the specified 4151 * access control. The hal may not support all requested 4152 * queues in which case it will return a reference to a 4153 * previously setup queue. We record the mapping from ac's 4154 * to h/w queues for use by ath_tx_start and also track 4155 * the set of h/w queues being used to optimize work in the 4156 * transmit interrupt handler and related routines. 4157 */ 4158 static int 4159 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4160 { 4161 #define N(a) (sizeof(a)/sizeof(a[0])) 4162 struct ath_txq *txq; 4163 4164 if (ac >= N(sc->sc_ac2q)) { 4165 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4166 ac, N(sc->sc_ac2q)); 4167 return 0; 4168 } 4169 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4170 if (txq != NULL) { 4171 txq->axq_ac = ac; 4172 sc->sc_ac2q[ac] = txq; 4173 return 1; 4174 } else 4175 return 0; 4176 #undef N 4177 } 4178 4179 /* 4180 * Update WME parameters for a transmit queue. 4181 */ 4182 static int 4183 ath_txq_update(struct ath_softc *sc, int ac) 4184 { 4185 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4186 #define ATH_TXOP_TO_US(v) (v<<5) 4187 struct ifnet *ifp = sc->sc_ifp; 4188 struct ieee80211com *ic = ifp->if_l2com; 4189 struct ath_txq *txq = sc->sc_ac2q[ac]; 4190 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4191 struct ath_hal *ah = sc->sc_ah; 4192 HAL_TXQ_INFO qi; 4193 4194 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4195 #ifdef IEEE80211_SUPPORT_TDMA 4196 if (sc->sc_tdma) { 4197 /* 4198 * AIFS is zero so there's no pre-transmit wait. The 4199 * burst time defines the slot duration and is configured 4200 * through net80211. The QCU is setup to not do post-xmit 4201 * back off, lockout all lower-priority QCU's, and fire 4202 * off the DMA beacon alert timer which is setup based 4203 * on the slot configuration. 4204 */ 4205 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4206 | HAL_TXQ_TXERRINT_ENABLE 4207 | HAL_TXQ_TXURNINT_ENABLE 4208 | HAL_TXQ_TXEOLINT_ENABLE 4209 | HAL_TXQ_DBA_GATED 4210 | HAL_TXQ_BACKOFF_DISABLE 4211 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4212 ; 4213 qi.tqi_aifs = 0; 4214 /* XXX +dbaprep? */ 4215 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4216 qi.tqi_burstTime = qi.tqi_readyTime; 4217 } else { 4218 #endif 4219 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4220 | HAL_TXQ_TXERRINT_ENABLE 4221 | HAL_TXQ_TXDESCINT_ENABLE 4222 | HAL_TXQ_TXURNINT_ENABLE 4223 ; 4224 qi.tqi_aifs = wmep->wmep_aifsn; 4225 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4226 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4227 qi.tqi_readyTime = 0; 4228 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4229 #ifdef IEEE80211_SUPPORT_TDMA 4230 } 4231 #endif 4232 4233 DPRINTF(sc, ATH_DEBUG_RESET, 4234 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4235 __func__, txq->axq_qnum, qi.tqi_qflags, 4236 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4237 4238 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4239 if_printf(ifp, "unable to update hardware queue " 4240 "parameters for %s traffic!\n", 4241 ieee80211_wme_acnames[ac]); 4242 return 0; 4243 } else { 4244 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4245 return 1; 4246 } 4247 #undef ATH_TXOP_TO_US 4248 #undef ATH_EXPONENT_TO_VALUE 4249 } 4250 4251 /* 4252 * Callback from the 802.11 layer to update WME parameters. 4253 */ 4254 static int 4255 ath_wme_update(struct ieee80211com *ic) 4256 { 4257 struct ath_softc *sc = ic->ic_ifp->if_softc; 4258 4259 return !ath_txq_update(sc, WME_AC_BE) || 4260 !ath_txq_update(sc, WME_AC_BK) || 4261 !ath_txq_update(sc, WME_AC_VI) || 4262 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4263 } 4264 4265 /* 4266 * Reclaim resources for a setup queue. 4267 */ 4268 static void 4269 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4270 { 4271 4272 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4273 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4274 } 4275 4276 /* 4277 * Reclaim all tx queue resources. 4278 */ 4279 static void 4280 ath_tx_cleanup(struct ath_softc *sc) 4281 { 4282 int i; 4283 4284 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4285 if (ATH_TXQ_SETUP(sc, i)) 4286 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4287 } 4288 4289 /* 4290 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4291 * using the current rates in sc_rixmap. 4292 */ 4293 static __inline int 4294 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4295 { 4296 int rix = sc->sc_rixmap[rate]; 4297 /* NB: return lowest rix for invalid rate */ 4298 return (rix == 0xff ? 0 : rix); 4299 } 4300 4301 /* 4302 * Reclaim mbuf resources. For fragmented frames we 4303 * need to claim each frag chained with m_nextpkt. 4304 */ 4305 static void 4306 ath_freetx(struct mbuf *m) 4307 { 4308 struct mbuf *next; 4309 4310 do { 4311 next = m->m_nextpkt; 4312 m->m_nextpkt = NULL; 4313 m_freem(m); 4314 } while ((m = next) != NULL); 4315 } 4316 4317 static int 4318 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4319 { 4320 int error; 4321 4322 /* 4323 * 4324 * Load the DMA map so any coalescing is done. This 4325 * also calculates the number of descriptors we need. 4326 */ 4327 error = bus_dmamap_load_mbuf_defrag(sc->sc_dmat, bf->bf_dmamap, &m0, 4328 bf->bf_segs, ATH_TXDESC, 4329 &bf->bf_nseg, BUS_DMA_NOWAIT); 4330 if (error != 0) { 4331 sc->sc_stats.ast_tx_busdma++; 4332 ath_freetx(m0); 4333 return error; 4334 } 4335 4336 /* 4337 * Discard null packets. 4338 */ 4339 if (bf->bf_nseg == 0) { /* null packet, discard */ 4340 sc->sc_stats.ast_tx_nodata++; 4341 ath_freetx(m0); 4342 return EIO; 4343 } 4344 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4345 __func__, m0, m0->m_pkthdr.len); 4346 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4347 bf->bf_m = m0; 4348 4349 return 0; 4350 } 4351 4352 static void 4353 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4354 { 4355 struct ath_hal *ah = sc->sc_ah; 4356 struct ath_desc *ds, *ds0; 4357 int i; 4358 4359 /* 4360 * Fillin the remainder of the descriptor info. 4361 */ 4362 ds0 = ds = bf->bf_desc; 4363 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4364 ds->ds_data = bf->bf_segs[i].ds_addr; 4365 if (i == bf->bf_nseg - 1) 4366 ds->ds_link = 0; 4367 else 4368 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4369 ath_hal_filltxdesc(ah, ds 4370 , bf->bf_segs[i].ds_len /* segment length */ 4371 , i == 0 /* first segment */ 4372 , i == bf->bf_nseg - 1 /* last segment */ 4373 , ds0 /* first descriptor */ 4374 ); 4375 DPRINTF(sc, ATH_DEBUG_XMIT, 4376 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4377 __func__, i, ds->ds_link, ds->ds_data, 4378 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4379 } 4380 /* 4381 * Insert the frame on the outbound list and pass it on 4382 * to the hardware. Multicast frames buffered for power 4383 * save stations and transmit from the CAB queue are stored 4384 * on a s/w only queue and loaded on to the CAB queue in 4385 * the SWBA handler since frames only go out on DTIM and 4386 * to avoid possible races. 4387 */ 4388 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4389 ("busy status 0x%x", bf->bf_flags)); 4390 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4391 #ifdef IEEE80211_SUPPORT_TDMA 4392 /* 4393 * Supporting transmit dma. If the queue is busy it is 4394 * impossible to determine if we've won the race against 4395 * the chipset checking the link field or not, so we don't 4396 * try. Instead we let the TX interrupt detect the case 4397 * and restart the transmitter. 4398 * 4399 * If the queue is not busy we can start things rolling 4400 * right here. 4401 */ 4402 int qbusy; 4403 4404 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4405 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4406 4407 if (qbusy == 0) { 4408 if (txq->axq_link != NULL) { 4409 /* 4410 * We had already started one previously but 4411 * not yet processed the TX interrupt. Don't 4412 * try to race a restart because we do not 4413 * know where it stopped, let the TX interrupt 4414 * restart us when it figures out where we 4415 * stopped. 4416 */ 4417 cpu_sfence(); 4418 *txq->axq_link = bf->bf_daddr; 4419 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4420 } else { 4421 /* 4422 * We are first in line, we can safely start 4423 * at this address. 4424 */ 4425 cpu_sfence(); 4426 ath_hal_puttxbuf(ah, txq->axq_qnum, 4427 bf->bf_daddr); 4428 } 4429 } else { 4430 /* 4431 * The queue is busy, go ahead and link us in but 4432 * do not try to start/restart the tx. We just 4433 * don't know whether it will pick up our link 4434 * or not and we don't want to double-xmit. 4435 */ 4436 if (txq->axq_link != NULL) { 4437 cpu_sfence(); 4438 *txq->axq_link = bf->bf_daddr; 4439 } 4440 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4441 } 4442 #if 0 4443 ath_hal_puttxbuf(ah, txq->axq_qnum, 4444 STAILQ_FIRST(&txq->axq_q)->bf_daddr); 4445 #endif 4446 #else 4447 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4448 if (txq->axq_link == NULL) { 4449 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4450 DPRINTF(sc, ATH_DEBUG_XMIT, 4451 "%s: TXDP[%u] = %p (%p) depth %d\n", 4452 __func__, txq->axq_qnum, 4453 (caddr_t)bf->bf_daddr, bf->bf_desc, 4454 txq->axq_depth); 4455 } else { 4456 *txq->axq_link = bf->bf_daddr; 4457 DPRINTF(sc, ATH_DEBUG_XMIT, 4458 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4459 txq->axq_qnum, txq->axq_link, 4460 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4461 } 4462 #endif /* IEEE80211_SUPPORT_TDMA */ 4463 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4464 ath_hal_txstart(ah, txq->axq_qnum); 4465 } else { 4466 if (txq->axq_link != NULL) { 4467 struct ath_buf *last = ATH_TXQ_LAST(txq); 4468 struct ieee80211_frame *wh; 4469 4470 /* mark previous frame */ 4471 wh = mtod(last->bf_m, struct ieee80211_frame *); 4472 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4473 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4474 BUS_DMASYNC_PREWRITE); 4475 4476 /* link descriptor */ 4477 *txq->axq_link = bf->bf_daddr; 4478 } 4479 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4480 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4481 } 4482 } 4483 4484 static int 4485 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4486 struct mbuf *m0) 4487 { 4488 struct ieee80211vap *vap = ni->ni_vap; 4489 struct ath_vap *avp = ATH_VAP(vap); 4490 struct ath_hal *ah = sc->sc_ah; 4491 struct ifnet *ifp = sc->sc_ifp; 4492 struct ieee80211com *ic = ifp->if_l2com; 4493 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4494 int error, iswep, ismcast, isfrag, ismrr; 4495 int keyix, hdrlen, pktlen, try0; 4496 u_int8_t rix, txrate, ctsrate; 4497 u_int8_t cix = 0xff; /* NB: silence compiler */ 4498 struct ath_desc *ds; 4499 struct ath_txq *txq; 4500 struct ieee80211_frame *wh; 4501 u_int subtype, flags, ctsduration; 4502 HAL_PKT_TYPE atype; 4503 const HAL_RATE_TABLE *rt; 4504 HAL_BOOL shortPreamble; 4505 struct ath_node *an; 4506 u_int pri; 4507 4508 wh = mtod(m0, struct ieee80211_frame *); 4509 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4510 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4511 isfrag = m0->m_flags & M_FRAG; 4512 hdrlen = ieee80211_anyhdrsize(wh); 4513 /* 4514 * Packet length must not include any 4515 * pad bytes; deduct them here. 4516 */ 4517 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4518 4519 if (iswep) { 4520 const struct ieee80211_cipher *cip; 4521 struct ieee80211_key *k; 4522 4523 /* 4524 * Construct the 802.11 header+trailer for an encrypted 4525 * frame. The only reason this can fail is because of an 4526 * unknown or unsupported cipher/key type. 4527 */ 4528 k = ieee80211_crypto_encap(ni, m0); 4529 if (k == NULL) { 4530 /* 4531 * This can happen when the key is yanked after the 4532 * frame was queued. Just discard the frame; the 4533 * 802.11 layer counts failures and provides 4534 * debugging/diagnostics. 4535 */ 4536 ath_freetx(m0); 4537 return EIO; 4538 } 4539 /* 4540 * Adjust the packet + header lengths for the crypto 4541 * additions and calculate the h/w key index. When 4542 * a s/w mic is done the frame will have had any mic 4543 * added to it prior to entry so m0->m_pkthdr.len will 4544 * account for it. Otherwise we need to add it to the 4545 * packet length. 4546 */ 4547 cip = k->wk_cipher; 4548 hdrlen += cip->ic_header; 4549 pktlen += cip->ic_header + cip->ic_trailer; 4550 /* NB: frags always have any TKIP MIC done in s/w */ 4551 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4552 pktlen += cip->ic_miclen; 4553 keyix = k->wk_keyix; 4554 4555 /* packet header may have moved, reset our local pointer */ 4556 wh = mtod(m0, struct ieee80211_frame *); 4557 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4558 /* 4559 * Use station key cache slot, if assigned. 4560 */ 4561 keyix = ni->ni_ucastkey.wk_keyix; 4562 if (keyix == IEEE80211_KEYIX_NONE) 4563 keyix = HAL_TXKEYIX_INVALID; 4564 } else 4565 keyix = HAL_TXKEYIX_INVALID; 4566 4567 pktlen += IEEE80211_CRC_LEN; 4568 4569 /* 4570 * Load the DMA map so any coalescing is done. This 4571 * also calculates the number of descriptors we need. 4572 */ 4573 error = ath_tx_dmasetup(sc, bf, m0); 4574 if (error != 0) { 4575 return error; 4576 } 4577 bf->bf_node = ni; /* NB: held reference */ 4578 m0 = bf->bf_m; /* NB: may have changed */ 4579 wh = mtod(m0, struct ieee80211_frame *); 4580 4581 /* setup descriptors */ 4582 ds = bf->bf_desc; 4583 rt = sc->sc_currates; 4584 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4585 4586 /* 4587 * NB: the 802.11 layer marks whether or not we should 4588 * use short preamble based on the current mode and 4589 * negotiated parameters. 4590 */ 4591 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4592 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4593 shortPreamble = AH_TRUE; 4594 sc->sc_stats.ast_tx_shortpre++; 4595 } else { 4596 shortPreamble = AH_FALSE; 4597 } 4598 4599 an = ATH_NODE(ni); 4600 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4601 ismrr = 0; /* default no multi-rate retry*/ 4602 pri = M_WME_GETAC(m0); /* honor classification */ 4603 /* XXX use txparams instead of fixed values */ 4604 /* 4605 * Calculate Atheros packet type from IEEE80211 packet header, 4606 * setup for rate calculations, and select h/w transmit queue. 4607 */ 4608 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4609 case IEEE80211_FC0_TYPE_MGT: 4610 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4611 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4612 atype = HAL_PKT_TYPE_BEACON; 4613 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4614 atype = HAL_PKT_TYPE_PROBE_RESP; 4615 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4616 atype = HAL_PKT_TYPE_ATIM; 4617 else 4618 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4619 rix = an->an_mgmtrix; 4620 txrate = rt->info[rix].rateCode; 4621 if (shortPreamble) 4622 txrate |= rt->info[rix].shortPreamble; 4623 try0 = ATH_TXMGTTRY; 4624 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4625 break; 4626 case IEEE80211_FC0_TYPE_CTL: 4627 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4628 rix = an->an_mgmtrix; 4629 txrate = rt->info[rix].rateCode; 4630 if (shortPreamble) 4631 txrate |= rt->info[rix].shortPreamble; 4632 try0 = ATH_TXMGTTRY; 4633 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4634 break; 4635 case IEEE80211_FC0_TYPE_DATA: 4636 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4637 /* 4638 * Data frames: multicast frames go out at a fixed rate, 4639 * EAPOL frames use the mgmt frame rate; otherwise consult 4640 * the rate control module for the rate to use. 4641 */ 4642 if (ismcast) { 4643 rix = an->an_mcastrix; 4644 txrate = rt->info[rix].rateCode; 4645 if (shortPreamble) 4646 txrate |= rt->info[rix].shortPreamble; 4647 try0 = 1; 4648 } else if (m0->m_flags & M_EAPOL) { 4649 /* XXX? maybe always use long preamble? */ 4650 rix = an->an_mgmtrix; 4651 txrate = rt->info[rix].rateCode; 4652 if (shortPreamble) 4653 txrate |= rt->info[rix].shortPreamble; 4654 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4655 } else { 4656 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4657 &rix, &try0, &txrate); 4658 sc->sc_txrix = rix; /* for LED blinking */ 4659 sc->sc_lastdatarix = rix; /* for fast frames */ 4660 if (try0 != ATH_TXMAXTRY) 4661 ismrr = 1; 4662 } 4663 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4664 flags |= HAL_TXDESC_NOACK; 4665 break; 4666 default: 4667 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4668 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4669 /* XXX statistic */ 4670 ath_freetx(m0); 4671 return EIO; 4672 } 4673 txq = sc->sc_ac2q[pri]; 4674 4675 /* 4676 * When servicing one or more stations in power-save mode 4677 * (or) if there is some mcast data waiting on the mcast 4678 * queue (to prevent out of order delivery) multicast 4679 * frames must be buffered until after the beacon. 4680 */ 4681 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4682 txq = &avp->av_mcastq; 4683 4684 /* 4685 * Calculate miscellaneous flags. 4686 */ 4687 if (ismcast) { 4688 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4689 } else if (pktlen > vap->iv_rtsthreshold && 4690 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4691 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4692 cix = rt->info[rix].controlRate; 4693 sc->sc_stats.ast_tx_rts++; 4694 } 4695 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4696 sc->sc_stats.ast_tx_noack++; 4697 #ifdef IEEE80211_SUPPORT_TDMA 4698 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 4699 DPRINTF(sc, ATH_DEBUG_TDMA, 4700 "%s: discard frame, ACK required w/ TDMA\n", __func__); 4701 sc->sc_stats.ast_tdma_ack++; 4702 ath_freetx(m0); 4703 return EIO; 4704 } 4705 #endif 4706 4707 /* 4708 * If 802.11g protection is enabled, determine whether 4709 * to use RTS/CTS or just CTS. Note that this is only 4710 * done for OFDM unicast frames. 4711 */ 4712 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4713 rt->info[rix].phy == IEEE80211_T_OFDM && 4714 (flags & HAL_TXDESC_NOACK) == 0) { 4715 /* XXX fragments must use CCK rates w/ protection */ 4716 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4717 flags |= HAL_TXDESC_RTSENA; 4718 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4719 flags |= HAL_TXDESC_CTSENA; 4720 if (isfrag) { 4721 /* 4722 * For frags it would be desirable to use the 4723 * highest CCK rate for RTS/CTS. But stations 4724 * farther away may detect it at a lower CCK rate 4725 * so use the configured protection rate instead 4726 * (for now). 4727 */ 4728 cix = rt->info[sc->sc_protrix].controlRate; 4729 } else 4730 cix = rt->info[sc->sc_protrix].controlRate; 4731 sc->sc_stats.ast_tx_protect++; 4732 } 4733 4734 /* 4735 * Calculate duration. This logically belongs in the 802.11 4736 * layer but it lacks sufficient information to calculate it. 4737 */ 4738 if ((flags & HAL_TXDESC_NOACK) == 0 && 4739 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4740 u_int16_t dur; 4741 if (shortPreamble) 4742 dur = rt->info[rix].spAckDuration; 4743 else 4744 dur = rt->info[rix].lpAckDuration; 4745 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4746 dur += dur; /* additional SIFS+ACK */ 4747 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4748 /* 4749 * Include the size of next fragment so NAV is 4750 * updated properly. The last fragment uses only 4751 * the ACK duration 4752 */ 4753 dur += ath_hal_computetxtime(ah, rt, 4754 m0->m_nextpkt->m_pkthdr.len, 4755 rix, shortPreamble); 4756 } 4757 if (isfrag) { 4758 /* 4759 * Force hardware to use computed duration for next 4760 * fragment by disabling multi-rate retry which updates 4761 * duration based on the multi-rate duration table. 4762 */ 4763 ismrr = 0; 4764 try0 = ATH_TXMGTTRY; /* XXX? */ 4765 } 4766 *(u_int16_t *)wh->i_dur = htole16(dur); 4767 } 4768 4769 /* 4770 * Calculate RTS/CTS rate and duration if needed. 4771 */ 4772 ctsduration = 0; 4773 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4774 /* 4775 * CTS transmit rate is derived from the transmit rate 4776 * by looking in the h/w rate table. We must also factor 4777 * in whether or not a short preamble is to be used. 4778 */ 4779 /* NB: cix is set above where RTS/CTS is enabled */ 4780 KASSERT(cix != 0xff, ("cix not setup")); 4781 ctsrate = rt->info[cix].rateCode; 4782 /* 4783 * Compute the transmit duration based on the frame 4784 * size and the size of an ACK frame. We call into the 4785 * HAL to do the computation since it depends on the 4786 * characteristics of the actual PHY being used. 4787 * 4788 * NB: CTS is assumed the same size as an ACK so we can 4789 * use the precalculated ACK durations. 4790 */ 4791 if (shortPreamble) { 4792 ctsrate |= rt->info[cix].shortPreamble; 4793 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4794 ctsduration += rt->info[cix].spAckDuration; 4795 ctsduration += ath_hal_computetxtime(ah, 4796 rt, pktlen, rix, AH_TRUE); 4797 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4798 ctsduration += rt->info[rix].spAckDuration; 4799 } else { 4800 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4801 ctsduration += rt->info[cix].lpAckDuration; 4802 ctsduration += ath_hal_computetxtime(ah, 4803 rt, pktlen, rix, AH_FALSE); 4804 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4805 ctsduration += rt->info[rix].lpAckDuration; 4806 } 4807 /* 4808 * Must disable multi-rate retry when using RTS/CTS. 4809 */ 4810 ismrr = 0; 4811 try0 = ATH_TXMGTTRY; /* XXX */ 4812 } else 4813 ctsrate = 0; 4814 4815 /* 4816 * At this point we are committed to sending the frame 4817 * and we don't need to look at m_nextpkt; clear it in 4818 * case this frame is part of frag chain. 4819 */ 4820 m0->m_nextpkt = NULL; 4821 4822 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4823 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 4824 sc->sc_hwmap[rix].ieeerate, -1); 4825 4826 if (ieee80211_radiotap_active_vap(vap)) { 4827 u_int64_t tsf = ath_hal_gettsf64(ah); 4828 4829 sc->sc_tx_th.wt_tsf = htole64(tsf); 4830 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 4831 if (iswep) 4832 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4833 if (isfrag) 4834 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4835 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 4836 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4837 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4838 4839 ieee80211_radiotap_tx(vap, m0); 4840 } 4841 4842 /* 4843 * Determine if a tx interrupt should be generated for 4844 * this descriptor. We take a tx interrupt to reap 4845 * descriptors when the h/w hits an EOL condition or 4846 * when the descriptor is specifically marked to generate 4847 * an interrupt. We periodically mark descriptors in this 4848 * way to insure timely replenishing of the supply needed 4849 * for sending frames. Defering interrupts reduces system 4850 * load and potentially allows more concurrent work to be 4851 * done but if done to aggressively can cause senders to 4852 * backup. 4853 * 4854 * NB: use >= to deal with sc_txintrperiod changing 4855 * dynamically through sysctl. 4856 */ 4857 if (flags & HAL_TXDESC_INTREQ) { 4858 txq->axq_intrcnt = 0; 4859 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4860 flags |= HAL_TXDESC_INTREQ; 4861 txq->axq_intrcnt = 0; 4862 } 4863 4864 /* 4865 * Formulate first tx descriptor with tx controls. 4866 */ 4867 /* XXX check return value? */ 4868 ath_hal_setuptxdesc(ah, ds 4869 , pktlen /* packet length */ 4870 , hdrlen /* header length */ 4871 , atype /* Atheros packet type */ 4872 , ni->ni_txpower /* txpower */ 4873 , txrate, try0 /* series 0 rate/tries */ 4874 , keyix /* key cache index */ 4875 , sc->sc_txantenna /* antenna mode */ 4876 , flags /* flags */ 4877 , ctsrate /* rts/cts rate */ 4878 , ctsduration /* rts/cts duration */ 4879 ); 4880 bf->bf_txflags = flags; 4881 /* 4882 * Setup the multi-rate retry state only when we're 4883 * going to use it. This assumes ath_hal_setuptxdesc 4884 * initializes the descriptors (so we don't have to) 4885 * when the hardware supports multi-rate retry and 4886 * we don't use it. 4887 */ 4888 if (ismrr) 4889 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4890 4891 ath_tx_handoff(sc, txq, bf); 4892 return 0; 4893 } 4894 4895 /* 4896 * Process completed xmit descriptors from the specified queue. 4897 */ 4898 static int 4899 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4900 { 4901 struct ath_hal *ah = sc->sc_ah; 4902 struct ifnet *ifp = sc->sc_ifp; 4903 struct ieee80211com *ic = ifp->if_l2com; 4904 struct ath_buf *bf, *last; 4905 struct ath_desc *ds, *ds0; 4906 struct ath_tx_status *ts; 4907 struct ieee80211_node *ni; 4908 struct ath_node *an; 4909 int sr, lr, pri, nacked; 4910 HAL_STATUS status; 4911 4912 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4913 __func__, txq->axq_qnum, 4914 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4915 txq->axq_link); 4916 nacked = 0; 4917 for (;;) { 4918 int qbusy; 4919 4920 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4921 bf = STAILQ_FIRST(&txq->axq_q); 4922 if (bf == NULL) 4923 break; 4924 ds0 = &bf->bf_desc[0]; 4925 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4926 ts = &bf->bf_status.ds_txstat; 4927 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4928 status = ath_hal_txprocdesc(ah, ds, ts); 4929 #ifdef ATH_DEBUG 4930 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4931 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4932 status == HAL_OK); 4933 #endif 4934 if (status == HAL_EINPROGRESS) { 4935 #ifdef IEEE80211_SUPPORT_TDMA 4936 /* 4937 * If not done and the queue is not busy then the 4938 * transmitter raced the hardware on the link field 4939 * and we have to restart it. 4940 */ 4941 if (!qbusy) { 4942 cpu_sfence(); 4943 ath_hal_puttxbuf(ah, txq->axq_qnum, 4944 bf->bf_daddr); 4945 ath_hal_txstart(ah, txq->axq_qnum); 4946 } 4947 #endif 4948 break; 4949 } 4950 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4951 #ifdef IEEE80211_SUPPORT_TDMA 4952 if (txq->axq_depth > 0) { 4953 /* 4954 * More frames follow. Mark the buffer busy 4955 * so it's not re-used while the hardware may 4956 * still re-read the link field in the descriptor. 4957 */ 4958 bf->bf_flags |= ATH_BUF_BUSY; 4959 } else 4960 #else 4961 if (txq->axq_depth == 0) 4962 #endif 4963 txq->axq_link = NULL; 4964 4965 ni = bf->bf_node; 4966 if (ni != NULL) { 4967 an = ATH_NODE(ni); 4968 if (ts->ts_status == 0) { 4969 u_int8_t txant = ts->ts_antenna; 4970 sc->sc_stats.ast_ant_tx[txant]++; 4971 sc->sc_ant_tx[txant]++; 4972 if (ts->ts_finaltsi != 0) 4973 sc->sc_stats.ast_tx_altrate++; 4974 pri = M_WME_GETAC(bf->bf_m); 4975 if (pri >= WME_AC_VO) 4976 ic->ic_wme.wme_hipri_traffic++; 4977 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4978 ni->ni_inact = ni->ni_inact_reload; 4979 } else { 4980 if (ts->ts_status & HAL_TXERR_XRETRY) 4981 sc->sc_stats.ast_tx_xretries++; 4982 if (ts->ts_status & HAL_TXERR_FIFO) 4983 sc->sc_stats.ast_tx_fifoerr++; 4984 if (ts->ts_status & HAL_TXERR_FILT) 4985 sc->sc_stats.ast_tx_filtered++; 4986 if (bf->bf_m->m_flags & M_FF) 4987 sc->sc_stats.ast_ff_txerr++; 4988 } 4989 sr = ts->ts_shortretry; 4990 lr = ts->ts_longretry; 4991 sc->sc_stats.ast_tx_shortretry += sr; 4992 sc->sc_stats.ast_tx_longretry += lr; 4993 /* 4994 * Hand the descriptor to the rate control algorithm. 4995 */ 4996 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4997 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4998 /* 4999 * If frame was ack'd update statistics, 5000 * including the last rx time used to 5001 * workaround phantom bmiss interrupts. 5002 */ 5003 if (ts->ts_status == 0) { 5004 nacked++; 5005 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 5006 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 5007 ts->ts_rssi); 5008 } 5009 ath_rate_tx_complete(sc, an, bf); 5010 } 5011 /* 5012 * Do any tx complete callback. Note this must 5013 * be done before releasing the node reference. 5014 */ 5015 if (bf->bf_m->m_flags & M_TXCB) 5016 ieee80211_process_callback(ni, bf->bf_m, 5017 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 5018 ts->ts_status : HAL_TXERR_XRETRY); 5019 ieee80211_free_node(ni); 5020 } 5021 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5022 BUS_DMASYNC_POSTWRITE); 5023 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5024 5025 m_freem(bf->bf_m); 5026 bf->bf_m = NULL; 5027 bf->bf_node = NULL; 5028 5029 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5030 if (last != NULL) 5031 last->bf_flags &= ~ATH_BUF_BUSY; 5032 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5033 } 5034 #ifdef IEEE80211_SUPPORT_SUPERG 5035 /* 5036 * Flush fast-frame staging queue when traffic slows. 5037 */ 5038 if (txq->axq_depth <= 1) 5039 ieee80211_ff_flush(ic, txq->axq_ac); 5040 #endif 5041 return nacked; 5042 } 5043 5044 static __inline int 5045 txqactive(struct ath_hal *ah, int qnum) 5046 { 5047 u_int32_t txqs = 1<<qnum; 5048 ath_hal_gettxintrtxqs(ah, &txqs); 5049 return (txqs & (1<<qnum)); 5050 } 5051 5052 /* 5053 * Deferred processing of transmit interrupt; special-cased 5054 * for a single hardware transmit queue (e.g. 5210 and 5211). 5055 */ 5056 static void 5057 ath_tx_task_q0(void *arg, int npending) 5058 { 5059 struct ath_softc *sc = arg; 5060 struct ifnet *ifp = sc->sc_ifp; 5061 5062 wlan_serialize_enter(); 5063 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5064 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5065 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5066 ath_tx_processq(sc, sc->sc_cabq); 5067 ifp->if_flags &= ~IFF_OACTIVE; 5068 sc->sc_wd_timer = 0; 5069 5070 if (sc->sc_softled) 5071 ath_led_event(sc, sc->sc_txrix); 5072 5073 ath_start(ifp); 5074 wlan_serialize_exit(); 5075 } 5076 5077 /* 5078 * Deferred processing of transmit interrupt; special-cased 5079 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5080 */ 5081 static void 5082 ath_tx_task_q0123(void *arg, int npending) 5083 { 5084 struct ath_softc *sc = arg; 5085 struct ifnet *ifp = sc->sc_ifp; 5086 int nacked; 5087 5088 wlan_serialize_enter(); 5089 /* 5090 * Process each active queue. 5091 */ 5092 nacked = 0; 5093 if (txqactive(sc->sc_ah, 0)) 5094 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5095 if (txqactive(sc->sc_ah, 1)) 5096 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5097 if (txqactive(sc->sc_ah, 2)) 5098 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5099 if (txqactive(sc->sc_ah, 3)) 5100 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5101 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5102 ath_tx_processq(sc, sc->sc_cabq); 5103 if (nacked) 5104 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5105 5106 ifp->if_flags &= ~IFF_OACTIVE; 5107 sc->sc_wd_timer = 0; 5108 5109 if (sc->sc_softled) 5110 ath_led_event(sc, sc->sc_txrix); 5111 5112 ath_start(ifp); 5113 wlan_serialize_exit(); 5114 } 5115 5116 /* 5117 * Deferred processing of transmit interrupt. 5118 */ 5119 static void 5120 ath_tx_task(void *arg, int npending) 5121 { 5122 struct ath_softc *sc = arg; 5123 struct ifnet *ifp = sc->sc_ifp; 5124 int i, nacked; 5125 5126 wlan_serialize_enter(); 5127 5128 /* 5129 * Process each active queue. 5130 */ 5131 nacked = 0; 5132 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5133 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5134 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5135 } 5136 if (nacked) 5137 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5138 5139 ifp->if_flags &= ~IFF_OACTIVE; 5140 sc->sc_wd_timer = 0; 5141 5142 if (sc->sc_softled) 5143 ath_led_event(sc, sc->sc_txrix); 5144 5145 ath_start(ifp); 5146 wlan_serialize_exit(); 5147 } 5148 5149 static void 5150 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5151 { 5152 #ifdef ATH_DEBUG 5153 struct ath_hal *ah = sc->sc_ah; 5154 #endif 5155 struct ieee80211_node *ni; 5156 struct ath_buf *bf; 5157 u_int ix; 5158 5159 /* 5160 * NB: this assumes output has been stopped and 5161 * we do not need to block ath_tx_proc 5162 */ 5163 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5164 if (bf != NULL) 5165 bf->bf_flags &= ~ATH_BUF_BUSY; 5166 for (ix = 0;; ix++) { 5167 bf = STAILQ_FIRST(&txq->axq_q); 5168 if (bf == NULL) { 5169 txq->axq_link = NULL; 5170 break; 5171 } 5172 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5173 #ifdef ATH_DEBUG 5174 if (sc->sc_debug & ATH_DEBUG_RESET) { 5175 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5176 5177 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5178 ath_hal_txprocdesc(ah, bf->bf_desc, 5179 &bf->bf_status.ds_txstat) == HAL_OK); 5180 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5181 bf->bf_m->m_len, 0, -1); 5182 } 5183 #endif /* ATH_DEBUG */ 5184 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5185 ni = bf->bf_node; 5186 bf->bf_node = NULL; 5187 if (ni != NULL) { 5188 /* 5189 * Do any callback and reclaim the node reference. 5190 */ 5191 if (bf->bf_m->m_flags & M_TXCB) 5192 ieee80211_process_callback(ni, bf->bf_m, -1); 5193 ieee80211_free_node(ni); 5194 } 5195 m_freem(bf->bf_m); 5196 bf->bf_m = NULL; 5197 bf->bf_flags &= ~ATH_BUF_BUSY; 5198 5199 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5200 } 5201 } 5202 5203 static void 5204 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5205 { 5206 struct ath_hal *ah = sc->sc_ah; 5207 5208 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5209 __func__, txq->axq_qnum, 5210 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5211 txq->axq_link); 5212 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5213 } 5214 5215 /* 5216 * Drain the transmit queues and reclaim resources. 5217 */ 5218 static void 5219 ath_draintxq(struct ath_softc *sc) 5220 { 5221 struct ath_hal *ah = sc->sc_ah; 5222 struct ifnet *ifp = sc->sc_ifp; 5223 int i; 5224 5225 /* XXX return value */ 5226 if (!sc->sc_invalid) { 5227 /* don't touch the hardware if marked invalid */ 5228 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5229 __func__, sc->sc_bhalq, 5230 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5231 NULL); 5232 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5233 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5234 if (ATH_TXQ_SETUP(sc, i)) 5235 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5236 } 5237 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5238 if (ATH_TXQ_SETUP(sc, i)) 5239 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5240 #ifdef ATH_DEBUG 5241 if (sc->sc_debug & ATH_DEBUG_RESET) { 5242 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5243 if (bf != NULL && bf->bf_m != NULL) { 5244 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5245 ath_hal_txprocdesc(ah, bf->bf_desc, 5246 &bf->bf_status.ds_txstat) == HAL_OK); 5247 ieee80211_dump_pkt(ifp->if_l2com, 5248 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5249 0, -1); 5250 } 5251 } 5252 #endif /* ATH_DEBUG */ 5253 ifp->if_flags &= ~IFF_OACTIVE; 5254 sc->sc_wd_timer = 0; 5255 } 5256 5257 /* 5258 * Disable the receive h/w in preparation for a reset. 5259 */ 5260 static void 5261 ath_stoprecv(struct ath_softc *sc) 5262 { 5263 #define PA2DESC(_sc, _pa) \ 5264 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5265 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5266 struct ath_hal *ah = sc->sc_ah; 5267 5268 ath_hal_stoppcurecv(ah); /* disable PCU */ 5269 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5270 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5271 DELAY(3000); /* 3ms is long enough for 1 frame */ 5272 #ifdef ATH_DEBUG 5273 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5274 struct ath_buf *bf; 5275 u_int ix; 5276 5277 kprintf("%s: rx queue %p, link %p\n", __func__, 5278 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5279 ix = 0; 5280 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5281 struct ath_desc *ds = bf->bf_desc; 5282 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5283 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5284 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5285 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5286 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5287 ix++; 5288 } 5289 } 5290 #endif 5291 if (sc->sc_rxpending != NULL) { 5292 m_freem(sc->sc_rxpending); 5293 sc->sc_rxpending = NULL; 5294 } 5295 sc->sc_rxlink = NULL; /* just in case */ 5296 #undef PA2DESC 5297 } 5298 5299 /* 5300 * Enable the receive h/w following a reset. 5301 */ 5302 static int 5303 ath_startrecv(struct ath_softc *sc) 5304 { 5305 struct ath_hal *ah = sc->sc_ah; 5306 struct ath_buf *bf; 5307 5308 sc->sc_rxlink = NULL; 5309 sc->sc_rxpending = NULL; 5310 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5311 int error = ath_rxbuf_init(sc, bf); 5312 if (error != 0) { 5313 DPRINTF(sc, ATH_DEBUG_RECV, 5314 "%s: ath_rxbuf_init failed %d\n", 5315 __func__, error); 5316 return error; 5317 } 5318 } 5319 5320 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5321 ath_hal_putrxbuf(ah, bf->bf_daddr); 5322 ath_hal_rxena(ah); /* enable recv descriptors */ 5323 ath_mode_init(sc); /* set filters, etc. */ 5324 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5325 return 0; 5326 } 5327 5328 /* 5329 * Update internal state after a channel change. 5330 */ 5331 static void 5332 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5333 { 5334 enum ieee80211_phymode mode; 5335 5336 /* 5337 * Change channels and update the h/w rate map 5338 * if we're switching; e.g. 11a to 11b/g. 5339 */ 5340 mode = ieee80211_chan2mode(chan); 5341 if (mode != sc->sc_curmode) 5342 ath_setcurmode(sc, mode); 5343 sc->sc_curchan = chan; 5344 } 5345 5346 /* 5347 * Set/change channels. If the channel is really being changed, 5348 * it's done by reseting the chip. To accomplish this we must 5349 * first cleanup any pending DMA, then restart stuff after a la 5350 * ath_init. 5351 */ 5352 static int 5353 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5354 { 5355 struct ifnet *ifp = sc->sc_ifp; 5356 struct ieee80211com *ic = ifp->if_l2com; 5357 struct ath_hal *ah = sc->sc_ah; 5358 5359 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5360 __func__, ieee80211_chan2ieee(ic, chan), 5361 chan->ic_freq, chan->ic_flags); 5362 if (chan != sc->sc_curchan) { 5363 HAL_STATUS status; 5364 /* 5365 * To switch channels clear any pending DMA operations; 5366 * wait long enough for the RX fifo to drain, reset the 5367 * hardware at the new frequency, and then re-enable 5368 * the relevant bits of the h/w. 5369 */ 5370 ath_hal_intrset(ah, 0); /* disable interrupts */ 5371 ath_draintxq(sc); /* clear pending tx frames */ 5372 ath_stoprecv(sc); /* turn off frame recv */ 5373 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5374 if_printf(ifp, "%s: unable to reset " 5375 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5376 __func__, ieee80211_chan2ieee(ic, chan), 5377 chan->ic_freq, chan->ic_flags, status); 5378 return EIO; 5379 } 5380 sc->sc_diversity = ath_hal_getdiversity(ah); 5381 5382 /* 5383 * Re-enable rx framework. 5384 */ 5385 if (ath_startrecv(sc) != 0) { 5386 if_printf(ifp, "%s: unable to restart recv logic\n", 5387 __func__); 5388 return EIO; 5389 } 5390 5391 /* 5392 * Change channels and update the h/w rate map 5393 * if we're switching; e.g. 11a to 11b/g. 5394 */ 5395 ath_chan_change(sc, chan); 5396 5397 /* 5398 * Re-enable interrupts. 5399 */ 5400 ath_hal_intrset(ah, sc->sc_imask); 5401 } 5402 return 0; 5403 } 5404 5405 /* 5406 * Periodically recalibrate the PHY to account 5407 * for temperature/environment changes. 5408 */ 5409 static void 5410 ath_calibrate_callout(void *arg) 5411 { 5412 struct ath_softc *sc = arg; 5413 struct ath_hal *ah = sc->sc_ah; 5414 struct ifnet *ifp = sc->sc_ifp; 5415 struct ieee80211com *ic = ifp->if_l2com; 5416 HAL_BOOL longCal, isCalDone; 5417 int nextcal; 5418 5419 wlan_serialize_enter(); 5420 5421 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5422 goto restart; 5423 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5424 if (longCal) { 5425 sc->sc_stats.ast_per_cal++; 5426 sc->sc_lastlongcal = ticks; 5427 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5428 /* 5429 * Rfgain is out of bounds, reset the chip 5430 * to load new gain values. 5431 */ 5432 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5433 "%s: rfgain change\n", __func__); 5434 sc->sc_stats.ast_per_rfgain++; 5435 ath_reset(ifp); 5436 } 5437 /* 5438 * If this long cal is after an idle period, then 5439 * reset the data collection state so we start fresh. 5440 */ 5441 if (sc->sc_resetcal) { 5442 (void) ath_hal_calreset(ah, sc->sc_curchan); 5443 sc->sc_lastcalreset = ticks; 5444 sc->sc_resetcal = 0; 5445 } 5446 } 5447 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5448 if (longCal) { 5449 /* 5450 * Calibrate noise floor data again in case of change. 5451 */ 5452 ath_hal_process_noisefloor(ah); 5453 } 5454 } else { 5455 DPRINTF(sc, ATH_DEBUG_ANY, 5456 "%s: calibration of channel %u failed\n", 5457 __func__, sc->sc_curchan->ic_freq); 5458 sc->sc_stats.ast_per_calfail++; 5459 } 5460 if (!isCalDone) { 5461 restart: 5462 /* 5463 * Use a shorter interval to potentially collect multiple 5464 * data samples required to complete calibration. Once 5465 * we're told the work is done we drop back to a longer 5466 * interval between requests. We're more aggressive doing 5467 * work when operating as an AP to improve operation right 5468 * after startup. 5469 */ 5470 nextcal = (1000*ath_shortcalinterval)/hz; 5471 if (sc->sc_opmode != HAL_M_HOSTAP) 5472 nextcal *= 10; 5473 } else { 5474 nextcal = ath_longcalinterval*hz; 5475 if (sc->sc_lastcalreset == 0) 5476 sc->sc_lastcalreset = sc->sc_lastlongcal; 5477 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5478 sc->sc_resetcal = 1; /* setup reset next trip */ 5479 } 5480 5481 if (nextcal != 0) { 5482 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5483 __func__, nextcal, isCalDone ? "" : "!"); 5484 callout_reset(&sc->sc_cal_ch, nextcal, 5485 ath_calibrate_callout, sc); 5486 } else { 5487 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5488 __func__); 5489 /* NB: don't rearm timer */ 5490 } 5491 wlan_serialize_exit(); 5492 } 5493 5494 static void 5495 ath_scan_start(struct ieee80211com *ic) 5496 { 5497 struct ifnet *ifp = ic->ic_ifp; 5498 struct ath_softc *sc = ifp->if_softc; 5499 struct ath_hal *ah = sc->sc_ah; 5500 u_int32_t rfilt; 5501 5502 /* XXX calibration timer? */ 5503 5504 sc->sc_scanning = 1; 5505 sc->sc_syncbeacon = 0; 5506 rfilt = ath_calcrxfilter(sc); 5507 ath_hal_setrxfilter(ah, rfilt); 5508 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5509 5510 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0\n", 5511 __func__, rfilt, ifp->if_broadcastaddr, ":"); 5512 } 5513 5514 static void 5515 ath_scan_end(struct ieee80211com *ic) 5516 { 5517 struct ifnet *ifp = ic->ic_ifp; 5518 struct ath_softc *sc = ifp->if_softc; 5519 struct ath_hal *ah = sc->sc_ah; 5520 u_int32_t rfilt; 5521 5522 sc->sc_scanning = 0; 5523 rfilt = ath_calcrxfilter(sc); 5524 ath_hal_setrxfilter(ah, rfilt); 5525 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5526 5527 ath_hal_process_noisefloor(ah); 5528 5529 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0x%x\n", 5530 __func__, rfilt, sc->sc_curbssid, ":", 5531 sc->sc_curaid); 5532 } 5533 5534 static void 5535 ath_set_channel(struct ieee80211com *ic) 5536 { 5537 struct ifnet *ifp = ic->ic_ifp; 5538 struct ath_softc *sc = ifp->if_softc; 5539 5540 (void) ath_chan_set(sc, ic->ic_curchan); 5541 /* 5542 * If we are returning to our bss channel then mark state 5543 * so the next recv'd beacon's tsf will be used to sync the 5544 * beacon timers. Note that since we only hear beacons in 5545 * sta/ibss mode this has no effect in other operating modes. 5546 */ 5547 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5548 sc->sc_syncbeacon = 1; 5549 } 5550 5551 /* 5552 * Walk the vap list and check if there any vap's in RUN state. 5553 */ 5554 static int 5555 ath_isanyrunningvaps(struct ieee80211vap *this) 5556 { 5557 struct ieee80211com *ic = this->iv_ic; 5558 struct ieee80211vap *vap; 5559 5560 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5561 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5562 return 1; 5563 } 5564 return 0; 5565 } 5566 5567 static int 5568 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5569 { 5570 struct ieee80211com *ic = vap->iv_ic; 5571 struct ath_softc *sc = ic->ic_ifp->if_softc; 5572 struct ath_vap *avp = ATH_VAP(vap); 5573 struct ath_hal *ah = sc->sc_ah; 5574 struct ieee80211_node *ni = NULL; 5575 int i, error, stamode; 5576 u_int32_t rfilt; 5577 static const HAL_LED_STATE leds[] = { 5578 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5579 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5580 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5581 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5582 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5583 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5584 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5585 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5586 }; 5587 5588 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5589 ieee80211_state_name[vap->iv_state], 5590 ieee80211_state_name[nstate]); 5591 5592 callout_stop(&sc->sc_cal_ch); 5593 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5594 5595 if (nstate == IEEE80211_S_SCAN) { 5596 /* 5597 * Scanning: turn off beacon miss and don't beacon. 5598 * Mark beacon state so when we reach RUN state we'll 5599 * [re]setup beacons. Unblock the task q thread so 5600 * deferred interrupt processing is done. 5601 */ 5602 ath_hal_intrset(ah, 5603 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5604 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5605 sc->sc_beacons = 0; 5606 taskqueue_unblock(sc->sc_tq); 5607 } 5608 5609 ni = vap->iv_bss; 5610 rfilt = ath_calcrxfilter(sc); 5611 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5612 vap->iv_opmode == IEEE80211_M_AHDEMO || 5613 vap->iv_opmode == IEEE80211_M_IBSS); 5614 if (stamode && nstate == IEEE80211_S_RUN) { 5615 sc->sc_curaid = ni->ni_associd; 5616 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5617 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5618 } 5619 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0x%x\n", 5620 __func__, rfilt, sc->sc_curbssid, ":", sc->sc_curaid); 5621 ath_hal_setrxfilter(ah, rfilt); 5622 5623 /* XXX is this to restore keycache on resume? */ 5624 if (vap->iv_opmode != IEEE80211_M_STA && 5625 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5626 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5627 if (ath_hal_keyisvalid(ah, i)) 5628 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5629 } 5630 5631 /* 5632 * Invoke the parent method to do net80211 work. 5633 */ 5634 error = avp->av_newstate(vap, nstate, arg); 5635 if (error != 0) 5636 goto bad; 5637 5638 if (nstate == IEEE80211_S_RUN) { 5639 /* NB: collect bss node again, it may have changed */ 5640 ni = vap->iv_bss; 5641 5642 DPRINTF(sc, ATH_DEBUG_STATE, 5643 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %6D " 5644 "capinfo 0x%04x chan %d\n", __func__, 5645 vap->iv_flags, ni->ni_intval, ni->ni_bssid, ":", 5646 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5647 5648 switch (vap->iv_opmode) { 5649 #ifdef IEEE80211_SUPPORT_TDMA 5650 case IEEE80211_M_AHDEMO: 5651 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5652 break; 5653 /* fall thru... */ 5654 #endif 5655 case IEEE80211_M_HOSTAP: 5656 case IEEE80211_M_IBSS: 5657 case IEEE80211_M_MBSS: 5658 /* 5659 * Allocate and setup the beacon frame. 5660 * 5661 * Stop any previous beacon DMA. This may be 5662 * necessary, for example, when an ibss merge 5663 * causes reconfiguration; there will be a state 5664 * transition from RUN->RUN that means we may 5665 * be called with beacon transmission active. 5666 */ 5667 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5668 5669 error = ath_beacon_alloc(sc, ni); 5670 if (error != 0) 5671 goto bad; 5672 /* 5673 * If joining an adhoc network defer beacon timer 5674 * configuration to the next beacon frame so we 5675 * have a current TSF to use. Otherwise we're 5676 * starting an ibss/bss so there's no need to delay; 5677 * if this is the first vap moving to RUN state, then 5678 * beacon state needs to be [re]configured. 5679 */ 5680 if (vap->iv_opmode == IEEE80211_M_IBSS && 5681 ni->ni_tstamp.tsf != 0) { 5682 sc->sc_syncbeacon = 1; 5683 } else if (!sc->sc_beacons) { 5684 #ifdef IEEE80211_SUPPORT_TDMA 5685 if (vap->iv_caps & IEEE80211_C_TDMA) 5686 ath_tdma_config(sc, vap); 5687 else 5688 #endif 5689 ath_beacon_config(sc, vap); 5690 sc->sc_beacons = 1; 5691 } 5692 break; 5693 case IEEE80211_M_STA: 5694 /* 5695 * Defer beacon timer configuration to the next 5696 * beacon frame so we have a current TSF to use 5697 * (any TSF collected when scanning is likely old). 5698 */ 5699 sc->sc_syncbeacon = 1; 5700 break; 5701 case IEEE80211_M_MONITOR: 5702 /* 5703 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5704 * transitions so we must re-enable interrupts here to 5705 * handle the case of a single monitor mode vap. 5706 */ 5707 ath_hal_intrset(ah, sc->sc_imask); 5708 break; 5709 case IEEE80211_M_WDS: 5710 break; 5711 default: 5712 break; 5713 } 5714 /* 5715 * Let the hal process statistics collected during a 5716 * scan so it can provide calibrated noise floor data. 5717 */ 5718 ath_hal_process_noisefloor(ah); 5719 /* 5720 * Reset rssi stats; maybe not the best place... 5721 */ 5722 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5723 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5724 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5725 /* 5726 * Finally, start any timers and the task q thread 5727 * (in case we didn't go through SCAN state). 5728 */ 5729 if (ath_longcalinterval != 0) { 5730 /* start periodic recalibration timer */ 5731 callout_reset(&sc->sc_cal_ch, 1, 5732 ath_calibrate_callout, sc); 5733 } else { 5734 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5735 "%s: calibration disabled\n", __func__); 5736 } 5737 taskqueue_unblock(sc->sc_tq); 5738 } else if (nstate == IEEE80211_S_INIT) { 5739 /* 5740 * If there are no vaps left in RUN state then 5741 * shutdown host/driver operation: 5742 * o disable interrupts 5743 * o disable the task queue thread 5744 * o mark beacon processing as stopped 5745 */ 5746 if (!ath_isanyrunningvaps(vap)) { 5747 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5748 /* disable interrupts */ 5749 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5750 taskqueue_block(sc->sc_tq); 5751 sc->sc_beacons = 0; 5752 } 5753 #ifdef IEEE80211_SUPPORT_TDMA 5754 ath_hal_setcca(ah, AH_TRUE); 5755 #endif 5756 } 5757 bad: 5758 return error; 5759 } 5760 5761 /* 5762 * Allocate a key cache slot to the station so we can 5763 * setup a mapping from key index to node. The key cache 5764 * slot is needed for managing antenna state and for 5765 * compression when stations do not use crypto. We do 5766 * it uniliaterally here; if crypto is employed this slot 5767 * will be reassigned. 5768 */ 5769 static void 5770 ath_setup_stationkey(struct ieee80211_node *ni) 5771 { 5772 struct ieee80211vap *vap = ni->ni_vap; 5773 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5774 ieee80211_keyix keyix, rxkeyix; 5775 5776 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5777 /* 5778 * Key cache is full; we'll fall back to doing 5779 * the more expensive lookup in software. Note 5780 * this also means no h/w compression. 5781 */ 5782 /* XXX msg+statistic */ 5783 } else { 5784 /* XXX locking? */ 5785 ni->ni_ucastkey.wk_keyix = keyix; 5786 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5787 /* NB: must mark device key to get called back on delete */ 5788 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5789 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5790 /* NB: this will create a pass-thru key entry */ 5791 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5792 } 5793 } 5794 5795 /* 5796 * Setup driver-specific state for a newly associated node. 5797 * Note that we're called also on a re-associate, the isnew 5798 * param tells us if this is the first time or not. 5799 */ 5800 static void 5801 ath_newassoc(struct ieee80211_node *ni, int isnew) 5802 { 5803 struct ath_node *an = ATH_NODE(ni); 5804 struct ieee80211vap *vap = ni->ni_vap; 5805 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5806 const struct ieee80211_txparam *tp = ni->ni_txparms; 5807 5808 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5809 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5810 5811 ath_rate_newassoc(sc, an, isnew); 5812 if (isnew && 5813 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5814 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5815 ath_setup_stationkey(ni); 5816 } 5817 5818 static int 5819 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5820 int nchans, struct ieee80211_channel chans[]) 5821 { 5822 struct ath_softc *sc = ic->ic_ifp->if_softc; 5823 struct ath_hal *ah = sc->sc_ah; 5824 HAL_STATUS status; 5825 5826 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5827 "%s: rd %u cc %u location %c%s\n", 5828 __func__, reg->regdomain, reg->country, reg->location, 5829 reg->ecm ? " ecm" : ""); 5830 5831 status = ath_hal_set_channels(ah, chans, nchans, 5832 reg->country, reg->regdomain); 5833 if (status != HAL_OK) { 5834 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5835 __func__, status); 5836 return EINVAL; /* XXX */ 5837 } 5838 return 0; 5839 } 5840 5841 static void 5842 ath_getradiocaps(struct ieee80211com *ic, 5843 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5844 { 5845 struct ath_softc *sc = ic->ic_ifp->if_softc; 5846 struct ath_hal *ah = sc->sc_ah; 5847 5848 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5849 __func__, SKU_DEBUG, CTRY_DEFAULT); 5850 5851 /* XXX check return */ 5852 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5853 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5854 5855 } 5856 5857 static int 5858 ath_getchannels(struct ath_softc *sc) 5859 { 5860 struct ifnet *ifp = sc->sc_ifp; 5861 struct ieee80211com *ic = ifp->if_l2com; 5862 struct ath_hal *ah = sc->sc_ah; 5863 HAL_STATUS status; 5864 5865 /* 5866 * Collect channel set based on EEPROM contents. 5867 */ 5868 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5869 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5870 if (status != HAL_OK) { 5871 if_printf(ifp, "%s: unable to collect channel list from hal, " 5872 "status %d\n", __func__, status); 5873 return EINVAL; 5874 } 5875 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5876 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5877 /* XXX map Atheros sku's to net80211 SKU's */ 5878 /* XXX net80211 types too small */ 5879 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5880 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5881 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5882 ic->ic_regdomain.isocc[1] = ' '; 5883 5884 ic->ic_regdomain.ecm = 1; 5885 ic->ic_regdomain.location = 'I'; 5886 5887 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5888 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5889 __func__, sc->sc_eerd, sc->sc_eecc, 5890 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5891 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5892 return 0; 5893 } 5894 5895 static void 5896 ath_led_done_callout(void *arg) 5897 { 5898 struct ath_softc *sc = arg; 5899 5900 wlan_serialize_enter(); 5901 sc->sc_blinking = 0; 5902 wlan_serialize_exit(); 5903 } 5904 5905 /* 5906 * Turn the LED off: flip the pin and then set a timer so no 5907 * update will happen for the specified duration. 5908 */ 5909 static void 5910 ath_led_off_callout(void *arg) 5911 { 5912 struct ath_softc *sc = arg; 5913 5914 wlan_serialize_enter(); 5915 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5916 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, 5917 ath_led_done_callout, sc); 5918 wlan_serialize_exit(); 5919 } 5920 5921 /* 5922 * Blink the LED according to the specified on/off times. 5923 */ 5924 static void 5925 ath_led_blink(struct ath_softc *sc, int on, int off) 5926 { 5927 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5928 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5929 sc->sc_blinking = 1; 5930 sc->sc_ledoff = off; 5931 callout_reset(&sc->sc_ledtimer, on, ath_led_off_callout, sc); 5932 } 5933 5934 static void 5935 ath_led_event(struct ath_softc *sc, int rix) 5936 { 5937 sc->sc_ledevent = ticks; /* time of last event */ 5938 if (sc->sc_blinking) /* don't interrupt active blink */ 5939 return; 5940 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5941 } 5942 5943 static int 5944 ath_rate_setup(struct ath_softc *sc, u_int mode) 5945 { 5946 struct ath_hal *ah = sc->sc_ah; 5947 const HAL_RATE_TABLE *rt; 5948 5949 switch (mode) { 5950 case IEEE80211_MODE_11A: 5951 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5952 break; 5953 case IEEE80211_MODE_HALF: 5954 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5955 break; 5956 case IEEE80211_MODE_QUARTER: 5957 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5958 break; 5959 case IEEE80211_MODE_11B: 5960 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5961 break; 5962 case IEEE80211_MODE_11G: 5963 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5964 break; 5965 case IEEE80211_MODE_TURBO_A: 5966 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5967 break; 5968 case IEEE80211_MODE_TURBO_G: 5969 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5970 break; 5971 case IEEE80211_MODE_STURBO_A: 5972 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5973 break; 5974 case IEEE80211_MODE_11NA: 5975 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5976 break; 5977 case IEEE80211_MODE_11NG: 5978 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5979 break; 5980 default: 5981 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5982 __func__, mode); 5983 return 0; 5984 } 5985 sc->sc_rates[mode] = rt; 5986 return (rt != NULL); 5987 } 5988 5989 static void 5990 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5991 { 5992 #define N(a) (sizeof(a)/sizeof(a[0])) 5993 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5994 static const struct { 5995 u_int rate; /* tx/rx 802.11 rate */ 5996 u_int16_t timeOn; /* LED on time (ms) */ 5997 u_int16_t timeOff; /* LED off time (ms) */ 5998 } blinkrates[] = { 5999 { 108, 40, 10 }, 6000 { 96, 44, 11 }, 6001 { 72, 50, 13 }, 6002 { 48, 57, 14 }, 6003 { 36, 67, 16 }, 6004 { 24, 80, 20 }, 6005 { 22, 100, 25 }, 6006 { 18, 133, 34 }, 6007 { 12, 160, 40 }, 6008 { 10, 200, 50 }, 6009 { 6, 240, 58 }, 6010 { 4, 267, 66 }, 6011 { 2, 400, 100 }, 6012 { 0, 500, 130 }, 6013 /* XXX half/quarter rates */ 6014 }; 6015 const HAL_RATE_TABLE *rt; 6016 int i, j; 6017 6018 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6019 rt = sc->sc_rates[mode]; 6020 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6021 for (i = 0; i < rt->rateCount; i++) { 6022 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6023 if (rt->info[i].phy != IEEE80211_T_HT) 6024 sc->sc_rixmap[ieeerate] = i; 6025 else 6026 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6027 } 6028 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6029 for (i = 0; i < N(sc->sc_hwmap); i++) { 6030 if (i >= rt->rateCount) { 6031 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6032 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6033 continue; 6034 } 6035 sc->sc_hwmap[i].ieeerate = 6036 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6037 if (rt->info[i].phy == IEEE80211_T_HT) 6038 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6039 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6040 if (rt->info[i].shortPreamble || 6041 rt->info[i].phy == IEEE80211_T_OFDM) 6042 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6043 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6044 for (j = 0; j < N(blinkrates)-1; j++) 6045 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6046 break; 6047 /* NB: this uses the last entry if the rate isn't found */ 6048 /* XXX beware of overlow */ 6049 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6050 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6051 } 6052 sc->sc_currates = rt; 6053 sc->sc_curmode = mode; 6054 /* 6055 * All protection frames are transmited at 2Mb/s for 6056 * 11g, otherwise at 1Mb/s. 6057 */ 6058 if (mode == IEEE80211_MODE_11G) 6059 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6060 else 6061 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6062 /* NB: caller is responsible for reseting rate control state */ 6063 #undef N 6064 } 6065 6066 #ifdef ATH_DEBUG 6067 static void 6068 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6069 u_int ix, int done) 6070 { 6071 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6072 struct ath_hal *ah = sc->sc_ah; 6073 const struct ath_desc *ds; 6074 int i; 6075 6076 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6077 kprintf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6078 " %08x %08x %08x %08x\n", 6079 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6080 ds->ds_link, ds->ds_data, 6081 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6082 ds->ds_ctl0, ds->ds_ctl1, 6083 ds->ds_hw[0], ds->ds_hw[1]); 6084 if (ah->ah_magic == 0x20065416) { 6085 kprintf(" %08x %08x %08x %08x %08x %08x %08x\n", 6086 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6087 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6088 ds->ds_hw[8]); 6089 } 6090 } 6091 } 6092 6093 static void 6094 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6095 u_int qnum, u_int ix, int done) 6096 { 6097 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6098 struct ath_hal *ah = sc->sc_ah; 6099 const struct ath_desc *ds; 6100 int i; 6101 6102 kprintf("Q%u[%3u]", qnum, ix); 6103 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6104 kprintf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6105 " %08x %08x %08x %08x %08x %08x\n", 6106 ds, (const struct ath_desc *)bf->bf_daddr + i, 6107 ds->ds_link, ds->ds_data, bf->bf_txflags, 6108 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6109 ds->ds_ctl0, ds->ds_ctl1, 6110 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6111 if (ah->ah_magic == 0x20065416) { 6112 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6113 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6114 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6115 ds->ds_hw[10],ds->ds_hw[11]); 6116 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6117 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6118 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6119 ds->ds_hw[18], ds->ds_hw[19]); 6120 } 6121 } 6122 } 6123 #endif /* ATH_DEBUG */ 6124 6125 static void 6126 ath_watchdog_callout(void *arg) 6127 { 6128 struct ath_softc *sc = arg; 6129 6130 wlan_serialize_enter(); 6131 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6132 struct ifnet *ifp = sc->sc_ifp; 6133 uint32_t hangs; 6134 6135 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6136 hangs != 0) { 6137 if_printf(ifp, "%s hang detected (0x%x)\n", 6138 hangs & 0xff ? "bb" : "mac", hangs); 6139 } else 6140 if_printf(ifp, "device timeout\n"); 6141 ath_reset(ifp); 6142 ifp->if_oerrors++; 6143 sc->sc_stats.ast_watchdog++; 6144 } 6145 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 6146 wlan_serialize_exit(); 6147 } 6148 6149 #ifdef ATH_DIAGAPI 6150 /* 6151 * Diagnostic interface to the HAL. This is used by various 6152 * tools to do things like retrieve register contents for 6153 * debugging. The mechanism is intentionally opaque so that 6154 * it can change frequently w/o concern for compatiblity. 6155 */ 6156 static int 6157 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6158 { 6159 struct ath_hal *ah = sc->sc_ah; 6160 u_int id = ad->ad_id & ATH_DIAG_ID; 6161 void *indata = NULL; 6162 void *outdata = NULL; 6163 u_int32_t insize = ad->ad_in_size; 6164 u_int32_t outsize = ad->ad_out_size; 6165 int error = 0; 6166 6167 if (ad->ad_id & ATH_DIAG_IN) { 6168 /* 6169 * Copy in data. 6170 */ 6171 indata = kmalloc(insize, M_TEMP, M_INTWAIT); 6172 if (indata == NULL) { 6173 error = ENOMEM; 6174 goto bad; 6175 } 6176 error = copyin(ad->ad_in_data, indata, insize); 6177 if (error) 6178 goto bad; 6179 } 6180 if (ad->ad_id & ATH_DIAG_DYN) { 6181 /* 6182 * Allocate a buffer for the results (otherwise the HAL 6183 * returns a pointer to a buffer where we can read the 6184 * results). Note that we depend on the HAL leaving this 6185 * pointer for us to use below in reclaiming the buffer; 6186 * may want to be more defensive. 6187 */ 6188 outdata = kmalloc(outsize, M_TEMP, M_INTWAIT); 6189 if (outdata == NULL) { 6190 error = ENOMEM; 6191 goto bad; 6192 } 6193 } 6194 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6195 if (outsize < ad->ad_out_size) 6196 ad->ad_out_size = outsize; 6197 if (outdata != NULL) 6198 error = copyout(outdata, ad->ad_out_data, 6199 ad->ad_out_size); 6200 } else { 6201 error = EINVAL; 6202 } 6203 bad: 6204 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6205 kfree(indata, M_TEMP); 6206 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6207 kfree(outdata, M_TEMP); 6208 return error; 6209 } 6210 #endif /* ATH_DIAGAPI */ 6211 6212 static int 6213 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 6214 { 6215 #define IS_RUNNING(ifp) \ 6216 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 6217 struct ath_softc *sc = ifp->if_softc; 6218 struct ieee80211com *ic = ifp->if_l2com; 6219 struct ifreq *ifr = (struct ifreq *)data; 6220 const HAL_RATE_TABLE *rt; 6221 int error = 0; 6222 6223 switch (cmd) { 6224 case SIOCSIFFLAGS: 6225 if (IS_RUNNING(ifp)) { 6226 /* 6227 * To avoid rescanning another access point, 6228 * do not call ath_init() here. Instead, 6229 * only reflect promisc mode settings. 6230 */ 6231 ath_mode_init(sc); 6232 } else if (ifp->if_flags & IFF_UP) { 6233 /* 6234 * Beware of being called during attach/detach 6235 * to reset promiscuous mode. In that case we 6236 * will still be marked UP but not RUNNING. 6237 * However trying to re-init the interface 6238 * is the wrong thing to do as we've already 6239 * torn down much of our state. There's 6240 * probably a better way to deal with this. 6241 */ 6242 if (!sc->sc_invalid) 6243 ath_init(sc); /* XXX lose error */ 6244 } else { 6245 ath_stop_locked(ifp); 6246 #ifdef notyet 6247 /* XXX must wakeup in places like ath_vap_delete */ 6248 if (!sc->sc_invalid) 6249 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6250 #endif 6251 } 6252 break; 6253 case SIOCGIFMEDIA: 6254 case SIOCSIFMEDIA: 6255 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6256 break; 6257 case SIOCGATHSTATS: 6258 /* NB: embed these numbers to get a consistent view */ 6259 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6260 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6261 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6262 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6263 #ifdef IEEE80211_SUPPORT_TDMA 6264 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6265 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6266 #endif 6267 rt = sc->sc_currates; 6268 /* XXX HT rates */ 6269 sc->sc_stats.ast_tx_rate = 6270 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6271 return copyout(&sc->sc_stats, 6272 ifr->ifr_data, sizeof (sc->sc_stats)); 6273 case SIOCZATHSTATS: 6274 error = priv_check(curthread, PRIV_DRIVER); 6275 if (error == 0) 6276 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6277 break; 6278 #ifdef ATH_DIAGAPI 6279 case SIOCGATHDIAG: 6280 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6281 break; 6282 #endif 6283 case SIOCGIFADDR: 6284 error = ether_ioctl(ifp, cmd, data); 6285 break; 6286 default: 6287 error = EINVAL; 6288 break; 6289 } 6290 return error; 6291 #undef IS_RUNNING 6292 } 6293 6294 static int 6295 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6296 { 6297 struct ath_softc *sc = arg1; 6298 u_int slottime; 6299 int error; 6300 6301 wlan_serialize_enter(); 6302 slottime = ath_hal_getslottime(sc->sc_ah); 6303 error = sysctl_handle_int(oidp, &slottime, 0, req); 6304 if (error == 0 && req->newptr) { 6305 if (!ath_hal_setslottime(sc->sc_ah, slottime)) 6306 error = EINVAL; 6307 } 6308 wlan_serialize_exit(); 6309 return error; 6310 } 6311 6312 static int 6313 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6314 { 6315 struct ath_softc *sc = arg1; 6316 u_int acktimeout; 6317 int error; 6318 6319 wlan_serialize_enter(); 6320 acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6321 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6322 if (error == 0 && req->newptr) { 6323 if (!ath_hal_setacktimeout(sc->sc_ah, acktimeout)) 6324 error = EINVAL; 6325 } 6326 wlan_serialize_exit(); 6327 return error; 6328 } 6329 6330 static int 6331 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6332 { 6333 struct ath_softc *sc = arg1; 6334 u_int ctstimeout; 6335 int error; 6336 6337 wlan_serialize_enter(); 6338 ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6339 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6340 if (error == 0 && req->newptr) { 6341 if (!ath_hal_setctstimeout(sc->sc_ah, ctstimeout)) 6342 error = EINVAL; 6343 } 6344 wlan_serialize_exit(); 6345 return error; 6346 } 6347 6348 static int 6349 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6350 { 6351 struct ath_softc *sc = arg1; 6352 int softled = sc->sc_softled; 6353 int error; 6354 6355 error = sysctl_handle_int(oidp, &softled, 0, req); 6356 if (error || !req->newptr) 6357 return error; 6358 wlan_serialize_enter(); 6359 softled = (softled != 0); 6360 if (softled != sc->sc_softled) { 6361 if (softled) { 6362 /* NB: handle any sc_ledpin change */ 6363 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6364 HAL_GPIO_MUX_MAC_NETWORK_LED); 6365 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6366 !sc->sc_ledon); 6367 } 6368 sc->sc_softled = softled; 6369 } 6370 wlan_serialize_exit(); 6371 return 0; 6372 } 6373 6374 static int 6375 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6376 { 6377 struct ath_softc *sc = arg1; 6378 int ledpin = sc->sc_ledpin; 6379 int error; 6380 6381 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6382 if (error || !req->newptr) 6383 return error; 6384 wlan_serialize_enter(); 6385 if (ledpin != sc->sc_ledpin) { 6386 sc->sc_ledpin = ledpin; 6387 if (sc->sc_softled) { 6388 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6389 HAL_GPIO_MUX_MAC_NETWORK_LED); 6390 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6391 !sc->sc_ledon); 6392 } 6393 } 6394 wlan_serialize_exit(); 6395 return 0; 6396 } 6397 6398 static int 6399 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6400 { 6401 struct ath_softc *sc = arg1; 6402 u_int txantenna; 6403 int error; 6404 6405 wlan_serialize_enter(); 6406 txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6407 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6408 6409 if (!error && req->newptr) { 6410 /* XXX assumes 2 antenna ports */ 6411 if (txantenna < HAL_ANT_VARIABLE || 6412 txantenna > HAL_ANT_FIXED_B) { 6413 error = EINVAL; 6414 } else { 6415 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6416 /* 6417 * NB: with the switch locked this isn't meaningful, 6418 * but set it anyway so things like radiotap get 6419 * consistent info in their data. 6420 */ 6421 sc->sc_txantenna = txantenna; 6422 } 6423 } 6424 wlan_serialize_exit(); 6425 return error; 6426 } 6427 6428 static int 6429 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6430 { 6431 struct ath_softc *sc = arg1; 6432 u_int defantenna; 6433 int error; 6434 6435 wlan_serialize_enter(); 6436 defantenna = ath_hal_getdefantenna(sc->sc_ah); 6437 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6438 if (error == 0 && req->newptr) 6439 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6440 wlan_serialize_exit(); 6441 return error; 6442 } 6443 6444 static int 6445 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6446 { 6447 struct ath_softc *sc = arg1; 6448 u_int diversity; 6449 int error; 6450 6451 wlan_serialize_enter(); 6452 diversity = ath_hal_getdiversity(sc->sc_ah); 6453 error = sysctl_handle_int(oidp, &diversity, 0, req); 6454 if (error == 0 && req->newptr) { 6455 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6456 error = EINVAL; 6457 else 6458 sc->sc_diversity = diversity; 6459 } 6460 wlan_serialize_exit(); 6461 return error; 6462 } 6463 6464 static int 6465 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6466 { 6467 struct ath_softc *sc = arg1; 6468 u_int32_t diag; 6469 int error; 6470 6471 wlan_serialize_enter(); 6472 if (!ath_hal_getdiag(sc->sc_ah, &diag)) { 6473 error = EINVAL; 6474 } else { 6475 error = sysctl_handle_int(oidp, &diag, 0, req); 6476 if (error == 0 && req->newptr) { 6477 if (!ath_hal_setdiag(sc->sc_ah, diag)) 6478 error = EINVAL; 6479 } 6480 } 6481 wlan_serialize_exit(); 6482 return error; 6483 } 6484 6485 static int 6486 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6487 { 6488 struct ath_softc *sc = arg1; 6489 struct ifnet *ifp = sc->sc_ifp; 6490 u_int32_t scale; 6491 int error; 6492 6493 wlan_serialize_enter(); 6494 (void)ath_hal_gettpscale(sc->sc_ah, &scale); 6495 error = sysctl_handle_int(oidp, &scale, 0, req); 6496 if (error == 0 && req->newptr) { 6497 if (!ath_hal_settpscale(sc->sc_ah, scale)) 6498 error = EINVAL; 6499 else if (ifp->if_flags & IFF_RUNNING) 6500 error = ath_reset(ifp); 6501 } 6502 wlan_serialize_exit(); 6503 return error; 6504 } 6505 6506 static int 6507 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6508 { 6509 struct ath_softc *sc = arg1; 6510 u_int tpc; 6511 int error; 6512 6513 wlan_serialize_enter(); 6514 tpc = ath_hal_gettpc(sc->sc_ah); 6515 error = sysctl_handle_int(oidp, &tpc, 0, req); 6516 if (error == 0 && req->newptr) { 6517 if (!ath_hal_settpc(sc->sc_ah, tpc)) 6518 error = EINVAL; 6519 } 6520 wlan_serialize_exit(); 6521 return error; 6522 } 6523 6524 static int 6525 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6526 { 6527 struct ath_softc *sc = arg1; 6528 struct ifnet *ifp; 6529 struct ath_hal *ah; 6530 u_int rfkill; 6531 int error; 6532 6533 wlan_serialize_enter(); 6534 ifp = sc->sc_ifp; 6535 ah = sc->sc_ah; 6536 rfkill = ath_hal_getrfkill(ah); 6537 6538 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6539 if (error == 0 && req->newptr) { 6540 if (rfkill != ath_hal_getrfkill(ah)) { 6541 if (!ath_hal_setrfkill(ah, rfkill)) 6542 error = EINVAL; 6543 else if (ifp->if_flags & IFF_RUNNING) 6544 error = ath_reset(ifp); 6545 } 6546 } 6547 wlan_serialize_exit(); 6548 return error; 6549 } 6550 6551 static int 6552 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6553 { 6554 struct ath_softc *sc = arg1; 6555 u_int rfsilent; 6556 int error; 6557 6558 wlan_serialize_enter(); 6559 (void)ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6560 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6561 if (error == 0 && req->newptr) { 6562 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) { 6563 error = EINVAL; 6564 } else { 6565 sc->sc_rfsilentpin = rfsilent & 0x1c; 6566 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6567 } 6568 } 6569 wlan_serialize_exit(); 6570 return error; 6571 } 6572 6573 static int 6574 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6575 { 6576 struct ath_softc *sc = arg1; 6577 u_int32_t tpack; 6578 int error; 6579 6580 wlan_serialize_enter(); 6581 (void)ath_hal_gettpack(sc->sc_ah, &tpack); 6582 error = sysctl_handle_int(oidp, &tpack, 0, req); 6583 if (error == 0 && req->newptr) { 6584 if (!ath_hal_settpack(sc->sc_ah, tpack)) 6585 error = EINVAL; 6586 } 6587 wlan_serialize_exit(); 6588 return error; 6589 } 6590 6591 static int 6592 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6593 { 6594 struct ath_softc *sc = arg1; 6595 u_int32_t tpcts; 6596 int error; 6597 6598 wlan_serialize_enter(); 6599 (void)ath_hal_gettpcts(sc->sc_ah, &tpcts); 6600 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6601 if (error == 0 && req->newptr) { 6602 if (!ath_hal_settpcts(sc->sc_ah, tpcts)) 6603 error = EINVAL; 6604 } 6605 wlan_serialize_exit(); 6606 return error; 6607 } 6608 6609 static int 6610 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6611 { 6612 struct ath_softc *sc = arg1; 6613 int intmit, error; 6614 6615 wlan_serialize_enter(); 6616 intmit = ath_hal_getintmit(sc->sc_ah); 6617 error = sysctl_handle_int(oidp, &intmit, 0, req); 6618 if (error == 0 && req->newptr) { 6619 if (!ath_hal_setintmit(sc->sc_ah, intmit)) 6620 error = EINVAL; 6621 } 6622 wlan_serialize_exit(); 6623 return error; 6624 } 6625 6626 #ifdef IEEE80211_SUPPORT_TDMA 6627 static int 6628 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) 6629 { 6630 struct ath_softc *sc = arg1; 6631 int setcca, error; 6632 6633 wlan_serialize_enter(); 6634 setcca = sc->sc_setcca; 6635 error = sysctl_handle_int(oidp, &setcca, 0, req); 6636 if (error == 0 && req->newptr) 6637 sc->sc_setcca = (setcca != 0); 6638 wlan_serialize_exit(); 6639 return error; 6640 } 6641 #endif /* IEEE80211_SUPPORT_TDMA */ 6642 6643 static void 6644 ath_sysctlattach(struct ath_softc *sc) 6645 { 6646 struct sysctl_ctx_list *ctx; 6647 struct sysctl_oid *tree; 6648 struct ath_hal *ah = sc->sc_ah; 6649 6650 ctx = &sc->sc_sysctl_ctx; 6651 tree = sc->sc_sysctl_tree; 6652 if (tree == NULL) { 6653 device_printf(sc->sc_dev, "can't add sysctl node\n"); 6654 return; 6655 } 6656 6657 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6658 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6659 "EEPROM country code"); 6660 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6661 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6662 "EEPROM regdomain code"); 6663 #ifdef ATH_DEBUG 6664 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6665 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6666 "control debugging printfs"); 6667 #endif 6668 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6669 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6670 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6671 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6672 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6673 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6674 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6675 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6676 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6677 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6678 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6679 ath_sysctl_softled, "I", "enable/disable software LED support"); 6680 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6681 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6682 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6683 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6684 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6685 "setting to turn LED on"); 6686 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6687 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6688 "idle time for inactivity LED (ticks)"); 6689 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6690 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6691 ath_sysctl_txantenna, "I", "antenna switch"); 6692 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6693 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6694 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6695 if (ath_hal_hasdiversity(ah)) 6696 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6697 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6698 ath_sysctl_diversity, "I", "antenna diversity"); 6699 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6700 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6701 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6702 "tx descriptor batching"); 6703 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6704 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6705 ath_sysctl_diag, "I", "h/w diagnostic control"); 6706 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6707 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6708 ath_sysctl_tpscale, "I", "tx power scaling"); 6709 if (ath_hal_hastpc(ah)) { 6710 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6711 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6712 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6713 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6714 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6715 ath_sysctl_tpack, "I", "tx power for ack frames"); 6716 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6717 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6718 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6719 } 6720 if (ath_hal_hasrfsilent(ah)) { 6721 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6722 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6723 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6724 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6725 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6726 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6727 } 6728 if (ath_hal_hasintmit(ah)) { 6729 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6730 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6731 ath_sysctl_intmit, "I", "interference mitigation"); 6732 } 6733 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6734 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6735 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6736 "mask of error frames to pass when monitoring"); 6737 #ifdef IEEE80211_SUPPORT_TDMA 6738 if (ath_hal_macversion(ah) > 0x78) { 6739 sc->sc_tdmadbaprep = 2; 6740 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6741 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, 6742 "TDMA DBA preparation time"); 6743 sc->sc_tdmaswbaprep = 10; 6744 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6745 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, 6746 "TDMA SWBA preparation time"); 6747 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6748 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, 6749 "TDMA slot guard time"); 6750 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6751 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, 6752 "TDMA calculated super frame"); 6753 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6754 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6755 ath_sysctl_setcca, "I", "enable CCA control"); 6756 } 6757 #endif 6758 } 6759 6760 static int 6761 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6762 struct ath_buf *bf, struct mbuf *m0, 6763 const struct ieee80211_bpf_params *params) 6764 { 6765 struct ifnet *ifp = sc->sc_ifp; 6766 struct ieee80211com *ic = ifp->if_l2com; 6767 struct ath_hal *ah = sc->sc_ah; 6768 struct ieee80211vap *vap = ni->ni_vap; 6769 int error, ismcast, ismrr; 6770 int keyix, hdrlen, pktlen, try0, txantenna; 6771 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6772 struct ieee80211_frame *wh; 6773 u_int flags, ctsduration; 6774 HAL_PKT_TYPE atype; 6775 const HAL_RATE_TABLE *rt; 6776 struct ath_desc *ds; 6777 u_int pri; 6778 6779 wh = mtod(m0, struct ieee80211_frame *); 6780 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6781 hdrlen = ieee80211_anyhdrsize(wh); 6782 /* 6783 * Packet length must not include any 6784 * pad bytes; deduct them here. 6785 */ 6786 /* XXX honor IEEE80211_BPF_DATAPAD */ 6787 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6788 6789 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 6790 const struct ieee80211_cipher *cip; 6791 struct ieee80211_key *k; 6792 6793 /* 6794 * Construct the 802.11 header+trailer for an encrypted 6795 * frame. The only reason this can fail is because of an 6796 * unknown or unsupported cipher/key type. 6797 */ 6798 k = ieee80211_crypto_encap(ni, m0); 6799 if (k == NULL) { 6800 /* 6801 * This can happen when the key is yanked after the 6802 * frame was queued. Just discard the frame; the 6803 * 802.11 layer counts failures and provides 6804 * debugging/diagnostics. 6805 */ 6806 ath_freetx(m0); 6807 return EIO; 6808 } 6809 /* 6810 * Adjust the packet + header lengths for the crypto 6811 * additions and calculate the h/w key index. When 6812 * a s/w mic is done the frame will have had any mic 6813 * added to it prior to entry so m0->m_pkthdr.len will 6814 * account for it. Otherwise we need to add it to the 6815 * packet length. 6816 */ 6817 cip = k->wk_cipher; 6818 hdrlen += cip->ic_header; 6819 pktlen += cip->ic_header + cip->ic_trailer; 6820 /* NB: frags always have any TKIP MIC done in s/w */ 6821 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 6822 pktlen += cip->ic_miclen; 6823 keyix = k->wk_keyix; 6824 6825 /* packet header may have moved, reset our local pointer */ 6826 wh = mtod(m0, struct ieee80211_frame *); 6827 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 6828 /* 6829 * Use station key cache slot, if assigned. 6830 */ 6831 keyix = ni->ni_ucastkey.wk_keyix; 6832 if (keyix == IEEE80211_KEYIX_NONE) 6833 keyix = HAL_TXKEYIX_INVALID; 6834 } else 6835 keyix = HAL_TXKEYIX_INVALID; 6836 6837 error = ath_tx_dmasetup(sc, bf, m0); 6838 if (error != 0) 6839 return error; 6840 m0 = bf->bf_m; /* NB: may have changed */ 6841 wh = mtod(m0, struct ieee80211_frame *); 6842 bf->bf_node = ni; /* NB: held reference */ 6843 6844 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6845 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6846 if (params->ibp_flags & IEEE80211_BPF_RTS) 6847 flags |= HAL_TXDESC_RTSENA; 6848 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6849 flags |= HAL_TXDESC_CTSENA; 6850 /* XXX leave ismcast to injector? */ 6851 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6852 flags |= HAL_TXDESC_NOACK; 6853 6854 rt = sc->sc_currates; 6855 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6856 rix = ath_tx_findrix(sc, params->ibp_rate0); 6857 txrate = rt->info[rix].rateCode; 6858 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6859 txrate |= rt->info[rix].shortPreamble; 6860 sc->sc_txrix = rix; 6861 try0 = params->ibp_try0; 6862 ismrr = (params->ibp_try1 != 0); 6863 txantenna = params->ibp_pri >> 2; 6864 if (txantenna == 0) /* XXX? */ 6865 txantenna = sc->sc_txantenna; 6866 ctsduration = 0; 6867 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6868 cix = ath_tx_findrix(sc, params->ibp_ctsrate); 6869 ctsrate = rt->info[cix].rateCode; 6870 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6871 ctsrate |= rt->info[cix].shortPreamble; 6872 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6873 ctsduration += rt->info[cix].spAckDuration; 6874 ctsduration += ath_hal_computetxtime(ah, 6875 rt, pktlen, rix, AH_TRUE); 6876 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6877 ctsduration += rt->info[rix].spAckDuration; 6878 } else { 6879 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6880 ctsduration += rt->info[cix].lpAckDuration; 6881 ctsduration += ath_hal_computetxtime(ah, 6882 rt, pktlen, rix, AH_FALSE); 6883 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6884 ctsduration += rt->info[rix].lpAckDuration; 6885 } 6886 ismrr = 0; /* XXX */ 6887 } else 6888 ctsrate = 0; 6889 pri = params->ibp_pri & 3; 6890 /* 6891 * NB: we mark all packets as type PSPOLL so the h/w won't 6892 * set the sequence number, duration, etc. 6893 */ 6894 atype = HAL_PKT_TYPE_PSPOLL; 6895 6896 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6897 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6898 sc->sc_hwmap[rix].ieeerate, -1); 6899 6900 if (ieee80211_radiotap_active_vap(vap)) { 6901 u_int64_t tsf = ath_hal_gettsf64(ah); 6902 6903 sc->sc_tx_th.wt_tsf = htole64(tsf); 6904 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 6905 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6906 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6907 if (m0->m_flags & M_FRAG) 6908 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 6909 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 6910 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6911 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6912 6913 ieee80211_radiotap_tx(vap, m0); 6914 } 6915 6916 /* 6917 * Formulate first tx descriptor with tx controls. 6918 */ 6919 ds = bf->bf_desc; 6920 /* XXX check return value? */ 6921 ath_hal_setuptxdesc(ah, ds 6922 , pktlen /* packet length */ 6923 , hdrlen /* header length */ 6924 , atype /* Atheros packet type */ 6925 , params->ibp_power /* txpower */ 6926 , txrate, try0 /* series 0 rate/tries */ 6927 , keyix /* key cache index */ 6928 , txantenna /* antenna mode */ 6929 , flags /* flags */ 6930 , ctsrate /* rts/cts rate */ 6931 , ctsduration /* rts/cts duration */ 6932 ); 6933 bf->bf_txflags = flags; 6934 6935 if (ismrr) { 6936 rix = ath_tx_findrix(sc, params->ibp_rate1); 6937 rate1 = rt->info[rix].rateCode; 6938 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6939 rate1 |= rt->info[rix].shortPreamble; 6940 if (params->ibp_try2) { 6941 rix = ath_tx_findrix(sc, params->ibp_rate2); 6942 rate2 = rt->info[rix].rateCode; 6943 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6944 rate2 |= rt->info[rix].shortPreamble; 6945 } else 6946 rate2 = 0; 6947 if (params->ibp_try3) { 6948 rix = ath_tx_findrix(sc, params->ibp_rate3); 6949 rate3 = rt->info[rix].rateCode; 6950 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6951 rate3 |= rt->info[rix].shortPreamble; 6952 } else 6953 rate3 = 0; 6954 ath_hal_setupxtxdesc(ah, ds 6955 , rate1, params->ibp_try1 /* series 1 */ 6956 , rate2, params->ibp_try2 /* series 2 */ 6957 , rate3, params->ibp_try3 /* series 3 */ 6958 ); 6959 } 6960 6961 /* NB: no buffered multicast in power save support */ 6962 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 6963 return 0; 6964 } 6965 6966 static int 6967 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6968 const struct ieee80211_bpf_params *params) 6969 { 6970 struct ieee80211com *ic = ni->ni_ic; 6971 struct ifnet *ifp = ic->ic_ifp; 6972 struct ath_softc *sc = ifp->if_softc; 6973 struct ath_buf *bf; 6974 int error; 6975 6976 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 6977 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 6978 (ifp->if_flags & IFF_RUNNING) == 0 ? 6979 "!running" : "invalid"); 6980 m_freem(m); 6981 error = ENETDOWN; 6982 goto bad; 6983 } 6984 /* 6985 * Grab a TX buffer and associated resources. 6986 */ 6987 bf = ath_getbuf(sc); 6988 if (bf == NULL) { 6989 sc->sc_stats.ast_tx_nobuf++; 6990 m_freem(m); 6991 error = ENOBUFS; 6992 goto bad; 6993 } 6994 6995 if (params == NULL) { 6996 /* 6997 * Legacy path; interpret frame contents to decide 6998 * precisely how to send the frame. 6999 */ 7000 if (ath_tx_start(sc, ni, bf, m)) { 7001 error = EIO; /* XXX */ 7002 goto bad2; 7003 } 7004 } else { 7005 /* 7006 * Caller supplied explicit parameters to use in 7007 * sending the frame. 7008 */ 7009 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 7010 error = EIO; /* XXX */ 7011 goto bad2; 7012 } 7013 } 7014 sc->sc_wd_timer = 5; 7015 ifp->if_opackets++; 7016 sc->sc_stats.ast_tx_raw++; 7017 7018 return 0; 7019 bad2: 7020 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 7021 bad: 7022 ifp->if_oerrors++; 7023 sc->sc_stats.ast_tx_raw_fail++; 7024 ieee80211_free_node(ni); 7025 return error; 7026 } 7027 7028 /* 7029 * Announce various information on device/driver attach. 7030 */ 7031 static void 7032 ath_announce(struct ath_softc *sc) 7033 { 7034 struct ifnet *ifp = sc->sc_ifp; 7035 struct ath_hal *ah = sc->sc_ah; 7036 7037 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 7038 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 7039 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 7040 if (bootverbose) { 7041 int i; 7042 for (i = 0; i <= WME_AC_VO; i++) { 7043 struct ath_txq *txq = sc->sc_ac2q[i]; 7044 if_printf(ifp, "Use hw queue %u for %s traffic\n", 7045 txq->axq_qnum, ieee80211_wme_acnames[i]); 7046 } 7047 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 7048 sc->sc_cabq->axq_qnum); 7049 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 7050 } 7051 if (ath_rxbuf != ATH_RXBUF) 7052 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 7053 if (ath_txbuf != ATH_TXBUF) 7054 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 7055 if (sc->sc_mcastkey && bootverbose) 7056 if_printf(ifp, "using multicast key search\n"); 7057 } 7058 7059 #ifdef IEEE80211_SUPPORT_TDMA 7060 static __inline uint32_t 7061 ath_hal_getnexttbtt(struct ath_hal *ah) 7062 { 7063 #define AR_TIMER0 0x8028 7064 return OS_REG_READ(ah, AR_TIMER0); 7065 } 7066 7067 static __inline void 7068 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 7069 { 7070 /* XXX handle wrap/overflow */ 7071 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 7072 } 7073 7074 static void 7075 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 7076 { 7077 struct ath_hal *ah = sc->sc_ah; 7078 HAL_BEACON_TIMERS bt; 7079 7080 bt.bt_intval = bintval | HAL_BEACON_ENA; 7081 bt.bt_nexttbtt = nexttbtt; 7082 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 7083 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 7084 bt.bt_nextatim = nexttbtt+1; 7085 ath_hal_beaconsettimers(ah, &bt); 7086 } 7087 7088 /* 7089 * Calculate the beacon interval. This is periodic in the 7090 * superframe for the bss. We assume each station is configured 7091 * identically wrt transmit rate so the guard time we calculate 7092 * above will be the same on all stations. Note we need to 7093 * factor in the xmit time because the hardware will schedule 7094 * a frame for transmit if the start of the frame is within 7095 * the burst time. When we get hardware that properly kills 7096 * frames in the PCU we can reduce/eliminate the guard time. 7097 * 7098 * Roundup to 1024 is so we have 1 TU buffer in the guard time 7099 * to deal with the granularity of the nexttbtt timer. 11n MAC's 7100 * with 1us timer granularity should allow us to reduce/eliminate 7101 * this. 7102 */ 7103 static void 7104 ath_tdma_bintvalsetup(struct ath_softc *sc, 7105 const struct ieee80211_tdma_state *tdma) 7106 { 7107 /* copy from vap state (XXX check all vaps have same value?) */ 7108 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 7109 7110 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 7111 tdma->tdma_slotcnt, 1024); 7112 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 7113 if (sc->sc_tdmabintval & 1) 7114 sc->sc_tdmabintval++; 7115 7116 if (tdma->tdma_slot == 0) { 7117 /* 7118 * Only slot 0 beacons; other slots respond. 7119 */ 7120 sc->sc_imask |= HAL_INT_SWBA; 7121 sc->sc_tdmaswba = 0; /* beacon immediately */ 7122 } else { 7123 /* XXX all vaps must be slot 0 or slot !0 */ 7124 sc->sc_imask &= ~HAL_INT_SWBA; 7125 } 7126 } 7127 7128 /* 7129 * Max 802.11 overhead. This assumes no 4-address frames and 7130 * the encapsulation done by ieee80211_encap (llc). We also 7131 * include potential crypto overhead. 7132 */ 7133 #define IEEE80211_MAXOVERHEAD \ 7134 (sizeof(struct ieee80211_qosframe) \ 7135 + sizeof(struct llc) \ 7136 + IEEE80211_ADDR_LEN \ 7137 + IEEE80211_WEP_IVLEN \ 7138 + IEEE80211_WEP_KIDLEN \ 7139 + IEEE80211_WEP_CRCLEN \ 7140 + IEEE80211_WEP_MICLEN \ 7141 + IEEE80211_CRC_LEN) 7142 7143 /* 7144 * Setup initially for tdma operation. Start the beacon 7145 * timers and enable SWBA if we are slot 0. Otherwise 7146 * we wait for slot 0 to arrive so we can sync up before 7147 * starting to transmit. 7148 */ 7149 static void 7150 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 7151 { 7152 struct ath_hal *ah = sc->sc_ah; 7153 struct ifnet *ifp = sc->sc_ifp; 7154 struct ieee80211com *ic = ifp->if_l2com; 7155 const struct ieee80211_txparam *tp; 7156 const struct ieee80211_tdma_state *tdma = NULL; 7157 int rix; 7158 7159 if (vap == NULL) { 7160 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 7161 if (vap == NULL) { 7162 if_printf(ifp, "%s: no vaps?\n", __func__); 7163 return; 7164 } 7165 } 7166 tp = vap->iv_bss->ni_txparms; 7167 /* 7168 * Calculate the guard time for each slot. This is the 7169 * time to send a maximal-size frame according to the 7170 * fixed/lowest transmit rate. Note that the interface 7171 * mtu does not include the 802.11 overhead so we must 7172 * tack that on (ath_hal_computetxtime includes the 7173 * preamble and plcp in it's calculation). 7174 */ 7175 tdma = vap->iv_tdma; 7176 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 7177 rix = ath_tx_findrix(sc, tp->ucastrate); 7178 else 7179 rix = ath_tx_findrix(sc, tp->mcastrate); 7180 /* XXX short preamble assumed */ 7181 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 7182 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 7183 7184 ath_hal_intrset(ah, 0); 7185 7186 ath_beaconq_config(sc); /* setup h/w beacon q */ 7187 if (sc->sc_setcca) 7188 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 7189 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 7190 ath_tdma_settimers(sc, sc->sc_tdmabintval, 7191 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 7192 sc->sc_syncbeacon = 0; 7193 7194 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 7195 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 7196 7197 ath_hal_intrset(ah, sc->sc_imask); 7198 7199 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 7200 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 7201 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 7202 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 7203 sc->sc_tdmadbaprep); 7204 } 7205 7206 /* 7207 * Update tdma operation. Called from the 802.11 layer 7208 * when a beacon is received from the TDMA station operating 7209 * in the slot immediately preceding us in the bss. Use 7210 * the rx timestamp for the beacon frame to update our 7211 * beacon timers so we follow their schedule. Note that 7212 * by using the rx timestamp we implicitly include the 7213 * propagation delay in our schedule. 7214 */ 7215 static void 7216 ath_tdma_update(struct ieee80211_node *ni, 7217 const struct ieee80211_tdma_param *tdma, int changed) 7218 { 7219 #define TSF_TO_TU(_h,_l) \ 7220 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 7221 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 7222 struct ieee80211vap *vap = ni->ni_vap; 7223 struct ieee80211com *ic = ni->ni_ic; 7224 struct ath_softc *sc = ic->ic_ifp->if_softc; 7225 struct ath_hal *ah = sc->sc_ah; 7226 const HAL_RATE_TABLE *rt = sc->sc_currates; 7227 u_int64_t tsf, rstamp, nextslot; 7228 u_int32_t txtime, nextslottu, timer0; 7229 int32_t tudelta, tsfdelta; 7230 const struct ath_rx_status *rs; 7231 int rix; 7232 7233 sc->sc_stats.ast_tdma_update++; 7234 7235 /* 7236 * Check for and adopt configuration changes. 7237 */ 7238 if (changed != 0) { 7239 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 7240 7241 ath_tdma_bintvalsetup(sc, ts); 7242 if (changed & TDMA_UPDATE_SLOTLEN) 7243 ath_wme_update(ic); 7244 7245 DPRINTF(sc, ATH_DEBUG_TDMA, 7246 "%s: adopt slot %u slotcnt %u slotlen %u us " 7247 "bintval %u TU\n", __func__, 7248 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 7249 sc->sc_tdmabintval); 7250 7251 /* XXX right? */ 7252 ath_hal_intrset(ah, sc->sc_imask); 7253 /* NB: beacon timers programmed below */ 7254 } 7255 7256 /* extend rx timestamp to 64 bits */ 7257 rs = sc->sc_lastrs; 7258 tsf = ath_hal_gettsf64(ah); 7259 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf); 7260 /* 7261 * The rx timestamp is set by the hardware on completing 7262 * reception (at the point where the rx descriptor is DMA'd 7263 * to the host). To find the start of our next slot we 7264 * must adjust this time by the time required to send 7265 * the packet just received. 7266 */ 7267 rix = rt->rateCodeToIndex[rs->rs_rate]; 7268 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 7269 rt->info[rix].shortPreamble); 7270 /* NB: << 9 is to cvt to TU and /2 */ 7271 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 7272 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 7273 7274 /* 7275 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 7276 * to usecs and calculate the difference between what the 7277 * other station thinks and what we have programmed. This 7278 * lets us figure how to adjust our timers to match. The 7279 * adjustments are done by pulling the TSF forward and possibly 7280 * rewriting the beacon timers. 7281 */ 7282 timer0 = ath_hal_getnexttbtt(ah); 7283 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 7284 7285 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7286 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 7287 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 7288 7289 if (tsfdelta < 0) { 7290 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7291 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 7292 tsfdelta = -tsfdelta % 1024; 7293 nextslottu++; 7294 } else if (tsfdelta > 0) { 7295 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 7296 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7297 tsfdelta = 1024 - (tsfdelta % 1024); 7298 nextslottu++; 7299 } else { 7300 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7301 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7302 } 7303 tudelta = nextslottu - timer0; 7304 7305 /* 7306 * Copy sender's timetstamp into tdma ie so they can 7307 * calculate roundtrip time. We submit a beacon frame 7308 * below after any timer adjustment. The frame goes out 7309 * at the next TBTT so the sender can calculate the 7310 * roundtrip by inspecting the tdma ie in our beacon frame. 7311 * 7312 * NB: This tstamp is subtlely preserved when 7313 * IEEE80211_BEACON_TDMA is marked (e.g. when the 7314 * slot position changes) because ieee80211_add_tdma 7315 * skips over the data. 7316 */ 7317 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 7318 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 7319 &ni->ni_tstamp.data, 8); 7320 #if 0 7321 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7322 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 7323 (unsigned long long) tsf, (unsigned long long) nextslot, 7324 (int)(nextslot - tsf), tsfdelta, 7325 nextslottu, timer0, tudelta); 7326 #endif 7327 /* 7328 * Adjust the beacon timers only when pulling them forward 7329 * or when going back by less than the beacon interval. 7330 * Negative jumps larger than the beacon interval seem to 7331 * cause the timers to stop and generally cause instability. 7332 * This basically filters out jumps due to missed beacons. 7333 */ 7334 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 7335 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 7336 sc->sc_stats.ast_tdma_timers++; 7337 } 7338 if (tsfdelta > 0) { 7339 ath_hal_adjusttsf(ah, tsfdelta); 7340 sc->sc_stats.ast_tdma_tsf++; 7341 } 7342 ath_tdma_beacon_send(sc, vap); /* prepare response */ 7343 #undef TU_TO_TSF 7344 #undef TSF_TO_TU 7345 } 7346 7347 /* 7348 * Transmit a beacon frame at SWBA. Dynamic updates 7349 * to the frame contents are done as needed. 7350 */ 7351 static void 7352 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 7353 { 7354 struct ath_hal *ah = sc->sc_ah; 7355 struct ath_buf *bf; 7356 int otherant; 7357 7358 /* 7359 * Check if the previous beacon has gone out. If 7360 * not don't try to post another, skip this period 7361 * and wait for the next. Missed beacons indicate 7362 * a problem and should not occur. If we miss too 7363 * many consecutive beacons reset the device. 7364 */ 7365 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 7366 sc->sc_bmisscount++; 7367 DPRINTF(sc, ATH_DEBUG_BEACON, 7368 "%s: missed %u consecutive beacons\n", 7369 __func__, sc->sc_bmisscount); 7370 if (sc->sc_bmisscount >= ath_bstuck_threshold) 7371 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 7372 return; 7373 } 7374 if (sc->sc_bmisscount != 0) { 7375 DPRINTF(sc, ATH_DEBUG_BEACON, 7376 "%s: resume beacon xmit after %u misses\n", 7377 __func__, sc->sc_bmisscount); 7378 sc->sc_bmisscount = 0; 7379 } 7380 7381 /* 7382 * Check recent per-antenna transmit statistics and flip 7383 * the default antenna if noticeably more frames went out 7384 * on the non-default antenna. 7385 * XXX assumes 2 anntenae 7386 */ 7387 if (!sc->sc_diversity) { 7388 otherant = sc->sc_defant & 1 ? 2 : 1; 7389 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 7390 ath_setdefantenna(sc, otherant); 7391 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 7392 } 7393 7394 /* 7395 * Stop any current dma before messing with the beacon linkages. 7396 * 7397 * This should never fail since we check above that no frames 7398 * are still pending on the queue. 7399 */ 7400 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 7401 DPRINTF(sc, ATH_DEBUG_ANY, 7402 "%s: beacon queue %u did not stop?\n", 7403 __func__, sc->sc_bhalq); 7404 /* NB: the HAL still stops DMA, so proceed */ 7405 } 7406 bf = ath_beacon_generate(sc, vap); 7407 if (bf != NULL) { 7408 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 7409 ath_hal_txstart(ah, sc->sc_bhalq); 7410 7411 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 7412 7413 /* 7414 * Record local TSF for our last send for use 7415 * in arbitrating slot collisions. 7416 */ 7417 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 7418 } else { 7419 device_printf(sc->sc_dev, "tdma beacon gen failed!\n"); 7420 } 7421 } 7422 #endif /* IEEE80211_SUPPORT_TDMA */ 7423 7424 static int 7425 ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS) 7426 { 7427 struct ath_softc *sc = arg1; 7428 int val = 0; 7429 int error; 7430 7431 error = sysctl_handle_int(oidp, &val, 0, req); 7432 if (error || !req->newptr) 7433 return error; 7434 if (val == 0) 7435 return 0; /* Not clearing the stats is still valid */ 7436 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 7437 val = 0; 7438 return 0; 7439 } 7440 7441 static void 7442 ath_sysctl_stats_attach(struct ath_softc *sc) 7443 { 7444 struct sysctl_oid *tree; 7445 struct sysctl_ctx_list *ctx; 7446 struct sysctl_oid_list *child; 7447 7448 ctx = &sc->sc_sysctl_ctx; 7449 tree = sc->sc_sysctl_tree; 7450 child = SYSCTL_CHILDREN(tree); 7451 7452 /* Create "clear" node */ 7453 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 7454 "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 7455 ath_sysctl_clearstats, "I", "clear stats"); 7456 7457 /* Create stats node */ 7458 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 7459 NULL, "Statistics"); 7460 child = SYSCTL_CHILDREN(tree); 7461 7462 /* This was generated from if_athioctl.h */ 7463 7464 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD, 7465 &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog"); 7466 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD, 7467 &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts"); 7468 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD, 7469 &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts"); 7470 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD, 7471 &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts"); 7472 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD, 7473 &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts"); 7474 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD, 7475 &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts"); 7476 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD, 7477 &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts"); 7478 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD, 7479 &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts"); 7480 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD, 7481 &sc->sc_stats.ast_mib, 0, "mib interrupts"); 7482 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD, 7483 &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced"); 7484 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD, 7485 &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface"); 7486 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD, 7487 &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted"); 7488 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD, 7489 &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc"); 7490 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD, 7491 &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer"); 7492 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD, 7493 &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed"); 7494 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD, 7495 &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node"); 7496 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD, 7497 &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf"); 7498 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD, 7499 &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster"); 7500 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD, 7501 &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster"); 7502 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD, 7503 &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame"); 7504 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD, 7505 &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs"); 7506 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD, 7507 &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries"); 7508 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD, 7509 &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun"); 7510 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD, 7511 &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered"); 7512 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD, 7513 &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)"); 7514 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD, 7515 &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)"); 7516 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD, 7517 &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate"); 7518 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD, 7519 &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked"); 7520 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD, 7521 &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled"); 7522 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD, 7523 &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled"); 7524 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD, 7525 &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble"); 7526 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD, 7527 &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate"); 7528 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD, 7529 &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection"); 7530 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD, 7531 &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting"); 7532 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD, 7533 &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension"); 7534 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD, 7535 &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf"); 7536 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD, 7537 &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs"); 7538 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD, 7539 &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun"); 7540 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD, 7541 &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC"); 7542 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD, 7543 &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun"); 7544 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD, 7545 &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption"); 7546 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD, 7547 &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure"); 7548 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD, 7549 &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err"); 7550 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD, 7551 &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short"); 7552 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD, 7553 &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large"); 7554 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD, 7555 &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface"); 7556 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD, 7557 &sc->sc_stats.ast_rx_mgt, 0, "management frames received"); 7558 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD, 7559 &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame"); 7560 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD, 7561 &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted"); 7562 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD, 7563 &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf"); 7564 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD, 7565 &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls"); 7566 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD, 7567 &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed"); 7568 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD, 7569 &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset"); 7570 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD, 7571 &sc->sc_stats.ast_rate_calls, 0, "rate control checks"); 7572 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD, 7573 &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate"); 7574 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD, 7575 &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate"); 7576 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD, 7577 &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches"); 7578 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD, 7579 &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches"); 7580 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD, 7581 &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted"); 7582 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD, 7583 &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy"); 7584 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD, 7585 &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api"); 7586 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD, 7587 &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully"); 7588 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD, 7589 &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error"); 7590 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD, 7591 &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd"); 7592 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD, 7593 &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q"); 7594 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD, 7595 &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit"); 7596 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD, 7597 &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer"); 7598 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD, 7599 &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates"); 7600 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD, 7601 &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers"); 7602 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD, 7603 &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF"); 7604 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD, 7605 &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required"); 7606 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD, 7607 &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down"); 7608 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD, 7609 &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer"); 7610 #if 0 7611 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD, 7612 &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons"); 7613 #endif 7614 } 7615