1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_ath.c 203751 2010-02-10 11:12:39Z rpaulo $"); 30 */ 31 32 /* 33 * Driver for the Atheros Wireless LAN controller. 34 * 35 * This software is derived from work of Atsushi Onoe; his contribution 36 * is greatly appreciated. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ath.h" 41 #include "opt_wlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sysctl.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/errno.h> 54 #include <sys/callout.h> 55 #include <sys/bus.h> 56 #include <sys/endian.h> 57 #include <sys/kthread.h> 58 #include <sys/taskqueue.h> 59 #include <sys/priv.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_arp.h> 66 #include <net/if_llc.h> 67 #include <net/ifq_var.h> 68 69 #include <netproto/802_11/ieee80211_var.h> 70 #include <netproto/802_11/ieee80211_regdomain.h> 71 #ifdef IEEE80211_SUPPORT_SUPERG 72 #include <netproto/802_11/ieee80211_superg.h> 73 #endif 74 #ifdef IEEE80211_SUPPORT_TDMA 75 #include <netproto/802_11/ieee80211_tdma.h> 76 #endif 77 78 #include <net/bpf.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/if_ether.h> 83 #endif 84 85 #include <dev/netif/ath/ath/if_athvar.h> 86 #include <dev/netif/ath/hal/ath_hal/ah_devid.h> /* XXX for softled */ 87 88 #ifdef ATH_TX99_DIAG 89 #include <dev/netif/ath_tx99/ath_tx99.h> 90 #endif 91 92 /* 93 * ATH_BCBUF determines the number of vap's that can transmit 94 * beacons and also (currently) the number of vap's that can 95 * have unique mac addresses/bssid. When staggering beacons 96 * 4 is probably a good max as otherwise the beacons become 97 * very closely spaced and there is limited time for cab q traffic 98 * to go out. You can burst beacons instead but that is not good 99 * for stations in power save and at some point you really want 100 * another radio (and channel). 101 * 102 * The limit on the number of mac addresses is tied to our use of 103 * the U/L bit and tracking addresses in a byte; it would be 104 * worthwhile to allow more for applications like proxy sta. 105 */ 106 CTASSERT(ATH_BCBUF <= 8); 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 118 const char name[IFNAMSIZ], int unit, int opmode, 119 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 120 const uint8_t mac[IEEE80211_ADDR_LEN]); 121 static void ath_vap_delete(struct ieee80211vap *); 122 static void ath_init(void *); 123 static void ath_stop_locked(struct ifnet *); 124 static void ath_stop(struct ifnet *); 125 static void ath_start(struct ifnet *); 126 static int ath_reset(struct ifnet *); 127 static int ath_reset_vap(struct ieee80211vap *, u_long); 128 static int ath_media_change(struct ifnet *); 129 static void ath_watchdog_callout(void *); 130 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 131 static void ath_fatal_proc(void *, int); 132 static void ath_bmiss_vap(struct ieee80211vap *); 133 static void ath_bmiss_task(void *, int); 134 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 135 struct ieee80211_node *); 136 static int ath_key_alloc(struct ieee80211vap *, 137 struct ieee80211_key *, 138 ieee80211_keyix *, ieee80211_keyix *); 139 static int ath_key_delete(struct ieee80211vap *, 140 const struct ieee80211_key *); 141 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 142 const u_int8_t mac[IEEE80211_ADDR_LEN]); 143 static void ath_key_update_begin(struct ieee80211vap *); 144 static void ath_key_update_end(struct ieee80211vap *); 145 static void ath_update_mcast(struct ifnet *); 146 static void ath_update_promisc(struct ifnet *); 147 static void ath_mode_init(struct ath_softc *); 148 static void ath_setslottime(struct ath_softc *); 149 static void ath_updateslot(struct ifnet *); 150 static int ath_beaconq_setup(struct ath_hal *); 151 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 152 static void ath_beacon_update(struct ieee80211vap *, int item); 153 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 154 static void ath_beacon_proc(void *, int); 155 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 156 struct ieee80211vap *); 157 static void ath_bstuck_task(void *, int); 158 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 159 static void ath_beacon_free(struct ath_softc *); 160 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 161 static void ath_descdma_cleanup(struct ath_softc *sc, 162 struct ath_descdma *, ath_bufhead *); 163 static int ath_desc_alloc(struct ath_softc *); 164 static void ath_desc_free(struct ath_softc *); 165 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 166 const uint8_t [IEEE80211_ADDR_LEN]); 167 static void ath_node_free(struct ieee80211_node *); 168 static void ath_node_getsignal(const struct ieee80211_node *, 169 int8_t *, int8_t *); 170 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 171 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 172 int subtype, int rssi, int nf); 173 static void ath_setdefantenna(struct ath_softc *, u_int); 174 static void ath_rx_task(void *, int); 175 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 176 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 177 static int ath_tx_setup(struct ath_softc *, int, int); 178 static int ath_wme_update(struct ieee80211com *); 179 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 180 static void ath_tx_cleanup(struct ath_softc *); 181 static void ath_freetx(struct mbuf *); 182 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 183 struct ath_buf *, struct mbuf *); 184 static void ath_tx_task_q0(void *, int); 185 static void ath_tx_task_q0123(void *, int); 186 static void ath_tx_task(void *, int); 187 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 188 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 189 static void ath_draintxq(struct ath_softc *); 190 static void ath_stoprecv(struct ath_softc *); 191 static int ath_startrecv(struct ath_softc *); 192 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 193 static void ath_scan_start(struct ieee80211com *); 194 static void ath_scan_end(struct ieee80211com *); 195 static void ath_set_channel(struct ieee80211com *); 196 static void ath_calibrate_callout(void *); 197 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 198 static void ath_setup_stationkey(struct ieee80211_node *); 199 static void ath_newassoc(struct ieee80211_node *, int); 200 static int ath_setregdomain(struct ieee80211com *, 201 struct ieee80211_regdomain *, int, 202 struct ieee80211_channel []); 203 static void ath_getradiocaps(struct ieee80211com *, int, int *, 204 struct ieee80211_channel []); 205 static int ath_getchannels(struct ath_softc *); 206 static void ath_led_event(struct ath_softc *, int); 207 208 static int ath_rate_setup(struct ath_softc *, u_int mode); 209 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 210 211 static void ath_sysctlattach(struct ath_softc *); 212 static int ath_raw_xmit(struct ieee80211_node *, 213 struct mbuf *, const struct ieee80211_bpf_params *); 214 static void ath_announce(struct ath_softc *); 215 static void ath_sysctl_stats_attach(struct ath_softc *sc); 216 217 #ifdef IEEE80211_SUPPORT_TDMA 218 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 219 u_int32_t bintval); 220 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 221 const struct ieee80211_tdma_state *tdma); 222 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 223 static void ath_tdma_update(struct ieee80211_node *ni, 224 const struct ieee80211_tdma_param *tdma, int); 225 static void ath_tdma_beacon_send(struct ath_softc *sc, 226 struct ieee80211vap *vap); 227 228 static __inline void 229 ath_hal_setcca(struct ath_hal *ah, int ena) 230 { 231 /* 232 * NB: fill me in; this is not provided by default because disabling 233 * CCA in most locales violates regulatory. 234 */ 235 } 236 237 static __inline int 238 ath_hal_getcca(struct ath_hal *ah) 239 { 240 u_int32_t diag; 241 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 242 return 1; 243 return ((diag & 0x500000) == 0); 244 } 245 246 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 247 #define TDMA_LPF_LEN 6 248 #define TDMA_DUMMY_MARKER 0x127 249 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 250 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 251 #define TDMA_LPF(x, y, len) \ 252 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 253 #define TDMA_SAMPLE(x, y) do { \ 254 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 255 } while (0) 256 #define TDMA_EP_RND(x,mul) \ 257 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 258 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 259 #endif /* IEEE80211_SUPPORT_TDMA */ 260 261 SYSCTL_DECL(_hw_ath); 262 263 /* XXX validate sysctl values */ 264 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 265 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 266 0, "long chip calibration interval (secs)"); 267 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 268 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 269 0, "short chip calibration interval (msecs)"); 270 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 271 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 272 0, "reset chip calibration results (secs)"); 273 274 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 275 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 276 0, "rx buffers allocated"); 277 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 278 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 279 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 280 0, "tx buffers allocated"); 281 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 282 283 static int ath_bstuck_threshold = 4; /* max missed beacons */ 284 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 285 0, "max missed beacon xmits before chip reset"); 286 287 #ifdef ATH_DEBUG 288 enum { 289 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 290 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 291 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 292 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 293 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 294 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 295 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 296 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 297 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 298 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 299 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 300 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 301 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 302 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 303 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 304 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 305 ATH_DEBUG_NODE = 0x00080000, /* node management */ 306 ATH_DEBUG_LED = 0x00100000, /* led management */ 307 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 308 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 309 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */ 310 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */ 311 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 312 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 313 ATH_DEBUG_ANY = 0xffffffff 314 }; 315 static int ath_debug = 0; 316 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 317 0, "control debugging printfs"); 318 TUNABLE_INT("hw.ath.debug", &ath_debug); 319 320 #define IFF_DUMPPKTS(sc, m) \ 321 ((sc->sc_debug & (m)) || \ 322 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 323 #define DPRINTF(sc, m, fmt, ...) do { \ 324 if (sc->sc_debug & (m)) \ 325 kprintf(fmt, __VA_ARGS__); \ 326 } while (0) 327 #define KEYPRINTF(sc, ix, hk, mac) do { \ 328 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 329 ath_keyprint(sc, __func__, ix, hk, mac); \ 330 } while (0) 331 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 332 u_int ix, int); 333 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 334 u_int qnum, u_int ix, int done); 335 #else 336 #define IFF_DUMPPKTS(sc, m) \ 337 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 338 #define DPRINTF(sc, m, fmt, ...) do { \ 339 (void) sc; \ 340 } while (0) 341 #define KEYPRINTF(sc, k, ix, mac) do { \ 342 (void) sc; \ 343 } while (0) 344 #endif 345 346 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 347 348 int 349 ath_attach(u_int16_t devid, struct ath_softc *sc) 350 { 351 struct ifnet *ifp; 352 struct ieee80211com *ic; 353 struct ath_hal *ah = NULL; 354 HAL_STATUS status; 355 int error = 0, i; 356 u_int wmodes; 357 uint8_t macaddr[IEEE80211_ADDR_LEN]; 358 359 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 360 361 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 362 if (ifp == NULL) { 363 device_printf(sc->sc_dev, "can not if_alloc()\n"); 364 error = ENOSPC; 365 goto bad; 366 } 367 ic = ifp->if_l2com; 368 369 /* set these up early for if_printf use */ 370 if_initname(ifp, device_get_name(sc->sc_dev), 371 device_get_unit(sc->sc_dev)); 372 373 /* prepare sysctl tree for use in sub modules */ 374 sysctl_ctx_init(&sc->sc_sysctl_ctx); 375 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 376 SYSCTL_STATIC_CHILDREN(_hw), 377 OID_AUTO, 378 device_get_nameunit(sc->sc_dev), 379 CTLFLAG_RD, 0, ""); 380 381 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 382 if (ah == NULL) { 383 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 384 status); 385 error = ENXIO; 386 goto bad; 387 } 388 sc->sc_ah = ah; 389 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 390 #ifdef ATH_DEBUG 391 sc->sc_debug = ath_debug; 392 #endif 393 394 /* 395 * Check if the MAC has multi-rate retry support. 396 * We do this by trying to setup a fake extended 397 * descriptor. MAC's that don't have support will 398 * return false w/o doing anything. MAC's that do 399 * support it will return true w/o doing anything. 400 */ 401 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 402 403 /* 404 * Check if the device has hardware counters for PHY 405 * errors. If so we need to enable the MIB interrupt 406 * so we can act on stat triggers. 407 */ 408 if (ath_hal_hwphycounters(ah)) 409 sc->sc_needmib = 1; 410 411 /* 412 * Get the hardware key cache size. 413 */ 414 sc->sc_keymax = ath_hal_keycachesize(ah); 415 if (sc->sc_keymax > ATH_KEYMAX) { 416 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 417 ATH_KEYMAX, sc->sc_keymax); 418 sc->sc_keymax = ATH_KEYMAX; 419 } 420 /* 421 * Reset the key cache since some parts do not 422 * reset the contents on initial power up. 423 */ 424 for (i = 0; i < sc->sc_keymax; i++) 425 ath_hal_keyreset(ah, i); 426 427 /* 428 * Collect the default channel list. 429 */ 430 error = ath_getchannels(sc); 431 if (error != 0) 432 goto bad; 433 434 /* 435 * Setup rate tables for all potential media types. 436 */ 437 ath_rate_setup(sc, IEEE80211_MODE_11A); 438 ath_rate_setup(sc, IEEE80211_MODE_11B); 439 ath_rate_setup(sc, IEEE80211_MODE_11G); 440 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 441 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 442 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 443 ath_rate_setup(sc, IEEE80211_MODE_11NA); 444 ath_rate_setup(sc, IEEE80211_MODE_11NG); 445 ath_rate_setup(sc, IEEE80211_MODE_HALF); 446 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 447 448 /* NB: setup here so ath_rate_update is happy */ 449 ath_setcurmode(sc, IEEE80211_MODE_11A); 450 451 /* 452 * Allocate tx+rx descriptors and populate the lists. 453 */ 454 wlan_assert_serialized(); 455 wlan_serialize_exit(); 456 error = ath_desc_alloc(sc); 457 wlan_serialize_enter(); 458 if (error != 0) { 459 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 460 goto bad; 461 } 462 callout_init(&sc->sc_cal_ch); 463 callout_init(&sc->sc_wd_ch); 464 465 sc->sc_tq = taskqueue_create("ath_taskq", M_INTWAIT, 466 taskqueue_thread_enqueue, &sc->sc_tq); 467 taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1, 468 "%s taskq", ifp->if_xname); 469 470 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_task, sc); 471 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_task, sc); 472 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_task, sc); 473 474 /* 475 * Allocate hardware transmit queues: one queue for 476 * beacon frames and one data queue for each QoS 477 * priority. Note that the hal handles reseting 478 * these queues at the needed time. 479 * 480 * XXX PS-Poll 481 */ 482 sc->sc_bhalq = ath_beaconq_setup(ah); 483 if (sc->sc_bhalq == (u_int) -1) { 484 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 485 error = EIO; 486 goto bad2; 487 } 488 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 489 if (sc->sc_cabq == NULL) { 490 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 491 error = EIO; 492 goto bad2; 493 } 494 /* NB: insure BK queue is the lowest priority h/w queue */ 495 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 496 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 497 ieee80211_wme_acnames[WME_AC_BK]); 498 error = EIO; 499 goto bad2; 500 } 501 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 502 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 503 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 504 /* 505 * Not enough hardware tx queues to properly do WME; 506 * just punt and assign them all to the same h/w queue. 507 * We could do a better job of this if, for example, 508 * we allocate queues when we switch from station to 509 * AP mode. 510 */ 511 if (sc->sc_ac2q[WME_AC_VI] != NULL) 512 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 513 if (sc->sc_ac2q[WME_AC_BE] != NULL) 514 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 515 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 516 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 517 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 518 } 519 520 /* 521 * Special case certain configurations. Note the 522 * CAB queue is handled by these specially so don't 523 * include them when checking the txq setup mask. 524 */ 525 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 526 case 0x01: 527 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0, sc); 528 break; 529 case 0x0f: 530 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0123, sc); 531 break; 532 default: 533 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task, sc); 534 break; 535 } 536 537 /* 538 * Setup rate control. Some rate control modules 539 * call back to change the anntena state so expose 540 * the necessary entry points. 541 * XXX maybe belongs in struct ath_ratectrl? 542 */ 543 sc->sc_setdefantenna = ath_setdefantenna; 544 sc->sc_rc = ath_rate_attach(sc); 545 if (sc->sc_rc == NULL) { 546 error = EIO; 547 goto bad2; 548 } 549 550 sc->sc_blinking = 0; 551 sc->sc_ledstate = 1; 552 sc->sc_ledon = 0; /* low true */ 553 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 554 callout_init_mp(&sc->sc_ledtimer); 555 /* 556 * Auto-enable soft led processing for IBM cards and for 557 * 5211 minipci cards. Users can also manually enable/disable 558 * support with a sysctl. 559 */ 560 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 561 if (sc->sc_softled) { 562 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 563 HAL_GPIO_MUX_MAC_NETWORK_LED); 564 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 565 } 566 567 ifp->if_softc = sc; 568 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 569 ifp->if_start = ath_start; 570 ifp->if_ioctl = ath_ioctl; 571 ifp->if_init = ath_init; 572 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 573 ifq_set_ready(&ifp->if_snd); 574 575 ic->ic_ifp = ifp; 576 /* XXX not right but it's not used anywhere important */ 577 ic->ic_phytype = IEEE80211_T_OFDM; 578 ic->ic_opmode = IEEE80211_M_STA; 579 ic->ic_caps = 580 IEEE80211_C_STA /* station mode */ 581 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 582 | IEEE80211_C_HOSTAP /* hostap mode */ 583 | IEEE80211_C_MONITOR /* monitor mode */ 584 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 585 | IEEE80211_C_WDS /* 4-address traffic works */ 586 | IEEE80211_C_MBSS /* mesh point link mode */ 587 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 588 | IEEE80211_C_SHSLOT /* short slot time supported */ 589 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 590 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 591 | IEEE80211_C_TXFRAG /* handle tx frags */ 592 ; 593 /* 594 * Query the hal to figure out h/w crypto support. 595 */ 596 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 597 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 598 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 599 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 600 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 601 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 602 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 603 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 604 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 605 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 606 /* 607 * Check if h/w does the MIC and/or whether the 608 * separate key cache entries are required to 609 * handle both tx+rx MIC keys. 610 */ 611 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 612 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 613 /* 614 * If the h/w supports storing tx+rx MIC keys 615 * in one cache slot automatically enable use. 616 */ 617 if (ath_hal_hastkipsplit(ah) || 618 !ath_hal_settkipsplit(ah, AH_FALSE)) 619 sc->sc_splitmic = 1; 620 /* 621 * If the h/w can do TKIP MIC together with WME then 622 * we use it; otherwise we force the MIC to be done 623 * in software by the net80211 layer. 624 */ 625 if (ath_hal_haswmetkipmic(ah)) 626 sc->sc_wmetkipmic = 1; 627 } 628 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 629 /* 630 * Check for multicast key search support. 631 */ 632 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 633 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 634 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 635 } 636 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 637 /* 638 * Mark key cache slots associated with global keys 639 * as in use. If we knew TKIP was not to be used we 640 * could leave the +32, +64, and +32+64 slots free. 641 */ 642 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 643 setbit(sc->sc_keymap, i); 644 setbit(sc->sc_keymap, i+64); 645 if (sc->sc_splitmic) { 646 setbit(sc->sc_keymap, i+32); 647 setbit(sc->sc_keymap, i+32+64); 648 } 649 } 650 /* 651 * TPC support can be done either with a global cap or 652 * per-packet support. The latter is not available on 653 * all parts. We're a bit pedantic here as all parts 654 * support a global cap. 655 */ 656 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 657 ic->ic_caps |= IEEE80211_C_TXPMGT; 658 659 /* 660 * Mark WME capability only if we have sufficient 661 * hardware queues to do proper priority scheduling. 662 */ 663 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 664 ic->ic_caps |= IEEE80211_C_WME; 665 /* 666 * Check for misc other capabilities. 667 */ 668 if (ath_hal_hasbursting(ah)) 669 ic->ic_caps |= IEEE80211_C_BURST; 670 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 671 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 672 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 673 if (ath_hal_hasfastframes(ah)) 674 ic->ic_caps |= IEEE80211_C_FF; 675 wmodes = ath_hal_getwirelessmodes(ah); 676 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 677 ic->ic_caps |= IEEE80211_C_TURBOP; 678 #ifdef IEEE80211_SUPPORT_TDMA 679 if (ath_hal_macversion(ah) > 0x78) { 680 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 681 ic->ic_tdma_update = ath_tdma_update; 682 } 683 #endif 684 /* 685 * Indicate we need the 802.11 header padded to a 686 * 32-bit boundary for 4-address and QoS frames. 687 */ 688 ic->ic_flags |= IEEE80211_F_DATAPAD; 689 690 /* 691 * Query the hal about antenna support. 692 */ 693 sc->sc_defant = ath_hal_getdefantenna(ah); 694 695 /* 696 * Not all chips have the VEOL support we want to 697 * use with IBSS beacons; check here for it. 698 */ 699 sc->sc_hasveol = ath_hal_hasveol(ah); 700 701 /* get mac address from hardware */ 702 ath_hal_getmac(ah, macaddr); 703 if (sc->sc_hasbmask) 704 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 705 706 /* NB: used to size node table key mapping array */ 707 ic->ic_max_keyix = sc->sc_keymax; 708 /* call MI attach routine. */ 709 ieee80211_ifattach(ic, macaddr); 710 ic->ic_setregdomain = ath_setregdomain; 711 ic->ic_getradiocaps = ath_getradiocaps; 712 sc->sc_opmode = HAL_M_STA; 713 714 /* override default methods */ 715 ic->ic_newassoc = ath_newassoc; 716 ic->ic_updateslot = ath_updateslot; 717 ic->ic_wme.wme_update = ath_wme_update; 718 ic->ic_vap_create = ath_vap_create; 719 ic->ic_vap_delete = ath_vap_delete; 720 ic->ic_raw_xmit = ath_raw_xmit; 721 ic->ic_update_mcast = ath_update_mcast; 722 ic->ic_update_promisc = ath_update_promisc; 723 ic->ic_node_alloc = ath_node_alloc; 724 sc->sc_node_free = ic->ic_node_free; 725 ic->ic_node_free = ath_node_free; 726 ic->ic_node_getsignal = ath_node_getsignal; 727 ic->ic_scan_start = ath_scan_start; 728 ic->ic_scan_end = ath_scan_end; 729 ic->ic_set_channel = ath_set_channel; 730 731 ieee80211_radiotap_attach(ic, 732 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 733 ATH_TX_RADIOTAP_PRESENT, 734 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 735 ATH_RX_RADIOTAP_PRESENT); 736 737 /* 738 * Setup dynamic sysctl's now that country code and 739 * regdomain are available from the hal. 740 */ 741 ath_sysctlattach(sc); 742 ath_sysctl_stats_attach(sc); 743 744 if (bootverbose) 745 ieee80211_announce(ic); 746 ath_announce(sc); 747 return 0; 748 bad2: 749 ath_tx_cleanup(sc); 750 ath_desc_free(sc); 751 bad: 752 if (ah) 753 ath_hal_detach(ah); 754 if (ifp != NULL) 755 if_free(ifp); 756 sc->sc_invalid = 1; 757 return error; 758 } 759 760 int 761 ath_detach(struct ath_softc *sc) 762 { 763 struct ifnet *ifp = sc->sc_ifp; 764 765 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 766 __func__, ifp->if_flags); 767 768 /* 769 * NB: the order of these is important: 770 * o stop the chip so no more interrupts will fire 771 * o call the 802.11 layer before detaching the hal to 772 * insure callbacks into the driver to delete global 773 * key cache entries can be handled 774 * o free the taskqueue which drains any pending tasks 775 * o reclaim the tx queue data structures after calling 776 * the 802.11 layer as we'll get called back to reclaim 777 * node state and potentially want to use them 778 * o to cleanup the tx queues the hal is called, so detach 779 * it last 780 * Other than that, it's straightforward... 781 */ 782 ath_stop(ifp); 783 ieee80211_ifdetach(ifp->if_l2com); 784 taskqueue_free(sc->sc_tq); 785 #ifdef ATH_TX99_DIAG 786 if (sc->sc_tx99 != NULL) 787 sc->sc_tx99->detach(sc->sc_tx99); 788 #endif 789 ath_rate_detach(sc->sc_rc); 790 ath_desc_free(sc); 791 ath_tx_cleanup(sc); 792 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 793 if (sc->sc_sysctl_tree) { 794 sysctl_ctx_free(&sc->sc_sysctl_ctx); 795 sc->sc_sysctl_tree = NULL; 796 } 797 if_free(ifp); 798 799 return 0; 800 } 801 802 /* 803 * MAC address handling for multiple BSS on the same radio. 804 * The first vap uses the MAC address from the EEPROM. For 805 * subsequent vap's we set the U/L bit (bit 1) in the MAC 806 * address and use the next six bits as an index. 807 */ 808 static void 809 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 810 { 811 int i; 812 813 if (clone && sc->sc_hasbmask) { 814 /* NB: we only do this if h/w supports multiple bssid */ 815 for (i = 0; i < 8; i++) 816 if ((sc->sc_bssidmask & (1<<i)) == 0) 817 break; 818 if (i != 0) 819 mac[0] |= (i << 2)|0x2; 820 } else 821 i = 0; 822 sc->sc_bssidmask |= 1<<i; 823 sc->sc_hwbssidmask[0] &= ~mac[0]; 824 if (i == 0) 825 sc->sc_nbssid0++; 826 } 827 828 static void 829 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 830 { 831 int i = mac[0] >> 2; 832 uint8_t mask; 833 834 if (i != 0 || --sc->sc_nbssid0 == 0) { 835 sc->sc_bssidmask &= ~(1<<i); 836 /* recalculate bssid mask from remaining addresses */ 837 mask = 0xff; 838 for (i = 1; i < 8; i++) 839 if (sc->sc_bssidmask & (1<<i)) 840 mask &= ~((i<<2)|0x2); 841 sc->sc_hwbssidmask[0] |= mask; 842 } 843 } 844 845 /* 846 * Assign a beacon xmit slot. We try to space out 847 * assignments so when beacons are staggered the 848 * traffic coming out of the cab q has maximal time 849 * to go out before the next beacon is scheduled. 850 */ 851 static int 852 assign_bslot(struct ath_softc *sc) 853 { 854 u_int slot, free; 855 856 free = 0; 857 for (slot = 0; slot < ATH_BCBUF; slot++) 858 if (sc->sc_bslot[slot] == NULL) { 859 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 860 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 861 return slot; 862 free = slot; 863 /* NB: keep looking for a double slot */ 864 } 865 return free; 866 } 867 868 static struct ieee80211vap * 869 ath_vap_create(struct ieee80211com *ic, 870 const char name[IFNAMSIZ], int unit, int opmode, int flags, 871 const uint8_t bssid[IEEE80211_ADDR_LEN], 872 const uint8_t mac0[IEEE80211_ADDR_LEN]) 873 { 874 struct ath_softc *sc = ic->ic_ifp->if_softc; 875 struct ath_vap *avp; 876 struct ieee80211vap *vap; 877 uint8_t mac[IEEE80211_ADDR_LEN]; 878 int ic_opmode, needbeacon, error; 879 880 avp = (struct ath_vap *) kmalloc(sizeof(struct ath_vap), 881 M_80211_VAP, M_WAITOK | M_ZERO); 882 needbeacon = 0; 883 IEEE80211_ADDR_COPY(mac, mac0); 884 885 ic_opmode = opmode; /* default to opmode of new vap */ 886 switch (opmode) { 887 case IEEE80211_M_STA: 888 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 889 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 890 goto bad; 891 } 892 if (sc->sc_nvaps) { 893 /* 894 * With multiple vaps we must fall back 895 * to s/w beacon miss handling. 896 */ 897 flags |= IEEE80211_CLONE_NOBEACONS; 898 } 899 if (flags & IEEE80211_CLONE_NOBEACONS) { 900 /* 901 * Station mode w/o beacons are implemented w/ AP mode. 902 */ 903 ic_opmode = IEEE80211_M_HOSTAP; 904 } 905 break; 906 case IEEE80211_M_IBSS: 907 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 908 device_printf(sc->sc_dev, 909 "only 1 ibss vap supported\n"); 910 goto bad; 911 } 912 needbeacon = 1; 913 break; 914 case IEEE80211_M_AHDEMO: 915 #ifdef IEEE80211_SUPPORT_TDMA 916 if (flags & IEEE80211_CLONE_TDMA) { 917 if (sc->sc_nvaps != 0) { 918 device_printf(sc->sc_dev, 919 "only 1 tdma vap supported\n"); 920 goto bad; 921 } 922 needbeacon = 1; 923 flags |= IEEE80211_CLONE_NOBEACONS; 924 } 925 /* fall thru... */ 926 #endif 927 case IEEE80211_M_MONITOR: 928 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 929 /* 930 * Adopt existing mode. Adding a monitor or ahdemo 931 * vap to an existing configuration is of dubious 932 * value but should be ok. 933 */ 934 /* XXX not right for monitor mode */ 935 ic_opmode = ic->ic_opmode; 936 } 937 break; 938 case IEEE80211_M_HOSTAP: 939 case IEEE80211_M_MBSS: 940 needbeacon = 1; 941 break; 942 case IEEE80211_M_WDS: 943 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 944 device_printf(sc->sc_dev, 945 "wds not supported in sta mode\n"); 946 goto bad; 947 } 948 /* 949 * Silently remove any request for a unique 950 * bssid; WDS vap's always share the local 951 * mac address. 952 */ 953 flags &= ~IEEE80211_CLONE_BSSID; 954 if (sc->sc_nvaps == 0) 955 ic_opmode = IEEE80211_M_HOSTAP; 956 else 957 ic_opmode = ic->ic_opmode; 958 break; 959 default: 960 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 961 goto bad; 962 } 963 /* 964 * Check that a beacon buffer is available; the code below assumes it. 965 */ 966 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 967 device_printf(sc->sc_dev, "no beacon buffer available\n"); 968 goto bad; 969 } 970 971 /* STA, AHDEMO? */ 972 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 973 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 974 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 975 } 976 977 vap = &avp->av_vap; 978 /* XXX can't hold mutex across if_alloc */ 979 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 980 bssid, mac); 981 if (error != 0) { 982 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 983 __func__, error); 984 goto bad2; 985 } 986 987 /* h/w crypto support */ 988 vap->iv_key_alloc = ath_key_alloc; 989 vap->iv_key_delete = ath_key_delete; 990 vap->iv_key_set = ath_key_set; 991 vap->iv_key_update_begin = ath_key_update_begin; 992 vap->iv_key_update_end = ath_key_update_end; 993 994 /* override various methods */ 995 avp->av_recv_mgmt = vap->iv_recv_mgmt; 996 vap->iv_recv_mgmt = ath_recv_mgmt; 997 vap->iv_reset = ath_reset_vap; 998 vap->iv_update_beacon = ath_beacon_update; 999 avp->av_newstate = vap->iv_newstate; 1000 vap->iv_newstate = ath_newstate; 1001 avp->av_bmiss = vap->iv_bmiss; 1002 vap->iv_bmiss = ath_bmiss_vap; 1003 1004 avp->av_bslot = -1; 1005 if (needbeacon) { 1006 /* 1007 * Allocate beacon state and setup the q for buffered 1008 * multicast frames. We know a beacon buffer is 1009 * available because we checked above. 1010 */ 1011 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 1012 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 1013 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1014 /* 1015 * Assign the vap to a beacon xmit slot. As above 1016 * this cannot fail to find a free one. 1017 */ 1018 avp->av_bslot = assign_bslot(sc); 1019 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1020 ("beacon slot %u not empty", avp->av_bslot)); 1021 sc->sc_bslot[avp->av_bslot] = vap; 1022 sc->sc_nbcnvaps++; 1023 } 1024 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1025 /* 1026 * Multple vaps are to transmit beacons and we 1027 * have h/w support for TSF adjusting; enable 1028 * use of staggered beacons. 1029 */ 1030 sc->sc_stagbeacons = 1; 1031 } 1032 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1033 } 1034 1035 ic->ic_opmode = ic_opmode; 1036 if (opmode != IEEE80211_M_WDS) { 1037 sc->sc_nvaps++; 1038 if (opmode == IEEE80211_M_STA) 1039 sc->sc_nstavaps++; 1040 if (opmode == IEEE80211_M_MBSS) 1041 sc->sc_nmeshvaps++; 1042 } 1043 switch (ic_opmode) { 1044 case IEEE80211_M_IBSS: 1045 sc->sc_opmode = HAL_M_IBSS; 1046 break; 1047 case IEEE80211_M_STA: 1048 sc->sc_opmode = HAL_M_STA; 1049 break; 1050 case IEEE80211_M_AHDEMO: 1051 #ifdef IEEE80211_SUPPORT_TDMA 1052 if (vap->iv_caps & IEEE80211_C_TDMA) { 1053 sc->sc_tdma = 1; 1054 /* NB: disable tsf adjust */ 1055 sc->sc_stagbeacons = 0; 1056 } 1057 /* 1058 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1059 * just ap mode. 1060 */ 1061 /* fall thru... */ 1062 #endif 1063 case IEEE80211_M_HOSTAP: 1064 case IEEE80211_M_MBSS: 1065 sc->sc_opmode = HAL_M_HOSTAP; 1066 break; 1067 case IEEE80211_M_MONITOR: 1068 sc->sc_opmode = HAL_M_MONITOR; 1069 break; 1070 default: 1071 /* XXX should not happen */ 1072 break; 1073 } 1074 if (sc->sc_hastsfadd) { 1075 /* 1076 * Configure whether or not TSF adjust should be done. 1077 */ 1078 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1079 } 1080 if (flags & IEEE80211_CLONE_NOBEACONS) { 1081 /* 1082 * Enable s/w beacon miss handling. 1083 */ 1084 sc->sc_swbmiss = 1; 1085 } 1086 1087 /* complete setup */ 1088 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1089 return vap; 1090 bad2: 1091 reclaim_address(sc, mac); 1092 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1093 bad: 1094 kfree(avp, M_80211_VAP); 1095 return NULL; 1096 } 1097 1098 static void 1099 ath_vap_delete(struct ieee80211vap *vap) 1100 { 1101 struct ieee80211com *ic = vap->iv_ic; 1102 struct ifnet *ifp = ic->ic_ifp; 1103 struct ath_softc *sc = ifp->if_softc; 1104 struct ath_hal *ah = sc->sc_ah; 1105 struct ath_vap *avp = ATH_VAP(vap); 1106 1107 if (ifp->if_flags & IFF_RUNNING) { 1108 /* 1109 * Quiesce the hardware while we remove the vap. In 1110 * particular we need to reclaim all references to 1111 * the vap state by any frames pending on the tx queues. 1112 */ 1113 ath_hal_intrset(ah, 0); /* disable interrupts */ 1114 ath_draintxq(sc); /* stop xmit side */ 1115 ath_stoprecv(sc); /* stop recv side */ 1116 } 1117 1118 ieee80211_vap_detach(vap); 1119 /* 1120 * Reclaim beacon state. Note this must be done before 1121 * the vap instance is reclaimed as we may have a reference 1122 * to it in the buffer for the beacon frame. 1123 */ 1124 if (avp->av_bcbuf != NULL) { 1125 if (avp->av_bslot != -1) { 1126 sc->sc_bslot[avp->av_bslot] = NULL; 1127 sc->sc_nbcnvaps--; 1128 } 1129 ath_beacon_return(sc, avp->av_bcbuf); 1130 avp->av_bcbuf = NULL; 1131 if (sc->sc_nbcnvaps == 0) { 1132 sc->sc_stagbeacons = 0; 1133 if (sc->sc_hastsfadd) 1134 ath_hal_settsfadjust(sc->sc_ah, 0); 1135 } 1136 /* 1137 * Reclaim any pending mcast frames for the vap. 1138 */ 1139 ath_tx_draintxq(sc, &avp->av_mcastq); 1140 } 1141 /* 1142 * Update bookkeeping. 1143 */ 1144 if (vap->iv_opmode == IEEE80211_M_STA) { 1145 sc->sc_nstavaps--; 1146 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1147 sc->sc_swbmiss = 0; 1148 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1149 vap->iv_opmode == IEEE80211_M_MBSS) { 1150 reclaim_address(sc, vap->iv_myaddr); 1151 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1152 if (vap->iv_opmode == IEEE80211_M_MBSS) 1153 sc->sc_nmeshvaps--; 1154 } 1155 if (vap->iv_opmode != IEEE80211_M_WDS) 1156 sc->sc_nvaps--; 1157 #ifdef IEEE80211_SUPPORT_TDMA 1158 /* TDMA operation ceases when the last vap is destroyed */ 1159 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1160 sc->sc_tdma = 0; 1161 sc->sc_swbmiss = 0; 1162 } 1163 #endif 1164 kfree(avp, M_80211_VAP); 1165 1166 if (ifp->if_flags & IFF_RUNNING) { 1167 /* 1168 * Restart rx+tx machines if still running (RUNNING will 1169 * be reset if we just destroyed the last vap). 1170 */ 1171 if (ath_startrecv(sc) != 0) 1172 if_printf(ifp, "%s: unable to restart recv logic\n", 1173 __func__); 1174 if (sc->sc_beacons) { /* restart beacons */ 1175 #ifdef IEEE80211_SUPPORT_TDMA 1176 if (sc->sc_tdma) 1177 ath_tdma_config(sc, NULL); 1178 else 1179 #endif 1180 ath_beacon_config(sc, NULL); 1181 } 1182 ath_hal_intrset(ah, sc->sc_imask); 1183 } 1184 } 1185 1186 void 1187 ath_suspend(struct ath_softc *sc) 1188 { 1189 struct ifnet *ifp = sc->sc_ifp; 1190 struct ieee80211com *ic = ifp->if_l2com; 1191 1192 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1193 __func__, ifp->if_flags); 1194 1195 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1196 if (ic->ic_opmode == IEEE80211_M_STA) 1197 ath_stop(ifp); 1198 else 1199 ieee80211_suspend_all(ic); 1200 /* 1201 * NB: don't worry about putting the chip in low power 1202 * mode; pci will power off our socket on suspend and 1203 * CardBus detaches the device. 1204 */ 1205 } 1206 1207 /* 1208 * Reset the key cache since some parts do not reset the 1209 * contents on resume. First we clear all entries, then 1210 * re-load keys that the 802.11 layer assumes are setup 1211 * in h/w. 1212 */ 1213 static void 1214 ath_reset_keycache(struct ath_softc *sc) 1215 { 1216 struct ifnet *ifp = sc->sc_ifp; 1217 struct ieee80211com *ic = ifp->if_l2com; 1218 struct ath_hal *ah = sc->sc_ah; 1219 int i; 1220 1221 for (i = 0; i < sc->sc_keymax; i++) 1222 ath_hal_keyreset(ah, i); 1223 ieee80211_crypto_reload_keys(ic); 1224 } 1225 1226 void 1227 ath_resume(struct ath_softc *sc) 1228 { 1229 struct ifnet *ifp = sc->sc_ifp; 1230 struct ieee80211com *ic = ifp->if_l2com; 1231 struct ath_hal *ah = sc->sc_ah; 1232 HAL_STATUS status; 1233 1234 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1235 __func__, ifp->if_flags); 1236 1237 /* 1238 * Must reset the chip before we reload the 1239 * keycache as we were powered down on suspend. 1240 */ 1241 ath_hal_reset(ah, sc->sc_opmode, 1242 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1243 AH_FALSE, &status); 1244 ath_reset_keycache(sc); 1245 if (sc->sc_resume_up) { 1246 if (ic->ic_opmode == IEEE80211_M_STA) { 1247 ath_init(sc); 1248 /* 1249 * Program the beacon registers using the last rx'd 1250 * beacon frame and enable sync on the next beacon 1251 * we see. This should handle the case where we 1252 * wakeup and find the same AP and also the case where 1253 * we wakeup and need to roam. For the latter we 1254 * should get bmiss events that trigger a roam. 1255 */ 1256 ath_beacon_config(sc, NULL); 1257 sc->sc_syncbeacon = 1; 1258 } else 1259 ieee80211_resume_all(ic); 1260 } 1261 if (sc->sc_softled) { 1262 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1263 HAL_GPIO_MUX_MAC_NETWORK_LED); 1264 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1265 } 1266 } 1267 1268 void 1269 ath_shutdown(struct ath_softc *sc) 1270 { 1271 struct ifnet *ifp = sc->sc_ifp; 1272 1273 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1274 __func__, ifp->if_flags); 1275 1276 ath_stop(ifp); 1277 /* NB: no point powering down chip as we're about to reboot */ 1278 } 1279 1280 /* 1281 * Interrupt handler. Most of the actual processing is deferred. 1282 */ 1283 void 1284 ath_intr(void *arg) 1285 { 1286 struct ath_softc *sc = arg; 1287 struct ifnet *ifp = sc->sc_ifp; 1288 struct ath_hal *ah = sc->sc_ah; 1289 HAL_INT status; 1290 HAL_INT ostatus; 1291 1292 if (sc->sc_invalid) { 1293 /* 1294 * The hardware is not ready/present, don't touch anything. 1295 * Note this can happen early on if the IRQ is shared. 1296 */ 1297 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1298 return; 1299 } 1300 1301 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1302 return; 1303 if ((ifp->if_flags & IFF_UP) == 0 || 1304 (ifp->if_flags & IFF_RUNNING) == 0) { 1305 HAL_INT status; 1306 1307 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1308 __func__, ifp->if_flags); 1309 ath_hal_getisr(ah, &status); /* clear ISR */ 1310 ath_hal_intrset(ah, 0); /* disable further intr's */ 1311 return; 1312 } 1313 /* 1314 * Figure out the reason(s) for the interrupt. Note 1315 * that the hal returns a pseudo-ISR that may include 1316 * bits we haven't explicitly enabled so we mask the 1317 * value to insure we only process bits we requested. 1318 */ 1319 ath_hal_getisr(ah, &ostatus); /* NB: clears ISR too */ 1320 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, ostatus); 1321 status = ostatus & sc->sc_imask; /* discard unasked for bits */ 1322 if (status & HAL_INT_FATAL) { 1323 sc->sc_stats.ast_hardware++; 1324 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1325 ath_fatal_proc(sc, 0); 1326 } else { 1327 if (status & HAL_INT_SWBA) { 1328 /* 1329 * Software beacon alert--time to send a beacon. 1330 * Handle beacon transmission directly; deferring 1331 * this is too slow to meet timing constraints 1332 * under load. 1333 */ 1334 #ifdef IEEE80211_SUPPORT_TDMA 1335 if (sc->sc_tdma) { 1336 if (sc->sc_tdmaswba == 0) { 1337 struct ieee80211com *ic = ifp->if_l2com; 1338 struct ieee80211vap *vap = 1339 TAILQ_FIRST(&ic->ic_vaps); 1340 ath_tdma_beacon_send(sc, vap); 1341 sc->sc_tdmaswba = 1342 vap->iv_tdma->tdma_bintval; 1343 } else 1344 sc->sc_tdmaswba--; 1345 } else 1346 #endif 1347 { 1348 ath_beacon_proc(sc, 0); 1349 #ifdef IEEE80211_SUPPORT_SUPERG 1350 /* 1351 * Schedule the rx taskq in case there's no 1352 * traffic so any frames held on the staging 1353 * queue are aged and potentially flushed. 1354 */ 1355 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1356 #endif 1357 } 1358 } 1359 1360 /* 1361 * NB: The hardware should re-read the link when the RXE 1362 * bit is written, but it doesn't work at least on 1363 * older chipsets. 1364 */ 1365 if (status & HAL_INT_RXEOL) { 1366 sc->sc_stats.ast_rxeol++; 1367 sc->sc_rxlink = NULL; 1368 } 1369 1370 if (status & HAL_INT_TXURN) { 1371 sc->sc_stats.ast_txurn++; 1372 /* bump tx trigger level */ 1373 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1374 } 1375 1376 if (status & HAL_INT_RX) 1377 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1378 1379 if (status & HAL_INT_TX) 1380 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1381 1382 if (status & HAL_INT_BMISS) { 1383 sc->sc_stats.ast_bmiss++; 1384 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1385 } 1386 1387 if (status & HAL_INT_MIB) { 1388 sc->sc_stats.ast_mib++; 1389 /* 1390 * Disable interrupts until we service the MIB 1391 * interrupt; otherwise it will continue to fire. 1392 */ 1393 ath_hal_intrset(ah, 0); 1394 /* 1395 * Let the hal handle the event. We assume it will 1396 * clear whatever condition caused the interrupt. 1397 */ 1398 ath_hal_mibevent(ah, &sc->sc_halstats); 1399 ath_hal_intrset(ah, sc->sc_imask); 1400 } 1401 1402 if (status & HAL_INT_RXORN) { 1403 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1404 sc->sc_stats.ast_rxorn++; 1405 } 1406 } 1407 } 1408 1409 static void 1410 ath_fatal_proc(void *arg, int pending) 1411 { 1412 struct ath_softc *sc = arg; 1413 struct ifnet *ifp = sc->sc_ifp; 1414 u_int32_t *state; 1415 u_int32_t len; 1416 void *sp; 1417 1418 if_printf(ifp, "hardware error; resetting\n"); 1419 /* 1420 * Fatal errors are unrecoverable. Typically these 1421 * are caused by DMA errors. Collect h/w state from 1422 * the hal so we can diagnose what's going on. 1423 */ 1424 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1425 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1426 state = sp; 1427 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1428 state[0], state[1] , state[2], state[3], 1429 state[4], state[5]); 1430 } 1431 ath_reset(ifp); 1432 } 1433 1434 static void 1435 ath_bmiss_vap(struct ieee80211vap *vap) 1436 { 1437 /* 1438 * Workaround phantom bmiss interrupts by sanity-checking 1439 * the time of our last rx'd frame. If it is within the 1440 * beacon miss interval then ignore the interrupt. If it's 1441 * truly a bmiss we'll get another interrupt soon and that'll 1442 * be dispatched up for processing. Note this applies only 1443 * for h/w beacon miss events. 1444 */ 1445 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1446 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1447 struct ath_softc *sc = ifp->if_softc; 1448 u_int64_t lastrx = sc->sc_lastrx; 1449 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1450 u_int bmisstimeout = 1451 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1452 1453 DPRINTF(sc, ATH_DEBUG_BEACON, 1454 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1455 __func__, (unsigned long long) tsf, 1456 (unsigned long long)(tsf - lastrx), 1457 (unsigned long long) lastrx, bmisstimeout); 1458 1459 if (tsf - lastrx <= bmisstimeout) { 1460 sc->sc_stats.ast_bmiss_phantom++; 1461 return; 1462 } 1463 } 1464 ATH_VAP(vap)->av_bmiss(vap); 1465 } 1466 1467 static int 1468 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1469 { 1470 uint32_t rsize; 1471 void *sp; 1472 1473 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(mask), &sp, &rsize)) 1474 return 0; 1475 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1476 *hangs = *(uint32_t *)sp; 1477 return 1; 1478 } 1479 1480 static void 1481 ath_bmiss_task(void *arg, int pending) 1482 { 1483 struct ath_softc *sc = arg; 1484 struct ifnet *ifp = sc->sc_ifp; 1485 uint32_t hangs; 1486 1487 wlan_serialize_enter(); 1488 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1489 1490 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1491 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs); 1492 ath_reset(ifp); 1493 } else { 1494 ieee80211_beacon_miss(ifp->if_l2com); 1495 } 1496 wlan_serialize_exit(); 1497 } 1498 1499 /* 1500 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1501 * calcs together with WME. If necessary disable the crypto 1502 * hardware and mark the 802.11 state so keys will be setup 1503 * with the MIC work done in software. 1504 */ 1505 static void 1506 ath_settkipmic(struct ath_softc *sc) 1507 { 1508 struct ifnet *ifp = sc->sc_ifp; 1509 struct ieee80211com *ic = ifp->if_l2com; 1510 1511 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1512 if (ic->ic_flags & IEEE80211_F_WME) { 1513 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1514 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1515 } else { 1516 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1517 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1518 } 1519 } 1520 } 1521 1522 static void 1523 ath_init(void *arg) 1524 { 1525 struct ath_softc *sc = (struct ath_softc *) arg; 1526 struct ifnet *ifp = sc->sc_ifp; 1527 struct ieee80211com *ic = ifp->if_l2com; 1528 struct ath_hal *ah = sc->sc_ah; 1529 HAL_STATUS status; 1530 1531 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1532 __func__, ifp->if_flags); 1533 1534 /* 1535 * Stop anything previously setup. This is safe 1536 * whether this is the first time through or not. 1537 */ 1538 ath_stop_locked(ifp); 1539 1540 /* 1541 * The basic interface to setting the hardware in a good 1542 * state is ``reset''. On return the hardware is known to 1543 * be powered up and with interrupts disabled. This must 1544 * be followed by initialization of the appropriate bits 1545 * and then setup of the interrupt mask. 1546 */ 1547 ath_settkipmic(sc); 1548 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1549 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1550 status); 1551 return; 1552 } 1553 ath_chan_change(sc, ic->ic_curchan); 1554 1555 /* 1556 * Likewise this is set during reset so update 1557 * state cached in the driver. 1558 */ 1559 sc->sc_diversity = ath_hal_getdiversity(ah); 1560 sc->sc_lastlongcal = 0; 1561 sc->sc_resetcal = 1; 1562 sc->sc_lastcalreset = 0; 1563 1564 /* 1565 * Setup the hardware after reset: the key cache 1566 * is filled as needed and the receive engine is 1567 * set going. Frame transmit is handled entirely 1568 * in the frame output path; there's nothing to do 1569 * here except setup the interrupt mask. 1570 */ 1571 if (ath_startrecv(sc) != 0) { 1572 if_printf(ifp, "unable to start recv logic\n"); 1573 return; 1574 } 1575 1576 /* 1577 * Enable interrupts. 1578 */ 1579 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1580 | HAL_INT_RXEOL | HAL_INT_RXORN 1581 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1582 /* 1583 * Enable MIB interrupts when there are hardware phy counters. 1584 * Note we only do this (at the moment) for station mode. 1585 */ 1586 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1587 sc->sc_imask |= HAL_INT_MIB; 1588 1589 ifp->if_flags |= IFF_RUNNING; 1590 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 1591 ath_hal_intrset(ah, sc->sc_imask); 1592 1593 1594 #ifdef ATH_TX99_DIAG 1595 if (sc->sc_tx99 != NULL) 1596 sc->sc_tx99->start(sc->sc_tx99); 1597 else 1598 #endif 1599 ieee80211_start_all(ic); /* start all vap's */ 1600 } 1601 1602 static void 1603 ath_stop_locked(struct ifnet *ifp) 1604 { 1605 struct ath_softc *sc = ifp->if_softc; 1606 struct ath_hal *ah = sc->sc_ah; 1607 1608 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1609 __func__, sc->sc_invalid, ifp->if_flags); 1610 1611 if (ifp->if_flags & IFF_RUNNING) { 1612 /* 1613 * Shutdown the hardware and driver: 1614 * reset 802.11 state machine 1615 * turn off timers 1616 * disable interrupts 1617 * turn off the radio 1618 * clear transmit machinery 1619 * clear receive machinery 1620 * drain and release tx queues 1621 * reclaim beacon resources 1622 * power down hardware 1623 * 1624 * Note that some of this work is not possible if the 1625 * hardware is gone (invalid). 1626 */ 1627 #ifdef ATH_TX99_DIAG 1628 if (sc->sc_tx99 != NULL) 1629 sc->sc_tx99->stop(sc->sc_tx99); 1630 #endif 1631 callout_stop(&sc->sc_wd_ch); 1632 sc->sc_wd_timer = 0; 1633 ifp->if_flags &= ~IFF_RUNNING; 1634 if (!sc->sc_invalid) { 1635 if (sc->sc_softled) { 1636 callout_stop(&sc->sc_ledtimer); 1637 ath_hal_gpioset(ah, sc->sc_ledpin, 1638 !sc->sc_ledon); 1639 sc->sc_blinking = 0; 1640 } 1641 ath_hal_intrset(ah, 0); 1642 } 1643 ath_draintxq(sc); 1644 if (!sc->sc_invalid) { 1645 ath_stoprecv(sc); 1646 ath_hal_phydisable(ah); 1647 } else 1648 sc->sc_rxlink = NULL; 1649 ath_beacon_free(sc); /* XXX not needed */ 1650 } 1651 } 1652 1653 static void 1654 ath_stop(struct ifnet *ifp) 1655 { 1656 struct ath_softc *sc __unused = ifp->if_softc; 1657 1658 ath_stop_locked(ifp); 1659 } 1660 1661 /* 1662 * Reset the hardware w/o losing operational state. This is 1663 * basically a more efficient way of doing ath_stop, ath_init, 1664 * followed by state transitions to the current 802.11 1665 * operational state. Used to recover from various errors and 1666 * to reset or reload hardware state. 1667 */ 1668 static int 1669 ath_reset(struct ifnet *ifp) 1670 { 1671 struct ath_softc *sc = ifp->if_softc; 1672 struct ieee80211com *ic = ifp->if_l2com; 1673 struct ath_hal *ah = sc->sc_ah; 1674 HAL_STATUS status; 1675 1676 ath_hal_intrset(ah, 0); /* disable interrupts */ 1677 ath_draintxq(sc); /* stop xmit side */ 1678 ath_stoprecv(sc); /* stop recv side */ 1679 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1680 /* NB: indicate channel change so we do a full reset */ 1681 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1682 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1683 __func__, status); 1684 sc->sc_diversity = ath_hal_getdiversity(ah); 1685 if (ath_startrecv(sc) != 0) /* restart recv */ 1686 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1687 /* 1688 * We may be doing a reset in response to an ioctl 1689 * that changes the channel so update any state that 1690 * might change as a result. 1691 */ 1692 ath_chan_change(sc, ic->ic_curchan); 1693 if (sc->sc_beacons) { /* restart beacons */ 1694 #ifdef IEEE80211_SUPPORT_TDMA 1695 if (sc->sc_tdma) 1696 ath_tdma_config(sc, NULL); 1697 else 1698 #endif 1699 ath_beacon_config(sc, NULL); 1700 } 1701 ath_hal_intrset(ah, sc->sc_imask); 1702 1703 ath_start(ifp); /* restart xmit */ 1704 return 0; 1705 } 1706 1707 static int 1708 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1709 { 1710 struct ieee80211com *ic = vap->iv_ic; 1711 struct ifnet *ifp = ic->ic_ifp; 1712 struct ath_softc *sc = ifp->if_softc; 1713 struct ath_hal *ah = sc->sc_ah; 1714 1715 switch (cmd) { 1716 case IEEE80211_IOC_TXPOWER: 1717 /* 1718 * If per-packet TPC is enabled, then we have nothing 1719 * to do; otherwise we need to force the global limit. 1720 * All this can happen directly; no need to reset. 1721 */ 1722 if (!ath_hal_gettpc(ah)) 1723 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1724 return 0; 1725 } 1726 return ath_reset(ifp); 1727 } 1728 1729 static struct ath_buf * 1730 _ath_getbuf_locked(struct ath_softc *sc) 1731 { 1732 struct ath_buf *bf; 1733 1734 bf = STAILQ_FIRST(&sc->sc_txbuf); 1735 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1736 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1737 else 1738 bf = NULL; 1739 if (bf == NULL) { 1740 kprintf("ath: ran out of descriptors\n"); 1741 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 1742 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 1743 "out of xmit buffers" : "xmit buffer busy"); 1744 } 1745 return bf; 1746 } 1747 1748 static struct ath_buf * 1749 ath_getbuf(struct ath_softc *sc) 1750 { 1751 struct ath_buf *bf; 1752 1753 bf = _ath_getbuf_locked(sc); 1754 if (bf == NULL) { 1755 struct ifnet *ifp = sc->sc_ifp; 1756 1757 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1758 sc->sc_stats.ast_tx_qstop++; 1759 ifp->if_flags |= IFF_OACTIVE; 1760 } 1761 return bf; 1762 } 1763 1764 /* 1765 * Cleanup driver resources when we run out of buffers 1766 * while processing fragments; return the tx buffers 1767 * allocated and drop node references. 1768 */ 1769 static void 1770 ath_txfrag_cleanup(struct ath_softc *sc, 1771 ath_bufhead *frags, struct ieee80211_node *ni) 1772 { 1773 struct ath_buf *bf, *next; 1774 1775 STAILQ_FOREACH_MUTABLE(bf, frags, bf_list, next) { 1776 /* NB: bf assumed clean */ 1777 STAILQ_REMOVE_HEAD(frags, bf_list); 1778 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1779 ieee80211_node_decref(ni); 1780 } 1781 } 1782 1783 /* 1784 * Setup xmit of a fragmented frame. Allocate a buffer 1785 * for each frag and bump the node reference count to 1786 * reflect the held reference to be setup by ath_tx_start. 1787 */ 1788 static int 1789 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1790 struct mbuf *m0, struct ieee80211_node *ni) 1791 { 1792 struct mbuf *m; 1793 struct ath_buf *bf; 1794 1795 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1796 bf = _ath_getbuf_locked(sc); 1797 if (bf == NULL) { /* out of buffers, cleanup */ 1798 ath_txfrag_cleanup(sc, frags, ni); 1799 break; 1800 } 1801 ieee80211_node_incref(ni); 1802 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1803 } 1804 1805 return !STAILQ_EMPTY(frags); 1806 } 1807 1808 static void 1809 ath_start(struct ifnet *ifp) 1810 { 1811 struct ath_softc *sc = ifp->if_softc; 1812 struct ieee80211_node *ni; 1813 struct ath_buf *bf; 1814 struct mbuf *m, *next; 1815 ath_bufhead frags; 1816 1817 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 1818 ifq_purge(&ifp->if_snd); 1819 return; 1820 } 1821 for (;;) { 1822 /* 1823 * Grab a TX buffer and associated resources. 1824 */ 1825 bf = ath_getbuf(sc); 1826 if (bf == NULL) 1827 break; 1828 1829 IF_DEQUEUE(&ifp->if_snd, m); 1830 if (m == NULL) { 1831 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1832 break; 1833 } 1834 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1835 /* 1836 * Check for fragmentation. If this frame 1837 * has been broken up verify we have enough 1838 * buffers to send all the fragments so all 1839 * go out or none... 1840 */ 1841 STAILQ_INIT(&frags); 1842 if ((m->m_flags & M_FRAG) && 1843 !ath_txfrag_setup(sc, &frags, m, ni)) { 1844 DPRINTF(sc, ATH_DEBUG_XMIT, 1845 "%s: out of txfrag buffers\n", __func__); 1846 sc->sc_stats.ast_tx_nofrag++; 1847 ifp->if_oerrors++; 1848 ath_freetx(m); 1849 goto bad; 1850 } 1851 ifp->if_opackets++; 1852 nextfrag: 1853 /* 1854 * Pass the frame to the h/w for transmission. 1855 * Fragmented frames have each frag chained together 1856 * with m_nextpkt. We know there are sufficient ath_buf's 1857 * to send all the frags because of work done by 1858 * ath_txfrag_setup. We leave m_nextpkt set while 1859 * calling ath_tx_start so it can use it to extend the 1860 * the tx duration to cover the subsequent frag and 1861 * so it can reclaim all the mbufs in case of an error; 1862 * ath_tx_start clears m_nextpkt once it commits to 1863 * handing the frame to the hardware. 1864 */ 1865 next = m->m_nextpkt; 1866 if (ath_tx_start(sc, ni, bf, m)) { 1867 bad: 1868 ifp->if_oerrors++; 1869 reclaim: 1870 bf->bf_m = NULL; 1871 bf->bf_node = NULL; 1872 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1873 ath_txfrag_cleanup(sc, &frags, ni); 1874 if (ni != NULL) 1875 ieee80211_free_node(ni); 1876 continue; 1877 } 1878 if (next != NULL) { 1879 /* 1880 * Beware of state changing between frags. 1881 * XXX check sta power-save state? 1882 */ 1883 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1884 DPRINTF(sc, ATH_DEBUG_XMIT, 1885 "%s: flush fragmented packet, state %s\n", 1886 __func__, 1887 ieee80211_state_name[ni->ni_vap->iv_state]); 1888 ath_freetx(next); 1889 goto reclaim; 1890 } 1891 m = next; 1892 bf = STAILQ_FIRST(&frags); 1893 KASSERT(bf != NULL, ("no buf for txfrag")); 1894 STAILQ_REMOVE_HEAD(&frags, bf_list); 1895 goto nextfrag; 1896 } 1897 1898 sc->sc_wd_timer = 5; 1899 } 1900 } 1901 1902 static int 1903 ath_media_change(struct ifnet *ifp) 1904 { 1905 int error = ieee80211_media_change(ifp); 1906 /* NB: only the fixed rate can change and that doesn't need a reset */ 1907 return (error == ENETRESET ? 0 : error); 1908 } 1909 1910 #ifdef ATH_DEBUG 1911 static void 1912 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1913 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1914 { 1915 static const char *ciphers[] = { 1916 "WEP", 1917 "AES-OCB", 1918 "AES-CCM", 1919 "CKIP", 1920 "TKIP", 1921 "CLR", 1922 }; 1923 int i, n; 1924 1925 kprintf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1926 for (i = 0, n = hk->kv_len; i < n; i++) 1927 kprintf("%02x", hk->kv_val[i]); 1928 kprintf(" mac %6D", mac, ":"); 1929 if (hk->kv_type == HAL_CIPHER_TKIP) { 1930 kprintf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1931 for (i = 0; i < sizeof(hk->kv_mic); i++) 1932 kprintf("%02x", hk->kv_mic[i]); 1933 if (!sc->sc_splitmic) { 1934 kprintf(" txmic "); 1935 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1936 kprintf("%02x", hk->kv_txmic[i]); 1937 } 1938 } 1939 kprintf("\n"); 1940 } 1941 #endif 1942 1943 /* 1944 * Set a TKIP key into the hardware. This handles the 1945 * potential distribution of key state to multiple key 1946 * cache slots for TKIP. 1947 */ 1948 static int 1949 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1950 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1951 { 1952 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1953 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1954 struct ath_hal *ah = sc->sc_ah; 1955 1956 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1957 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1958 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1959 if (sc->sc_splitmic) { 1960 /* 1961 * TX key goes at first index, RX key at the rx index. 1962 * The hal handles the MIC keys at index+64. 1963 */ 1964 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1965 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1966 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1967 return 0; 1968 1969 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1970 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1971 /* XXX delete tx key on failure? */ 1972 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1973 } else { 1974 /* 1975 * Room for both TX+RX MIC keys in one key cache 1976 * slot, just set key at the first index; the hal 1977 * will handle the rest. 1978 */ 1979 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1980 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1981 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1982 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1983 } 1984 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1985 if (sc->sc_splitmic) { 1986 /* 1987 * NB: must pass MIC key in expected location when 1988 * the keycache only holds one MIC key per entry. 1989 */ 1990 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 1991 } else 1992 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1993 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1994 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1995 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 1996 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1997 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1998 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1999 } 2000 return 0; 2001 #undef IEEE80211_KEY_XR 2002 } 2003 2004 /* 2005 * Set a net80211 key into the hardware. This handles the 2006 * potential distribution of key state to multiple key 2007 * cache slots for TKIP with hardware MIC support. 2008 */ 2009 static int 2010 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2011 struct ieee80211_node *bss) 2012 { 2013 static const u_int8_t ciphermap[] = { 2014 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2015 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2016 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2017 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2018 (u_int8_t) -1, /* 4 is not allocated */ 2019 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2020 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2021 }; 2022 struct ath_hal *ah = sc->sc_ah; 2023 const struct ieee80211_cipher *cip = k->wk_cipher; 2024 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2025 const u_int8_t *mac; 2026 HAL_KEYVAL hk; 2027 2028 memset(&hk, 0, sizeof(hk)); 2029 /* 2030 * Software crypto uses a "clear key" so non-crypto 2031 * state kept in the key cache are maintained and 2032 * so that rx frames have an entry to match. 2033 */ 2034 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2035 KASSERT(cip->ic_cipher < NELEM(ciphermap), 2036 ("invalid cipher type %u", cip->ic_cipher)); 2037 hk.kv_type = ciphermap[cip->ic_cipher]; 2038 hk.kv_len = k->wk_keylen; 2039 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2040 } else 2041 hk.kv_type = HAL_CIPHER_CLR; 2042 2043 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2044 /* 2045 * Group keys on hardware that supports multicast frame 2046 * key search use a MAC that is the sender's address with 2047 * the high bit set instead of the app-specified address. 2048 */ 2049 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2050 gmac[0] |= 0x80; 2051 mac = gmac; 2052 } else 2053 mac = k->wk_macaddr; 2054 2055 if (hk.kv_type == HAL_CIPHER_TKIP && 2056 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2057 return ath_keyset_tkip(sc, k, &hk, mac); 2058 } else { 2059 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2060 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2061 } 2062 } 2063 2064 /* 2065 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2066 * each key, one for decrypt/encrypt and the other for the MIC. 2067 */ 2068 static u_int16_t 2069 key_alloc_2pair(struct ath_softc *sc, 2070 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2071 { 2072 u_int i, keyix; 2073 2074 KASSERT(sc->sc_splitmic, ("key cache !split")); 2075 /* XXX could optimize */ 2076 for (i = 0; i < NELEM(sc->sc_keymap)/4; i++) { 2077 u_int8_t b = sc->sc_keymap[i]; 2078 if (b != 0xff) { 2079 /* 2080 * One or more slots in this byte are free. 2081 */ 2082 keyix = i*NBBY; 2083 while (b & 1) { 2084 again: 2085 keyix++; 2086 b >>= 1; 2087 } 2088 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2089 if (isset(sc->sc_keymap, keyix+32) || 2090 isset(sc->sc_keymap, keyix+64) || 2091 isset(sc->sc_keymap, keyix+32+64)) { 2092 /* full pair unavailable */ 2093 /* XXX statistic */ 2094 if (keyix == (i+1)*NBBY) { 2095 /* no slots were appropriate, advance */ 2096 continue; 2097 } 2098 goto again; 2099 } 2100 setbit(sc->sc_keymap, keyix); 2101 setbit(sc->sc_keymap, keyix+64); 2102 setbit(sc->sc_keymap, keyix+32); 2103 setbit(sc->sc_keymap, keyix+32+64); 2104 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2105 "%s: key pair %u,%u %u,%u\n", 2106 __func__, keyix, keyix+64, 2107 keyix+32, keyix+32+64); 2108 *txkeyix = keyix; 2109 *rxkeyix = keyix+32; 2110 return 1; 2111 } 2112 } 2113 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2114 return 0; 2115 } 2116 2117 /* 2118 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2119 * each key, one for decrypt/encrypt and the other for the MIC. 2120 */ 2121 static u_int16_t 2122 key_alloc_pair(struct ath_softc *sc, 2123 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2124 { 2125 u_int i, keyix; 2126 2127 KASSERT(!sc->sc_splitmic, ("key cache split")); 2128 /* XXX could optimize */ 2129 for (i = 0; i < NELEM(sc->sc_keymap)/4; i++) { 2130 u_int8_t b = sc->sc_keymap[i]; 2131 if (b != 0xff) { 2132 /* 2133 * One or more slots in this byte are free. 2134 */ 2135 keyix = i*NBBY; 2136 while (b & 1) { 2137 again: 2138 keyix++; 2139 b >>= 1; 2140 } 2141 if (isset(sc->sc_keymap, keyix+64)) { 2142 /* full pair unavailable */ 2143 /* XXX statistic */ 2144 if (keyix == (i+1)*NBBY) { 2145 /* no slots were appropriate, advance */ 2146 continue; 2147 } 2148 goto again; 2149 } 2150 setbit(sc->sc_keymap, keyix); 2151 setbit(sc->sc_keymap, keyix+64); 2152 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2153 "%s: key pair %u,%u\n", 2154 __func__, keyix, keyix+64); 2155 *txkeyix = *rxkeyix = keyix; 2156 return 1; 2157 } 2158 } 2159 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2160 return 0; 2161 } 2162 2163 /* 2164 * Allocate a single key cache slot. 2165 */ 2166 static int 2167 key_alloc_single(struct ath_softc *sc, 2168 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2169 { 2170 u_int i, keyix; 2171 2172 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2173 for (i = 0; i < NELEM(sc->sc_keymap); i++) { 2174 u_int8_t b = sc->sc_keymap[i]; 2175 if (b != 0xff) { 2176 /* 2177 * One or more slots are free. 2178 */ 2179 keyix = i*NBBY; 2180 while (b & 1) 2181 keyix++, b >>= 1; 2182 setbit(sc->sc_keymap, keyix); 2183 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2184 __func__, keyix); 2185 *txkeyix = *rxkeyix = keyix; 2186 return 1; 2187 } 2188 } 2189 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2190 return 0; 2191 } 2192 2193 /* 2194 * Allocate one or more key cache slots for a uniacst key. The 2195 * key itself is needed only to identify the cipher. For hardware 2196 * TKIP with split cipher+MIC keys we allocate two key cache slot 2197 * pairs so that we can setup separate TX and RX MIC keys. Note 2198 * that the MIC key for a TKIP key at slot i is assumed by the 2199 * hardware to be at slot i+64. This limits TKIP keys to the first 2200 * 64 entries. 2201 */ 2202 static int 2203 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2204 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2205 { 2206 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2207 2208 /* 2209 * Group key allocation must be handled specially for 2210 * parts that do not support multicast key cache search 2211 * functionality. For those parts the key id must match 2212 * the h/w key index so lookups find the right key. On 2213 * parts w/ the key search facility we install the sender's 2214 * mac address (with the high bit set) and let the hardware 2215 * find the key w/o using the key id. This is preferred as 2216 * it permits us to support multiple users for adhoc and/or 2217 * multi-station operation. 2218 */ 2219 if (k->wk_keyix != IEEE80211_KEYIX_NONE) { 2220 /* 2221 * Only global keys should have key index assigned. 2222 */ 2223 if (!(&vap->iv_nw_keys[0] <= k && 2224 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2225 /* should not happen */ 2226 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2227 "%s: bogus group key\n", __func__); 2228 return 0; 2229 } 2230 if (vap->iv_opmode != IEEE80211_M_HOSTAP || 2231 !(k->wk_flags & IEEE80211_KEY_GROUP) || 2232 !sc->sc_mcastkey) { 2233 /* 2234 * XXX we pre-allocate the global keys so 2235 * have no way to check if they've already 2236 * been allocated. 2237 */ 2238 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2239 return 1; 2240 } 2241 /* 2242 * Group key and device supports multicast key search. 2243 */ 2244 k->wk_keyix = IEEE80211_KEYIX_NONE; 2245 } 2246 2247 /* 2248 * We allocate two pair for TKIP when using the h/w to do 2249 * the MIC. For everything else, including software crypto, 2250 * we allocate a single entry. Note that s/w crypto requires 2251 * a pass-through slot on the 5211 and 5212. The 5210 does 2252 * not support pass-through cache entries and we map all 2253 * those requests to slot 0. 2254 */ 2255 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2256 return key_alloc_single(sc, keyix, rxkeyix); 2257 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2258 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2259 if (sc->sc_splitmic) 2260 return key_alloc_2pair(sc, keyix, rxkeyix); 2261 else 2262 return key_alloc_pair(sc, keyix, rxkeyix); 2263 } else { 2264 return key_alloc_single(sc, keyix, rxkeyix); 2265 } 2266 } 2267 2268 /* 2269 * Delete an entry in the key cache allocated by ath_key_alloc. 2270 */ 2271 static int 2272 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2273 { 2274 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2275 struct ath_hal *ah = sc->sc_ah; 2276 const struct ieee80211_cipher *cip = k->wk_cipher; 2277 u_int keyix = k->wk_keyix; 2278 2279 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2280 2281 ath_hal_keyreset(ah, keyix); 2282 /* 2283 * Handle split tx/rx keying required for TKIP with h/w MIC. 2284 */ 2285 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2286 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2287 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2288 if (keyix >= IEEE80211_WEP_NKID) { 2289 /* 2290 * Don't touch keymap entries for global keys so 2291 * they are never considered for dynamic allocation. 2292 */ 2293 clrbit(sc->sc_keymap, keyix); 2294 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2295 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2296 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2297 if (sc->sc_splitmic) { 2298 /* +32 for RX key, +32+64 for RX key MIC */ 2299 clrbit(sc->sc_keymap, keyix+32); 2300 clrbit(sc->sc_keymap, keyix+32+64); 2301 } 2302 } 2303 } 2304 return 1; 2305 } 2306 2307 /* 2308 * Set the key cache contents for the specified key. Key cache 2309 * slot(s) must already have been allocated by ath_key_alloc. 2310 */ 2311 static int 2312 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2313 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2314 { 2315 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2316 2317 return ath_keyset(sc, k, vap->iv_bss); 2318 } 2319 2320 /* 2321 * Block/unblock tx+rx processing while a key change is done. 2322 * We assume the caller serializes key management operations 2323 * so we only need to worry about synchronization with other 2324 * uses that originate in the driver. 2325 */ 2326 static void 2327 ath_key_update_begin(struct ieee80211vap *vap) 2328 { 2329 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2330 struct ath_softc *sc = ifp->if_softc; 2331 2332 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2333 taskqueue_block(sc->sc_tq); 2334 } 2335 2336 static void 2337 ath_key_update_end(struct ieee80211vap *vap) 2338 { 2339 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2340 struct ath_softc *sc = ifp->if_softc; 2341 2342 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2343 taskqueue_unblock(sc->sc_tq); 2344 } 2345 2346 /* 2347 * Calculate the receive filter according to the 2348 * operating mode and state: 2349 * 2350 * o always accept unicast, broadcast, and multicast traffic 2351 * o accept PHY error frames when hardware doesn't have MIB support 2352 * to count and we need them for ANI (sta mode only until recently) 2353 * and we are not scanning (ANI is disabled) 2354 * NB: older hal's add rx filter bits out of sight and we need to 2355 * blindly preserve them 2356 * o probe request frames are accepted only when operating in 2357 * hostap, adhoc, mesh, or monitor modes 2358 * o enable promiscuous mode 2359 * - when in monitor mode 2360 * - if interface marked PROMISC (assumes bridge setting is filtered) 2361 * o accept beacons: 2362 * - when operating in station mode for collecting rssi data when 2363 * the station is otherwise quiet, or 2364 * - when operating in adhoc mode so the 802.11 layer creates 2365 * node table entries for peers, 2366 * - when scanning 2367 * - when doing s/w beacon miss (e.g. for ap+sta) 2368 * - when operating in ap mode in 11g to detect overlapping bss that 2369 * require protection 2370 * - when operating in mesh mode to detect neighbors 2371 * o accept control frames: 2372 * - when in monitor mode 2373 * XXX BAR frames for 11n 2374 * XXX HT protection for 11n 2375 */ 2376 static u_int32_t 2377 ath_calcrxfilter(struct ath_softc *sc) 2378 { 2379 struct ifnet *ifp = sc->sc_ifp; 2380 struct ieee80211com *ic = ifp->if_l2com; 2381 u_int32_t rfilt; 2382 2383 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2384 if (!sc->sc_needmib && !sc->sc_scanning) 2385 rfilt |= HAL_RX_FILTER_PHYERR; 2386 if (ic->ic_opmode != IEEE80211_M_STA) 2387 rfilt |= HAL_RX_FILTER_PROBEREQ; 2388 /* XXX ic->ic_monvaps != 0? */ 2389 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2390 rfilt |= HAL_RX_FILTER_PROM; 2391 if (ic->ic_opmode == IEEE80211_M_STA || 2392 ic->ic_opmode == IEEE80211_M_IBSS || 2393 sc->sc_swbmiss || sc->sc_scanning) 2394 rfilt |= HAL_RX_FILTER_BEACON; 2395 /* 2396 * NB: We don't recalculate the rx filter when 2397 * ic_protmode changes; otherwise we could do 2398 * this only when ic_protmode != NONE. 2399 */ 2400 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2401 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2402 rfilt |= HAL_RX_FILTER_BEACON; 2403 if (sc->sc_nmeshvaps) { 2404 rfilt |= HAL_RX_FILTER_BEACON; 2405 if (sc->sc_hasbmatch) 2406 rfilt |= HAL_RX_FILTER_BSSID; 2407 else 2408 rfilt |= HAL_RX_FILTER_PROM; 2409 } 2410 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2411 rfilt |= HAL_RX_FILTER_CONTROL; 2412 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2413 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2414 return rfilt; 2415 } 2416 2417 static void 2418 ath_update_promisc(struct ifnet *ifp) 2419 { 2420 struct ath_softc *sc = ifp->if_softc; 2421 u_int32_t rfilt; 2422 2423 /* configure rx filter */ 2424 rfilt = ath_calcrxfilter(sc); 2425 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2426 2427 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2428 } 2429 2430 static void 2431 ath_update_mcast(struct ifnet *ifp) 2432 { 2433 struct ath_softc *sc = ifp->if_softc; 2434 u_int32_t mfilt[2]; 2435 2436 /* calculate and install multicast filter */ 2437 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2438 struct ifmultiaddr *ifma; 2439 /* 2440 * Merge multicast addresses to form the hardware filter. 2441 */ 2442 mfilt[0] = mfilt[1] = 0; 2443 #ifdef __FreeBSD__ 2444 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2445 #endif 2446 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2447 caddr_t dl; 2448 u_int32_t val; 2449 u_int8_t pos; 2450 2451 /* calculate XOR of eight 6bit values */ 2452 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2453 val = LE_READ_4(dl + 0); 2454 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2455 val = LE_READ_4(dl + 3); 2456 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2457 pos &= 0x3f; 2458 mfilt[pos / 32] |= (1 << (pos % 32)); 2459 } 2460 #ifdef __FreeBSD__ 2461 if_maddr_runlock(ifp); 2462 #endif 2463 } else 2464 mfilt[0] = mfilt[1] = ~0; 2465 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2466 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2467 __func__, mfilt[0], mfilt[1]); 2468 } 2469 2470 static void 2471 ath_mode_init(struct ath_softc *sc) 2472 { 2473 struct ifnet *ifp = sc->sc_ifp; 2474 struct ath_hal *ah = sc->sc_ah; 2475 u_int32_t rfilt; 2476 2477 /* configure rx filter */ 2478 rfilt = ath_calcrxfilter(sc); 2479 ath_hal_setrxfilter(ah, rfilt); 2480 2481 /* configure operational mode */ 2482 ath_hal_setopmode(ah); 2483 2484 /* handle any link-level address change */ 2485 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2486 2487 /* calculate and install multicast filter */ 2488 ath_update_mcast(ifp); 2489 } 2490 2491 /* 2492 * Set the slot time based on the current setting. 2493 */ 2494 static void 2495 ath_setslottime(struct ath_softc *sc) 2496 { 2497 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2498 struct ath_hal *ah = sc->sc_ah; 2499 u_int usec; 2500 2501 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2502 usec = 13; 2503 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2504 usec = 21; 2505 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2506 /* honor short/long slot time only in 11g */ 2507 /* XXX shouldn't honor on pure g or turbo g channel */ 2508 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2509 usec = HAL_SLOT_TIME_9; 2510 else 2511 usec = HAL_SLOT_TIME_20; 2512 } else 2513 usec = HAL_SLOT_TIME_9; 2514 2515 DPRINTF(sc, ATH_DEBUG_RESET, 2516 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2517 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2518 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2519 2520 ath_hal_setslottime(ah, usec); 2521 sc->sc_updateslot = OK; 2522 } 2523 2524 /* 2525 * Callback from the 802.11 layer to update the 2526 * slot time based on the current setting. 2527 */ 2528 static void 2529 ath_updateslot(struct ifnet *ifp) 2530 { 2531 struct ath_softc *sc = ifp->if_softc; 2532 struct ieee80211com *ic = ifp->if_l2com; 2533 2534 /* 2535 * When not coordinating the BSS, change the hardware 2536 * immediately. For other operation we defer the change 2537 * until beacon updates have propagated to the stations. 2538 */ 2539 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2540 ic->ic_opmode == IEEE80211_M_MBSS) 2541 sc->sc_updateslot = UPDATE; 2542 else 2543 ath_setslottime(sc); 2544 } 2545 2546 /* 2547 * Setup a h/w transmit queue for beacons. 2548 */ 2549 static int 2550 ath_beaconq_setup(struct ath_hal *ah) 2551 { 2552 HAL_TXQ_INFO qi; 2553 2554 memset(&qi, 0, sizeof(qi)); 2555 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2556 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2557 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2558 /* NB: for dynamic turbo, don't enable any other interrupts */ 2559 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2560 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2561 } 2562 2563 /* 2564 * Setup the transmit queue parameters for the beacon queue. 2565 */ 2566 static int 2567 ath_beaconq_config(struct ath_softc *sc) 2568 { 2569 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2570 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2571 struct ath_hal *ah = sc->sc_ah; 2572 HAL_TXQ_INFO qi; 2573 2574 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2575 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2576 ic->ic_opmode == IEEE80211_M_MBSS) { 2577 /* 2578 * Always burst out beacon and CAB traffic. 2579 */ 2580 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2581 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2582 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2583 } else { 2584 struct wmeParams *wmep = 2585 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2586 /* 2587 * Adhoc mode; important thing is to use 2x cwmin. 2588 */ 2589 qi.tqi_aifs = wmep->wmep_aifsn; 2590 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2591 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2592 } 2593 2594 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2595 device_printf(sc->sc_dev, "unable to update parameters for " 2596 "beacon hardware queue!\n"); 2597 return 0; 2598 } else { 2599 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2600 return 1; 2601 } 2602 #undef ATH_EXPONENT_TO_VALUE 2603 } 2604 2605 /* 2606 * Allocate and setup an initial beacon frame. 2607 */ 2608 static int 2609 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2610 { 2611 struct ieee80211vap *vap = ni->ni_vap; 2612 struct ath_vap *avp = ATH_VAP(vap); 2613 struct ath_buf *bf; 2614 struct mbuf *m; 2615 int error; 2616 2617 bf = avp->av_bcbuf; 2618 if (bf->bf_m != NULL) { 2619 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2620 m_freem(bf->bf_m); 2621 bf->bf_m = NULL; 2622 } 2623 if (bf->bf_node != NULL) { 2624 ieee80211_free_node(bf->bf_node); 2625 bf->bf_node = NULL; 2626 } 2627 2628 /* 2629 * NB: the beacon data buffer must be 32-bit aligned; 2630 * we assume the mbuf routines will return us something 2631 * with this alignment (perhaps should assert). 2632 */ 2633 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2634 if (m == NULL) { 2635 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2636 sc->sc_stats.ast_be_nombuf++; 2637 return ENOMEM; 2638 } 2639 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2640 bf->bf_segs, 1, &bf->bf_nseg, 2641 BUS_DMA_NOWAIT); 2642 if (error != 0) { 2643 device_printf(sc->sc_dev, 2644 "%s: cannot map mbuf, bus_dmamap_load_mbuf_segment returns %d\n", 2645 __func__, error); 2646 m_freem(m); 2647 return error; 2648 } 2649 2650 /* 2651 * Calculate a TSF adjustment factor required for staggered 2652 * beacons. Note that we assume the format of the beacon 2653 * frame leaves the tstamp field immediately following the 2654 * header. 2655 */ 2656 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2657 uint64_t tsfadjust; 2658 struct ieee80211_frame *wh; 2659 2660 /* 2661 * The beacon interval is in TU's; the TSF is in usecs. 2662 * We figure out how many TU's to add to align the timestamp 2663 * then convert to TSF units and handle byte swapping before 2664 * inserting it in the frame. The hardware will then add this 2665 * each time a beacon frame is sent. Note that we align vap's 2666 * 1..N and leave vap 0 untouched. This means vap 0 has a 2667 * timestamp in one beacon interval while the others get a 2668 * timstamp aligned to the next interval. 2669 */ 2670 tsfadjust = ni->ni_intval * 2671 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2672 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2673 2674 DPRINTF(sc, ATH_DEBUG_BEACON, 2675 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2676 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2677 avp->av_bslot, ni->ni_intval, 2678 (long long unsigned) le64toh(tsfadjust)); 2679 2680 wh = mtod(m, struct ieee80211_frame *); 2681 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2682 } 2683 bf->bf_m = m; 2684 bf->bf_node = ieee80211_ref_node(ni); 2685 2686 return 0; 2687 } 2688 2689 /* 2690 * Setup the beacon frame for transmit. 2691 */ 2692 static void 2693 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2694 { 2695 #define USE_SHPREAMBLE(_ic) \ 2696 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2697 == IEEE80211_F_SHPREAMBLE) 2698 struct ieee80211_node *ni = bf->bf_node; 2699 struct ieee80211com *ic = ni->ni_ic; 2700 struct mbuf *m = bf->bf_m; 2701 struct ath_hal *ah = sc->sc_ah; 2702 struct ath_desc *ds; 2703 int flags, antenna; 2704 const HAL_RATE_TABLE *rt; 2705 u_int8_t rix, rate; 2706 2707 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2708 __func__, m, m->m_len); 2709 2710 /* setup descriptors */ 2711 ds = bf->bf_desc; 2712 2713 flags = HAL_TXDESC_NOACK; 2714 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2715 ds->ds_link = bf->bf_daddr; /* self-linked */ 2716 flags |= HAL_TXDESC_VEOL; 2717 /* 2718 * Let hardware handle antenna switching. 2719 */ 2720 antenna = sc->sc_txantenna; 2721 } else { 2722 ds->ds_link = 0; 2723 /* 2724 * Switch antenna every 4 beacons. 2725 * XXX assumes two antenna 2726 */ 2727 if (sc->sc_txantenna != 0) 2728 antenna = sc->sc_txantenna; 2729 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2730 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2731 else 2732 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2733 } 2734 2735 KASSERT(bf->bf_nseg == 1, 2736 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2737 ds->ds_data = bf->bf_segs[0].ds_addr; 2738 /* 2739 * Calculate rate code. 2740 * XXX everything at min xmit rate 2741 */ 2742 rix = 0; 2743 rt = sc->sc_currates; 2744 rate = rt->info[rix].rateCode; 2745 if (USE_SHPREAMBLE(ic)) 2746 rate |= rt->info[rix].shortPreamble; 2747 ath_hal_setuptxdesc(ah, ds 2748 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2749 , sizeof(struct ieee80211_frame)/* header length */ 2750 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2751 , ni->ni_txpower /* txpower XXX */ 2752 , rate, 1 /* series 0 rate/tries */ 2753 , HAL_TXKEYIX_INVALID /* no encryption */ 2754 , antenna /* antenna mode */ 2755 , flags /* no ack, veol for beacons */ 2756 , 0 /* rts/cts rate */ 2757 , 0 /* rts/cts duration */ 2758 ); 2759 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2760 ath_hal_filltxdesc(ah, ds 2761 , roundup(m->m_len, 4) /* buffer length */ 2762 , AH_TRUE /* first segment */ 2763 , AH_TRUE /* last segment */ 2764 , ds /* first descriptor */ 2765 ); 2766 #if 0 2767 ath_desc_swap(ds); 2768 #endif 2769 #undef USE_SHPREAMBLE 2770 } 2771 2772 static void 2773 ath_beacon_update(struct ieee80211vap *vap, int item) 2774 { 2775 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2776 2777 setbit(bo->bo_flags, item); 2778 } 2779 2780 /* 2781 * Append the contents of src to dst; both queues 2782 * are assumed to be locked. 2783 */ 2784 static void 2785 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2786 { 2787 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2788 if (src->axq_depth) 2789 dst->axq_link = src->axq_link; 2790 src->axq_link = NULL; 2791 dst->axq_depth += src->axq_depth; 2792 src->axq_depth = 0; 2793 } 2794 2795 /* 2796 * Transmit a beacon frame at SWBA. Dynamic updates to the 2797 * frame contents are done as needed and the slot time is 2798 * also adjusted based on current state. 2799 */ 2800 static void 2801 ath_beacon_proc(void *arg, int pending) 2802 { 2803 struct ath_softc *sc = arg; 2804 struct ath_hal *ah = sc->sc_ah; 2805 struct ieee80211vap *vap; 2806 struct ath_buf *bf; 2807 int slot, otherant; 2808 uint32_t bfaddr; 2809 2810 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2811 __func__, pending); 2812 /* 2813 * Check if the previous beacon has gone out. If 2814 * not don't try to post another, skip this period 2815 * and wait for the next. Missed beacons indicate 2816 * a problem and should not occur. If we miss too 2817 * many consecutive beacons reset the device. 2818 */ 2819 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2820 sc->sc_bmisscount++; 2821 DPRINTF(sc, ATH_DEBUG_BEACON, 2822 "%s: missed %u consecutive beacons\n", 2823 __func__, sc->sc_bmisscount); 2824 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2825 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2826 return; 2827 } 2828 if (sc->sc_bmisscount != 0) { 2829 DPRINTF(sc, ATH_DEBUG_BEACON, 2830 "%s: resume beacon xmit after %u misses\n", 2831 __func__, sc->sc_bmisscount); 2832 sc->sc_bmisscount = 0; 2833 } 2834 2835 /* 2836 * Stop any current dma before messing with the beacon linkages. 2837 */ 2838 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2839 DPRINTF(sc, ATH_DEBUG_ANY, 2840 "%s: beacon queue %u did not stop?\n", 2841 __func__, sc->sc_bhalq); 2842 } 2843 2844 if (sc->sc_stagbeacons) { /* staggered beacons */ 2845 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2846 uint32_t tsftu; 2847 2848 tsftu = ath_hal_gettsf32(ah) >> 10; 2849 /* XXX lintval */ 2850 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2851 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2852 bfaddr = 0; 2853 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2854 bf = ath_beacon_generate(sc, vap); 2855 if (bf != NULL) 2856 bfaddr = bf->bf_daddr; 2857 } 2858 } else { /* burst'd beacons */ 2859 uint32_t *bflink = &bfaddr; 2860 2861 for (slot = 0; slot < ATH_BCBUF; slot++) { 2862 vap = sc->sc_bslot[slot]; 2863 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2864 bf = ath_beacon_generate(sc, vap); 2865 if (bf != NULL) { 2866 *bflink = bf->bf_daddr; 2867 bflink = &bf->bf_desc->ds_link; 2868 } 2869 } 2870 } 2871 *bflink = 0; /* terminate list */ 2872 } 2873 2874 /* 2875 * Handle slot time change when a non-ERP station joins/leaves 2876 * an 11g network. The 802.11 layer notifies us via callback, 2877 * we mark updateslot, then wait one beacon before effecting 2878 * the change. This gives associated stations at least one 2879 * beacon interval to note the state change. 2880 */ 2881 /* XXX locking */ 2882 if (sc->sc_updateslot == UPDATE) { 2883 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2884 sc->sc_slotupdate = slot; 2885 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2886 ath_setslottime(sc); /* commit change to h/w */ 2887 2888 /* 2889 * Check recent per-antenna transmit statistics and flip 2890 * the default antenna if noticeably more frames went out 2891 * on the non-default antenna. 2892 * XXX assumes 2 anntenae 2893 */ 2894 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2895 otherant = sc->sc_defant & 1 ? 2 : 1; 2896 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2897 ath_setdefantenna(sc, otherant); 2898 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2899 } 2900 2901 if (bfaddr != 0) { 2902 /* NB: cabq traffic should already be queued and primed */ 2903 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2904 sc->sc_stats.ast_be_xmit++; 2905 ath_hal_txstart(ah, sc->sc_bhalq); 2906 } 2907 /* else no beacon will be generated */ 2908 } 2909 2910 static struct ath_buf * 2911 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2912 { 2913 struct ath_vap *avp = ATH_VAP(vap); 2914 struct ath_txq *cabq = sc->sc_cabq; 2915 struct ath_buf *bf; 2916 struct mbuf *m; 2917 int nmcastq, error; 2918 2919 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2920 ("not running, state %d", vap->iv_state)); 2921 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2922 2923 /* 2924 * Update dynamic beacon contents. If this returns 2925 * non-zero then we need to remap the memory because 2926 * the beacon frame changed size (probably because 2927 * of the TIM bitmap). 2928 */ 2929 bf = avp->av_bcbuf; 2930 m = bf->bf_m; 2931 nmcastq = avp->av_mcastq.axq_depth; 2932 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2933 /* XXX too conservative? */ 2934 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2935 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2936 bf->bf_segs, 1, &bf->bf_nseg, 2937 BUS_DMA_NOWAIT); 2938 if (error != 0) { 2939 if_printf(vap->iv_ifp, 2940 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 2941 __func__, error); 2942 return NULL; 2943 } 2944 } 2945 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2946 DPRINTF(sc, ATH_DEBUG_BEACON, 2947 "%s: cabq did not drain, mcastq %u cabq %u\n", 2948 __func__, nmcastq, cabq->axq_depth); 2949 sc->sc_stats.ast_cabq_busy++; 2950 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2951 /* 2952 * CABQ traffic from a previous vap is still pending. 2953 * We must drain the q before this beacon frame goes 2954 * out as otherwise this vap's stations will get cab 2955 * frames from a different vap. 2956 * XXX could be slow causing us to miss DBA 2957 */ 2958 ath_tx_draintxq(sc, cabq); 2959 } 2960 } 2961 ath_beacon_setup(sc, bf); 2962 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2963 2964 /* 2965 * Enable the CAB queue before the beacon queue to 2966 * insure cab frames are triggered by this beacon. 2967 */ 2968 if (avp->av_boff.bo_tim[4] & 1) { 2969 struct ath_hal *ah = sc->sc_ah; 2970 2971 /* NB: only at DTIM */ 2972 if (nmcastq) { 2973 struct ath_buf *bfm; 2974 int qbusy; 2975 2976 /* 2977 * Move frames from the s/w mcast q to the h/w cab q. 2978 * XXX MORE_DATA bit 2979 */ 2980 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 2981 qbusy = ath_hal_txqenabled(ah, cabq->axq_qnum); 2982 if (qbusy == 0) { 2983 if (cabq->axq_link != NULL) { 2984 cpu_sfence(); 2985 *cabq->axq_link = bfm->bf_daddr; 2986 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 2987 } else { 2988 cpu_sfence(); 2989 ath_hal_puttxbuf(ah, cabq->axq_qnum, 2990 bfm->bf_daddr); 2991 } 2992 } else { 2993 if (cabq->axq_link != NULL) { 2994 cpu_sfence(); 2995 *cabq->axq_link = bfm->bf_daddr; 2996 } 2997 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 2998 } 2999 ath_txqmove(cabq, &avp->av_mcastq); 3000 3001 sc->sc_stats.ast_cabq_xmit += nmcastq; 3002 } 3003 /* NB: gated by beacon so safe to start here */ 3004 ath_hal_txstart(ah, cabq->axq_qnum); 3005 } 3006 return bf; 3007 } 3008 3009 static void 3010 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3011 { 3012 struct ath_vap *avp = ATH_VAP(vap); 3013 struct ath_hal *ah = sc->sc_ah; 3014 struct ath_buf *bf; 3015 struct mbuf *m; 3016 int error; 3017 3018 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3019 3020 /* 3021 * Update dynamic beacon contents. If this returns 3022 * non-zero then we need to remap the memory because 3023 * the beacon frame changed size (probably because 3024 * of the TIM bitmap). 3025 */ 3026 bf = avp->av_bcbuf; 3027 m = bf->bf_m; 3028 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3029 /* XXX too conservative? */ 3030 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3031 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 3032 bf->bf_segs, 1, &bf->bf_nseg, 3033 BUS_DMA_NOWAIT); 3034 if (error != 0) { 3035 if_printf(vap->iv_ifp, 3036 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 3037 __func__, error); 3038 return; 3039 } 3040 } 3041 ath_beacon_setup(sc, bf); 3042 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3043 3044 /* NB: caller is known to have already stopped tx dma */ 3045 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3046 ath_hal_txstart(ah, sc->sc_bhalq); 3047 } 3048 3049 /* 3050 * Reset the hardware after detecting beacons have stopped. 3051 */ 3052 static void 3053 ath_bstuck_task(void *arg, int pending) 3054 { 3055 struct ath_softc *sc = arg; 3056 struct ifnet *ifp = sc->sc_ifp; 3057 3058 wlan_serialize_enter(); 3059 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3060 sc->sc_bmisscount); 3061 sc->sc_stats.ast_bstuck++; 3062 ath_reset(ifp); 3063 wlan_serialize_exit(); 3064 } 3065 3066 /* 3067 * Reclaim beacon resources and return buffer to the pool. 3068 */ 3069 static void 3070 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3071 { 3072 3073 if (bf->bf_m != NULL) { 3074 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3075 m_freem(bf->bf_m); 3076 bf->bf_m = NULL; 3077 } 3078 if (bf->bf_node != NULL) { 3079 ieee80211_free_node(bf->bf_node); 3080 bf->bf_node = NULL; 3081 } 3082 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3083 } 3084 3085 /* 3086 * Reclaim beacon resources. 3087 */ 3088 static void 3089 ath_beacon_free(struct ath_softc *sc) 3090 { 3091 struct ath_buf *bf; 3092 3093 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3094 if (bf->bf_m != NULL) { 3095 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3096 m_freem(bf->bf_m); 3097 bf->bf_m = NULL; 3098 } 3099 if (bf->bf_node != NULL) { 3100 ieee80211_free_node(bf->bf_node); 3101 bf->bf_node = NULL; 3102 } 3103 } 3104 } 3105 3106 /* 3107 * Configure the beacon and sleep timers. 3108 * 3109 * When operating as an AP this resets the TSF and sets 3110 * up the hardware to notify us when we need to issue beacons. 3111 * 3112 * When operating in station mode this sets up the beacon 3113 * timers according to the timestamp of the last received 3114 * beacon and the current TSF, configures PCF and DTIM 3115 * handling, programs the sleep registers so the hardware 3116 * will wakeup in time to receive beacons, and configures 3117 * the beacon miss handling so we'll receive a BMISS 3118 * interrupt when we stop seeing beacons from the AP 3119 * we've associated with. 3120 */ 3121 static void 3122 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3123 { 3124 #define TSF_TO_TU(_h,_l) \ 3125 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3126 #define FUDGE 2 3127 struct ath_hal *ah = sc->sc_ah; 3128 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3129 struct ieee80211_node *ni; 3130 u_int32_t nexttbtt, intval, tsftu; 3131 u_int64_t tsf; 3132 3133 if (vap == NULL) 3134 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3135 ni = vap->iv_bss; 3136 3137 /* extract tstamp from last beacon and convert to TU */ 3138 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3139 LE_READ_4(ni->ni_tstamp.data)); 3140 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3141 ic->ic_opmode == IEEE80211_M_MBSS) { 3142 /* 3143 * For multi-bss ap/mesh support beacons are either staggered 3144 * evenly over N slots or burst together. For the former 3145 * arrange for the SWBA to be delivered for each slot. 3146 * Slots that are not occupied will generate nothing. 3147 */ 3148 /* NB: the beacon interval is kept internally in TU's */ 3149 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3150 if (sc->sc_stagbeacons) 3151 intval /= ATH_BCBUF; 3152 } else { 3153 /* NB: the beacon interval is kept internally in TU's */ 3154 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3155 } 3156 if (nexttbtt == 0) /* e.g. for ap mode */ 3157 nexttbtt = intval; 3158 else if (intval) /* NB: can be 0 for monitor mode */ 3159 nexttbtt = roundup(nexttbtt, intval); 3160 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3161 __func__, nexttbtt, intval, ni->ni_intval); 3162 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3163 HAL_BEACON_STATE bs; 3164 int dtimperiod, dtimcount; 3165 int cfpperiod, cfpcount; 3166 3167 /* 3168 * Setup dtim and cfp parameters according to 3169 * last beacon we received (which may be none). 3170 */ 3171 dtimperiod = ni->ni_dtim_period; 3172 if (dtimperiod <= 0) /* NB: 0 if not known */ 3173 dtimperiod = 1; 3174 dtimcount = ni->ni_dtim_count; 3175 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3176 dtimcount = 0; /* XXX? */ 3177 cfpperiod = 1; /* NB: no PCF support yet */ 3178 cfpcount = 0; 3179 /* 3180 * Pull nexttbtt forward to reflect the current 3181 * TSF and calculate dtim+cfp state for the result. 3182 */ 3183 tsf = ath_hal_gettsf64(ah); 3184 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3185 do { 3186 nexttbtt += intval; 3187 if (--dtimcount < 0) { 3188 dtimcount = dtimperiod - 1; 3189 if (--cfpcount < 0) 3190 cfpcount = cfpperiod - 1; 3191 } 3192 } while (nexttbtt < tsftu); 3193 memset(&bs, 0, sizeof(bs)); 3194 bs.bs_intval = intval; 3195 bs.bs_nexttbtt = nexttbtt; 3196 bs.bs_dtimperiod = dtimperiod*intval; 3197 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3198 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3199 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3200 bs.bs_cfpmaxduration = 0; 3201 #if 0 3202 /* 3203 * The 802.11 layer records the offset to the DTIM 3204 * bitmap while receiving beacons; use it here to 3205 * enable h/w detection of our AID being marked in 3206 * the bitmap vector (to indicate frames for us are 3207 * pending at the AP). 3208 * XXX do DTIM handling in s/w to WAR old h/w bugs 3209 * XXX enable based on h/w rev for newer chips 3210 */ 3211 bs.bs_timoffset = ni->ni_timoff; 3212 #endif 3213 /* 3214 * Calculate the number of consecutive beacons to miss 3215 * before taking a BMISS interrupt. 3216 * Note that we clamp the result to at most 10 beacons. 3217 */ 3218 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3219 if (bs.bs_bmissthreshold > 10) 3220 bs.bs_bmissthreshold = 10; 3221 else if (bs.bs_bmissthreshold <= 0) 3222 bs.bs_bmissthreshold = 1; 3223 3224 /* 3225 * Calculate sleep duration. The configuration is 3226 * given in ms. We insure a multiple of the beacon 3227 * period is used. Also, if the sleep duration is 3228 * greater than the DTIM period then it makes senses 3229 * to make it a multiple of that. 3230 * 3231 * XXX fixed at 100ms 3232 */ 3233 bs.bs_sleepduration = 3234 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3235 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3236 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3237 3238 DPRINTF(sc, ATH_DEBUG_BEACON, 3239 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3240 , __func__ 3241 , tsf, tsftu 3242 , bs.bs_intval 3243 , bs.bs_nexttbtt 3244 , bs.bs_dtimperiod 3245 , bs.bs_nextdtim 3246 , bs.bs_bmissthreshold 3247 , bs.bs_sleepduration 3248 , bs.bs_cfpperiod 3249 , bs.bs_cfpmaxduration 3250 , bs.bs_cfpnext 3251 , bs.bs_timoffset 3252 ); 3253 ath_hal_intrset(ah, 0); 3254 ath_hal_beacontimers(ah, &bs); 3255 sc->sc_imask |= HAL_INT_BMISS; 3256 ath_hal_intrset(ah, sc->sc_imask); 3257 } else { 3258 ath_hal_intrset(ah, 0); 3259 if (nexttbtt == intval) 3260 intval |= HAL_BEACON_RESET_TSF; 3261 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3262 /* 3263 * In IBSS mode enable the beacon timers but only 3264 * enable SWBA interrupts if we need to manually 3265 * prepare beacon frames. Otherwise we use a 3266 * self-linked tx descriptor and let the hardware 3267 * deal with things. 3268 */ 3269 intval |= HAL_BEACON_ENA; 3270 if (!sc->sc_hasveol) 3271 sc->sc_imask |= HAL_INT_SWBA; 3272 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3273 /* 3274 * Pull nexttbtt forward to reflect 3275 * the current TSF. 3276 */ 3277 tsf = ath_hal_gettsf64(ah); 3278 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3279 do { 3280 nexttbtt += intval; 3281 } while (nexttbtt < tsftu); 3282 } 3283 ath_beaconq_config(sc); 3284 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3285 ic->ic_opmode == IEEE80211_M_MBSS) { 3286 /* 3287 * In AP/mesh mode we enable the beacon timers 3288 * and SWBA interrupts to prepare beacon frames. 3289 */ 3290 intval |= HAL_BEACON_ENA; 3291 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3292 ath_beaconq_config(sc); 3293 } 3294 ath_hal_beaconinit(ah, nexttbtt, intval); 3295 sc->sc_bmisscount = 0; 3296 ath_hal_intrset(ah, sc->sc_imask); 3297 /* 3298 * When using a self-linked beacon descriptor in 3299 * ibss mode load it once here. 3300 */ 3301 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3302 ath_beacon_start_adhoc(sc, vap); 3303 } 3304 sc->sc_syncbeacon = 0; 3305 #undef FUDGE 3306 #undef TSF_TO_TU 3307 } 3308 3309 static void 3310 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3311 { 3312 bus_addr_t *paddr = (bus_addr_t*) arg; 3313 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3314 *paddr = segs->ds_addr; 3315 } 3316 3317 static int 3318 ath_descdma_setup(struct ath_softc *sc, 3319 struct ath_descdma *dd, ath_bufhead *head, 3320 const char *name, int nbuf, int ndesc) 3321 { 3322 #define DS2PHYS(_dd, _ds) \ 3323 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3324 struct ifnet *ifp = sc->sc_ifp; 3325 struct ath_desc *ds; 3326 struct ath_buf *bf; 3327 int i, bsize, error; 3328 3329 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3330 __func__, name, nbuf, ndesc); 3331 3332 dd->dd_name = name; 3333 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3334 3335 /* 3336 * Setup DMA descriptor area. 3337 */ 3338 error = bus_dma_tag_create(dd->dd_dmat, /* parent */ 3339 PAGE_SIZE, 0, /* alignment, bounds */ 3340 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3341 BUS_SPACE_MAXADDR, /* highaddr */ 3342 NULL, NULL, /* filter, filterarg */ 3343 dd->dd_desc_len, /* maxsize */ 3344 1, /* nsegments */ 3345 dd->dd_desc_len, /* maxsegsize */ 3346 BUS_DMA_ALLOCNOW, /* flags */ 3347 &dd->dd_dmat); 3348 if (error != 0) { 3349 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3350 return error; 3351 } 3352 3353 /* allocate descriptors */ 3354 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3355 if (error != 0) { 3356 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3357 "error %u\n", dd->dd_name, error); 3358 goto fail0; 3359 } 3360 3361 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3362 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3363 &dd->dd_dmamap); 3364 if (error != 0) { 3365 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3366 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3367 goto fail1; 3368 } 3369 3370 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3371 dd->dd_desc, dd->dd_desc_len, 3372 ath_load_cb, &dd->dd_desc_paddr, 3373 BUS_DMA_NOWAIT); 3374 if (error != 0) { 3375 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3376 dd->dd_name, error); 3377 goto fail2; 3378 } 3379 3380 ds = dd->dd_desc; 3381 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3382 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3383 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3384 3385 /* allocate rx buffers */ 3386 bsize = sizeof(struct ath_buf) * nbuf; 3387 bf = kmalloc(bsize, M_ATHDEV, M_INTWAIT | M_ZERO); 3388 if (bf == NULL) { 3389 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 3390 dd->dd_name, bsize); 3391 goto fail3; 3392 } 3393 dd->dd_bufptr = bf; 3394 3395 STAILQ_INIT(head); 3396 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3397 bf->bf_desc = ds; 3398 bf->bf_daddr = DS2PHYS(dd, ds); 3399 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3400 &bf->bf_dmamap); 3401 if (error != 0) { 3402 if_printf(ifp, "unable to create dmamap for %s " 3403 "buffer %u, error %u\n", dd->dd_name, i, error); 3404 ath_descdma_cleanup(sc, dd, head); 3405 return error; 3406 } 3407 STAILQ_INSERT_TAIL(head, bf, bf_list); 3408 } 3409 return 0; 3410 fail3: 3411 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3412 fail2: 3413 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3414 fail1: 3415 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3416 fail0: 3417 bus_dma_tag_destroy(dd->dd_dmat); 3418 memset(dd, 0, sizeof(*dd)); 3419 return error; 3420 #undef DS2PHYS 3421 } 3422 3423 static void 3424 ath_descdma_cleanup(struct ath_softc *sc, 3425 struct ath_descdma *dd, ath_bufhead *head) 3426 { 3427 struct ath_buf *bf; 3428 struct ieee80211_node *ni; 3429 3430 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3431 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3432 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3433 bus_dma_tag_destroy(dd->dd_dmat); 3434 3435 STAILQ_FOREACH(bf, head, bf_list) { 3436 if (bf->bf_m) { 3437 m_freem(bf->bf_m); 3438 bf->bf_m = NULL; 3439 } 3440 if (bf->bf_dmamap != NULL) { 3441 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3442 bf->bf_dmamap = NULL; 3443 } 3444 ni = bf->bf_node; 3445 bf->bf_node = NULL; 3446 if (ni != NULL) { 3447 /* 3448 * Reclaim node reference. 3449 */ 3450 ieee80211_free_node(ni); 3451 } 3452 } 3453 3454 STAILQ_INIT(head); 3455 kfree(dd->dd_bufptr, M_ATHDEV); 3456 memset(dd, 0, sizeof(*dd)); 3457 } 3458 3459 static int 3460 ath_desc_alloc(struct ath_softc *sc) 3461 { 3462 int error; 3463 3464 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3465 "rx", ath_rxbuf, 1); 3466 if (error != 0) 3467 return error; 3468 3469 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3470 "tx", ath_txbuf, ATH_TXDESC); 3471 if (error != 0) { 3472 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3473 return error; 3474 } 3475 3476 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3477 "beacon", ATH_BCBUF, 1); 3478 if (error != 0) { 3479 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3480 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3481 return error; 3482 } 3483 return 0; 3484 } 3485 3486 static void 3487 ath_desc_free(struct ath_softc *sc) 3488 { 3489 3490 if (sc->sc_bdma.dd_desc_len != 0) 3491 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3492 if (sc->sc_txdma.dd_desc_len != 0) 3493 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3494 if (sc->sc_rxdma.dd_desc_len != 0) 3495 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3496 } 3497 3498 static struct ieee80211_node * 3499 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3500 { 3501 struct ieee80211com *ic = vap->iv_ic; 3502 struct ath_softc *sc = ic->ic_ifp->if_softc; 3503 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3504 struct ath_node *an; 3505 3506 an = kmalloc(space, M_80211_NODE, M_INTWAIT|M_ZERO); 3507 if (an == NULL) { 3508 /* XXX stat+msg */ 3509 return NULL; 3510 } 3511 ath_rate_node_init(sc, an); 3512 3513 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3514 return &an->an_node; 3515 } 3516 3517 static void 3518 ath_node_free(struct ieee80211_node *ni) 3519 { 3520 struct ieee80211com *ic = ni->ni_ic; 3521 struct ath_softc *sc = ic->ic_ifp->if_softc; 3522 3523 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3524 3525 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3526 sc->sc_node_free(ni); 3527 } 3528 3529 static void 3530 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3531 { 3532 struct ieee80211com *ic = ni->ni_ic; 3533 struct ath_softc *sc = ic->ic_ifp->if_softc; 3534 struct ath_hal *ah = sc->sc_ah; 3535 3536 *rssi = ic->ic_node_getrssi(ni); 3537 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3538 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3539 else 3540 *noise = -95; /* nominally correct */ 3541 } 3542 3543 static int 3544 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3545 { 3546 struct ath_hal *ah = sc->sc_ah; 3547 int error; 3548 struct mbuf *m; 3549 struct ath_desc *ds; 3550 3551 m = bf->bf_m; 3552 if (m == NULL) { 3553 /* 3554 * NB: by assigning a page to the rx dma buffer we 3555 * implicitly satisfy the Atheros requirement that 3556 * this buffer be cache-line-aligned and sized to be 3557 * multiple of the cache line size. Not doing this 3558 * causes weird stuff to happen (for the 5210 at least). 3559 */ 3560 m = m_getcl(MB_WAIT, MT_DATA, M_PKTHDR); 3561 if (m == NULL) { 3562 kprintf("ath_rxbuf_init: no mbuf\n"); 3563 DPRINTF(sc, ATH_DEBUG_ANY, 3564 "%s: no mbuf/cluster\n", __func__); 3565 sc->sc_stats.ast_rx_nombuf++; 3566 return ENOMEM; 3567 } 3568 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3569 3570 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 3571 bf->bf_dmamap, m, 3572 bf->bf_segs, 1, &bf->bf_nseg, 3573 BUS_DMA_NOWAIT); 3574 if (error != 0) { 3575 DPRINTF(sc, ATH_DEBUG_ANY, 3576 "%s: bus_dmamap_load_mbuf_segment failed; error %d\n", 3577 __func__, error); 3578 sc->sc_stats.ast_rx_busdma++; 3579 m_freem(m); 3580 return error; 3581 } 3582 KASSERT(bf->bf_nseg == 1, 3583 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3584 bf->bf_m = m; 3585 } 3586 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3587 3588 /* 3589 * Setup descriptors. For receive we always terminate 3590 * the descriptor list with a self-linked entry so we'll 3591 * not get overrun under high load (as can happen with a 3592 * 5212 when ANI processing enables PHY error frames). 3593 * 3594 * To insure the last descriptor is self-linked we create 3595 * each descriptor as self-linked and add it to the end. As 3596 * each additional descriptor is added the previous self-linked 3597 * entry is ``fixed'' naturally. This should be safe even 3598 * if DMA is happening. When processing RX interrupts we 3599 * never remove/process the last, self-linked, entry on the 3600 * descriptor list. This insures the hardware always has 3601 * someplace to write a new frame. 3602 */ 3603 ds = bf->bf_desc; 3604 ds->ds_link = bf->bf_daddr; /* link to self */ 3605 ds->ds_data = bf->bf_segs[0].ds_addr; 3606 ath_hal_setuprxdesc(ah, ds 3607 , m->m_len /* buffer size */ 3608 , 0 3609 ); 3610 3611 if (sc->sc_rxlink != NULL) 3612 *sc->sc_rxlink = bf->bf_daddr; 3613 sc->sc_rxlink = &ds->ds_link; 3614 return 0; 3615 } 3616 3617 /* 3618 * Extend 15-bit time stamp from rx descriptor to 3619 * a full 64-bit TSF using the specified TSF. 3620 */ 3621 static __inline u_int64_t 3622 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3623 { 3624 if ((tsf & 0x7fff) < rstamp) 3625 tsf -= 0x8000; 3626 return ((tsf &~ 0x7fff) | rstamp); 3627 } 3628 3629 /* 3630 * Intercept management frames to collect beacon rssi data 3631 * and to do ibss merges. 3632 */ 3633 static void 3634 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3635 int subtype, int rssi, int nf) 3636 { 3637 struct ieee80211vap *vap = ni->ni_vap; 3638 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3639 3640 /* 3641 * Call up first so subsequent work can use information 3642 * potentially stored in the node (e.g. for ibss merge). 3643 */ 3644 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3645 switch (subtype) { 3646 case IEEE80211_FC0_SUBTYPE_BEACON: 3647 /* update rssi statistics for use by the hal */ 3648 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3649 if (sc->sc_syncbeacon && 3650 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3651 /* 3652 * Resync beacon timers using the tsf of the beacon 3653 * frame we just received. 3654 */ 3655 ath_beacon_config(sc, vap); 3656 } 3657 /* fall thru... */ 3658 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3659 if (vap->iv_opmode == IEEE80211_M_IBSS && 3660 vap->iv_state == IEEE80211_S_RUN) { 3661 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3662 u_int64_t tsf = ath_extend_tsf(rstamp, 3663 ath_hal_gettsf64(sc->sc_ah)); 3664 /* 3665 * Handle ibss merge as needed; check the tsf on the 3666 * frame before attempting the merge. The 802.11 spec 3667 * says the station should change it's bssid to match 3668 * the oldest station with the same ssid, where oldest 3669 * is determined by the tsf. Note that hardware 3670 * reconfiguration happens through callback to 3671 * ath_newstate as the state machine will go from 3672 * RUN -> RUN when this happens. 3673 */ 3674 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3675 DPRINTF(sc, ATH_DEBUG_STATE, 3676 "ibss merge, rstamp %u tsf %ju " 3677 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3678 (uintmax_t)ni->ni_tstamp.tsf); 3679 (void) ieee80211_ibss_merge(ni); 3680 } 3681 } 3682 break; 3683 } 3684 } 3685 3686 /* 3687 * Set the default antenna. 3688 */ 3689 static void 3690 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3691 { 3692 struct ath_hal *ah = sc->sc_ah; 3693 3694 /* XXX block beacon interrupts */ 3695 ath_hal_setdefantenna(ah, antenna); 3696 if (sc->sc_defant != antenna) 3697 sc->sc_stats.ast_ant_defswitch++; 3698 sc->sc_defant = antenna; 3699 sc->sc_rxotherant = 0; 3700 } 3701 3702 static void 3703 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3704 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3705 { 3706 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3707 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3708 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3709 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3710 struct ath_softc *sc = ifp->if_softc; 3711 const HAL_RATE_TABLE *rt; 3712 uint8_t rix; 3713 3714 rt = sc->sc_currates; 3715 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3716 rix = rt->rateCodeToIndex[rs->rs_rate]; 3717 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3718 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3719 #ifdef AH_SUPPORT_AR5416 3720 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3721 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3722 struct ieee80211com *ic = ifp->if_l2com; 3723 3724 if ((rs->rs_flags & HAL_RX_2040) == 0) 3725 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3726 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3727 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3728 else 3729 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3730 if ((rs->rs_flags & HAL_RX_GI) == 0) 3731 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3732 } 3733 #endif 3734 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3735 if (rs->rs_status & HAL_RXERR_CRC) 3736 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3737 /* XXX propagate other error flags from descriptor */ 3738 sc->sc_rx_th.wr_antnoise = nf; 3739 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3740 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3741 #undef CHAN_HT 3742 #undef CHAN_HT20 3743 #undef CHAN_HT40U 3744 #undef CHAN_HT40D 3745 } 3746 3747 static void 3748 ath_handle_micerror(struct ieee80211com *ic, 3749 struct ieee80211_frame *wh, int keyix) 3750 { 3751 struct ieee80211_node *ni; 3752 3753 /* XXX recheck MIC to deal w/ chips that lie */ 3754 /* XXX discard MIC errors on !data frames */ 3755 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3756 if (ni != NULL) { 3757 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3758 ieee80211_free_node(ni); 3759 } 3760 } 3761 3762 static void 3763 ath_rx_task(void *arg, int npending) 3764 { 3765 #define PA2DESC(_sc, _pa) \ 3766 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3767 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3768 struct ath_softc *sc = arg; 3769 struct ath_buf *bf; 3770 struct ifnet *ifp; 3771 struct ieee80211com *ic; 3772 struct ath_hal *ah; 3773 struct ath_desc *ds; 3774 struct ath_rx_status *rs; 3775 struct mbuf *m; 3776 struct ieee80211_node *ni; 3777 int len, type, ngood; 3778 u_int phyerr; 3779 HAL_STATUS status; 3780 int16_t nf; 3781 u_int64_t tsf; 3782 3783 wlan_serialize_enter(); 3784 ifp = sc->sc_ifp; 3785 ic = ifp->if_l2com; 3786 ah = sc->sc_ah; 3787 3788 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3789 ngood = 0; 3790 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3791 sc->sc_stats.ast_rx_noise = nf; 3792 tsf = ath_hal_gettsf64(ah); 3793 do { 3794 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3795 if (bf == NULL) { /* NB: shouldn't happen */ 3796 if_printf(ifp, "%s: no buffer!\n", __func__); 3797 break; 3798 } 3799 m = bf->bf_m; 3800 if (m == NULL) { /* NB: shouldn't happen */ 3801 /* 3802 * If mbuf allocation failed previously there 3803 * will be no mbuf; try again to re-populate it. 3804 */ 3805 /* XXX make debug msg */ 3806 if_printf(ifp, "%s: no mbuf!\n", __func__); 3807 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3808 goto rx_next; 3809 } 3810 ds = bf->bf_desc; 3811 if (ds->ds_link == bf->bf_daddr) { 3812 /* NB: never process the self-linked entry at the end */ 3813 break; 3814 } 3815 /* XXX sync descriptor memory */ 3816 /* 3817 * Must provide the virtual address of the current 3818 * descriptor, the physical address, and the virtual 3819 * address of the next descriptor in the h/w chain. 3820 * This allows the HAL to look ahead to see if the 3821 * hardware is done with a descriptor by checking the 3822 * done bit in the following descriptor and the address 3823 * of the current descriptor the DMA engine is working 3824 * on. All this is necessary because of our use of 3825 * a self-linked list to avoid rx overruns. 3826 */ 3827 rs = &bf->bf_status.ds_rxstat; 3828 status = ath_hal_rxprocdesc(ah, ds, 3829 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3830 #ifdef ATH_DEBUG 3831 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3832 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3833 #endif 3834 if (status == HAL_EINPROGRESS) 3835 break; 3836 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3837 if (rs->rs_status != 0) { 3838 if (rs->rs_status & HAL_RXERR_CRC) 3839 sc->sc_stats.ast_rx_crcerr++; 3840 if (rs->rs_status & HAL_RXERR_FIFO) 3841 sc->sc_stats.ast_rx_fifoerr++; 3842 if (rs->rs_status & HAL_RXERR_PHY) { 3843 sc->sc_stats.ast_rx_phyerr++; 3844 phyerr = rs->rs_phyerr & 0x1f; 3845 sc->sc_stats.ast_rx_phy[phyerr]++; 3846 goto rx_error; /* NB: don't count in ierrors */ 3847 } 3848 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3849 /* 3850 * Decrypt error. If the error occurred 3851 * because there was no hardware key, then 3852 * let the frame through so the upper layers 3853 * can process it. This is necessary for 5210 3854 * parts which have no way to setup a ``clear'' 3855 * key cache entry. 3856 * 3857 * XXX do key cache faulting 3858 */ 3859 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3860 goto rx_accept; 3861 sc->sc_stats.ast_rx_badcrypt++; 3862 } 3863 if (rs->rs_status & HAL_RXERR_MIC) { 3864 sc->sc_stats.ast_rx_badmic++; 3865 /* 3866 * Do minimal work required to hand off 3867 * the 802.11 header for notification. 3868 */ 3869 /* XXX frag's and qos frames */ 3870 len = rs->rs_datalen; 3871 if (len >= sizeof (struct ieee80211_frame)) { 3872 bus_dmamap_sync(sc->sc_dmat, 3873 bf->bf_dmamap, 3874 BUS_DMASYNC_POSTREAD); 3875 ath_handle_micerror(ic, 3876 mtod(m, struct ieee80211_frame *), 3877 sc->sc_splitmic ? 3878 rs->rs_keyix-32 : rs->rs_keyix); 3879 } 3880 } 3881 ifp->if_ierrors++; 3882 rx_error: 3883 /* 3884 * Cleanup any pending partial frame. 3885 */ 3886 if (sc->sc_rxpending != NULL) { 3887 m_freem(sc->sc_rxpending); 3888 sc->sc_rxpending = NULL; 3889 } 3890 /* 3891 * When a tap is present pass error frames 3892 * that have been requested. By default we 3893 * pass decrypt+mic errors but others may be 3894 * interesting (e.g. crc). 3895 */ 3896 if (ieee80211_radiotap_active(ic) && 3897 (rs->rs_status & sc->sc_monpass)) { 3898 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3899 BUS_DMASYNC_POSTREAD); 3900 /* NB: bpf needs the mbuf length setup */ 3901 len = rs->rs_datalen; 3902 m->m_pkthdr.len = m->m_len = len; 3903 ath_rx_tap(ifp, m, rs, tsf, nf); 3904 ieee80211_radiotap_rx_all(ic, m); 3905 } 3906 /* XXX pass MIC errors up for s/w reclaculation */ 3907 goto rx_next; 3908 } 3909 rx_accept: 3910 /* 3911 * Sync and unmap the frame. At this point we're 3912 * committed to passing the mbuf somewhere so clear 3913 * bf_m; this means a new mbuf must be allocated 3914 * when the rx descriptor is setup again to receive 3915 * another frame. 3916 */ 3917 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3918 BUS_DMASYNC_POSTREAD); 3919 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3920 bf->bf_m = NULL; 3921 3922 len = rs->rs_datalen; 3923 m->m_len = len; 3924 3925 if (rs->rs_more) { 3926 /* 3927 * Frame spans multiple descriptors; save 3928 * it for the next completed descriptor, it 3929 * will be used to construct a jumbogram. 3930 */ 3931 if (sc->sc_rxpending != NULL) { 3932 /* NB: max frame size is currently 2 clusters */ 3933 sc->sc_stats.ast_rx_toobig++; 3934 m_freem(sc->sc_rxpending); 3935 } 3936 m->m_pkthdr.rcvif = ifp; 3937 m->m_pkthdr.len = len; 3938 sc->sc_rxpending = m; 3939 goto rx_next; 3940 } else if (sc->sc_rxpending != NULL) { 3941 /* 3942 * This is the second part of a jumbogram, 3943 * chain it to the first mbuf, adjust the 3944 * frame length, and clear the rxpending state. 3945 */ 3946 sc->sc_rxpending->m_next = m; 3947 sc->sc_rxpending->m_pkthdr.len += len; 3948 m = sc->sc_rxpending; 3949 sc->sc_rxpending = NULL; 3950 } else { 3951 /* 3952 * Normal single-descriptor receive; setup 3953 * the rcvif and packet length. 3954 */ 3955 m->m_pkthdr.rcvif = ifp; 3956 m->m_pkthdr.len = len; 3957 } 3958 3959 ifp->if_ipackets++; 3960 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3961 3962 /* 3963 * Populate the rx status block. When there are bpf 3964 * listeners we do the additional work to provide 3965 * complete status. Otherwise we fill in only the 3966 * material required by ieee80211_input. Note that 3967 * noise setting is filled in above. 3968 */ 3969 if (ieee80211_radiotap_active(ic)) 3970 ath_rx_tap(ifp, m, rs, tsf, nf); 3971 3972 /* 3973 * From this point on we assume the frame is at least 3974 * as large as ieee80211_frame_min; verify that. 3975 */ 3976 if (len < IEEE80211_MIN_LEN) { 3977 if (!ieee80211_radiotap_active(ic)) { 3978 DPRINTF(sc, ATH_DEBUG_RECV, 3979 "%s: short packet %d\n", __func__, len); 3980 sc->sc_stats.ast_rx_tooshort++; 3981 } else { 3982 /* NB: in particular this captures ack's */ 3983 ieee80211_radiotap_rx_all(ic, m); 3984 } 3985 m_freem(m); 3986 goto rx_next; 3987 } 3988 3989 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3990 const HAL_RATE_TABLE *rt = sc->sc_currates; 3991 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 3992 3993 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 3994 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 3995 } 3996 3997 m_adj(m, -IEEE80211_CRC_LEN); 3998 3999 /* 4000 * Locate the node for sender, track state, and then 4001 * pass the (referenced) node up to the 802.11 layer 4002 * for its use. 4003 */ 4004 ni = ieee80211_find_rxnode_withkey(ic, 4005 mtod(m, const struct ieee80211_frame_min *), 4006 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4007 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4008 if (ni != NULL) { 4009 /* 4010 * Sending station is known, dispatch directly. 4011 */ 4012 sc->sc_lastrs = rs; 4013 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 4014 ieee80211_free_node(ni); 4015 /* 4016 * Arrange to update the last rx timestamp only for 4017 * frames from our ap when operating in station mode. 4018 * This assumes the rx key is always setup when 4019 * associated. 4020 */ 4021 if (ic->ic_opmode == IEEE80211_M_STA && 4022 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4023 ngood++; 4024 } else { 4025 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 4026 } 4027 /* 4028 * Track rx rssi and do any rx antenna management. 4029 */ 4030 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4031 if (sc->sc_diversity) { 4032 /* 4033 * When using fast diversity, change the default rx 4034 * antenna if diversity chooses the other antenna 3 4035 * times in a row. 4036 */ 4037 if (sc->sc_defant != rs->rs_antenna) { 4038 if (++sc->sc_rxotherant >= 3) 4039 ath_setdefantenna(sc, rs->rs_antenna); 4040 } else 4041 sc->sc_rxotherant = 0; 4042 } 4043 if (sc->sc_softled) { 4044 /* 4045 * Blink for any data frame. Otherwise do a 4046 * heartbeat-style blink when idle. The latter 4047 * is mainly for station mode where we depend on 4048 * periodic beacon frames to trigger the poll event. 4049 */ 4050 if (type == IEEE80211_FC0_TYPE_DATA) { 4051 const HAL_RATE_TABLE *rt = sc->sc_currates; 4052 ath_led_event(sc, 4053 rt->rateCodeToIndex[rs->rs_rate]); 4054 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4055 ath_led_event(sc, 0); 4056 } 4057 rx_next: 4058 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4059 } while (ath_rxbuf_init(sc, bf) == 0); 4060 4061 /* rx signal state monitoring */ 4062 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4063 if (ngood) 4064 sc->sc_lastrx = tsf; 4065 4066 if ((ifp->if_flags & IFF_OACTIVE) == 0) { 4067 #ifdef IEEE80211_SUPPORT_SUPERG 4068 ieee80211_ff_age_all(ic, 100); 4069 #endif 4070 if (!ifq_is_empty(&ifp->if_snd)) 4071 ath_start(ifp); 4072 } 4073 wlan_serialize_exit(); 4074 #undef PA2DESC 4075 } 4076 4077 static void 4078 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4079 { 4080 txq->axq_qnum = qnum; 4081 txq->axq_ac = 0; 4082 txq->axq_depth = 0; 4083 txq->axq_intrcnt = 0; 4084 txq->axq_link = NULL; 4085 STAILQ_INIT(&txq->axq_q); 4086 } 4087 4088 /* 4089 * Setup a h/w transmit queue. 4090 */ 4091 static struct ath_txq * 4092 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4093 { 4094 struct ath_hal *ah = sc->sc_ah; 4095 HAL_TXQ_INFO qi; 4096 int qnum; 4097 4098 memset(&qi, 0, sizeof(qi)); 4099 qi.tqi_subtype = subtype; 4100 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4101 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4102 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4103 /* 4104 * Enable interrupts only for EOL and DESC conditions. 4105 * We mark tx descriptors to receive a DESC interrupt 4106 * when a tx queue gets deep; otherwise waiting for the 4107 * EOL to reap descriptors. Note that this is done to 4108 * reduce interrupt load and this only defers reaping 4109 * descriptors, never transmitting frames. Aside from 4110 * reducing interrupts this also permits more concurrency. 4111 * The only potential downside is if the tx queue backs 4112 * up in which case the top half of the kernel may backup 4113 * due to a lack of tx descriptors. 4114 */ 4115 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4116 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4117 if (qnum == -1) { 4118 /* 4119 * NB: don't print a message, this happens 4120 * normally on parts with too few tx queues 4121 */ 4122 return NULL; 4123 } 4124 if (qnum >= NELEM(sc->sc_txq)) { 4125 device_printf(sc->sc_dev, 4126 "hal qnum %u out of range, max %zu!\n", 4127 qnum, NELEM(sc->sc_txq)); 4128 ath_hal_releasetxqueue(ah, qnum); 4129 return NULL; 4130 } 4131 if (!ATH_TXQ_SETUP(sc, qnum)) { 4132 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4133 sc->sc_txqsetup |= 1<<qnum; 4134 } 4135 return &sc->sc_txq[qnum]; 4136 } 4137 4138 /* 4139 * Setup a hardware data transmit queue for the specified 4140 * access control. The hal may not support all requested 4141 * queues in which case it will return a reference to a 4142 * previously setup queue. We record the mapping from ac's 4143 * to h/w queues for use by ath_tx_start and also track 4144 * the set of h/w queues being used to optimize work in the 4145 * transmit interrupt handler and related routines. 4146 */ 4147 static int 4148 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4149 { 4150 struct ath_txq *txq; 4151 4152 if (ac >= NELEM(sc->sc_ac2q)) { 4153 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4154 ac, NELEM(sc->sc_ac2q)); 4155 return 0; 4156 } 4157 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4158 if (txq != NULL) { 4159 txq->axq_ac = ac; 4160 sc->sc_ac2q[ac] = txq; 4161 return 1; 4162 } else 4163 return 0; 4164 } 4165 4166 /* 4167 * Update WME parameters for a transmit queue. 4168 */ 4169 static int 4170 ath_txq_update(struct ath_softc *sc, int ac) 4171 { 4172 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4173 #define ATH_TXOP_TO_US(v) (v<<5) 4174 struct ifnet *ifp = sc->sc_ifp; 4175 struct ieee80211com *ic = ifp->if_l2com; 4176 struct ath_txq *txq = sc->sc_ac2q[ac]; 4177 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4178 struct ath_hal *ah = sc->sc_ah; 4179 HAL_TXQ_INFO qi; 4180 4181 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4182 #ifdef IEEE80211_SUPPORT_TDMA 4183 if (sc->sc_tdma) { 4184 /* 4185 * AIFS is zero so there's no pre-transmit wait. The 4186 * burst time defines the slot duration and is configured 4187 * through net80211. The QCU is setup to not do post-xmit 4188 * back off, lockout all lower-priority QCU's, and fire 4189 * off the DMA beacon alert timer which is setup based 4190 * on the slot configuration. 4191 */ 4192 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4193 | HAL_TXQ_TXERRINT_ENABLE 4194 | HAL_TXQ_TXURNINT_ENABLE 4195 | HAL_TXQ_TXEOLINT_ENABLE 4196 | HAL_TXQ_DBA_GATED 4197 | HAL_TXQ_BACKOFF_DISABLE 4198 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4199 ; 4200 qi.tqi_aifs = 0; 4201 /* XXX +dbaprep? */ 4202 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4203 qi.tqi_burstTime = qi.tqi_readyTime; 4204 } else { 4205 #endif 4206 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4207 | HAL_TXQ_TXERRINT_ENABLE 4208 | HAL_TXQ_TXDESCINT_ENABLE 4209 | HAL_TXQ_TXURNINT_ENABLE 4210 ; 4211 qi.tqi_aifs = wmep->wmep_aifsn; 4212 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4213 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4214 qi.tqi_readyTime = 0; 4215 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4216 #ifdef IEEE80211_SUPPORT_TDMA 4217 } 4218 #endif 4219 4220 DPRINTF(sc, ATH_DEBUG_RESET, 4221 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4222 __func__, txq->axq_qnum, qi.tqi_qflags, 4223 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4224 4225 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4226 if_printf(ifp, "unable to update hardware queue " 4227 "parameters for %s traffic!\n", 4228 ieee80211_wme_acnames[ac]); 4229 return 0; 4230 } else { 4231 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4232 return 1; 4233 } 4234 #undef ATH_TXOP_TO_US 4235 #undef ATH_EXPONENT_TO_VALUE 4236 } 4237 4238 /* 4239 * Callback from the 802.11 layer to update WME parameters. 4240 */ 4241 static int 4242 ath_wme_update(struct ieee80211com *ic) 4243 { 4244 struct ath_softc *sc = ic->ic_ifp->if_softc; 4245 4246 return !ath_txq_update(sc, WME_AC_BE) || 4247 !ath_txq_update(sc, WME_AC_BK) || 4248 !ath_txq_update(sc, WME_AC_VI) || 4249 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4250 } 4251 4252 /* 4253 * Reclaim resources for a setup queue. 4254 */ 4255 static void 4256 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4257 { 4258 4259 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4260 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4261 } 4262 4263 /* 4264 * Reclaim all tx queue resources. 4265 */ 4266 static void 4267 ath_tx_cleanup(struct ath_softc *sc) 4268 { 4269 int i; 4270 4271 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4272 if (ATH_TXQ_SETUP(sc, i)) 4273 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4274 } 4275 4276 /* 4277 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4278 * using the current rates in sc_rixmap. 4279 */ 4280 static __inline int 4281 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4282 { 4283 int rix = sc->sc_rixmap[rate]; 4284 /* NB: return lowest rix for invalid rate */ 4285 return (rix == 0xff ? 0 : rix); 4286 } 4287 4288 /* 4289 * Reclaim mbuf resources. For fragmented frames we 4290 * need to claim each frag chained with m_nextpkt. 4291 */ 4292 static void 4293 ath_freetx(struct mbuf *m) 4294 { 4295 struct mbuf *next; 4296 4297 do { 4298 next = m->m_nextpkt; 4299 m->m_nextpkt = NULL; 4300 m_freem(m); 4301 } while ((m = next) != NULL); 4302 } 4303 4304 static int 4305 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4306 { 4307 int error; 4308 4309 /* 4310 * 4311 * Load the DMA map so any coalescing is done. This 4312 * also calculates the number of descriptors we need. 4313 */ 4314 error = bus_dmamap_load_mbuf_defrag(sc->sc_dmat, bf->bf_dmamap, &m0, 4315 bf->bf_segs, ATH_TXDESC, 4316 &bf->bf_nseg, BUS_DMA_NOWAIT); 4317 if (error != 0) { 4318 sc->sc_stats.ast_tx_busdma++; 4319 ath_freetx(m0); 4320 return error; 4321 } 4322 4323 /* 4324 * Discard null packets. 4325 */ 4326 if (bf->bf_nseg == 0) { /* null packet, discard */ 4327 sc->sc_stats.ast_tx_nodata++; 4328 ath_freetx(m0); 4329 return EIO; 4330 } 4331 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4332 __func__, m0, m0->m_pkthdr.len); 4333 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4334 bf->bf_m = m0; 4335 4336 return 0; 4337 } 4338 4339 static void 4340 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4341 { 4342 struct ath_hal *ah = sc->sc_ah; 4343 struct ath_desc *ds, *ds0; 4344 int i; 4345 4346 /* 4347 * Fillin the remainder of the descriptor info. 4348 */ 4349 ds0 = ds = bf->bf_desc; 4350 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4351 ds->ds_data = bf->bf_segs[i].ds_addr; 4352 if (i == bf->bf_nseg - 1) 4353 ds->ds_link = 0; 4354 else 4355 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4356 ath_hal_filltxdesc(ah, ds 4357 , bf->bf_segs[i].ds_len /* segment length */ 4358 , i == 0 /* first segment */ 4359 , i == bf->bf_nseg - 1 /* last segment */ 4360 , ds0 /* first descriptor */ 4361 ); 4362 DPRINTF(sc, ATH_DEBUG_XMIT, 4363 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4364 __func__, i, ds->ds_link, ds->ds_data, 4365 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4366 } 4367 /* 4368 * Insert the frame on the outbound list and pass it on 4369 * to the hardware. Multicast frames buffered for power 4370 * save stations and transmit from the CAB queue are stored 4371 * on a s/w only queue and loaded on to the CAB queue in 4372 * the SWBA handler since frames only go out on DTIM and 4373 * to avoid possible races. 4374 */ 4375 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4376 ("busy status 0x%x", bf->bf_flags)); 4377 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4378 #ifdef IEEE80211_SUPPORT_TDMA 4379 /* 4380 * Supporting transmit dma. If the queue is busy it is 4381 * impossible to determine if we've won the race against 4382 * the chipset checking the link field or not, so we don't 4383 * try. Instead we let the TX interrupt detect the case 4384 * and restart the transmitter. 4385 * 4386 * If the queue is not busy we can start things rolling 4387 * right here. 4388 */ 4389 int qbusy; 4390 4391 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4392 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4393 4394 if (qbusy == 0) { 4395 if (txq->axq_link != NULL) { 4396 /* 4397 * We had already started one previously but 4398 * not yet processed the TX interrupt. Don't 4399 * try to race a restart because we do not 4400 * know where it stopped, let the TX interrupt 4401 * restart us when it figures out where we 4402 * stopped. 4403 */ 4404 cpu_sfence(); 4405 *txq->axq_link = bf->bf_daddr; 4406 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4407 } else { 4408 /* 4409 * We are first in line, we can safely start 4410 * at this address. 4411 */ 4412 cpu_sfence(); 4413 ath_hal_puttxbuf(ah, txq->axq_qnum, 4414 bf->bf_daddr); 4415 } 4416 } else { 4417 /* 4418 * The queue is busy, go ahead and link us in but 4419 * do not try to start/restart the tx. We just 4420 * don't know whether it will pick up our link 4421 * or not and we don't want to double-xmit. 4422 */ 4423 if (txq->axq_link != NULL) { 4424 cpu_sfence(); 4425 *txq->axq_link = bf->bf_daddr; 4426 } 4427 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4428 } 4429 #if 0 4430 ath_hal_puttxbuf(ah, txq->axq_qnum, 4431 STAILQ_FIRST(&txq->axq_q)->bf_daddr); 4432 #endif 4433 #else 4434 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4435 if (txq->axq_link == NULL) { 4436 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4437 DPRINTF(sc, ATH_DEBUG_XMIT, 4438 "%s: TXDP[%u] = %p (%p) depth %d\n", 4439 __func__, txq->axq_qnum, 4440 (caddr_t)bf->bf_daddr, bf->bf_desc, 4441 txq->axq_depth); 4442 } else { 4443 *txq->axq_link = bf->bf_daddr; 4444 DPRINTF(sc, ATH_DEBUG_XMIT, 4445 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4446 txq->axq_qnum, txq->axq_link, 4447 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4448 } 4449 #endif /* IEEE80211_SUPPORT_TDMA */ 4450 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4451 ath_hal_txstart(ah, txq->axq_qnum); 4452 } else { 4453 if (txq->axq_link != NULL) { 4454 struct ath_buf *last = ATH_TXQ_LAST(txq); 4455 struct ieee80211_frame *wh; 4456 4457 /* mark previous frame */ 4458 wh = mtod(last->bf_m, struct ieee80211_frame *); 4459 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4460 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4461 BUS_DMASYNC_PREWRITE); 4462 4463 /* link descriptor */ 4464 *txq->axq_link = bf->bf_daddr; 4465 } 4466 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4467 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4468 } 4469 } 4470 4471 static int 4472 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4473 struct mbuf *m0) 4474 { 4475 struct ieee80211vap *vap = ni->ni_vap; 4476 struct ath_vap *avp = ATH_VAP(vap); 4477 struct ath_hal *ah = sc->sc_ah; 4478 struct ifnet *ifp = sc->sc_ifp; 4479 struct ieee80211com *ic = ifp->if_l2com; 4480 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4481 int error, iswep, ismcast, isfrag, ismrr; 4482 int keyix, hdrlen, pktlen, try0; 4483 u_int8_t rix, txrate, ctsrate; 4484 u_int8_t cix = 0xff; /* NB: silence compiler */ 4485 struct ath_desc *ds; 4486 struct ath_txq *txq; 4487 struct ieee80211_frame *wh; 4488 u_int subtype, flags, ctsduration; 4489 HAL_PKT_TYPE atype; 4490 const HAL_RATE_TABLE *rt; 4491 HAL_BOOL shortPreamble; 4492 struct ath_node *an; 4493 u_int pri; 4494 4495 wh = mtod(m0, struct ieee80211_frame *); 4496 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4497 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4498 isfrag = m0->m_flags & M_FRAG; 4499 hdrlen = ieee80211_anyhdrsize(wh); 4500 /* 4501 * Packet length must not include any 4502 * pad bytes; deduct them here. 4503 */ 4504 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4505 4506 if (iswep) { 4507 const struct ieee80211_cipher *cip; 4508 struct ieee80211_key *k; 4509 4510 /* 4511 * Construct the 802.11 header+trailer for an encrypted 4512 * frame. The only reason this can fail is because of an 4513 * unknown or unsupported cipher/key type. 4514 */ 4515 k = ieee80211_crypto_encap(ni, m0); 4516 if (k == NULL) { 4517 /* 4518 * This can happen when the key is yanked after the 4519 * frame was queued. Just discard the frame; the 4520 * 802.11 layer counts failures and provides 4521 * debugging/diagnostics. 4522 */ 4523 ath_freetx(m0); 4524 return EIO; 4525 } 4526 /* 4527 * Adjust the packet + header lengths for the crypto 4528 * additions and calculate the h/w key index. When 4529 * a s/w mic is done the frame will have had any mic 4530 * added to it prior to entry so m0->m_pkthdr.len will 4531 * account for it. Otherwise we need to add it to the 4532 * packet length. 4533 */ 4534 cip = k->wk_cipher; 4535 hdrlen += cip->ic_header; 4536 pktlen += cip->ic_header + cip->ic_trailer; 4537 /* NB: frags always have any TKIP MIC done in s/w */ 4538 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4539 pktlen += cip->ic_miclen; 4540 keyix = k->wk_keyix; 4541 4542 /* packet header may have moved, reset our local pointer */ 4543 wh = mtod(m0, struct ieee80211_frame *); 4544 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4545 /* 4546 * Use station key cache slot, if assigned. 4547 */ 4548 keyix = ni->ni_ucastkey.wk_keyix; 4549 if (keyix == IEEE80211_KEYIX_NONE) 4550 keyix = HAL_TXKEYIX_INVALID; 4551 } else 4552 keyix = HAL_TXKEYIX_INVALID; 4553 4554 pktlen += IEEE80211_CRC_LEN; 4555 4556 /* 4557 * Load the DMA map so any coalescing is done. This 4558 * also calculates the number of descriptors we need. 4559 */ 4560 error = ath_tx_dmasetup(sc, bf, m0); 4561 if (error != 0) { 4562 return error; 4563 } 4564 bf->bf_node = ni; /* NB: held reference */ 4565 m0 = bf->bf_m; /* NB: may have changed */ 4566 wh = mtod(m0, struct ieee80211_frame *); 4567 4568 /* setup descriptors */ 4569 ds = bf->bf_desc; 4570 rt = sc->sc_currates; 4571 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4572 4573 /* 4574 * NB: the 802.11 layer marks whether or not we should 4575 * use short preamble based on the current mode and 4576 * negotiated parameters. 4577 */ 4578 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4579 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4580 shortPreamble = AH_TRUE; 4581 sc->sc_stats.ast_tx_shortpre++; 4582 } else { 4583 shortPreamble = AH_FALSE; 4584 } 4585 4586 an = ATH_NODE(ni); 4587 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4588 ismrr = 0; /* default no multi-rate retry*/ 4589 pri = M_WME_GETAC(m0); /* honor classification */ 4590 /* XXX use txparams instead of fixed values */ 4591 /* 4592 * Calculate Atheros packet type from IEEE80211 packet header, 4593 * setup for rate calculations, and select h/w transmit queue. 4594 */ 4595 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4596 case IEEE80211_FC0_TYPE_MGT: 4597 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4598 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4599 atype = HAL_PKT_TYPE_BEACON; 4600 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4601 atype = HAL_PKT_TYPE_PROBE_RESP; 4602 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4603 atype = HAL_PKT_TYPE_ATIM; 4604 else 4605 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4606 rix = an->an_mgmtrix; 4607 txrate = rt->info[rix].rateCode; 4608 if (shortPreamble) 4609 txrate |= rt->info[rix].shortPreamble; 4610 try0 = ATH_TXMGTTRY; 4611 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4612 break; 4613 case IEEE80211_FC0_TYPE_CTL: 4614 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4615 rix = an->an_mgmtrix; 4616 txrate = rt->info[rix].rateCode; 4617 if (shortPreamble) 4618 txrate |= rt->info[rix].shortPreamble; 4619 try0 = ATH_TXMGTTRY; 4620 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4621 break; 4622 case IEEE80211_FC0_TYPE_DATA: 4623 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4624 /* 4625 * Data frames: multicast frames go out at a fixed rate, 4626 * EAPOL frames use the mgmt frame rate; otherwise consult 4627 * the rate control module for the rate to use. 4628 */ 4629 if (ismcast) { 4630 rix = an->an_mcastrix; 4631 txrate = rt->info[rix].rateCode; 4632 if (shortPreamble) 4633 txrate |= rt->info[rix].shortPreamble; 4634 try0 = 1; 4635 } else if (m0->m_flags & M_EAPOL) { 4636 /* XXX? maybe always use long preamble? */ 4637 rix = an->an_mgmtrix; 4638 txrate = rt->info[rix].rateCode; 4639 if (shortPreamble) 4640 txrate |= rt->info[rix].shortPreamble; 4641 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4642 } else { 4643 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4644 &rix, &try0, &txrate); 4645 sc->sc_txrix = rix; /* for LED blinking */ 4646 sc->sc_lastdatarix = rix; /* for fast frames */ 4647 if (try0 != ATH_TXMAXTRY) 4648 ismrr = 1; 4649 } 4650 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4651 flags |= HAL_TXDESC_NOACK; 4652 break; 4653 default: 4654 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4655 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4656 /* XXX statistic */ 4657 ath_freetx(m0); 4658 return EIO; 4659 } 4660 txq = sc->sc_ac2q[pri]; 4661 4662 /* 4663 * When servicing one or more stations in power-save mode 4664 * (or) if there is some mcast data waiting on the mcast 4665 * queue (to prevent out of order delivery) multicast 4666 * frames must be buffered until after the beacon. 4667 */ 4668 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4669 txq = &avp->av_mcastq; 4670 4671 /* 4672 * Calculate miscellaneous flags. 4673 */ 4674 if (ismcast) { 4675 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4676 } else if (pktlen > vap->iv_rtsthreshold && 4677 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4678 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4679 cix = rt->info[rix].controlRate; 4680 sc->sc_stats.ast_tx_rts++; 4681 } 4682 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4683 sc->sc_stats.ast_tx_noack++; 4684 #ifdef IEEE80211_SUPPORT_TDMA 4685 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 4686 DPRINTF(sc, ATH_DEBUG_TDMA, 4687 "%s: discard frame, ACK required w/ TDMA\n", __func__); 4688 sc->sc_stats.ast_tdma_ack++; 4689 ath_freetx(m0); 4690 return EIO; 4691 } 4692 #endif 4693 4694 /* 4695 * If 802.11g protection is enabled, determine whether 4696 * to use RTS/CTS or just CTS. Note that this is only 4697 * done for OFDM unicast frames. 4698 */ 4699 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4700 rt->info[rix].phy == IEEE80211_T_OFDM && 4701 (flags & HAL_TXDESC_NOACK) == 0) { 4702 /* XXX fragments must use CCK rates w/ protection */ 4703 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4704 flags |= HAL_TXDESC_RTSENA; 4705 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4706 flags |= HAL_TXDESC_CTSENA; 4707 if (isfrag) { 4708 /* 4709 * For frags it would be desirable to use the 4710 * highest CCK rate for RTS/CTS. But stations 4711 * farther away may detect it at a lower CCK rate 4712 * so use the configured protection rate instead 4713 * (for now). 4714 */ 4715 cix = rt->info[sc->sc_protrix].controlRate; 4716 } else 4717 cix = rt->info[sc->sc_protrix].controlRate; 4718 sc->sc_stats.ast_tx_protect++; 4719 } 4720 4721 /* 4722 * Calculate duration. This logically belongs in the 802.11 4723 * layer but it lacks sufficient information to calculate it. 4724 */ 4725 if ((flags & HAL_TXDESC_NOACK) == 0 && 4726 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4727 u_int16_t dur; 4728 if (shortPreamble) 4729 dur = rt->info[rix].spAckDuration; 4730 else 4731 dur = rt->info[rix].lpAckDuration; 4732 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4733 dur += dur; /* additional SIFS+ACK */ 4734 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4735 /* 4736 * Include the size of next fragment so NAV is 4737 * updated properly. The last fragment uses only 4738 * the ACK duration 4739 */ 4740 dur += ath_hal_computetxtime(ah, rt, 4741 m0->m_nextpkt->m_pkthdr.len, 4742 rix, shortPreamble); 4743 } 4744 if (isfrag) { 4745 /* 4746 * Force hardware to use computed duration for next 4747 * fragment by disabling multi-rate retry which updates 4748 * duration based on the multi-rate duration table. 4749 */ 4750 ismrr = 0; 4751 try0 = ATH_TXMGTTRY; /* XXX? */ 4752 } 4753 *(u_int16_t *)wh->i_dur = htole16(dur); 4754 } 4755 4756 /* 4757 * Calculate RTS/CTS rate and duration if needed. 4758 */ 4759 ctsduration = 0; 4760 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4761 /* 4762 * CTS transmit rate is derived from the transmit rate 4763 * by looking in the h/w rate table. We must also factor 4764 * in whether or not a short preamble is to be used. 4765 */ 4766 /* NB: cix is set above where RTS/CTS is enabled */ 4767 KASSERT(cix != 0xff, ("cix not setup")); 4768 ctsrate = rt->info[cix].rateCode; 4769 /* 4770 * Compute the transmit duration based on the frame 4771 * size and the size of an ACK frame. We call into the 4772 * HAL to do the computation since it depends on the 4773 * characteristics of the actual PHY being used. 4774 * 4775 * NB: CTS is assumed the same size as an ACK so we can 4776 * use the precalculated ACK durations. 4777 */ 4778 if (shortPreamble) { 4779 ctsrate |= rt->info[cix].shortPreamble; 4780 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4781 ctsduration += rt->info[cix].spAckDuration; 4782 ctsduration += ath_hal_computetxtime(ah, 4783 rt, pktlen, rix, AH_TRUE); 4784 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4785 ctsduration += rt->info[rix].spAckDuration; 4786 } else { 4787 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4788 ctsduration += rt->info[cix].lpAckDuration; 4789 ctsduration += ath_hal_computetxtime(ah, 4790 rt, pktlen, rix, AH_FALSE); 4791 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4792 ctsduration += rt->info[rix].lpAckDuration; 4793 } 4794 /* 4795 * Must disable multi-rate retry when using RTS/CTS. 4796 */ 4797 ismrr = 0; 4798 try0 = ATH_TXMGTTRY; /* XXX */ 4799 } else 4800 ctsrate = 0; 4801 4802 /* 4803 * At this point we are committed to sending the frame 4804 * and we don't need to look at m_nextpkt; clear it in 4805 * case this frame is part of frag chain. 4806 */ 4807 m0->m_nextpkt = NULL; 4808 4809 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4810 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 4811 sc->sc_hwmap[rix].ieeerate, -1); 4812 4813 if (ieee80211_radiotap_active_vap(vap)) { 4814 u_int64_t tsf = ath_hal_gettsf64(ah); 4815 4816 sc->sc_tx_th.wt_tsf = htole64(tsf); 4817 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 4818 if (iswep) 4819 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4820 if (isfrag) 4821 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4822 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 4823 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4824 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4825 4826 ieee80211_radiotap_tx(vap, m0); 4827 } 4828 4829 /* 4830 * Determine if a tx interrupt should be generated for 4831 * this descriptor. We take a tx interrupt to reap 4832 * descriptors when the h/w hits an EOL condition or 4833 * when the descriptor is specifically marked to generate 4834 * an interrupt. We periodically mark descriptors in this 4835 * way to insure timely replenishing of the supply needed 4836 * for sending frames. Defering interrupts reduces system 4837 * load and potentially allows more concurrent work to be 4838 * done but if done to aggressively can cause senders to 4839 * backup. 4840 * 4841 * NB: use >= to deal with sc_txintrperiod changing 4842 * dynamically through sysctl. 4843 */ 4844 if (flags & HAL_TXDESC_INTREQ) { 4845 txq->axq_intrcnt = 0; 4846 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4847 flags |= HAL_TXDESC_INTREQ; 4848 txq->axq_intrcnt = 0; 4849 } 4850 4851 /* 4852 * Formulate first tx descriptor with tx controls. 4853 */ 4854 /* XXX check return value? */ 4855 ath_hal_setuptxdesc(ah, ds 4856 , pktlen /* packet length */ 4857 , hdrlen /* header length */ 4858 , atype /* Atheros packet type */ 4859 , ni->ni_txpower /* txpower */ 4860 , txrate, try0 /* series 0 rate/tries */ 4861 , keyix /* key cache index */ 4862 , sc->sc_txantenna /* antenna mode */ 4863 , flags /* flags */ 4864 , ctsrate /* rts/cts rate */ 4865 , ctsduration /* rts/cts duration */ 4866 ); 4867 bf->bf_txflags = flags; 4868 /* 4869 * Setup the multi-rate retry state only when we're 4870 * going to use it. This assumes ath_hal_setuptxdesc 4871 * initializes the descriptors (so we don't have to) 4872 * when the hardware supports multi-rate retry and 4873 * we don't use it. 4874 */ 4875 if (ismrr) 4876 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4877 4878 ath_tx_handoff(sc, txq, bf); 4879 return 0; 4880 } 4881 4882 /* 4883 * Process completed xmit descriptors from the specified queue. 4884 */ 4885 static int 4886 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4887 { 4888 struct ath_hal *ah = sc->sc_ah; 4889 struct ifnet *ifp = sc->sc_ifp; 4890 struct ieee80211com *ic = ifp->if_l2com; 4891 struct ath_buf *bf, *last; 4892 struct ath_desc *ds, *ds0; 4893 struct ath_tx_status *ts; 4894 struct ieee80211_node *ni; 4895 struct ath_node *an; 4896 int sr, lr, pri, nacked; 4897 HAL_STATUS status; 4898 4899 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4900 __func__, txq->axq_qnum, 4901 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4902 txq->axq_link); 4903 nacked = 0; 4904 for (;;) { 4905 int qbusy; 4906 4907 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4908 bf = STAILQ_FIRST(&txq->axq_q); 4909 if (bf == NULL) 4910 break; 4911 ds0 = &bf->bf_desc[0]; 4912 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4913 ts = &bf->bf_status.ds_txstat; 4914 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4915 status = ath_hal_txprocdesc(ah, ds, ts); 4916 #ifdef ATH_DEBUG 4917 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4918 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4919 status == HAL_OK); 4920 #endif 4921 if (status == HAL_EINPROGRESS) { 4922 #ifdef IEEE80211_SUPPORT_TDMA 4923 /* 4924 * If not done and the queue is not busy then the 4925 * transmitter raced the hardware on the link field 4926 * and we have to restart it. 4927 */ 4928 if (!qbusy) { 4929 cpu_sfence(); 4930 ath_hal_puttxbuf(ah, txq->axq_qnum, 4931 bf->bf_daddr); 4932 ath_hal_txstart(ah, txq->axq_qnum); 4933 } 4934 #endif 4935 break; 4936 } 4937 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4938 #ifdef IEEE80211_SUPPORT_TDMA 4939 if (txq->axq_depth > 0) { 4940 /* 4941 * More frames follow. Mark the buffer busy 4942 * so it's not re-used while the hardware may 4943 * still re-read the link field in the descriptor. 4944 */ 4945 bf->bf_flags |= ATH_BUF_BUSY; 4946 } else 4947 #else 4948 if (txq->axq_depth == 0) 4949 #endif 4950 txq->axq_link = NULL; 4951 4952 ni = bf->bf_node; 4953 if (ni != NULL) { 4954 an = ATH_NODE(ni); 4955 if (ts->ts_status == 0) { 4956 u_int8_t txant = ts->ts_antenna; 4957 sc->sc_stats.ast_ant_tx[txant]++; 4958 sc->sc_ant_tx[txant]++; 4959 if (ts->ts_finaltsi != 0) 4960 sc->sc_stats.ast_tx_altrate++; 4961 pri = M_WME_GETAC(bf->bf_m); 4962 if (pri >= WME_AC_VO) 4963 ic->ic_wme.wme_hipri_traffic++; 4964 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4965 ni->ni_inact = ni->ni_inact_reload; 4966 } else { 4967 if (ts->ts_status & HAL_TXERR_XRETRY) 4968 sc->sc_stats.ast_tx_xretries++; 4969 if (ts->ts_status & HAL_TXERR_FIFO) 4970 sc->sc_stats.ast_tx_fifoerr++; 4971 if (ts->ts_status & HAL_TXERR_FILT) 4972 sc->sc_stats.ast_tx_filtered++; 4973 if (bf->bf_m->m_flags & M_FF) 4974 sc->sc_stats.ast_ff_txerr++; 4975 } 4976 sr = ts->ts_shortretry; 4977 lr = ts->ts_longretry; 4978 sc->sc_stats.ast_tx_shortretry += sr; 4979 sc->sc_stats.ast_tx_longretry += lr; 4980 /* 4981 * Hand the descriptor to the rate control algorithm. 4982 */ 4983 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4984 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4985 /* 4986 * If frame was ack'd update statistics, 4987 * including the last rx time used to 4988 * workaround phantom bmiss interrupts. 4989 */ 4990 if (ts->ts_status == 0) { 4991 nacked++; 4992 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4993 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4994 ts->ts_rssi); 4995 } 4996 ath_rate_tx_complete(sc, an, bf); 4997 } 4998 /* 4999 * Do any tx complete callback. Note this must 5000 * be done before releasing the node reference. 5001 */ 5002 if (bf->bf_m->m_flags & M_TXCB) 5003 ieee80211_process_callback(ni, bf->bf_m, 5004 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 5005 ts->ts_status : HAL_TXERR_XRETRY); 5006 ieee80211_free_node(ni); 5007 } 5008 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5009 BUS_DMASYNC_POSTWRITE); 5010 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5011 5012 m_freem(bf->bf_m); 5013 bf->bf_m = NULL; 5014 bf->bf_node = NULL; 5015 5016 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5017 if (last != NULL) 5018 last->bf_flags &= ~ATH_BUF_BUSY; 5019 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5020 } 5021 #ifdef IEEE80211_SUPPORT_SUPERG 5022 /* 5023 * Flush fast-frame staging queue when traffic slows. 5024 */ 5025 if (txq->axq_depth <= 1) 5026 ieee80211_ff_flush(ic, txq->axq_ac); 5027 #endif 5028 return nacked; 5029 } 5030 5031 static __inline int 5032 txqactive(struct ath_hal *ah, int qnum) 5033 { 5034 u_int32_t txqs = 1<<qnum; 5035 ath_hal_gettxintrtxqs(ah, &txqs); 5036 return (txqs & (1<<qnum)); 5037 } 5038 5039 /* 5040 * Deferred processing of transmit interrupt; special-cased 5041 * for a single hardware transmit queue (e.g. 5210 and 5211). 5042 */ 5043 static void 5044 ath_tx_task_q0(void *arg, int npending) 5045 { 5046 struct ath_softc *sc = arg; 5047 struct ifnet *ifp = sc->sc_ifp; 5048 5049 wlan_serialize_enter(); 5050 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5051 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5052 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5053 ath_tx_processq(sc, sc->sc_cabq); 5054 ifp->if_flags &= ~IFF_OACTIVE; 5055 sc->sc_wd_timer = 0; 5056 5057 if (sc->sc_softled) 5058 ath_led_event(sc, sc->sc_txrix); 5059 5060 ath_start(ifp); 5061 wlan_serialize_exit(); 5062 } 5063 5064 /* 5065 * Deferred processing of transmit interrupt; special-cased 5066 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5067 */ 5068 static void 5069 ath_tx_task_q0123(void *arg, int npending) 5070 { 5071 struct ath_softc *sc = arg; 5072 struct ifnet *ifp = sc->sc_ifp; 5073 int nacked; 5074 5075 wlan_serialize_enter(); 5076 /* 5077 * Process each active queue. 5078 */ 5079 nacked = 0; 5080 if (txqactive(sc->sc_ah, 0)) 5081 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5082 if (txqactive(sc->sc_ah, 1)) 5083 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5084 if (txqactive(sc->sc_ah, 2)) 5085 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5086 if (txqactive(sc->sc_ah, 3)) 5087 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5088 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5089 ath_tx_processq(sc, sc->sc_cabq); 5090 if (nacked) 5091 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5092 5093 ifp->if_flags &= ~IFF_OACTIVE; 5094 sc->sc_wd_timer = 0; 5095 5096 if (sc->sc_softled) 5097 ath_led_event(sc, sc->sc_txrix); 5098 5099 ath_start(ifp); 5100 wlan_serialize_exit(); 5101 } 5102 5103 /* 5104 * Deferred processing of transmit interrupt. 5105 */ 5106 static void 5107 ath_tx_task(void *arg, int npending) 5108 { 5109 struct ath_softc *sc = arg; 5110 struct ifnet *ifp = sc->sc_ifp; 5111 int i, nacked; 5112 5113 wlan_serialize_enter(); 5114 5115 /* 5116 * Process each active queue. 5117 */ 5118 nacked = 0; 5119 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5120 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5121 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5122 } 5123 if (nacked) 5124 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5125 5126 ifp->if_flags &= ~IFF_OACTIVE; 5127 sc->sc_wd_timer = 0; 5128 5129 if (sc->sc_softled) 5130 ath_led_event(sc, sc->sc_txrix); 5131 5132 ath_start(ifp); 5133 wlan_serialize_exit(); 5134 } 5135 5136 static void 5137 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5138 { 5139 #ifdef ATH_DEBUG 5140 struct ath_hal *ah = sc->sc_ah; 5141 #endif 5142 struct ieee80211_node *ni; 5143 struct ath_buf *bf; 5144 u_int ix; 5145 5146 /* 5147 * NB: this assumes output has been stopped and 5148 * we do not need to block ath_tx_proc 5149 */ 5150 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5151 if (bf != NULL) 5152 bf->bf_flags &= ~ATH_BUF_BUSY; 5153 for (ix = 0;; ix++) { 5154 bf = STAILQ_FIRST(&txq->axq_q); 5155 if (bf == NULL) { 5156 txq->axq_link = NULL; 5157 break; 5158 } 5159 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5160 #ifdef ATH_DEBUG 5161 if (sc->sc_debug & ATH_DEBUG_RESET) { 5162 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5163 5164 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5165 ath_hal_txprocdesc(ah, bf->bf_desc, 5166 &bf->bf_status.ds_txstat) == HAL_OK); 5167 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5168 bf->bf_m->m_len, 0, -1); 5169 } 5170 #endif /* ATH_DEBUG */ 5171 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5172 ni = bf->bf_node; 5173 bf->bf_node = NULL; 5174 if (ni != NULL) { 5175 /* 5176 * Do any callback and reclaim the node reference. 5177 */ 5178 if (bf->bf_m->m_flags & M_TXCB) 5179 ieee80211_process_callback(ni, bf->bf_m, -1); 5180 ieee80211_free_node(ni); 5181 } 5182 m_freem(bf->bf_m); 5183 bf->bf_m = NULL; 5184 bf->bf_flags &= ~ATH_BUF_BUSY; 5185 5186 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5187 } 5188 } 5189 5190 static void 5191 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5192 { 5193 struct ath_hal *ah = sc->sc_ah; 5194 5195 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5196 __func__, txq->axq_qnum, 5197 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5198 txq->axq_link); 5199 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5200 } 5201 5202 /* 5203 * Drain the transmit queues and reclaim resources. 5204 */ 5205 static void 5206 ath_draintxq(struct ath_softc *sc) 5207 { 5208 struct ath_hal *ah = sc->sc_ah; 5209 struct ifnet *ifp = sc->sc_ifp; 5210 int i; 5211 5212 /* XXX return value */ 5213 if (!sc->sc_invalid) { 5214 /* don't touch the hardware if marked invalid */ 5215 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5216 __func__, sc->sc_bhalq, 5217 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5218 NULL); 5219 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5220 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5221 if (ATH_TXQ_SETUP(sc, i)) 5222 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5223 } 5224 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5225 if (ATH_TXQ_SETUP(sc, i)) 5226 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5227 #ifdef ATH_DEBUG 5228 if (sc->sc_debug & ATH_DEBUG_RESET) { 5229 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5230 if (bf != NULL && bf->bf_m != NULL) { 5231 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5232 ath_hal_txprocdesc(ah, bf->bf_desc, 5233 &bf->bf_status.ds_txstat) == HAL_OK); 5234 ieee80211_dump_pkt(ifp->if_l2com, 5235 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5236 0, -1); 5237 } 5238 } 5239 #endif /* ATH_DEBUG */ 5240 ifp->if_flags &= ~IFF_OACTIVE; 5241 sc->sc_wd_timer = 0; 5242 } 5243 5244 /* 5245 * Disable the receive h/w in preparation for a reset. 5246 */ 5247 static void 5248 ath_stoprecv(struct ath_softc *sc) 5249 { 5250 #define PA2DESC(_sc, _pa) \ 5251 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5252 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5253 struct ath_hal *ah = sc->sc_ah; 5254 5255 ath_hal_stoppcurecv(ah); /* disable PCU */ 5256 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5257 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5258 DELAY(3000); /* 3ms is long enough for 1 frame */ 5259 #ifdef ATH_DEBUG 5260 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5261 struct ath_buf *bf; 5262 u_int ix; 5263 5264 kprintf("%s: rx queue %p, link %p\n", __func__, 5265 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5266 ix = 0; 5267 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5268 struct ath_desc *ds = bf->bf_desc; 5269 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5270 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5271 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5272 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5273 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5274 ix++; 5275 } 5276 } 5277 #endif 5278 if (sc->sc_rxpending != NULL) { 5279 m_freem(sc->sc_rxpending); 5280 sc->sc_rxpending = NULL; 5281 } 5282 sc->sc_rxlink = NULL; /* just in case */ 5283 #undef PA2DESC 5284 } 5285 5286 /* 5287 * Enable the receive h/w following a reset. 5288 */ 5289 static int 5290 ath_startrecv(struct ath_softc *sc) 5291 { 5292 struct ath_hal *ah = sc->sc_ah; 5293 struct ath_buf *bf; 5294 5295 sc->sc_rxlink = NULL; 5296 sc->sc_rxpending = NULL; 5297 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5298 int error = ath_rxbuf_init(sc, bf); 5299 if (error != 0) { 5300 DPRINTF(sc, ATH_DEBUG_RECV, 5301 "%s: ath_rxbuf_init failed %d\n", 5302 __func__, error); 5303 return error; 5304 } 5305 } 5306 5307 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5308 ath_hal_putrxbuf(ah, bf->bf_daddr); 5309 ath_hal_rxena(ah); /* enable recv descriptors */ 5310 ath_mode_init(sc); /* set filters, etc. */ 5311 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5312 return 0; 5313 } 5314 5315 /* 5316 * Update internal state after a channel change. 5317 */ 5318 static void 5319 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5320 { 5321 enum ieee80211_phymode mode; 5322 5323 /* 5324 * Change channels and update the h/w rate map 5325 * if we're switching; e.g. 11a to 11b/g. 5326 */ 5327 mode = ieee80211_chan2mode(chan); 5328 if (mode != sc->sc_curmode) 5329 ath_setcurmode(sc, mode); 5330 sc->sc_curchan = chan; 5331 } 5332 5333 /* 5334 * Set/change channels. If the channel is really being changed, 5335 * it's done by reseting the chip. To accomplish this we must 5336 * first cleanup any pending DMA, then restart stuff after a la 5337 * ath_init. 5338 */ 5339 static int 5340 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5341 { 5342 struct ifnet *ifp = sc->sc_ifp; 5343 struct ieee80211com *ic = ifp->if_l2com; 5344 struct ath_hal *ah = sc->sc_ah; 5345 5346 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5347 __func__, ieee80211_chan2ieee(ic, chan), 5348 chan->ic_freq, chan->ic_flags); 5349 if (chan != sc->sc_curchan) { 5350 HAL_STATUS status; 5351 /* 5352 * To switch channels clear any pending DMA operations; 5353 * wait long enough for the RX fifo to drain, reset the 5354 * hardware at the new frequency, and then re-enable 5355 * the relevant bits of the h/w. 5356 */ 5357 ath_hal_intrset(ah, 0); /* disable interrupts */ 5358 ath_draintxq(sc); /* clear pending tx frames */ 5359 ath_stoprecv(sc); /* turn off frame recv */ 5360 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5361 if_printf(ifp, "%s: unable to reset " 5362 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5363 __func__, ieee80211_chan2ieee(ic, chan), 5364 chan->ic_freq, chan->ic_flags, status); 5365 return EIO; 5366 } 5367 sc->sc_diversity = ath_hal_getdiversity(ah); 5368 5369 /* 5370 * Re-enable rx framework. 5371 */ 5372 if (ath_startrecv(sc) != 0) { 5373 if_printf(ifp, "%s: unable to restart recv logic\n", 5374 __func__); 5375 return EIO; 5376 } 5377 5378 /* 5379 * Change channels and update the h/w rate map 5380 * if we're switching; e.g. 11a to 11b/g. 5381 */ 5382 ath_chan_change(sc, chan); 5383 5384 /* 5385 * Re-enable interrupts. 5386 */ 5387 ath_hal_intrset(ah, sc->sc_imask); 5388 } 5389 return 0; 5390 } 5391 5392 /* 5393 * Periodically recalibrate the PHY to account 5394 * for temperature/environment changes. 5395 */ 5396 static void 5397 ath_calibrate_callout(void *arg) 5398 { 5399 struct ath_softc *sc = arg; 5400 struct ath_hal *ah = sc->sc_ah; 5401 struct ifnet *ifp = sc->sc_ifp; 5402 struct ieee80211com *ic = ifp->if_l2com; 5403 HAL_BOOL longCal, isCalDone; 5404 int nextcal; 5405 5406 wlan_serialize_enter(); 5407 5408 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5409 goto restart; 5410 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5411 if (longCal) { 5412 sc->sc_stats.ast_per_cal++; 5413 sc->sc_lastlongcal = ticks; 5414 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5415 /* 5416 * Rfgain is out of bounds, reset the chip 5417 * to load new gain values. 5418 */ 5419 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5420 "%s: rfgain change\n", __func__); 5421 sc->sc_stats.ast_per_rfgain++; 5422 ath_reset(ifp); 5423 } 5424 /* 5425 * If this long cal is after an idle period, then 5426 * reset the data collection state so we start fresh. 5427 */ 5428 if (sc->sc_resetcal) { 5429 (void) ath_hal_calreset(ah, sc->sc_curchan); 5430 sc->sc_lastcalreset = ticks; 5431 sc->sc_resetcal = 0; 5432 } 5433 } 5434 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5435 if (longCal) { 5436 /* 5437 * Calibrate noise floor data again in case of change. 5438 */ 5439 ath_hal_process_noisefloor(ah); 5440 } 5441 } else { 5442 DPRINTF(sc, ATH_DEBUG_ANY, 5443 "%s: calibration of channel %u failed\n", 5444 __func__, sc->sc_curchan->ic_freq); 5445 sc->sc_stats.ast_per_calfail++; 5446 } 5447 if (!isCalDone) { 5448 restart: 5449 /* 5450 * Use a shorter interval to potentially collect multiple 5451 * data samples required to complete calibration. Once 5452 * we're told the work is done we drop back to a longer 5453 * interval between requests. We're more aggressive doing 5454 * work when operating as an AP to improve operation right 5455 * after startup. 5456 */ 5457 nextcal = (1000*ath_shortcalinterval)/hz; 5458 if (sc->sc_opmode != HAL_M_HOSTAP) 5459 nextcal *= 10; 5460 } else { 5461 nextcal = ath_longcalinterval*hz; 5462 if (sc->sc_lastcalreset == 0) 5463 sc->sc_lastcalreset = sc->sc_lastlongcal; 5464 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5465 sc->sc_resetcal = 1; /* setup reset next trip */ 5466 } 5467 5468 if (nextcal != 0) { 5469 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5470 __func__, nextcal, isCalDone ? "" : "!"); 5471 callout_reset(&sc->sc_cal_ch, nextcal, 5472 ath_calibrate_callout, sc); 5473 } else { 5474 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5475 __func__); 5476 /* NB: don't rearm timer */ 5477 } 5478 wlan_serialize_exit(); 5479 } 5480 5481 static void 5482 ath_scan_start(struct ieee80211com *ic) 5483 { 5484 struct ifnet *ifp = ic->ic_ifp; 5485 struct ath_softc *sc = ifp->if_softc; 5486 struct ath_hal *ah = sc->sc_ah; 5487 u_int32_t rfilt; 5488 5489 /* XXX calibration timer? */ 5490 5491 sc->sc_scanning = 1; 5492 sc->sc_syncbeacon = 0; 5493 rfilt = ath_calcrxfilter(sc); 5494 ath_hal_setrxfilter(ah, rfilt); 5495 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5496 5497 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0\n", 5498 __func__, rfilt, ifp->if_broadcastaddr, ":"); 5499 } 5500 5501 static void 5502 ath_scan_end(struct ieee80211com *ic) 5503 { 5504 struct ifnet *ifp = ic->ic_ifp; 5505 struct ath_softc *sc = ifp->if_softc; 5506 struct ath_hal *ah = sc->sc_ah; 5507 u_int32_t rfilt; 5508 5509 sc->sc_scanning = 0; 5510 rfilt = ath_calcrxfilter(sc); 5511 ath_hal_setrxfilter(ah, rfilt); 5512 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5513 5514 ath_hal_process_noisefloor(ah); 5515 5516 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0x%x\n", 5517 __func__, rfilt, sc->sc_curbssid, ":", 5518 sc->sc_curaid); 5519 } 5520 5521 static void 5522 ath_set_channel(struct ieee80211com *ic) 5523 { 5524 struct ifnet *ifp = ic->ic_ifp; 5525 struct ath_softc *sc = ifp->if_softc; 5526 5527 (void) ath_chan_set(sc, ic->ic_curchan); 5528 /* 5529 * If we are returning to our bss channel then mark state 5530 * so the next recv'd beacon's tsf will be used to sync the 5531 * beacon timers. Note that since we only hear beacons in 5532 * sta/ibss mode this has no effect in other operating modes. 5533 */ 5534 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5535 sc->sc_syncbeacon = 1; 5536 } 5537 5538 /* 5539 * Walk the vap list and check if there any vap's in RUN state. 5540 */ 5541 static int 5542 ath_isanyrunningvaps(struct ieee80211vap *this) 5543 { 5544 struct ieee80211com *ic = this->iv_ic; 5545 struct ieee80211vap *vap; 5546 5547 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5548 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5549 return 1; 5550 } 5551 return 0; 5552 } 5553 5554 static int 5555 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5556 { 5557 struct ieee80211com *ic = vap->iv_ic; 5558 struct ath_softc *sc = ic->ic_ifp->if_softc; 5559 struct ath_vap *avp = ATH_VAP(vap); 5560 struct ath_hal *ah = sc->sc_ah; 5561 struct ieee80211_node *ni = NULL; 5562 int i, error, stamode; 5563 u_int32_t rfilt; 5564 static const HAL_LED_STATE leds[] = { 5565 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5566 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5567 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5568 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5569 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5570 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5571 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5572 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5573 }; 5574 5575 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5576 ieee80211_state_name[vap->iv_state], 5577 ieee80211_state_name[nstate]); 5578 5579 callout_stop(&sc->sc_cal_ch); 5580 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5581 5582 if (nstate == IEEE80211_S_SCAN) { 5583 /* 5584 * Scanning: turn off beacon miss and don't beacon. 5585 * Mark beacon state so when we reach RUN state we'll 5586 * [re]setup beacons. Unblock the task q thread so 5587 * deferred interrupt processing is done. 5588 */ 5589 ath_hal_intrset(ah, 5590 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5591 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5592 sc->sc_beacons = 0; 5593 taskqueue_unblock(sc->sc_tq); 5594 } 5595 5596 ni = vap->iv_bss; 5597 rfilt = ath_calcrxfilter(sc); 5598 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5599 vap->iv_opmode == IEEE80211_M_AHDEMO || 5600 vap->iv_opmode == IEEE80211_M_IBSS); 5601 if (stamode && nstate == IEEE80211_S_RUN) { 5602 sc->sc_curaid = ni->ni_associd; 5603 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5604 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5605 } 5606 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %6D aid 0x%x\n", 5607 __func__, rfilt, sc->sc_curbssid, ":", sc->sc_curaid); 5608 ath_hal_setrxfilter(ah, rfilt); 5609 5610 /* XXX is this to restore keycache on resume? */ 5611 if (vap->iv_opmode != IEEE80211_M_STA && 5612 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5613 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5614 if (ath_hal_keyisvalid(ah, i)) 5615 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5616 } 5617 5618 /* 5619 * Invoke the parent method to do net80211 work. 5620 */ 5621 error = avp->av_newstate(vap, nstate, arg); 5622 if (error != 0) 5623 goto bad; 5624 5625 if (nstate == IEEE80211_S_RUN) { 5626 /* NB: collect bss node again, it may have changed */ 5627 ni = vap->iv_bss; 5628 5629 DPRINTF(sc, ATH_DEBUG_STATE, 5630 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %6D " 5631 "capinfo 0x%04x chan %d\n", __func__, 5632 vap->iv_flags, ni->ni_intval, ni->ni_bssid, ":", 5633 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5634 5635 switch (vap->iv_opmode) { 5636 #ifdef IEEE80211_SUPPORT_TDMA 5637 case IEEE80211_M_AHDEMO: 5638 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5639 break; 5640 /* fall thru... */ 5641 #endif 5642 case IEEE80211_M_HOSTAP: 5643 case IEEE80211_M_IBSS: 5644 case IEEE80211_M_MBSS: 5645 /* 5646 * Allocate and setup the beacon frame. 5647 * 5648 * Stop any previous beacon DMA. This may be 5649 * necessary, for example, when an ibss merge 5650 * causes reconfiguration; there will be a state 5651 * transition from RUN->RUN that means we may 5652 * be called with beacon transmission active. 5653 */ 5654 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5655 5656 error = ath_beacon_alloc(sc, ni); 5657 if (error != 0) 5658 goto bad; 5659 /* 5660 * If joining an adhoc network defer beacon timer 5661 * configuration to the next beacon frame so we 5662 * have a current TSF to use. Otherwise we're 5663 * starting an ibss/bss so there's no need to delay; 5664 * if this is the first vap moving to RUN state, then 5665 * beacon state needs to be [re]configured. 5666 */ 5667 if (vap->iv_opmode == IEEE80211_M_IBSS && 5668 ni->ni_tstamp.tsf != 0) { 5669 sc->sc_syncbeacon = 1; 5670 } else if (!sc->sc_beacons) { 5671 #ifdef IEEE80211_SUPPORT_TDMA 5672 if (vap->iv_caps & IEEE80211_C_TDMA) 5673 ath_tdma_config(sc, vap); 5674 else 5675 #endif 5676 ath_beacon_config(sc, vap); 5677 sc->sc_beacons = 1; 5678 } 5679 break; 5680 case IEEE80211_M_STA: 5681 /* 5682 * Defer beacon timer configuration to the next 5683 * beacon frame so we have a current TSF to use 5684 * (any TSF collected when scanning is likely old). 5685 */ 5686 sc->sc_syncbeacon = 1; 5687 break; 5688 case IEEE80211_M_MONITOR: 5689 /* 5690 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5691 * transitions so we must re-enable interrupts here to 5692 * handle the case of a single monitor mode vap. 5693 */ 5694 ath_hal_intrset(ah, sc->sc_imask); 5695 break; 5696 case IEEE80211_M_WDS: 5697 break; 5698 default: 5699 break; 5700 } 5701 /* 5702 * Let the hal process statistics collected during a 5703 * scan so it can provide calibrated noise floor data. 5704 */ 5705 ath_hal_process_noisefloor(ah); 5706 /* 5707 * Reset rssi stats; maybe not the best place... 5708 */ 5709 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5710 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5711 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5712 /* 5713 * Finally, start any timers and the task q thread 5714 * (in case we didn't go through SCAN state). 5715 */ 5716 if (ath_longcalinterval != 0) { 5717 /* start periodic recalibration timer */ 5718 callout_reset(&sc->sc_cal_ch, 1, 5719 ath_calibrate_callout, sc); 5720 } else { 5721 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5722 "%s: calibration disabled\n", __func__); 5723 } 5724 taskqueue_unblock(sc->sc_tq); 5725 } else if (nstate == IEEE80211_S_INIT) { 5726 /* 5727 * If there are no vaps left in RUN state then 5728 * shutdown host/driver operation: 5729 * o disable interrupts 5730 * o disable the task queue thread 5731 * o mark beacon processing as stopped 5732 */ 5733 if (!ath_isanyrunningvaps(vap)) { 5734 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5735 /* disable interrupts */ 5736 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5737 taskqueue_block(sc->sc_tq); 5738 sc->sc_beacons = 0; 5739 } 5740 #ifdef IEEE80211_SUPPORT_TDMA 5741 ath_hal_setcca(ah, AH_TRUE); 5742 #endif 5743 } 5744 bad: 5745 return error; 5746 } 5747 5748 /* 5749 * Allocate a key cache slot to the station so we can 5750 * setup a mapping from key index to node. The key cache 5751 * slot is needed for managing antenna state and for 5752 * compression when stations do not use crypto. We do 5753 * it uniliaterally here; if crypto is employed this slot 5754 * will be reassigned. 5755 */ 5756 static void 5757 ath_setup_stationkey(struct ieee80211_node *ni) 5758 { 5759 struct ieee80211vap *vap = ni->ni_vap; 5760 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5761 ieee80211_keyix keyix, rxkeyix; 5762 5763 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5764 /* 5765 * Key cache is full; we'll fall back to doing 5766 * the more expensive lookup in software. Note 5767 * this also means no h/w compression. 5768 */ 5769 /* XXX msg+statistic */ 5770 } else { 5771 /* XXX locking? */ 5772 ni->ni_ucastkey.wk_keyix = keyix; 5773 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5774 /* NB: must mark device key to get called back on delete */ 5775 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5776 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5777 /* NB: this will create a pass-thru key entry */ 5778 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5779 } 5780 } 5781 5782 /* 5783 * Setup driver-specific state for a newly associated node. 5784 * Note that we're called also on a re-associate, the isnew 5785 * param tells us if this is the first time or not. 5786 */ 5787 static void 5788 ath_newassoc(struct ieee80211_node *ni, int isnew) 5789 { 5790 struct ath_node *an = ATH_NODE(ni); 5791 struct ieee80211vap *vap = ni->ni_vap; 5792 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5793 const struct ieee80211_txparam *tp = ni->ni_txparms; 5794 5795 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5796 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5797 5798 ath_rate_newassoc(sc, an, isnew); 5799 if (isnew && 5800 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5801 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5802 ath_setup_stationkey(ni); 5803 } 5804 5805 static int 5806 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5807 int nchans, struct ieee80211_channel chans[]) 5808 { 5809 struct ath_softc *sc = ic->ic_ifp->if_softc; 5810 struct ath_hal *ah = sc->sc_ah; 5811 HAL_STATUS status; 5812 5813 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5814 "%s: rd %u cc %u location %c%s\n", 5815 __func__, reg->regdomain, reg->country, reg->location, 5816 reg->ecm ? " ecm" : ""); 5817 5818 status = ath_hal_set_channels(ah, chans, nchans, 5819 reg->country, reg->regdomain); 5820 if (status != HAL_OK) { 5821 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5822 __func__, status); 5823 return EINVAL; /* XXX */ 5824 } 5825 return 0; 5826 } 5827 5828 static void 5829 ath_getradiocaps(struct ieee80211com *ic, 5830 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5831 { 5832 struct ath_softc *sc = ic->ic_ifp->if_softc; 5833 struct ath_hal *ah = sc->sc_ah; 5834 5835 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5836 __func__, SKU_DEBUG, CTRY_DEFAULT); 5837 5838 /* XXX check return */ 5839 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5840 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5841 5842 } 5843 5844 static int 5845 ath_getchannels(struct ath_softc *sc) 5846 { 5847 struct ifnet *ifp = sc->sc_ifp; 5848 struct ieee80211com *ic = ifp->if_l2com; 5849 struct ath_hal *ah = sc->sc_ah; 5850 HAL_STATUS status; 5851 5852 /* 5853 * Collect channel set based on EEPROM contents. 5854 */ 5855 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5856 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5857 if (status != HAL_OK) { 5858 if_printf(ifp, "%s: unable to collect channel list from hal, " 5859 "status %d\n", __func__, status); 5860 return EINVAL; 5861 } 5862 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5863 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5864 /* XXX map Atheros sku's to net80211 SKU's */ 5865 /* XXX net80211 types too small */ 5866 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5867 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5868 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5869 ic->ic_regdomain.isocc[1] = ' '; 5870 5871 ic->ic_regdomain.ecm = 1; 5872 ic->ic_regdomain.location = 'I'; 5873 5874 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5875 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5876 __func__, sc->sc_eerd, sc->sc_eecc, 5877 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5878 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5879 return 0; 5880 } 5881 5882 static void 5883 ath_led_done_callout(void *arg) 5884 { 5885 struct ath_softc *sc = arg; 5886 5887 wlan_serialize_enter(); 5888 sc->sc_blinking = 0; 5889 wlan_serialize_exit(); 5890 } 5891 5892 /* 5893 * Turn the LED off: flip the pin and then set a timer so no 5894 * update will happen for the specified duration. 5895 */ 5896 static void 5897 ath_led_off_callout(void *arg) 5898 { 5899 struct ath_softc *sc = arg; 5900 5901 wlan_serialize_enter(); 5902 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5903 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, 5904 ath_led_done_callout, sc); 5905 wlan_serialize_exit(); 5906 } 5907 5908 /* 5909 * Blink the LED according to the specified on/off times. 5910 */ 5911 static void 5912 ath_led_blink(struct ath_softc *sc, int on, int off) 5913 { 5914 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5915 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5916 sc->sc_blinking = 1; 5917 sc->sc_ledoff = off; 5918 callout_reset(&sc->sc_ledtimer, on, ath_led_off_callout, sc); 5919 } 5920 5921 static void 5922 ath_led_event(struct ath_softc *sc, int rix) 5923 { 5924 sc->sc_ledevent = ticks; /* time of last event */ 5925 if (sc->sc_blinking) /* don't interrupt active blink */ 5926 return; 5927 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5928 } 5929 5930 static int 5931 ath_rate_setup(struct ath_softc *sc, u_int mode) 5932 { 5933 struct ath_hal *ah = sc->sc_ah; 5934 const HAL_RATE_TABLE *rt; 5935 5936 switch (mode) { 5937 case IEEE80211_MODE_11A: 5938 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5939 break; 5940 case IEEE80211_MODE_HALF: 5941 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5942 break; 5943 case IEEE80211_MODE_QUARTER: 5944 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5945 break; 5946 case IEEE80211_MODE_11B: 5947 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5948 break; 5949 case IEEE80211_MODE_11G: 5950 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5951 break; 5952 case IEEE80211_MODE_TURBO_A: 5953 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5954 break; 5955 case IEEE80211_MODE_TURBO_G: 5956 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5957 break; 5958 case IEEE80211_MODE_STURBO_A: 5959 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5960 break; 5961 case IEEE80211_MODE_11NA: 5962 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5963 break; 5964 case IEEE80211_MODE_11NG: 5965 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5966 break; 5967 default: 5968 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5969 __func__, mode); 5970 return 0; 5971 } 5972 sc->sc_rates[mode] = rt; 5973 return (rt != NULL); 5974 } 5975 5976 static void 5977 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5978 { 5979 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5980 static const struct { 5981 u_int rate; /* tx/rx 802.11 rate */ 5982 u_int16_t timeOn; /* LED on time (ms) */ 5983 u_int16_t timeOff; /* LED off time (ms) */ 5984 } blinkrates[] = { 5985 { 108, 40, 10 }, 5986 { 96, 44, 11 }, 5987 { 72, 50, 13 }, 5988 { 48, 57, 14 }, 5989 { 36, 67, 16 }, 5990 { 24, 80, 20 }, 5991 { 22, 100, 25 }, 5992 { 18, 133, 34 }, 5993 { 12, 160, 40 }, 5994 { 10, 200, 50 }, 5995 { 6, 240, 58 }, 5996 { 4, 267, 66 }, 5997 { 2, 400, 100 }, 5998 { 0, 500, 130 }, 5999 /* XXX half/quarter rates */ 6000 }; 6001 const HAL_RATE_TABLE *rt; 6002 int i, j; 6003 6004 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6005 rt = sc->sc_rates[mode]; 6006 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6007 for (i = 0; i < rt->rateCount; i++) { 6008 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6009 if (rt->info[i].phy != IEEE80211_T_HT) 6010 sc->sc_rixmap[ieeerate] = i; 6011 else 6012 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6013 } 6014 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6015 for (i = 0; i < NELEM(sc->sc_hwmap); i++) { 6016 if (i >= rt->rateCount) { 6017 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6018 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6019 continue; 6020 } 6021 sc->sc_hwmap[i].ieeerate = 6022 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6023 if (rt->info[i].phy == IEEE80211_T_HT) 6024 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6025 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6026 if (rt->info[i].shortPreamble || 6027 rt->info[i].phy == IEEE80211_T_OFDM) 6028 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6029 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6030 for (j = 0; j < NELEM(blinkrates)-1; j++) 6031 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6032 break; 6033 /* NB: this uses the last entry if the rate isn't found */ 6034 /* XXX beware of overlow */ 6035 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6036 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6037 } 6038 sc->sc_currates = rt; 6039 sc->sc_curmode = mode; 6040 /* 6041 * All protection frames are transmited at 2Mb/s for 6042 * 11g, otherwise at 1Mb/s. 6043 */ 6044 if (mode == IEEE80211_MODE_11G) 6045 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6046 else 6047 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6048 /* NB: caller is responsible for reseting rate control state */ 6049 } 6050 6051 #ifdef ATH_DEBUG 6052 static void 6053 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6054 u_int ix, int done) 6055 { 6056 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6057 struct ath_hal *ah = sc->sc_ah; 6058 const struct ath_desc *ds; 6059 int i; 6060 6061 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6062 kprintf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6063 " %08x %08x %08x %08x\n", 6064 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6065 ds->ds_link, ds->ds_data, 6066 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6067 ds->ds_ctl0, ds->ds_ctl1, 6068 ds->ds_hw[0], ds->ds_hw[1]); 6069 if (ah->ah_magic == 0x20065416) { 6070 kprintf(" %08x %08x %08x %08x %08x %08x %08x\n", 6071 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6072 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6073 ds->ds_hw[8]); 6074 } 6075 } 6076 } 6077 6078 static void 6079 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6080 u_int qnum, u_int ix, int done) 6081 { 6082 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6083 struct ath_hal *ah = sc->sc_ah; 6084 const struct ath_desc *ds; 6085 int i; 6086 6087 kprintf("Q%u[%3u]", qnum, ix); 6088 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6089 kprintf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6090 " %08x %08x %08x %08x %08x %08x\n", 6091 ds, (const struct ath_desc *)bf->bf_daddr + i, 6092 ds->ds_link, ds->ds_data, bf->bf_txflags, 6093 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6094 ds->ds_ctl0, ds->ds_ctl1, 6095 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6096 if (ah->ah_magic == 0x20065416) { 6097 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6098 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6099 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6100 ds->ds_hw[10],ds->ds_hw[11]); 6101 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6102 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6103 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6104 ds->ds_hw[18], ds->ds_hw[19]); 6105 } 6106 } 6107 } 6108 #endif /* ATH_DEBUG */ 6109 6110 static void 6111 ath_watchdog_callout(void *arg) 6112 { 6113 struct ath_softc *sc = arg; 6114 6115 wlan_serialize_enter(); 6116 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6117 struct ifnet *ifp = sc->sc_ifp; 6118 uint32_t hangs; 6119 6120 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6121 hangs != 0) { 6122 if_printf(ifp, "%s hang detected (0x%x)\n", 6123 hangs & 0xff ? "bb" : "mac", hangs); 6124 } else 6125 if_printf(ifp, "device timeout\n"); 6126 ath_reset(ifp); 6127 ifp->if_oerrors++; 6128 sc->sc_stats.ast_watchdog++; 6129 } 6130 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 6131 wlan_serialize_exit(); 6132 } 6133 6134 #ifdef ATH_DIAGAPI 6135 /* 6136 * Diagnostic interface to the HAL. This is used by various 6137 * tools to do things like retrieve register contents for 6138 * debugging. The mechanism is intentionally opaque so that 6139 * it can change frequently w/o concern for compatiblity. 6140 */ 6141 static int 6142 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6143 { 6144 struct ath_hal *ah = sc->sc_ah; 6145 u_int id = ad->ad_id & ATH_DIAG_ID; 6146 void *indata = NULL; 6147 void *outdata = NULL; 6148 u_int32_t insize = ad->ad_in_size; 6149 u_int32_t outsize = ad->ad_out_size; 6150 int error = 0; 6151 6152 if (ad->ad_id & ATH_DIAG_IN) { 6153 /* 6154 * Copy in data. 6155 */ 6156 indata = kmalloc(insize, M_TEMP, M_INTWAIT); 6157 if (indata == NULL) { 6158 error = ENOMEM; 6159 goto bad; 6160 } 6161 error = copyin(ad->ad_in_data, indata, insize); 6162 if (error) 6163 goto bad; 6164 } 6165 if (ad->ad_id & ATH_DIAG_DYN) { 6166 /* 6167 * Allocate a buffer for the results (otherwise the HAL 6168 * returns a pointer to a buffer where we can read the 6169 * results). Note that we depend on the HAL leaving this 6170 * pointer for us to use below in reclaiming the buffer; 6171 * may want to be more defensive. 6172 */ 6173 outdata = kmalloc(outsize, M_TEMP, M_INTWAIT); 6174 if (outdata == NULL) { 6175 error = ENOMEM; 6176 goto bad; 6177 } 6178 } 6179 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6180 if (outsize < ad->ad_out_size) 6181 ad->ad_out_size = outsize; 6182 if (outdata != NULL) 6183 error = copyout(outdata, ad->ad_out_data, 6184 ad->ad_out_size); 6185 } else { 6186 error = EINVAL; 6187 } 6188 bad: 6189 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6190 kfree(indata, M_TEMP); 6191 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6192 kfree(outdata, M_TEMP); 6193 return error; 6194 } 6195 #endif /* ATH_DIAGAPI */ 6196 6197 static int 6198 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 6199 { 6200 #define IS_RUNNING(ifp) \ 6201 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 6202 struct ath_softc *sc = ifp->if_softc; 6203 struct ieee80211com *ic = ifp->if_l2com; 6204 struct ifreq *ifr = (struct ifreq *)data; 6205 const HAL_RATE_TABLE *rt; 6206 int error = 0; 6207 6208 switch (cmd) { 6209 case SIOCSIFFLAGS: 6210 if (IS_RUNNING(ifp)) { 6211 /* 6212 * To avoid rescanning another access point, 6213 * do not call ath_init() here. Instead, 6214 * only reflect promisc mode settings. 6215 */ 6216 ath_mode_init(sc); 6217 } else if (ifp->if_flags & IFF_UP) { 6218 /* 6219 * Beware of being called during attach/detach 6220 * to reset promiscuous mode. In that case we 6221 * will still be marked UP but not RUNNING. 6222 * However trying to re-init the interface 6223 * is the wrong thing to do as we've already 6224 * torn down much of our state. There's 6225 * probably a better way to deal with this. 6226 */ 6227 if (!sc->sc_invalid) 6228 ath_init(sc); /* XXX lose error */ 6229 } else { 6230 ath_stop_locked(ifp); 6231 #ifdef notyet 6232 /* XXX must wakeup in places like ath_vap_delete */ 6233 if (!sc->sc_invalid) 6234 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6235 #endif 6236 } 6237 break; 6238 case SIOCGIFMEDIA: 6239 case SIOCSIFMEDIA: 6240 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6241 break; 6242 case SIOCGATHSTATS: 6243 /* NB: embed these numbers to get a consistent view */ 6244 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 6245 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 6246 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6247 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6248 #ifdef IEEE80211_SUPPORT_TDMA 6249 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6250 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6251 #endif 6252 rt = sc->sc_currates; 6253 /* XXX HT rates */ 6254 sc->sc_stats.ast_tx_rate = 6255 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6256 return copyout(&sc->sc_stats, 6257 ifr->ifr_data, sizeof (sc->sc_stats)); 6258 case SIOCZATHSTATS: 6259 error = priv_check(curthread, PRIV_DRIVER); 6260 if (error == 0) 6261 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6262 break; 6263 #ifdef ATH_DIAGAPI 6264 case SIOCGATHDIAG: 6265 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6266 break; 6267 #endif 6268 case SIOCGIFADDR: 6269 error = ether_ioctl(ifp, cmd, data); 6270 break; 6271 default: 6272 error = EINVAL; 6273 break; 6274 } 6275 return error; 6276 #undef IS_RUNNING 6277 } 6278 6279 static int 6280 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6281 { 6282 struct ath_softc *sc = arg1; 6283 u_int slottime; 6284 int error; 6285 6286 wlan_serialize_enter(); 6287 slottime = ath_hal_getslottime(sc->sc_ah); 6288 error = sysctl_handle_int(oidp, &slottime, 0, req); 6289 if (error == 0 && req->newptr) { 6290 if (!ath_hal_setslottime(sc->sc_ah, slottime)) 6291 error = EINVAL; 6292 } 6293 wlan_serialize_exit(); 6294 return error; 6295 } 6296 6297 static int 6298 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6299 { 6300 struct ath_softc *sc = arg1; 6301 u_int acktimeout; 6302 int error; 6303 6304 wlan_serialize_enter(); 6305 acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6306 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6307 if (error == 0 && req->newptr) { 6308 if (!ath_hal_setacktimeout(sc->sc_ah, acktimeout)) 6309 error = EINVAL; 6310 } 6311 wlan_serialize_exit(); 6312 return error; 6313 } 6314 6315 static int 6316 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6317 { 6318 struct ath_softc *sc = arg1; 6319 u_int ctstimeout; 6320 int error; 6321 6322 wlan_serialize_enter(); 6323 ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6324 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6325 if (error == 0 && req->newptr) { 6326 if (!ath_hal_setctstimeout(sc->sc_ah, ctstimeout)) 6327 error = EINVAL; 6328 } 6329 wlan_serialize_exit(); 6330 return error; 6331 } 6332 6333 static int 6334 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6335 { 6336 struct ath_softc *sc = arg1; 6337 int softled = sc->sc_softled; 6338 int error; 6339 6340 error = sysctl_handle_int(oidp, &softled, 0, req); 6341 if (error || !req->newptr) 6342 return error; 6343 wlan_serialize_enter(); 6344 softled = (softled != 0); 6345 if (softled != sc->sc_softled) { 6346 if (softled) { 6347 /* NB: handle any sc_ledpin change */ 6348 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6349 HAL_GPIO_MUX_MAC_NETWORK_LED); 6350 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6351 !sc->sc_ledon); 6352 } 6353 sc->sc_softled = softled; 6354 } 6355 wlan_serialize_exit(); 6356 return 0; 6357 } 6358 6359 static int 6360 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6361 { 6362 struct ath_softc *sc = arg1; 6363 int ledpin = sc->sc_ledpin; 6364 int error; 6365 6366 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6367 if (error || !req->newptr) 6368 return error; 6369 wlan_serialize_enter(); 6370 if (ledpin != sc->sc_ledpin) { 6371 sc->sc_ledpin = ledpin; 6372 if (sc->sc_softled) { 6373 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6374 HAL_GPIO_MUX_MAC_NETWORK_LED); 6375 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6376 !sc->sc_ledon); 6377 } 6378 } 6379 wlan_serialize_exit(); 6380 return 0; 6381 } 6382 6383 static int 6384 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6385 { 6386 struct ath_softc *sc = arg1; 6387 u_int txantenna; 6388 int error; 6389 6390 wlan_serialize_enter(); 6391 txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6392 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6393 6394 if (!error && req->newptr) { 6395 /* XXX assumes 2 antenna ports */ 6396 if (txantenna < HAL_ANT_VARIABLE || 6397 txantenna > HAL_ANT_FIXED_B) { 6398 error = EINVAL; 6399 } else { 6400 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6401 /* 6402 * NB: with the switch locked this isn't meaningful, 6403 * but set it anyway so things like radiotap get 6404 * consistent info in their data. 6405 */ 6406 sc->sc_txantenna = txantenna; 6407 } 6408 } 6409 wlan_serialize_exit(); 6410 return error; 6411 } 6412 6413 static int 6414 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6415 { 6416 struct ath_softc *sc = arg1; 6417 u_int defantenna; 6418 int error; 6419 6420 wlan_serialize_enter(); 6421 defantenna = ath_hal_getdefantenna(sc->sc_ah); 6422 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6423 if (error == 0 && req->newptr) 6424 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6425 wlan_serialize_exit(); 6426 return error; 6427 } 6428 6429 static int 6430 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6431 { 6432 struct ath_softc *sc = arg1; 6433 u_int diversity; 6434 int error; 6435 6436 wlan_serialize_enter(); 6437 diversity = ath_hal_getdiversity(sc->sc_ah); 6438 error = sysctl_handle_int(oidp, &diversity, 0, req); 6439 if (error == 0 && req->newptr) { 6440 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6441 error = EINVAL; 6442 else 6443 sc->sc_diversity = diversity; 6444 } 6445 wlan_serialize_exit(); 6446 return error; 6447 } 6448 6449 static int 6450 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6451 { 6452 struct ath_softc *sc = arg1; 6453 u_int32_t diag; 6454 int error; 6455 6456 wlan_serialize_enter(); 6457 if (!ath_hal_getdiag(sc->sc_ah, &diag)) { 6458 error = EINVAL; 6459 } else { 6460 error = sysctl_handle_int(oidp, &diag, 0, req); 6461 if (error == 0 && req->newptr) { 6462 if (!ath_hal_setdiag(sc->sc_ah, diag)) 6463 error = EINVAL; 6464 } 6465 } 6466 wlan_serialize_exit(); 6467 return error; 6468 } 6469 6470 static int 6471 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6472 { 6473 struct ath_softc *sc = arg1; 6474 struct ifnet *ifp = sc->sc_ifp; 6475 u_int32_t scale; 6476 int error; 6477 6478 wlan_serialize_enter(); 6479 (void)ath_hal_gettpscale(sc->sc_ah, &scale); 6480 error = sysctl_handle_int(oidp, &scale, 0, req); 6481 if (error == 0 && req->newptr) { 6482 if (!ath_hal_settpscale(sc->sc_ah, scale)) 6483 error = EINVAL; 6484 else if (ifp->if_flags & IFF_RUNNING) 6485 error = ath_reset(ifp); 6486 } 6487 wlan_serialize_exit(); 6488 return error; 6489 } 6490 6491 static int 6492 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6493 { 6494 struct ath_softc *sc = arg1; 6495 u_int tpc; 6496 int error; 6497 6498 wlan_serialize_enter(); 6499 tpc = ath_hal_gettpc(sc->sc_ah); 6500 error = sysctl_handle_int(oidp, &tpc, 0, req); 6501 if (error == 0 && req->newptr) { 6502 if (!ath_hal_settpc(sc->sc_ah, tpc)) 6503 error = EINVAL; 6504 } 6505 wlan_serialize_exit(); 6506 return error; 6507 } 6508 6509 static int 6510 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6511 { 6512 struct ath_softc *sc = arg1; 6513 struct ifnet *ifp; 6514 struct ath_hal *ah; 6515 u_int rfkill; 6516 int error; 6517 6518 wlan_serialize_enter(); 6519 ifp = sc->sc_ifp; 6520 ah = sc->sc_ah; 6521 rfkill = ath_hal_getrfkill(ah); 6522 6523 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6524 if (error == 0 && req->newptr) { 6525 if (rfkill != ath_hal_getrfkill(ah)) { 6526 if (!ath_hal_setrfkill(ah, rfkill)) 6527 error = EINVAL; 6528 else if (ifp->if_flags & IFF_RUNNING) 6529 error = ath_reset(ifp); 6530 } 6531 } 6532 wlan_serialize_exit(); 6533 return error; 6534 } 6535 6536 static int 6537 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6538 { 6539 struct ath_softc *sc = arg1; 6540 u_int rfsilent; 6541 int error; 6542 6543 wlan_serialize_enter(); 6544 (void)ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6545 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6546 if (error == 0 && req->newptr) { 6547 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) { 6548 error = EINVAL; 6549 } else { 6550 sc->sc_rfsilentpin = rfsilent & 0x1c; 6551 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6552 } 6553 } 6554 wlan_serialize_exit(); 6555 return error; 6556 } 6557 6558 static int 6559 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6560 { 6561 struct ath_softc *sc = arg1; 6562 u_int32_t tpack; 6563 int error; 6564 6565 wlan_serialize_enter(); 6566 (void)ath_hal_gettpack(sc->sc_ah, &tpack); 6567 error = sysctl_handle_int(oidp, &tpack, 0, req); 6568 if (error == 0 && req->newptr) { 6569 if (!ath_hal_settpack(sc->sc_ah, tpack)) 6570 error = EINVAL; 6571 } 6572 wlan_serialize_exit(); 6573 return error; 6574 } 6575 6576 static int 6577 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6578 { 6579 struct ath_softc *sc = arg1; 6580 u_int32_t tpcts; 6581 int error; 6582 6583 wlan_serialize_enter(); 6584 (void)ath_hal_gettpcts(sc->sc_ah, &tpcts); 6585 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6586 if (error == 0 && req->newptr) { 6587 if (!ath_hal_settpcts(sc->sc_ah, tpcts)) 6588 error = EINVAL; 6589 } 6590 wlan_serialize_exit(); 6591 return error; 6592 } 6593 6594 static int 6595 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6596 { 6597 struct ath_softc *sc = arg1; 6598 int intmit, error; 6599 6600 wlan_serialize_enter(); 6601 intmit = ath_hal_getintmit(sc->sc_ah); 6602 error = sysctl_handle_int(oidp, &intmit, 0, req); 6603 if (error == 0 && req->newptr) { 6604 if (!ath_hal_setintmit(sc->sc_ah, intmit)) 6605 error = EINVAL; 6606 } 6607 wlan_serialize_exit(); 6608 return error; 6609 } 6610 6611 #ifdef IEEE80211_SUPPORT_TDMA 6612 static int 6613 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) 6614 { 6615 struct ath_softc *sc = arg1; 6616 int setcca, error; 6617 6618 wlan_serialize_enter(); 6619 setcca = sc->sc_setcca; 6620 error = sysctl_handle_int(oidp, &setcca, 0, req); 6621 if (error == 0 && req->newptr) 6622 sc->sc_setcca = (setcca != 0); 6623 wlan_serialize_exit(); 6624 return error; 6625 } 6626 #endif /* IEEE80211_SUPPORT_TDMA */ 6627 6628 static void 6629 ath_sysctlattach(struct ath_softc *sc) 6630 { 6631 struct sysctl_ctx_list *ctx; 6632 struct sysctl_oid *tree; 6633 struct ath_hal *ah = sc->sc_ah; 6634 6635 ctx = &sc->sc_sysctl_ctx; 6636 tree = sc->sc_sysctl_tree; 6637 if (tree == NULL) { 6638 device_printf(sc->sc_dev, "can't add sysctl node\n"); 6639 return; 6640 } 6641 6642 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6643 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6644 "EEPROM country code"); 6645 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6646 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6647 "EEPROM regdomain code"); 6648 #ifdef ATH_DEBUG 6649 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6650 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6651 "control debugging printfs"); 6652 #endif 6653 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6654 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6655 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6656 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6657 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6658 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6659 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6660 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6661 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6662 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6663 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6664 ath_sysctl_softled, "I", "enable/disable software LED support"); 6665 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6666 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6667 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6668 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6669 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6670 "setting to turn LED on"); 6671 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6672 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6673 "idle time for inactivity LED (ticks)"); 6674 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6675 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6676 ath_sysctl_txantenna, "I", "antenna switch"); 6677 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6678 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6679 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6680 if (ath_hal_hasdiversity(ah)) 6681 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6682 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6683 ath_sysctl_diversity, "I", "antenna diversity"); 6684 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6685 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6686 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6687 "tx descriptor batching"); 6688 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6689 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6690 ath_sysctl_diag, "I", "h/w diagnostic control"); 6691 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6692 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6693 ath_sysctl_tpscale, "I", "tx power scaling"); 6694 if (ath_hal_hastpc(ah)) { 6695 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6696 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6697 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6698 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6699 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6700 ath_sysctl_tpack, "I", "tx power for ack frames"); 6701 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6702 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6703 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6704 } 6705 if (ath_hal_hasrfsilent(ah)) { 6706 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6707 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6708 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6709 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6710 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6711 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6712 } 6713 if (ath_hal_hasintmit(ah)) { 6714 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6715 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6716 ath_sysctl_intmit, "I", "interference mitigation"); 6717 } 6718 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6719 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6720 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6721 "mask of error frames to pass when monitoring"); 6722 #ifdef IEEE80211_SUPPORT_TDMA 6723 if (ath_hal_macversion(ah) > 0x78) { 6724 sc->sc_tdmadbaprep = 2; 6725 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6726 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, 6727 "TDMA DBA preparation time"); 6728 sc->sc_tdmaswbaprep = 10; 6729 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6730 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, 6731 "TDMA SWBA preparation time"); 6732 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6733 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, 6734 "TDMA slot guard time"); 6735 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6736 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, 6737 "TDMA calculated super frame"); 6738 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6739 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6740 ath_sysctl_setcca, "I", "enable CCA control"); 6741 } 6742 #endif 6743 } 6744 6745 static int 6746 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6747 struct ath_buf *bf, struct mbuf *m0, 6748 const struct ieee80211_bpf_params *params) 6749 { 6750 struct ifnet *ifp = sc->sc_ifp; 6751 struct ieee80211com *ic = ifp->if_l2com; 6752 struct ath_hal *ah = sc->sc_ah; 6753 struct ieee80211vap *vap = ni->ni_vap; 6754 int error, ismcast, ismrr; 6755 int keyix, hdrlen, pktlen, try0, txantenna; 6756 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6757 struct ieee80211_frame *wh; 6758 u_int flags, ctsduration; 6759 HAL_PKT_TYPE atype; 6760 const HAL_RATE_TABLE *rt; 6761 struct ath_desc *ds; 6762 u_int pri; 6763 6764 wh = mtod(m0, struct ieee80211_frame *); 6765 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6766 hdrlen = ieee80211_anyhdrsize(wh); 6767 /* 6768 * Packet length must not include any 6769 * pad bytes; deduct them here. 6770 */ 6771 /* XXX honor IEEE80211_BPF_DATAPAD */ 6772 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6773 6774 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 6775 const struct ieee80211_cipher *cip; 6776 struct ieee80211_key *k; 6777 6778 /* 6779 * Construct the 802.11 header+trailer for an encrypted 6780 * frame. The only reason this can fail is because of an 6781 * unknown or unsupported cipher/key type. 6782 */ 6783 k = ieee80211_crypto_encap(ni, m0); 6784 if (k == NULL) { 6785 /* 6786 * This can happen when the key is yanked after the 6787 * frame was queued. Just discard the frame; the 6788 * 802.11 layer counts failures and provides 6789 * debugging/diagnostics. 6790 */ 6791 ath_freetx(m0); 6792 return EIO; 6793 } 6794 /* 6795 * Adjust the packet + header lengths for the crypto 6796 * additions and calculate the h/w key index. When 6797 * a s/w mic is done the frame will have had any mic 6798 * added to it prior to entry so m0->m_pkthdr.len will 6799 * account for it. Otherwise we need to add it to the 6800 * packet length. 6801 */ 6802 cip = k->wk_cipher; 6803 hdrlen += cip->ic_header; 6804 pktlen += cip->ic_header + cip->ic_trailer; 6805 /* NB: frags always have any TKIP MIC done in s/w */ 6806 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 6807 pktlen += cip->ic_miclen; 6808 keyix = k->wk_keyix; 6809 6810 /* packet header may have moved, reset our local pointer */ 6811 wh = mtod(m0, struct ieee80211_frame *); 6812 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 6813 /* 6814 * Use station key cache slot, if assigned. 6815 */ 6816 keyix = ni->ni_ucastkey.wk_keyix; 6817 if (keyix == IEEE80211_KEYIX_NONE) 6818 keyix = HAL_TXKEYIX_INVALID; 6819 } else 6820 keyix = HAL_TXKEYIX_INVALID; 6821 6822 error = ath_tx_dmasetup(sc, bf, m0); 6823 if (error != 0) 6824 return error; 6825 m0 = bf->bf_m; /* NB: may have changed */ 6826 wh = mtod(m0, struct ieee80211_frame *); 6827 bf->bf_node = ni; /* NB: held reference */ 6828 6829 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6830 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6831 if (params->ibp_flags & IEEE80211_BPF_RTS) 6832 flags |= HAL_TXDESC_RTSENA; 6833 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6834 flags |= HAL_TXDESC_CTSENA; 6835 /* XXX leave ismcast to injector? */ 6836 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6837 flags |= HAL_TXDESC_NOACK; 6838 6839 rt = sc->sc_currates; 6840 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6841 rix = ath_tx_findrix(sc, params->ibp_rate0); 6842 txrate = rt->info[rix].rateCode; 6843 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6844 txrate |= rt->info[rix].shortPreamble; 6845 sc->sc_txrix = rix; 6846 try0 = params->ibp_try0; 6847 ismrr = (params->ibp_try1 != 0); 6848 txantenna = params->ibp_pri >> 2; 6849 if (txantenna == 0) /* XXX? */ 6850 txantenna = sc->sc_txantenna; 6851 ctsduration = 0; 6852 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6853 cix = ath_tx_findrix(sc, params->ibp_ctsrate); 6854 ctsrate = rt->info[cix].rateCode; 6855 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6856 ctsrate |= rt->info[cix].shortPreamble; 6857 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6858 ctsduration += rt->info[cix].spAckDuration; 6859 ctsduration += ath_hal_computetxtime(ah, 6860 rt, pktlen, rix, AH_TRUE); 6861 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6862 ctsduration += rt->info[rix].spAckDuration; 6863 } else { 6864 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6865 ctsduration += rt->info[cix].lpAckDuration; 6866 ctsduration += ath_hal_computetxtime(ah, 6867 rt, pktlen, rix, AH_FALSE); 6868 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6869 ctsduration += rt->info[rix].lpAckDuration; 6870 } 6871 ismrr = 0; /* XXX */ 6872 } else 6873 ctsrate = 0; 6874 pri = params->ibp_pri & 3; 6875 /* 6876 * NB: we mark all packets as type PSPOLL so the h/w won't 6877 * set the sequence number, duration, etc. 6878 */ 6879 atype = HAL_PKT_TYPE_PSPOLL; 6880 6881 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6882 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6883 sc->sc_hwmap[rix].ieeerate, -1); 6884 6885 if (ieee80211_radiotap_active_vap(vap)) { 6886 u_int64_t tsf = ath_hal_gettsf64(ah); 6887 6888 sc->sc_tx_th.wt_tsf = htole64(tsf); 6889 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 6890 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6891 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6892 if (m0->m_flags & M_FRAG) 6893 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 6894 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 6895 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6896 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6897 6898 ieee80211_radiotap_tx(vap, m0); 6899 } 6900 6901 /* 6902 * Formulate first tx descriptor with tx controls. 6903 */ 6904 ds = bf->bf_desc; 6905 /* XXX check return value? */ 6906 ath_hal_setuptxdesc(ah, ds 6907 , pktlen /* packet length */ 6908 , hdrlen /* header length */ 6909 , atype /* Atheros packet type */ 6910 , params->ibp_power /* txpower */ 6911 , txrate, try0 /* series 0 rate/tries */ 6912 , keyix /* key cache index */ 6913 , txantenna /* antenna mode */ 6914 , flags /* flags */ 6915 , ctsrate /* rts/cts rate */ 6916 , ctsduration /* rts/cts duration */ 6917 ); 6918 bf->bf_txflags = flags; 6919 6920 if (ismrr) { 6921 rix = ath_tx_findrix(sc, params->ibp_rate1); 6922 rate1 = rt->info[rix].rateCode; 6923 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6924 rate1 |= rt->info[rix].shortPreamble; 6925 if (params->ibp_try2) { 6926 rix = ath_tx_findrix(sc, params->ibp_rate2); 6927 rate2 = rt->info[rix].rateCode; 6928 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6929 rate2 |= rt->info[rix].shortPreamble; 6930 } else 6931 rate2 = 0; 6932 if (params->ibp_try3) { 6933 rix = ath_tx_findrix(sc, params->ibp_rate3); 6934 rate3 = rt->info[rix].rateCode; 6935 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6936 rate3 |= rt->info[rix].shortPreamble; 6937 } else 6938 rate3 = 0; 6939 ath_hal_setupxtxdesc(ah, ds 6940 , rate1, params->ibp_try1 /* series 1 */ 6941 , rate2, params->ibp_try2 /* series 2 */ 6942 , rate3, params->ibp_try3 /* series 3 */ 6943 ); 6944 } 6945 6946 /* NB: no buffered multicast in power save support */ 6947 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 6948 return 0; 6949 } 6950 6951 static int 6952 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6953 const struct ieee80211_bpf_params *params) 6954 { 6955 struct ieee80211com *ic = ni->ni_ic; 6956 struct ifnet *ifp = ic->ic_ifp; 6957 struct ath_softc *sc = ifp->if_softc; 6958 struct ath_buf *bf; 6959 int error; 6960 6961 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 6962 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 6963 (ifp->if_flags & IFF_RUNNING) == 0 ? 6964 "!running" : "invalid"); 6965 m_freem(m); 6966 error = ENETDOWN; 6967 goto bad; 6968 } 6969 /* 6970 * Grab a TX buffer and associated resources. 6971 */ 6972 bf = ath_getbuf(sc); 6973 if (bf == NULL) { 6974 sc->sc_stats.ast_tx_nobuf++; 6975 m_freem(m); 6976 error = ENOBUFS; 6977 goto bad; 6978 } 6979 6980 if (params == NULL) { 6981 /* 6982 * Legacy path; interpret frame contents to decide 6983 * precisely how to send the frame. 6984 */ 6985 if (ath_tx_start(sc, ni, bf, m)) { 6986 error = EIO; /* XXX */ 6987 goto bad2; 6988 } 6989 } else { 6990 /* 6991 * Caller supplied explicit parameters to use in 6992 * sending the frame. 6993 */ 6994 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 6995 error = EIO; /* XXX */ 6996 goto bad2; 6997 } 6998 } 6999 sc->sc_wd_timer = 5; 7000 ifp->if_opackets++; 7001 sc->sc_stats.ast_tx_raw++; 7002 7003 return 0; 7004 bad2: 7005 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 7006 bad: 7007 ifp->if_oerrors++; 7008 sc->sc_stats.ast_tx_raw_fail++; 7009 ieee80211_free_node(ni); 7010 return error; 7011 } 7012 7013 /* 7014 * Announce various information on device/driver attach. 7015 */ 7016 static void 7017 ath_announce(struct ath_softc *sc) 7018 { 7019 struct ifnet *ifp = sc->sc_ifp; 7020 struct ath_hal *ah = sc->sc_ah; 7021 7022 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 7023 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 7024 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 7025 if (bootverbose) { 7026 int i; 7027 for (i = 0; i <= WME_AC_VO; i++) { 7028 struct ath_txq *txq = sc->sc_ac2q[i]; 7029 if_printf(ifp, "Use hw queue %u for %s traffic\n", 7030 txq->axq_qnum, ieee80211_wme_acnames[i]); 7031 } 7032 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 7033 sc->sc_cabq->axq_qnum); 7034 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 7035 } 7036 if (ath_rxbuf != ATH_RXBUF) 7037 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 7038 if (ath_txbuf != ATH_TXBUF) 7039 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 7040 if (sc->sc_mcastkey && bootverbose) 7041 if_printf(ifp, "using multicast key search\n"); 7042 } 7043 7044 #ifdef IEEE80211_SUPPORT_TDMA 7045 static __inline uint32_t 7046 ath_hal_getnexttbtt(struct ath_hal *ah) 7047 { 7048 #define AR_TIMER0 0x8028 7049 return OS_REG_READ(ah, AR_TIMER0); 7050 } 7051 7052 static __inline void 7053 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 7054 { 7055 /* XXX handle wrap/overflow */ 7056 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 7057 } 7058 7059 static void 7060 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 7061 { 7062 struct ath_hal *ah = sc->sc_ah; 7063 HAL_BEACON_TIMERS bt; 7064 7065 bt.bt_intval = bintval | HAL_BEACON_ENA; 7066 bt.bt_nexttbtt = nexttbtt; 7067 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 7068 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 7069 bt.bt_nextatim = nexttbtt+1; 7070 ath_hal_beaconsettimers(ah, &bt); 7071 } 7072 7073 /* 7074 * Calculate the beacon interval. This is periodic in the 7075 * superframe for the bss. We assume each station is configured 7076 * identically wrt transmit rate so the guard time we calculate 7077 * above will be the same on all stations. Note we need to 7078 * factor in the xmit time because the hardware will schedule 7079 * a frame for transmit if the start of the frame is within 7080 * the burst time. When we get hardware that properly kills 7081 * frames in the PCU we can reduce/eliminate the guard time. 7082 * 7083 * Roundup to 1024 is so we have 1 TU buffer in the guard time 7084 * to deal with the granularity of the nexttbtt timer. 11n MAC's 7085 * with 1us timer granularity should allow us to reduce/eliminate 7086 * this. 7087 */ 7088 static void 7089 ath_tdma_bintvalsetup(struct ath_softc *sc, 7090 const struct ieee80211_tdma_state *tdma) 7091 { 7092 /* copy from vap state (XXX check all vaps have same value?) */ 7093 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 7094 7095 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 7096 tdma->tdma_slotcnt, 1024); 7097 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 7098 if (sc->sc_tdmabintval & 1) 7099 sc->sc_tdmabintval++; 7100 7101 if (tdma->tdma_slot == 0) { 7102 /* 7103 * Only slot 0 beacons; other slots respond. 7104 */ 7105 sc->sc_imask |= HAL_INT_SWBA; 7106 sc->sc_tdmaswba = 0; /* beacon immediately */ 7107 } else { 7108 /* XXX all vaps must be slot 0 or slot !0 */ 7109 sc->sc_imask &= ~HAL_INT_SWBA; 7110 } 7111 } 7112 7113 /* 7114 * Max 802.11 overhead. This assumes no 4-address frames and 7115 * the encapsulation done by ieee80211_encap (llc). We also 7116 * include potential crypto overhead. 7117 */ 7118 #define IEEE80211_MAXOVERHEAD \ 7119 (sizeof(struct ieee80211_qosframe) \ 7120 + sizeof(struct llc) \ 7121 + IEEE80211_ADDR_LEN \ 7122 + IEEE80211_WEP_IVLEN \ 7123 + IEEE80211_WEP_KIDLEN \ 7124 + IEEE80211_WEP_CRCLEN \ 7125 + IEEE80211_WEP_MICLEN \ 7126 + IEEE80211_CRC_LEN) 7127 7128 /* 7129 * Setup initially for tdma operation. Start the beacon 7130 * timers and enable SWBA if we are slot 0. Otherwise 7131 * we wait for slot 0 to arrive so we can sync up before 7132 * starting to transmit. 7133 */ 7134 static void 7135 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 7136 { 7137 struct ath_hal *ah = sc->sc_ah; 7138 struct ifnet *ifp = sc->sc_ifp; 7139 struct ieee80211com *ic = ifp->if_l2com; 7140 const struct ieee80211_txparam *tp; 7141 const struct ieee80211_tdma_state *tdma = NULL; 7142 int rix; 7143 7144 if (vap == NULL) { 7145 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 7146 if (vap == NULL) { 7147 if_printf(ifp, "%s: no vaps?\n", __func__); 7148 return; 7149 } 7150 } 7151 tp = vap->iv_bss->ni_txparms; 7152 /* 7153 * Calculate the guard time for each slot. This is the 7154 * time to send a maximal-size frame according to the 7155 * fixed/lowest transmit rate. Note that the interface 7156 * mtu does not include the 802.11 overhead so we must 7157 * tack that on (ath_hal_computetxtime includes the 7158 * preamble and plcp in it's calculation). 7159 */ 7160 tdma = vap->iv_tdma; 7161 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 7162 rix = ath_tx_findrix(sc, tp->ucastrate); 7163 else 7164 rix = ath_tx_findrix(sc, tp->mcastrate); 7165 /* XXX short preamble assumed */ 7166 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 7167 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 7168 7169 ath_hal_intrset(ah, 0); 7170 7171 ath_beaconq_config(sc); /* setup h/w beacon q */ 7172 if (sc->sc_setcca) 7173 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 7174 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 7175 ath_tdma_settimers(sc, sc->sc_tdmabintval, 7176 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 7177 sc->sc_syncbeacon = 0; 7178 7179 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 7180 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 7181 7182 ath_hal_intrset(ah, sc->sc_imask); 7183 7184 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 7185 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 7186 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 7187 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 7188 sc->sc_tdmadbaprep); 7189 } 7190 7191 /* 7192 * Update tdma operation. Called from the 802.11 layer 7193 * when a beacon is received from the TDMA station operating 7194 * in the slot immediately preceding us in the bss. Use 7195 * the rx timestamp for the beacon frame to update our 7196 * beacon timers so we follow their schedule. Note that 7197 * by using the rx timestamp we implicitly include the 7198 * propagation delay in our schedule. 7199 */ 7200 static void 7201 ath_tdma_update(struct ieee80211_node *ni, 7202 const struct ieee80211_tdma_param *tdma, int changed) 7203 { 7204 #define TSF_TO_TU(_h,_l) \ 7205 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 7206 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 7207 struct ieee80211vap *vap = ni->ni_vap; 7208 struct ieee80211com *ic = ni->ni_ic; 7209 struct ath_softc *sc = ic->ic_ifp->if_softc; 7210 struct ath_hal *ah = sc->sc_ah; 7211 const HAL_RATE_TABLE *rt = sc->sc_currates; 7212 u_int64_t tsf, rstamp, nextslot; 7213 u_int32_t txtime, nextslottu, timer0; 7214 int32_t tudelta, tsfdelta; 7215 const struct ath_rx_status *rs; 7216 int rix; 7217 7218 sc->sc_stats.ast_tdma_update++; 7219 7220 /* 7221 * Check for and adopt configuration changes. 7222 */ 7223 if (changed != 0) { 7224 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 7225 7226 ath_tdma_bintvalsetup(sc, ts); 7227 if (changed & TDMA_UPDATE_SLOTLEN) 7228 ath_wme_update(ic); 7229 7230 DPRINTF(sc, ATH_DEBUG_TDMA, 7231 "%s: adopt slot %u slotcnt %u slotlen %u us " 7232 "bintval %u TU\n", __func__, 7233 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 7234 sc->sc_tdmabintval); 7235 7236 /* XXX right? */ 7237 ath_hal_intrset(ah, sc->sc_imask); 7238 /* NB: beacon timers programmed below */ 7239 } 7240 7241 /* extend rx timestamp to 64 bits */ 7242 rs = sc->sc_lastrs; 7243 tsf = ath_hal_gettsf64(ah); 7244 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf); 7245 /* 7246 * The rx timestamp is set by the hardware on completing 7247 * reception (at the point where the rx descriptor is DMA'd 7248 * to the host). To find the start of our next slot we 7249 * must adjust this time by the time required to send 7250 * the packet just received. 7251 */ 7252 rix = rt->rateCodeToIndex[rs->rs_rate]; 7253 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 7254 rt->info[rix].shortPreamble); 7255 /* NB: << 9 is to cvt to TU and /2 */ 7256 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 7257 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 7258 7259 /* 7260 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 7261 * to usecs and calculate the difference between what the 7262 * other station thinks and what we have programmed. This 7263 * lets us figure how to adjust our timers to match. The 7264 * adjustments are done by pulling the TSF forward and possibly 7265 * rewriting the beacon timers. 7266 */ 7267 timer0 = ath_hal_getnexttbtt(ah); 7268 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 7269 7270 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7271 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 7272 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 7273 7274 if (tsfdelta < 0) { 7275 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7276 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 7277 tsfdelta = -tsfdelta % 1024; 7278 nextslottu++; 7279 } else if (tsfdelta > 0) { 7280 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 7281 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7282 tsfdelta = 1024 - (tsfdelta % 1024); 7283 nextslottu++; 7284 } else { 7285 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7286 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7287 } 7288 tudelta = nextslottu - timer0; 7289 7290 /* 7291 * Copy sender's timetstamp into tdma ie so they can 7292 * calculate roundtrip time. We submit a beacon frame 7293 * below after any timer adjustment. The frame goes out 7294 * at the next TBTT so the sender can calculate the 7295 * roundtrip by inspecting the tdma ie in our beacon frame. 7296 * 7297 * NB: This tstamp is subtlely preserved when 7298 * IEEE80211_BEACON_TDMA is marked (e.g. when the 7299 * slot position changes) because ieee80211_add_tdma 7300 * skips over the data. 7301 */ 7302 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 7303 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 7304 &ni->ni_tstamp.data, 8); 7305 #if 0 7306 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7307 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 7308 (unsigned long long) tsf, (unsigned long long) nextslot, 7309 (int)(nextslot - tsf), tsfdelta, 7310 nextslottu, timer0, tudelta); 7311 #endif 7312 /* 7313 * Adjust the beacon timers only when pulling them forward 7314 * or when going back by less than the beacon interval. 7315 * Negative jumps larger than the beacon interval seem to 7316 * cause the timers to stop and generally cause instability. 7317 * This basically filters out jumps due to missed beacons. 7318 */ 7319 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 7320 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 7321 sc->sc_stats.ast_tdma_timers++; 7322 } 7323 if (tsfdelta > 0) { 7324 ath_hal_adjusttsf(ah, tsfdelta); 7325 sc->sc_stats.ast_tdma_tsf++; 7326 } 7327 ath_tdma_beacon_send(sc, vap); /* prepare response */ 7328 #undef TU_TO_TSF 7329 #undef TSF_TO_TU 7330 } 7331 7332 /* 7333 * Transmit a beacon frame at SWBA. Dynamic updates 7334 * to the frame contents are done as needed. 7335 */ 7336 static void 7337 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 7338 { 7339 struct ath_hal *ah = sc->sc_ah; 7340 struct ath_buf *bf; 7341 int otherant; 7342 7343 /* 7344 * Check if the previous beacon has gone out. If 7345 * not don't try to post another, skip this period 7346 * and wait for the next. Missed beacons indicate 7347 * a problem and should not occur. If we miss too 7348 * many consecutive beacons reset the device. 7349 */ 7350 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 7351 sc->sc_bmisscount++; 7352 DPRINTF(sc, ATH_DEBUG_BEACON, 7353 "%s: missed %u consecutive beacons\n", 7354 __func__, sc->sc_bmisscount); 7355 if (sc->sc_bmisscount >= ath_bstuck_threshold) 7356 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 7357 return; 7358 } 7359 if (sc->sc_bmisscount != 0) { 7360 DPRINTF(sc, ATH_DEBUG_BEACON, 7361 "%s: resume beacon xmit after %u misses\n", 7362 __func__, sc->sc_bmisscount); 7363 sc->sc_bmisscount = 0; 7364 } 7365 7366 /* 7367 * Check recent per-antenna transmit statistics and flip 7368 * the default antenna if noticeably more frames went out 7369 * on the non-default antenna. 7370 * XXX assumes 2 anntenae 7371 */ 7372 if (!sc->sc_diversity) { 7373 otherant = sc->sc_defant & 1 ? 2 : 1; 7374 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 7375 ath_setdefantenna(sc, otherant); 7376 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 7377 } 7378 7379 /* 7380 * Stop any current dma before messing with the beacon linkages. 7381 * 7382 * This should never fail since we check above that no frames 7383 * are still pending on the queue. 7384 */ 7385 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 7386 DPRINTF(sc, ATH_DEBUG_ANY, 7387 "%s: beacon queue %u did not stop?\n", 7388 __func__, sc->sc_bhalq); 7389 /* NB: the HAL still stops DMA, so proceed */ 7390 } 7391 bf = ath_beacon_generate(sc, vap); 7392 if (bf != NULL) { 7393 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 7394 ath_hal_txstart(ah, sc->sc_bhalq); 7395 7396 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 7397 7398 /* 7399 * Record local TSF for our last send for use 7400 * in arbitrating slot collisions. 7401 */ 7402 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 7403 } else { 7404 device_printf(sc->sc_dev, "tdma beacon gen failed!\n"); 7405 } 7406 } 7407 #endif /* IEEE80211_SUPPORT_TDMA */ 7408 7409 static int 7410 ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS) 7411 { 7412 struct ath_softc *sc = arg1; 7413 int val = 0; 7414 int error; 7415 7416 error = sysctl_handle_int(oidp, &val, 0, req); 7417 if (error || !req->newptr) 7418 return error; 7419 if (val == 0) 7420 return 0; /* Not clearing the stats is still valid */ 7421 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 7422 val = 0; 7423 return 0; 7424 } 7425 7426 static void 7427 ath_sysctl_stats_attach(struct ath_softc *sc) 7428 { 7429 struct sysctl_oid *tree; 7430 struct sysctl_ctx_list *ctx; 7431 struct sysctl_oid_list *child; 7432 7433 ctx = &sc->sc_sysctl_ctx; 7434 tree = sc->sc_sysctl_tree; 7435 child = SYSCTL_CHILDREN(tree); 7436 7437 /* Create "clear" node */ 7438 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 7439 "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 7440 ath_sysctl_clearstats, "I", "clear stats"); 7441 7442 /* Create stats node */ 7443 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 7444 NULL, "Statistics"); 7445 child = SYSCTL_CHILDREN(tree); 7446 7447 /* This was generated from if_athioctl.h */ 7448 7449 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD, 7450 &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog"); 7451 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD, 7452 &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts"); 7453 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD, 7454 &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts"); 7455 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD, 7456 &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts"); 7457 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD, 7458 &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts"); 7459 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD, 7460 &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts"); 7461 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD, 7462 &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts"); 7463 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD, 7464 &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts"); 7465 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD, 7466 &sc->sc_stats.ast_mib, 0, "mib interrupts"); 7467 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD, 7468 &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced"); 7469 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD, 7470 &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface"); 7471 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD, 7472 &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted"); 7473 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD, 7474 &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc"); 7475 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD, 7476 &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer"); 7477 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD, 7478 &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed"); 7479 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD, 7480 &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node"); 7481 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD, 7482 &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf"); 7483 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD, 7484 &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster"); 7485 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD, 7486 &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster"); 7487 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD, 7488 &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame"); 7489 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD, 7490 &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs"); 7491 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD, 7492 &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries"); 7493 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD, 7494 &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun"); 7495 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD, 7496 &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered"); 7497 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD, 7498 &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)"); 7499 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD, 7500 &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)"); 7501 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD, 7502 &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate"); 7503 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD, 7504 &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked"); 7505 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD, 7506 &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled"); 7507 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD, 7508 &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled"); 7509 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD, 7510 &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble"); 7511 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD, 7512 &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate"); 7513 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD, 7514 &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection"); 7515 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD, 7516 &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting"); 7517 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD, 7518 &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension"); 7519 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD, 7520 &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf"); 7521 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD, 7522 &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs"); 7523 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD, 7524 &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun"); 7525 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD, 7526 &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC"); 7527 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD, 7528 &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun"); 7529 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD, 7530 &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption"); 7531 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD, 7532 &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure"); 7533 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD, 7534 &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err"); 7535 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD, 7536 &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short"); 7537 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD, 7538 &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large"); 7539 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD, 7540 &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface"); 7541 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD, 7542 &sc->sc_stats.ast_rx_mgt, 0, "management frames received"); 7543 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD, 7544 &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame"); 7545 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD, 7546 &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted"); 7547 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD, 7548 &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf"); 7549 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD, 7550 &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls"); 7551 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD, 7552 &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed"); 7553 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD, 7554 &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset"); 7555 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD, 7556 &sc->sc_stats.ast_rate_calls, 0, "rate control checks"); 7557 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD, 7558 &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate"); 7559 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD, 7560 &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate"); 7561 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD, 7562 &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches"); 7563 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD, 7564 &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches"); 7565 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD, 7566 &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted"); 7567 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD, 7568 &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy"); 7569 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD, 7570 &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api"); 7571 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD, 7572 &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully"); 7573 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD, 7574 &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error"); 7575 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD, 7576 &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd"); 7577 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD, 7578 &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q"); 7579 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD, 7580 &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit"); 7581 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD, 7582 &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer"); 7583 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD, 7584 &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates"); 7585 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD, 7586 &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers"); 7587 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD, 7588 &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF"); 7589 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD, 7590 &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required"); 7591 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD, 7592 &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down"); 7593 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD, 7594 &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer"); 7595 #if 0 7596 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD, 7597 &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons"); 7598 #endif 7599 } 7600