1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD: head/sys/dev/ath/if_ath.c 203751 2010-02-10 11:12:39Z rpaulo $"); 30 */ 31 32 /* 33 * Driver for the Atheros Wireless LAN controller. 34 * 35 * This software is derived from work of Atsushi Onoe; his contribution 36 * is greatly appreciated. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ath.h" 41 #include "opt_wlan.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/sysctl.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/errno.h> 54 #include <sys/callout.h> 55 #include <sys/bus.h> 56 #include <sys/endian.h> 57 #include <sys/kthread.h> 58 #include <sys/taskqueue.h> 59 #include <sys/priv.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 #include <net/if_arp.h> 66 #include <net/if_llc.h> 67 #include <net/ifq_var.h> 68 69 #include <netproto/802_11/ieee80211_var.h> 70 #include <netproto/802_11/ieee80211_regdomain.h> 71 #ifdef IEEE80211_SUPPORT_SUPERG 72 #include <netproto/802_11/ieee80211_superg.h> 73 #endif 74 #ifdef IEEE80211_SUPPORT_TDMA 75 #include <netproto/802_11/ieee80211_tdma.h> 76 #endif 77 78 #include <net/bpf.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/if_ether.h> 83 #endif 84 85 #include <dev/netif/ath/ath/if_athvar.h> 86 #include <dev/netif/ath/hal/ath_hal/ah_devid.h> /* XXX for softled */ 87 88 #ifdef ATH_TX99_DIAG 89 #include <dev/netif/ath_tx99/ath_tx99.h> 90 #endif 91 92 /* 93 * ATH_BCBUF determines the number of vap's that can transmit 94 * beacons and also (currently) the number of vap's that can 95 * have unique mac addresses/bssid. When staggering beacons 96 * 4 is probably a good max as otherwise the beacons become 97 * very closely spaced and there is limited time for cab q traffic 98 * to go out. You can burst beacons instead but that is not good 99 * for stations in power save and at some point you really want 100 * another radio (and channel). 101 * 102 * The limit on the number of mac addresses is tied to our use of 103 * the U/L bit and tracking addresses in a byte; it would be 104 * worthwhile to allow more for applications like proxy sta. 105 */ 106 CTASSERT(ATH_BCBUF <= 8); 107 108 /* unaligned little endian access */ 109 #define LE_READ_2(p) \ 110 ((u_int16_t) \ 111 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 112 #define LE_READ_4(p) \ 113 ((u_int32_t) \ 114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 115 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 116 117 static struct ieee80211vap *ath_vap_create(struct ieee80211com *, 118 const char name[IFNAMSIZ], int unit, 119 enum ieee80211_opmode opmode, 120 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 121 const uint8_t mac[IEEE80211_ADDR_LEN]); 122 static void ath_vap_delete(struct ieee80211vap *); 123 static void ath_init(void *); 124 static void ath_stop_locked(struct ifnet *); 125 static void ath_stop(struct ifnet *); 126 static void ath_start(struct ifnet *, struct ifaltq_subque *); 127 static int ath_reset(struct ifnet *); 128 static int ath_reset_vap(struct ieee80211vap *, u_long); 129 static int ath_media_change(struct ifnet *); 130 static void ath_watchdog_callout(void *); 131 static int ath_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 132 static void ath_fatal_proc(void *, int); 133 static void ath_bmiss_vap(struct ieee80211vap *); 134 static void ath_bmiss_task(void *, int); 135 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *, 136 struct ieee80211_node *); 137 static int ath_key_alloc(struct ieee80211vap *, 138 struct ieee80211_key *, 139 ieee80211_keyix *, ieee80211_keyix *); 140 static int ath_key_delete(struct ieee80211vap *, 141 const struct ieee80211_key *); 142 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *, 143 const u_int8_t mac[IEEE80211_ADDR_LEN]); 144 static void ath_key_update_begin(struct ieee80211vap *); 145 static void ath_key_update_end(struct ieee80211vap *); 146 static void ath_update_mcast(struct ifnet *); 147 static void ath_update_promisc(struct ifnet *); 148 static void ath_mode_init(struct ath_softc *); 149 static void ath_setslottime(struct ath_softc *); 150 static void ath_updateslot(struct ifnet *); 151 static int ath_beaconq_setup(struct ath_hal *); 152 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 153 static void ath_beacon_update(struct ieee80211vap *, int item); 154 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 155 static void ath_beacon_proc(void *, int); 156 static struct ath_buf *ath_beacon_generate(struct ath_softc *, 157 struct ieee80211vap *); 158 static void ath_bstuck_task(void *, int); 159 static void ath_beacon_return(struct ath_softc *, struct ath_buf *); 160 static void ath_beacon_free(struct ath_softc *); 161 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *); 162 static void ath_descdma_cleanup(struct ath_softc *sc, 163 struct ath_descdma *, ath_bufhead *); 164 static int ath_desc_alloc(struct ath_softc *); 165 static void ath_desc_free(struct ath_softc *); 166 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, 167 const uint8_t [IEEE80211_ADDR_LEN]); 168 static void ath_node_free(struct ieee80211_node *); 169 static void ath_node_getsignal(const struct ieee80211_node *, 170 int8_t *, int8_t *); 171 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 172 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 173 int subtype, int rssi, int nf); 174 static void ath_setdefantenna(struct ath_softc *, u_int); 175 static void ath_rx_task(void *, int); 176 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); 177 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 178 static int ath_tx_setup(struct ath_softc *, int, int); 179 static int ath_wme_update(struct ieee80211com *); 180 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 181 static void ath_tx_cleanup(struct ath_softc *); 182 static void ath_freetx(struct mbuf *); 183 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 184 struct ath_buf *, struct mbuf *); 185 static void ath_tx_task_q0(void *, int); 186 static void ath_tx_task_q0123(void *, int); 187 static void ath_tx_task(void *, int); 188 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *); 189 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 190 static void ath_draintxq(struct ath_softc *); 191 static void ath_stoprecv(struct ath_softc *); 192 static int ath_startrecv(struct ath_softc *); 193 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 194 static void ath_scan_start(struct ieee80211com *); 195 static void ath_scan_end(struct ieee80211com *); 196 static void ath_set_channel(struct ieee80211com *); 197 static void ath_calibrate_callout(void *); 198 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int); 199 static void ath_setup_stationkey(struct ieee80211_node *); 200 static void ath_newassoc(struct ieee80211_node *, int); 201 static int ath_setregdomain(struct ieee80211com *, 202 struct ieee80211_regdomain *, int, 203 struct ieee80211_channel []); 204 static void ath_getradiocaps(struct ieee80211com *, int, int *, 205 struct ieee80211_channel []); 206 static int ath_getchannels(struct ath_softc *); 207 static void ath_led_event(struct ath_softc *, int); 208 209 static int ath_rate_setup(struct ath_softc *, u_int mode); 210 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 211 212 static void ath_sysctlattach(struct ath_softc *); 213 static int ath_raw_xmit(struct ieee80211_node *, 214 struct mbuf *, const struct ieee80211_bpf_params *); 215 static void ath_announce(struct ath_softc *); 216 static void ath_sysctl_stats_attach(struct ath_softc *sc); 217 218 #ifdef IEEE80211_SUPPORT_TDMA 219 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 220 u_int32_t bintval); 221 static void ath_tdma_bintvalsetup(struct ath_softc *sc, 222 const struct ieee80211_tdma_state *tdma); 223 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap); 224 static void ath_tdma_update(struct ieee80211_node *ni, 225 const struct ieee80211_tdma_param *tdma, int); 226 static void ath_tdma_beacon_send(struct ath_softc *sc, 227 struct ieee80211vap *vap); 228 229 static __inline void 230 ath_hal_setcca(struct ath_hal *ah, int ena) 231 { 232 /* 233 * NB: fill me in; this is not provided by default because disabling 234 * CCA in most locales violates regulatory. 235 */ 236 } 237 238 static __inline int 239 ath_hal_getcca(struct ath_hal *ah) 240 { 241 u_int32_t diag; 242 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK) 243 return 1; 244 return ((diag & 0x500000) == 0); 245 } 246 247 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */ 248 #define TDMA_LPF_LEN 6 249 #define TDMA_DUMMY_MARKER 0x127 250 #define TDMA_EP_MUL(x, mul) ((x) * (mul)) 251 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER)) 252 #define TDMA_LPF(x, y, len) \ 253 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y)) 254 #define TDMA_SAMPLE(x, y) do { \ 255 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \ 256 } while (0) 257 #define TDMA_EP_RND(x,mul) \ 258 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 259 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER) 260 #endif /* IEEE80211_SUPPORT_TDMA */ 261 262 SYSCTL_DECL(_hw_ath); 263 264 /* XXX validate sysctl values */ 265 static int ath_longcalinterval = 30; /* long cals every 30 secs */ 266 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval, 267 0, "long chip calibration interval (secs)"); 268 static int ath_shortcalinterval = 100; /* short cals every 100 ms */ 269 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval, 270 0, "short chip calibration interval (msecs)"); 271 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */ 272 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval, 273 0, "reset chip calibration results (secs)"); 274 275 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */ 276 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf, 277 0, "rx buffers allocated"); 278 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf); 279 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */ 280 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf, 281 0, "tx buffers allocated"); 282 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf); 283 284 static int ath_bstuck_threshold = 4; /* max missed beacons */ 285 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold, 286 0, "max missed beacon xmits before chip reset"); 287 288 #ifdef ATH_DEBUG 289 enum { 290 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 291 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 292 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 293 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 294 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 295 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 296 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 297 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 298 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 299 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 300 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 301 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 302 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 303 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 304 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 305 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 306 ATH_DEBUG_NODE = 0x00080000, /* node management */ 307 ATH_DEBUG_LED = 0x00100000, /* led management */ 308 ATH_DEBUG_FF = 0x00200000, /* fast frames */ 309 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */ 310 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */ 311 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */ 312 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */ 313 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 314 ATH_DEBUG_ANY = 0xffffffff 315 }; 316 static int ath_debug = 0; 317 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 318 0, "control debugging printfs"); 319 TUNABLE_INT("hw.ath.debug", &ath_debug); 320 321 #define IFF_DUMPPKTS(sc, m) \ 322 ((sc->sc_debug & (m)) || \ 323 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 324 #define DPRINTF(sc, m, fmt, ...) do { \ 325 if (sc->sc_debug & (m)) \ 326 kprintf(fmt, __VA_ARGS__); \ 327 } while (0) 328 #define KEYPRINTF(sc, ix, hk, mac) do { \ 329 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 330 ath_keyprint(sc, __func__, ix, hk, mac); \ 331 } while (0) 332 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf, 333 u_int ix, int); 334 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf, 335 u_int qnum, u_int ix, int done); 336 #else 337 #define IFF_DUMPPKTS(sc, m) \ 338 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 339 #define DPRINTF(sc, m, fmt, ...) do { \ 340 (void) sc; \ 341 } while (0) 342 #define KEYPRINTF(sc, k, ix, mac) do { \ 343 (void) sc; \ 344 } while (0) 345 #endif 346 347 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 348 349 int 350 ath_attach(u_int16_t devid, struct ath_softc *sc) 351 { 352 struct ifnet *ifp; 353 struct ieee80211com *ic; 354 struct ath_hal *ah = NULL; 355 HAL_STATUS status; 356 int error = 0, i; 357 u_int wmodes; 358 uint8_t macaddr[IEEE80211_ADDR_LEN]; 359 360 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 361 362 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 363 if (ifp == NULL) { 364 device_printf(sc->sc_dev, "can not if_alloc()\n"); 365 error = ENOSPC; 366 goto bad; 367 } 368 ic = ifp->if_l2com; 369 370 /* set these up early for if_printf use */ 371 if_initname(ifp, device_get_name(sc->sc_dev), 372 device_get_unit(sc->sc_dev)); 373 374 /* prepare sysctl tree for use in sub modules */ 375 sysctl_ctx_init(&sc->sc_sysctl_ctx); 376 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 377 SYSCTL_STATIC_CHILDREN(_hw), 378 OID_AUTO, 379 device_get_nameunit(sc->sc_dev), 380 CTLFLAG_RD, 0, ""); 381 382 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 383 if (ah == NULL) { 384 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 385 status); 386 error = ENXIO; 387 goto bad; 388 } 389 sc->sc_ah = ah; 390 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 391 #ifdef ATH_DEBUG 392 sc->sc_debug = ath_debug; 393 #endif 394 395 /* 396 * Check if the MAC has multi-rate retry support. 397 * We do this by trying to setup a fake extended 398 * descriptor. MAC's that don't have support will 399 * return false w/o doing anything. MAC's that do 400 * support it will return true w/o doing anything. 401 */ 402 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 403 404 /* 405 * Check if the device has hardware counters for PHY 406 * errors. If so we need to enable the MIB interrupt 407 * so we can act on stat triggers. 408 */ 409 if (ath_hal_hwphycounters(ah)) 410 sc->sc_needmib = 1; 411 412 /* 413 * Get the hardware key cache size. 414 */ 415 sc->sc_keymax = ath_hal_keycachesize(ah); 416 if (sc->sc_keymax > ATH_KEYMAX) { 417 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 418 ATH_KEYMAX, sc->sc_keymax); 419 sc->sc_keymax = ATH_KEYMAX; 420 } 421 /* 422 * Reset the key cache since some parts do not 423 * reset the contents on initial power up. 424 */ 425 for (i = 0; i < sc->sc_keymax; i++) 426 ath_hal_keyreset(ah, i); 427 428 /* 429 * Collect the default channel list. 430 */ 431 error = ath_getchannels(sc); 432 if (error != 0) 433 goto bad; 434 435 /* 436 * Setup rate tables for all potential media types. 437 */ 438 ath_rate_setup(sc, IEEE80211_MODE_11A); 439 ath_rate_setup(sc, IEEE80211_MODE_11B); 440 ath_rate_setup(sc, IEEE80211_MODE_11G); 441 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 442 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 443 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A); 444 ath_rate_setup(sc, IEEE80211_MODE_11NA); 445 ath_rate_setup(sc, IEEE80211_MODE_11NG); 446 ath_rate_setup(sc, IEEE80211_MODE_HALF); 447 ath_rate_setup(sc, IEEE80211_MODE_QUARTER); 448 449 /* NB: setup here so ath_rate_update is happy */ 450 ath_setcurmode(sc, IEEE80211_MODE_11A); 451 452 /* 453 * Allocate tx+rx descriptors and populate the lists. 454 */ 455 wlan_assert_serialized(); 456 wlan_serialize_exit(); 457 error = ath_desc_alloc(sc); 458 wlan_serialize_enter(); 459 if (error != 0) { 460 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 461 goto bad; 462 } 463 callout_init(&sc->sc_cal_ch); 464 callout_init(&sc->sc_wd_ch); 465 466 sc->sc_tq = taskqueue_create("ath_taskq", M_INTWAIT, 467 taskqueue_thread_enqueue, &sc->sc_tq); 468 taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1, 469 "%s taskq", ifp->if_xname); 470 471 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_task, sc); 472 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_task, sc); 473 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_task, sc); 474 475 /* 476 * Allocate hardware transmit queues: one queue for 477 * beacon frames and one data queue for each QoS 478 * priority. Note that the hal handles reseting 479 * these queues at the needed time. 480 * 481 * XXX PS-Poll 482 */ 483 sc->sc_bhalq = ath_beaconq_setup(ah); 484 if (sc->sc_bhalq == (u_int) -1) { 485 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 486 error = EIO; 487 goto bad2; 488 } 489 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 490 if (sc->sc_cabq == NULL) { 491 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 492 error = EIO; 493 goto bad2; 494 } 495 /* NB: insure BK queue is the lowest priority h/w queue */ 496 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 497 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 498 ieee80211_wme_acnames[WME_AC_BK]); 499 error = EIO; 500 goto bad2; 501 } 502 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 503 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 504 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 505 /* 506 * Not enough hardware tx queues to properly do WME; 507 * just punt and assign them all to the same h/w queue. 508 * We could do a better job of this if, for example, 509 * we allocate queues when we switch from station to 510 * AP mode. 511 */ 512 if (sc->sc_ac2q[WME_AC_VI] != NULL) 513 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 514 if (sc->sc_ac2q[WME_AC_BE] != NULL) 515 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 516 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 517 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 518 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 519 } 520 521 /* 522 * Special case certain configurations. Note the 523 * CAB queue is handled by these specially so don't 524 * include them when checking the txq setup mask. 525 */ 526 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 527 case 0x01: 528 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0, sc); 529 break; 530 case 0x0f: 531 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task_q0123, sc); 532 break; 533 default: 534 TASK_INIT(&sc->sc_txtask, 0, ath_tx_task, sc); 535 break; 536 } 537 538 /* 539 * Setup rate control. Some rate control modules 540 * call back to change the anntena state so expose 541 * the necessary entry points. 542 * XXX maybe belongs in struct ath_ratectrl? 543 */ 544 sc->sc_setdefantenna = ath_setdefantenna; 545 sc->sc_rc = ath_rate_attach(sc); 546 if (sc->sc_rc == NULL) { 547 error = EIO; 548 goto bad2; 549 } 550 551 sc->sc_blinking = 0; 552 sc->sc_ledstate = 1; 553 sc->sc_ledon = 0; /* low true */ 554 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 555 callout_init_mp(&sc->sc_ledtimer); 556 /* 557 * Auto-enable soft led processing for IBM cards and for 558 * 5211 minipci cards. Users can also manually enable/disable 559 * support with a sysctl. 560 */ 561 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 562 if (sc->sc_softled) { 563 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 564 HAL_GPIO_MUX_MAC_NETWORK_LED); 565 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 566 } 567 568 ifp->if_softc = sc; 569 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 570 ifp->if_start = ath_start; 571 ifp->if_ioctl = ath_ioctl; 572 ifp->if_init = ath_init; 573 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 574 #ifdef notyet 575 ifq_set_ready(&ifp->if_snd); 576 #endif 577 578 ic->ic_ifp = ifp; 579 /* XXX not right but it's not used anywhere important */ 580 ic->ic_phytype = IEEE80211_T_OFDM; 581 ic->ic_opmode = IEEE80211_M_STA; 582 ic->ic_caps = 583 IEEE80211_C_STA /* station mode */ 584 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 585 | IEEE80211_C_HOSTAP /* hostap mode */ 586 | IEEE80211_C_MONITOR /* monitor mode */ 587 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 588 | IEEE80211_C_WDS /* 4-address traffic works */ 589 | IEEE80211_C_MBSS /* mesh point link mode */ 590 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 591 | IEEE80211_C_SHSLOT /* short slot time supported */ 592 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 593 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 594 | IEEE80211_C_TXFRAG /* handle tx frags */ 595 ; 596 /* 597 * Query the hal to figure out h/w crypto support. 598 */ 599 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 600 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP; 601 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 602 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB; 603 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 604 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM; 605 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 606 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP; 607 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 608 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP; 609 /* 610 * Check if h/w does the MIC and/or whether the 611 * separate key cache entries are required to 612 * handle both tx+rx MIC keys. 613 */ 614 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 615 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 616 /* 617 * If the h/w supports storing tx+rx MIC keys 618 * in one cache slot automatically enable use. 619 */ 620 if (ath_hal_hastkipsplit(ah) || 621 !ath_hal_settkipsplit(ah, AH_FALSE)) 622 sc->sc_splitmic = 1; 623 /* 624 * If the h/w can do TKIP MIC together with WME then 625 * we use it; otherwise we force the MIC to be done 626 * in software by the net80211 layer. 627 */ 628 if (ath_hal_haswmetkipmic(ah)) 629 sc->sc_wmetkipmic = 1; 630 } 631 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 632 /* 633 * Check for multicast key search support. 634 */ 635 if (ath_hal_hasmcastkeysearch(sc->sc_ah) && 636 !ath_hal_getmcastkeysearch(sc->sc_ah)) { 637 ath_hal_setmcastkeysearch(sc->sc_ah, 1); 638 } 639 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 640 /* 641 * Mark key cache slots associated with global keys 642 * as in use. If we knew TKIP was not to be used we 643 * could leave the +32, +64, and +32+64 slots free. 644 */ 645 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 646 setbit(sc->sc_keymap, i); 647 setbit(sc->sc_keymap, i+64); 648 if (sc->sc_splitmic) { 649 setbit(sc->sc_keymap, i+32); 650 setbit(sc->sc_keymap, i+32+64); 651 } 652 } 653 /* 654 * TPC support can be done either with a global cap or 655 * per-packet support. The latter is not available on 656 * all parts. We're a bit pedantic here as all parts 657 * support a global cap. 658 */ 659 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 660 ic->ic_caps |= IEEE80211_C_TXPMGT; 661 662 /* 663 * Mark WME capability only if we have sufficient 664 * hardware queues to do proper priority scheduling. 665 */ 666 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 667 ic->ic_caps |= IEEE80211_C_WME; 668 /* 669 * Check for misc other capabilities. 670 */ 671 if (ath_hal_hasbursting(ah)) 672 ic->ic_caps |= IEEE80211_C_BURST; 673 sc->sc_hasbmask = ath_hal_hasbssidmask(ah); 674 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah); 675 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah); 676 if (ath_hal_hasfastframes(ah)) 677 ic->ic_caps |= IEEE80211_C_FF; 678 wmodes = ath_hal_getwirelessmodes(ah); 679 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO)) 680 ic->ic_caps |= IEEE80211_C_TURBOP; 681 #ifdef IEEE80211_SUPPORT_TDMA 682 if (ath_hal_macversion(ah) > 0x78) { 683 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */ 684 ic->ic_tdma_update = ath_tdma_update; 685 } 686 #endif 687 /* 688 * Indicate we need the 802.11 header padded to a 689 * 32-bit boundary for 4-address and QoS frames. 690 */ 691 ic->ic_flags |= IEEE80211_F_DATAPAD; 692 693 /* 694 * Query the hal about antenna support. 695 */ 696 sc->sc_defant = ath_hal_getdefantenna(ah); 697 698 /* 699 * Not all chips have the VEOL support we want to 700 * use with IBSS beacons; check here for it. 701 */ 702 sc->sc_hasveol = ath_hal_hasveol(ah); 703 704 /* get mac address from hardware */ 705 ath_hal_getmac(ah, macaddr); 706 if (sc->sc_hasbmask) 707 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask); 708 709 /* NB: used to size node table key mapping array */ 710 ic->ic_max_keyix = sc->sc_keymax; 711 /* call MI attach routine. */ 712 ieee80211_ifattach(ic, macaddr); 713 ic->ic_setregdomain = ath_setregdomain; 714 ic->ic_getradiocaps = ath_getradiocaps; 715 sc->sc_opmode = HAL_M_STA; 716 717 /* override default methods */ 718 ic->ic_newassoc = ath_newassoc; 719 ic->ic_updateslot = ath_updateslot; 720 ic->ic_wme.wme_update = ath_wme_update; 721 ic->ic_vap_create = ath_vap_create; 722 ic->ic_vap_delete = ath_vap_delete; 723 ic->ic_raw_xmit = ath_raw_xmit; 724 ic->ic_update_mcast = ath_update_mcast; 725 ic->ic_update_promisc = ath_update_promisc; 726 ic->ic_node_alloc = ath_node_alloc; 727 sc->sc_node_free = ic->ic_node_free; 728 ic->ic_node_free = ath_node_free; 729 ic->ic_node_getsignal = ath_node_getsignal; 730 ic->ic_scan_start = ath_scan_start; 731 ic->ic_scan_end = ath_scan_end; 732 ic->ic_set_channel = ath_set_channel; 733 734 ieee80211_radiotap_attach(ic, 735 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 736 ATH_TX_RADIOTAP_PRESENT, 737 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 738 ATH_RX_RADIOTAP_PRESENT); 739 740 /* 741 * Setup dynamic sysctl's now that country code and 742 * regdomain are available from the hal. 743 */ 744 ath_sysctlattach(sc); 745 ath_sysctl_stats_attach(sc); 746 747 if (bootverbose) 748 ieee80211_announce(ic); 749 ath_announce(sc); 750 return 0; 751 bad2: 752 ath_tx_cleanup(sc); 753 ath_desc_free(sc); 754 bad: 755 if (ah) 756 ath_hal_detach(ah); 757 if (ifp != NULL) 758 if_free(ifp); 759 sc->sc_invalid = 1; 760 return error; 761 } 762 763 int 764 ath_detach(struct ath_softc *sc) 765 { 766 struct ifnet *ifp = sc->sc_ifp; 767 768 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 769 __func__, ifp->if_flags); 770 771 /* 772 * NB: the order of these is important: 773 * o stop the chip so no more interrupts will fire 774 * o call the 802.11 layer before detaching the hal to 775 * insure callbacks into the driver to delete global 776 * key cache entries can be handled 777 * o free the taskqueue which drains any pending tasks 778 * o reclaim the tx queue data structures after calling 779 * the 802.11 layer as we'll get called back to reclaim 780 * node state and potentially want to use them 781 * o to cleanup the tx queues the hal is called, so detach 782 * it last 783 * Other than that, it's straightforward... 784 */ 785 ath_stop(ifp); 786 ieee80211_ifdetach(ifp->if_l2com); 787 taskqueue_free(sc->sc_tq); 788 #ifdef ATH_TX99_DIAG 789 if (sc->sc_tx99 != NULL) 790 sc->sc_tx99->detach(sc->sc_tx99); 791 #endif 792 ath_rate_detach(sc->sc_rc); 793 ath_desc_free(sc); 794 ath_tx_cleanup(sc); 795 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */ 796 if (sc->sc_sysctl_tree) { 797 sysctl_ctx_free(&sc->sc_sysctl_ctx); 798 sc->sc_sysctl_tree = NULL; 799 } 800 if_free(ifp); 801 802 return 0; 803 } 804 805 /* 806 * MAC address handling for multiple BSS on the same radio. 807 * The first vap uses the MAC address from the EEPROM. For 808 * subsequent vap's we set the U/L bit (bit 1) in the MAC 809 * address and use the next six bits as an index. 810 */ 811 static void 812 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone) 813 { 814 int i; 815 816 if (clone && sc->sc_hasbmask) { 817 /* NB: we only do this if h/w supports multiple bssid */ 818 for (i = 0; i < 8; i++) 819 if ((sc->sc_bssidmask & (1<<i)) == 0) 820 break; 821 if (i != 0) 822 mac[0] |= (i << 2)|0x2; 823 } else 824 i = 0; 825 sc->sc_bssidmask |= 1<<i; 826 sc->sc_hwbssidmask[0] &= ~mac[0]; 827 if (i == 0) 828 sc->sc_nbssid0++; 829 } 830 831 static void 832 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN]) 833 { 834 int i = mac[0] >> 2; 835 uint8_t mask; 836 837 if (i != 0 || --sc->sc_nbssid0 == 0) { 838 sc->sc_bssidmask &= ~(1<<i); 839 /* recalculate bssid mask from remaining addresses */ 840 mask = 0xff; 841 for (i = 1; i < 8; i++) 842 if (sc->sc_bssidmask & (1<<i)) 843 mask &= ~((i<<2)|0x2); 844 sc->sc_hwbssidmask[0] |= mask; 845 } 846 } 847 848 /* 849 * Assign a beacon xmit slot. We try to space out 850 * assignments so when beacons are staggered the 851 * traffic coming out of the cab q has maximal time 852 * to go out before the next beacon is scheduled. 853 */ 854 static int 855 assign_bslot(struct ath_softc *sc) 856 { 857 u_int slot, free; 858 859 free = 0; 860 for (slot = 0; slot < ATH_BCBUF; slot++) 861 if (sc->sc_bslot[slot] == NULL) { 862 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL && 863 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL) 864 return slot; 865 free = slot; 866 /* NB: keep looking for a double slot */ 867 } 868 return free; 869 } 870 871 static struct ieee80211vap * 872 ath_vap_create(struct ieee80211com *ic, 873 const char name[IFNAMSIZ], int unit, 874 enum ieee80211_opmode opmode, int flags, 875 const uint8_t bssid[IEEE80211_ADDR_LEN], 876 const uint8_t mac0[IEEE80211_ADDR_LEN]) 877 { 878 struct ath_softc *sc = ic->ic_ifp->if_softc; 879 struct ath_vap *avp; 880 struct ieee80211vap *vap; 881 uint8_t mac[IEEE80211_ADDR_LEN]; 882 int ic_opmode, needbeacon, error; 883 884 avp = (struct ath_vap *) kmalloc(sizeof(struct ath_vap), 885 M_80211_VAP, M_WAITOK | M_ZERO); 886 needbeacon = 0; 887 IEEE80211_ADDR_COPY(mac, mac0); 888 889 ic_opmode = opmode; /* default to opmode of new vap */ 890 switch (opmode) { 891 case IEEE80211_M_STA: 892 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */ 893 device_printf(sc->sc_dev, "only 1 sta vap supported\n"); 894 goto bad; 895 } 896 if (sc->sc_nvaps) { 897 /* 898 * With multiple vaps we must fall back 899 * to s/w beacon miss handling. 900 */ 901 flags |= IEEE80211_CLONE_NOBEACONS; 902 } 903 if (flags & IEEE80211_CLONE_NOBEACONS) { 904 /* 905 * Station mode w/o beacons are implemented w/ AP mode. 906 */ 907 ic_opmode = IEEE80211_M_HOSTAP; 908 } 909 break; 910 case IEEE80211_M_IBSS: 911 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */ 912 device_printf(sc->sc_dev, 913 "only 1 ibss vap supported\n"); 914 goto bad; 915 } 916 needbeacon = 1; 917 break; 918 case IEEE80211_M_AHDEMO: 919 #ifdef IEEE80211_SUPPORT_TDMA 920 if (flags & IEEE80211_CLONE_TDMA) { 921 if (sc->sc_nvaps != 0) { 922 device_printf(sc->sc_dev, 923 "only 1 tdma vap supported\n"); 924 goto bad; 925 } 926 needbeacon = 1; 927 flags |= IEEE80211_CLONE_NOBEACONS; 928 } 929 /* fall thru... */ 930 #endif 931 case IEEE80211_M_MONITOR: 932 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) { 933 /* 934 * Adopt existing mode. Adding a monitor or ahdemo 935 * vap to an existing configuration is of dubious 936 * value but should be ok. 937 */ 938 /* XXX not right for monitor mode */ 939 ic_opmode = ic->ic_opmode; 940 } 941 break; 942 case IEEE80211_M_HOSTAP: 943 case IEEE80211_M_MBSS: 944 needbeacon = 1; 945 break; 946 case IEEE80211_M_WDS: 947 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) { 948 device_printf(sc->sc_dev, 949 "wds not supported in sta mode\n"); 950 goto bad; 951 } 952 /* 953 * Silently remove any request for a unique 954 * bssid; WDS vap's always share the local 955 * mac address. 956 */ 957 flags &= ~IEEE80211_CLONE_BSSID; 958 if (sc->sc_nvaps == 0) 959 ic_opmode = IEEE80211_M_HOSTAP; 960 else 961 ic_opmode = ic->ic_opmode; 962 break; 963 default: 964 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 965 goto bad; 966 } 967 /* 968 * Check that a beacon buffer is available; the code below assumes it. 969 */ 970 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) { 971 device_printf(sc->sc_dev, "no beacon buffer available\n"); 972 goto bad; 973 } 974 975 /* STA, AHDEMO? */ 976 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) { 977 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID); 978 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 979 } 980 981 vap = &avp->av_vap; 982 /* XXX can't hold mutex across if_alloc */ 983 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, 984 bssid, mac); 985 if (error != 0) { 986 device_printf(sc->sc_dev, "%s: error %d creating vap\n", 987 __func__, error); 988 goto bad2; 989 } 990 991 /* h/w crypto support */ 992 vap->iv_key_alloc = ath_key_alloc; 993 vap->iv_key_delete = ath_key_delete; 994 vap->iv_key_set = ath_key_set; 995 vap->iv_key_update_begin = ath_key_update_begin; 996 vap->iv_key_update_end = ath_key_update_end; 997 998 /* override various methods */ 999 avp->av_recv_mgmt = vap->iv_recv_mgmt; 1000 vap->iv_recv_mgmt = ath_recv_mgmt; 1001 vap->iv_reset = ath_reset_vap; 1002 vap->iv_update_beacon = ath_beacon_update; 1003 avp->av_newstate = vap->iv_newstate; 1004 vap->iv_newstate = ath_newstate; 1005 avp->av_bmiss = vap->iv_bmiss; 1006 vap->iv_bmiss = ath_bmiss_vap; 1007 1008 avp->av_bslot = -1; 1009 if (needbeacon) { 1010 /* 1011 * Allocate beacon state and setup the q for buffered 1012 * multicast frames. We know a beacon buffer is 1013 * available because we checked above. 1014 */ 1015 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf); 1016 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list); 1017 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) { 1018 /* 1019 * Assign the vap to a beacon xmit slot. As above 1020 * this cannot fail to find a free one. 1021 */ 1022 avp->av_bslot = assign_bslot(sc); 1023 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL, 1024 ("beacon slot %u not empty", avp->av_bslot)); 1025 sc->sc_bslot[avp->av_bslot] = vap; 1026 sc->sc_nbcnvaps++; 1027 } 1028 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) { 1029 /* 1030 * Multple vaps are to transmit beacons and we 1031 * have h/w support for TSF adjusting; enable 1032 * use of staggered beacons. 1033 */ 1034 sc->sc_stagbeacons = 1; 1035 } 1036 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ); 1037 } 1038 1039 ic->ic_opmode = ic_opmode; 1040 if (opmode != IEEE80211_M_WDS) { 1041 sc->sc_nvaps++; 1042 if (opmode == IEEE80211_M_STA) 1043 sc->sc_nstavaps++; 1044 if (opmode == IEEE80211_M_MBSS) 1045 sc->sc_nmeshvaps++; 1046 } 1047 switch (ic_opmode) { 1048 case IEEE80211_M_IBSS: 1049 sc->sc_opmode = HAL_M_IBSS; 1050 break; 1051 case IEEE80211_M_STA: 1052 sc->sc_opmode = HAL_M_STA; 1053 break; 1054 case IEEE80211_M_AHDEMO: 1055 #ifdef IEEE80211_SUPPORT_TDMA 1056 if (vap->iv_caps & IEEE80211_C_TDMA) { 1057 sc->sc_tdma = 1; 1058 /* NB: disable tsf adjust */ 1059 sc->sc_stagbeacons = 0; 1060 } 1061 /* 1062 * NB: adhoc demo mode is a pseudo mode; to the hal it's 1063 * just ap mode. 1064 */ 1065 /* fall thru... */ 1066 #endif 1067 case IEEE80211_M_HOSTAP: 1068 case IEEE80211_M_MBSS: 1069 sc->sc_opmode = HAL_M_HOSTAP; 1070 break; 1071 case IEEE80211_M_MONITOR: 1072 sc->sc_opmode = HAL_M_MONITOR; 1073 break; 1074 default: 1075 /* XXX should not happen */ 1076 break; 1077 } 1078 if (sc->sc_hastsfadd) { 1079 /* 1080 * Configure whether or not TSF adjust should be done. 1081 */ 1082 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons); 1083 } 1084 if (flags & IEEE80211_CLONE_NOBEACONS) { 1085 /* 1086 * Enable s/w beacon miss handling. 1087 */ 1088 sc->sc_swbmiss = 1; 1089 } 1090 1091 /* complete setup */ 1092 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status); 1093 return vap; 1094 bad2: 1095 reclaim_address(sc, mac); 1096 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask); 1097 bad: 1098 kfree(avp, M_80211_VAP); 1099 return NULL; 1100 } 1101 1102 static void 1103 ath_vap_delete(struct ieee80211vap *vap) 1104 { 1105 struct ieee80211com *ic = vap->iv_ic; 1106 struct ifnet *ifp = ic->ic_ifp; 1107 struct ath_softc *sc = ifp->if_softc; 1108 struct ath_hal *ah = sc->sc_ah; 1109 struct ath_vap *avp = ATH_VAP(vap); 1110 1111 if (ifp->if_flags & IFF_RUNNING) { 1112 /* 1113 * Quiesce the hardware while we remove the vap. In 1114 * particular we need to reclaim all references to 1115 * the vap state by any frames pending on the tx queues. 1116 */ 1117 ath_hal_intrset(ah, 0); /* disable interrupts */ 1118 ath_draintxq(sc); /* stop xmit side */ 1119 ath_stoprecv(sc); /* stop recv side */ 1120 } 1121 1122 ieee80211_vap_detach(vap); 1123 /* 1124 * Reclaim beacon state. Note this must be done before 1125 * the vap instance is reclaimed as we may have a reference 1126 * to it in the buffer for the beacon frame. 1127 */ 1128 if (avp->av_bcbuf != NULL) { 1129 if (avp->av_bslot != -1) { 1130 sc->sc_bslot[avp->av_bslot] = NULL; 1131 sc->sc_nbcnvaps--; 1132 } 1133 ath_beacon_return(sc, avp->av_bcbuf); 1134 avp->av_bcbuf = NULL; 1135 if (sc->sc_nbcnvaps == 0) { 1136 sc->sc_stagbeacons = 0; 1137 if (sc->sc_hastsfadd) 1138 ath_hal_settsfadjust(sc->sc_ah, 0); 1139 } 1140 /* 1141 * Reclaim any pending mcast frames for the vap. 1142 */ 1143 ath_tx_draintxq(sc, &avp->av_mcastq); 1144 } 1145 /* 1146 * Update bookkeeping. 1147 */ 1148 if (vap->iv_opmode == IEEE80211_M_STA) { 1149 sc->sc_nstavaps--; 1150 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss) 1151 sc->sc_swbmiss = 0; 1152 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP || 1153 vap->iv_opmode == IEEE80211_M_MBSS) { 1154 reclaim_address(sc, vap->iv_myaddr); 1155 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask); 1156 if (vap->iv_opmode == IEEE80211_M_MBSS) 1157 sc->sc_nmeshvaps--; 1158 } 1159 if (vap->iv_opmode != IEEE80211_M_WDS) 1160 sc->sc_nvaps--; 1161 #ifdef IEEE80211_SUPPORT_TDMA 1162 /* TDMA operation ceases when the last vap is destroyed */ 1163 if (sc->sc_tdma && sc->sc_nvaps == 0) { 1164 sc->sc_tdma = 0; 1165 sc->sc_swbmiss = 0; 1166 } 1167 #endif 1168 kfree(avp, M_80211_VAP); 1169 1170 if (ifp->if_flags & IFF_RUNNING) { 1171 /* 1172 * Restart rx+tx machines if still running (RUNNING will 1173 * be reset if we just destroyed the last vap). 1174 */ 1175 if (ath_startrecv(sc) != 0) 1176 if_printf(ifp, "%s: unable to restart recv logic\n", 1177 __func__); 1178 if (sc->sc_beacons) { /* restart beacons */ 1179 #ifdef IEEE80211_SUPPORT_TDMA 1180 if (sc->sc_tdma) 1181 ath_tdma_config(sc, NULL); 1182 else 1183 #endif 1184 ath_beacon_config(sc, NULL); 1185 } 1186 ath_hal_intrset(ah, sc->sc_imask); 1187 } 1188 } 1189 1190 void 1191 ath_suspend(struct ath_softc *sc) 1192 { 1193 struct ifnet *ifp = sc->sc_ifp; 1194 struct ieee80211com *ic = ifp->if_l2com; 1195 1196 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1197 __func__, ifp->if_flags); 1198 1199 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0; 1200 if (ic->ic_opmode == IEEE80211_M_STA) 1201 ath_stop(ifp); 1202 else 1203 ieee80211_suspend_all(ic); 1204 /* 1205 * NB: don't worry about putting the chip in low power 1206 * mode; pci will power off our socket on suspend and 1207 * CardBus detaches the device. 1208 */ 1209 } 1210 1211 /* 1212 * Reset the key cache since some parts do not reset the 1213 * contents on resume. First we clear all entries, then 1214 * re-load keys that the 802.11 layer assumes are setup 1215 * in h/w. 1216 */ 1217 static void 1218 ath_reset_keycache(struct ath_softc *sc) 1219 { 1220 struct ifnet *ifp = sc->sc_ifp; 1221 struct ieee80211com *ic = ifp->if_l2com; 1222 struct ath_hal *ah = sc->sc_ah; 1223 int i; 1224 1225 for (i = 0; i < sc->sc_keymax; i++) 1226 ath_hal_keyreset(ah, i); 1227 ieee80211_crypto_reload_keys(ic); 1228 } 1229 1230 void 1231 ath_resume(struct ath_softc *sc) 1232 { 1233 struct ifnet *ifp = sc->sc_ifp; 1234 struct ieee80211com *ic = ifp->if_l2com; 1235 struct ath_hal *ah = sc->sc_ah; 1236 HAL_STATUS status; 1237 1238 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1239 __func__, ifp->if_flags); 1240 1241 /* 1242 * Must reset the chip before we reload the 1243 * keycache as we were powered down on suspend. 1244 */ 1245 ath_hal_reset(ah, sc->sc_opmode, 1246 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan, 1247 AH_FALSE, &status); 1248 ath_reset_keycache(sc); 1249 if (sc->sc_resume_up) { 1250 if (ic->ic_opmode == IEEE80211_M_STA) { 1251 ath_init(sc); 1252 /* 1253 * Program the beacon registers using the last rx'd 1254 * beacon frame and enable sync on the next beacon 1255 * we see. This should handle the case where we 1256 * wakeup and find the same AP and also the case where 1257 * we wakeup and need to roam. For the latter we 1258 * should get bmiss events that trigger a roam. 1259 */ 1260 ath_beacon_config(sc, NULL); 1261 sc->sc_syncbeacon = 1; 1262 } else 1263 ieee80211_resume_all(ic); 1264 } 1265 if (sc->sc_softled) { 1266 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin, 1267 HAL_GPIO_MUX_MAC_NETWORK_LED); 1268 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 1269 } 1270 } 1271 1272 void 1273 ath_shutdown(struct ath_softc *sc) 1274 { 1275 struct ifnet *ifp = sc->sc_ifp; 1276 1277 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 1278 __func__, ifp->if_flags); 1279 1280 ath_stop(ifp); 1281 /* NB: no point powering down chip as we're about to reboot */ 1282 } 1283 1284 /* 1285 * Interrupt handler. Most of the actual processing is deferred. 1286 */ 1287 void 1288 ath_intr(void *arg) 1289 { 1290 struct ath_softc *sc = arg; 1291 struct ifnet *ifp = sc->sc_ifp; 1292 struct ath_hal *ah = sc->sc_ah; 1293 HAL_INT status; 1294 HAL_INT ostatus; 1295 1296 if (sc->sc_invalid) { 1297 /* 1298 * The hardware is not ready/present, don't touch anything. 1299 * Note this can happen early on if the IRQ is shared. 1300 */ 1301 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 1302 return; 1303 } 1304 1305 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 1306 return; 1307 if ((ifp->if_flags & IFF_UP) == 0 || 1308 (ifp->if_flags & IFF_RUNNING) == 0) { 1309 HAL_INT status; 1310 1311 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1312 __func__, ifp->if_flags); 1313 ath_hal_getisr(ah, &status); /* clear ISR */ 1314 ath_hal_intrset(ah, 0); /* disable further intr's */ 1315 return; 1316 } 1317 /* 1318 * Figure out the reason(s) for the interrupt. Note 1319 * that the hal returns a pseudo-ISR that may include 1320 * bits we haven't explicitly enabled so we mask the 1321 * value to insure we only process bits we requested. 1322 */ 1323 ath_hal_getisr(ah, &ostatus); /* NB: clears ISR too */ 1324 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, ostatus); 1325 status = ostatus & sc->sc_imask; /* discard unasked for bits */ 1326 if (status & HAL_INT_FATAL) { 1327 sc->sc_stats.ast_hardware++; 1328 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 1329 ath_fatal_proc(sc, 0); 1330 } else { 1331 if (status & HAL_INT_SWBA) { 1332 /* 1333 * Software beacon alert--time to send a beacon. 1334 * Handle beacon transmission directly; deferring 1335 * this is too slow to meet timing constraints 1336 * under load. 1337 */ 1338 #ifdef IEEE80211_SUPPORT_TDMA 1339 if (sc->sc_tdma) { 1340 if (sc->sc_tdmaswba == 0) { 1341 struct ieee80211com *ic = ifp->if_l2com; 1342 struct ieee80211vap *vap = 1343 TAILQ_FIRST(&ic->ic_vaps); 1344 ath_tdma_beacon_send(sc, vap); 1345 sc->sc_tdmaswba = 1346 vap->iv_tdma->tdma_bintval; 1347 } else 1348 sc->sc_tdmaswba--; 1349 } else 1350 #endif 1351 { 1352 ath_beacon_proc(sc, 0); 1353 #ifdef IEEE80211_SUPPORT_SUPERG 1354 /* 1355 * Schedule the rx taskq in case there's no 1356 * traffic so any frames held on the staging 1357 * queue are aged and potentially flushed. 1358 */ 1359 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1360 #endif 1361 } 1362 } 1363 1364 /* 1365 * NB: The hardware should re-read the link when the RXE 1366 * bit is written, but it doesn't work at least on 1367 * older chipsets. 1368 */ 1369 if (status & HAL_INT_RXEOL) { 1370 sc->sc_stats.ast_rxeol++; 1371 sc->sc_rxlink = NULL; 1372 } 1373 1374 if (status & HAL_INT_TXURN) { 1375 sc->sc_stats.ast_txurn++; 1376 /* bump tx trigger level */ 1377 ath_hal_updatetxtriglevel(ah, AH_TRUE); 1378 } 1379 1380 if (status & HAL_INT_RX) 1381 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1382 1383 if (status & HAL_INT_TX) 1384 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask); 1385 1386 if (status & HAL_INT_BMISS) { 1387 sc->sc_stats.ast_bmiss++; 1388 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask); 1389 } 1390 1391 if (status & HAL_INT_MIB) { 1392 sc->sc_stats.ast_mib++; 1393 /* 1394 * Disable interrupts until we service the MIB 1395 * interrupt; otherwise it will continue to fire. 1396 */ 1397 ath_hal_intrset(ah, 0); 1398 /* 1399 * Let the hal handle the event. We assume it will 1400 * clear whatever condition caused the interrupt. 1401 */ 1402 ath_hal_mibevent(ah, &sc->sc_halstats); 1403 ath_hal_intrset(ah, sc->sc_imask); 1404 } 1405 1406 if (status & HAL_INT_RXORN) { 1407 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */ 1408 sc->sc_stats.ast_rxorn++; 1409 } 1410 } 1411 } 1412 1413 static void 1414 ath_fatal_proc(void *arg, int pending) 1415 { 1416 struct ath_softc *sc = arg; 1417 struct ifnet *ifp = sc->sc_ifp; 1418 u_int32_t *state; 1419 u_int32_t len; 1420 void *sp; 1421 1422 if_printf(ifp, "hardware error; resetting\n"); 1423 /* 1424 * Fatal errors are unrecoverable. Typically these 1425 * are caused by DMA errors. Collect h/w state from 1426 * the hal so we can diagnose what's going on. 1427 */ 1428 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) { 1429 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len)); 1430 state = sp; 1431 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", 1432 state[0], state[1] , state[2], state[3], 1433 state[4], state[5]); 1434 } 1435 ath_reset(ifp); 1436 } 1437 1438 static void 1439 ath_bmiss_vap(struct ieee80211vap *vap) 1440 { 1441 /* 1442 * Workaround phantom bmiss interrupts by sanity-checking 1443 * the time of our last rx'd frame. If it is within the 1444 * beacon miss interval then ignore the interrupt. If it's 1445 * truly a bmiss we'll get another interrupt soon and that'll 1446 * be dispatched up for processing. Note this applies only 1447 * for h/w beacon miss events. 1448 */ 1449 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) { 1450 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1451 struct ath_softc *sc = ifp->if_softc; 1452 u_int64_t lastrx = sc->sc_lastrx; 1453 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah); 1454 u_int bmisstimeout = 1455 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024; 1456 1457 DPRINTF(sc, ATH_DEBUG_BEACON, 1458 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n", 1459 __func__, (unsigned long long) tsf, 1460 (unsigned long long)(tsf - lastrx), 1461 (unsigned long long) lastrx, bmisstimeout); 1462 1463 if (tsf - lastrx <= bmisstimeout) { 1464 sc->sc_stats.ast_bmiss_phantom++; 1465 return; 1466 } 1467 } 1468 ATH_VAP(vap)->av_bmiss(vap); 1469 } 1470 1471 static int 1472 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs) 1473 { 1474 uint32_t rsize; 1475 void *sp; 1476 1477 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(mask), &sp, &rsize)) 1478 return 0; 1479 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize)); 1480 *hangs = *(uint32_t *)sp; 1481 return 1; 1482 } 1483 1484 static void 1485 ath_bmiss_task(void *arg, int pending) 1486 { 1487 struct ath_softc *sc = arg; 1488 struct ifnet *ifp = sc->sc_ifp; 1489 uint32_t hangs; 1490 1491 wlan_serialize_enter(); 1492 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 1493 1494 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) { 1495 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs); 1496 ath_reset(ifp); 1497 } else { 1498 ieee80211_beacon_miss(ifp->if_l2com); 1499 } 1500 wlan_serialize_exit(); 1501 } 1502 1503 /* 1504 * Handle TKIP MIC setup to deal hardware that doesn't do MIC 1505 * calcs together with WME. If necessary disable the crypto 1506 * hardware and mark the 802.11 state so keys will be setup 1507 * with the MIC work done in software. 1508 */ 1509 static void 1510 ath_settkipmic(struct ath_softc *sc) 1511 { 1512 struct ifnet *ifp = sc->sc_ifp; 1513 struct ieee80211com *ic = ifp->if_l2com; 1514 1515 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) { 1516 if (ic->ic_flags & IEEE80211_F_WME) { 1517 ath_hal_settkipmic(sc->sc_ah, AH_FALSE); 1518 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC; 1519 } else { 1520 ath_hal_settkipmic(sc->sc_ah, AH_TRUE); 1521 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC; 1522 } 1523 } 1524 } 1525 1526 static void 1527 ath_init(void *arg) 1528 { 1529 struct ath_softc *sc = (struct ath_softc *) arg; 1530 struct ifnet *ifp = sc->sc_ifp; 1531 struct ieee80211com *ic = ifp->if_l2com; 1532 struct ath_hal *ah = sc->sc_ah; 1533 HAL_STATUS status; 1534 1535 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 1536 __func__, ifp->if_flags); 1537 1538 wlan_assert_serialized(); 1539 1540 /* 1541 * Stop anything previously setup. This is safe 1542 * whether this is the first time through or not. 1543 */ 1544 ath_stop_locked(ifp); 1545 1546 /* 1547 * The basic interface to setting the hardware in a good 1548 * state is ``reset''. On return the hardware is known to 1549 * be powered up and with interrupts disabled. This must 1550 * be followed by initialization of the appropriate bits 1551 * and then setup of the interrupt mask. 1552 */ 1553 ath_settkipmic(sc); 1554 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) { 1555 if_printf(ifp, "unable to reset hardware; hal status %u\n", 1556 status); 1557 return; 1558 } 1559 ath_chan_change(sc, ic->ic_curchan); 1560 1561 /* 1562 * Likewise this is set during reset so update 1563 * state cached in the driver. 1564 */ 1565 sc->sc_diversity = ath_hal_getdiversity(ah); 1566 sc->sc_lastlongcal = 0; 1567 sc->sc_resetcal = 1; 1568 sc->sc_lastcalreset = 0; 1569 1570 /* 1571 * Setup the hardware after reset: the key cache 1572 * is filled as needed and the receive engine is 1573 * set going. Frame transmit is handled entirely 1574 * in the frame output path; there's nothing to do 1575 * here except setup the interrupt mask. 1576 */ 1577 if (ath_startrecv(sc) != 0) { 1578 if_printf(ifp, "unable to start recv logic\n"); 1579 return; 1580 } 1581 1582 /* 1583 * Enable interrupts. 1584 */ 1585 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 1586 | HAL_INT_RXEOL | HAL_INT_RXORN 1587 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1588 /* 1589 * Enable MIB interrupts when there are hardware phy counters. 1590 * Note we only do this (at the moment) for station mode. 1591 */ 1592 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 1593 sc->sc_imask |= HAL_INT_MIB; 1594 1595 ifp->if_flags |= IFF_RUNNING; 1596 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 1597 ath_hal_intrset(ah, sc->sc_imask); 1598 1599 1600 #ifdef ATH_TX99_DIAG 1601 if (sc->sc_tx99 != NULL) 1602 sc->sc_tx99->start(sc->sc_tx99); 1603 else 1604 #endif 1605 ieee80211_start_all(ic); /* start all vap's */ 1606 } 1607 1608 static void 1609 ath_stop_locked(struct ifnet *ifp) 1610 { 1611 struct ath_softc *sc = ifp->if_softc; 1612 struct ath_hal *ah = sc->sc_ah; 1613 1614 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 1615 __func__, sc->sc_invalid, ifp->if_flags); 1616 1617 if (ifp->if_flags & IFF_RUNNING) { 1618 /* 1619 * Shutdown the hardware and driver: 1620 * reset 802.11 state machine 1621 * turn off timers 1622 * disable interrupts 1623 * turn off the radio 1624 * clear transmit machinery 1625 * clear receive machinery 1626 * drain and release tx queues 1627 * reclaim beacon resources 1628 * power down hardware 1629 * 1630 * Note that some of this work is not possible if the 1631 * hardware is gone (invalid). 1632 */ 1633 #ifdef ATH_TX99_DIAG 1634 if (sc->sc_tx99 != NULL) 1635 sc->sc_tx99->stop(sc->sc_tx99); 1636 #endif 1637 callout_stop(&sc->sc_wd_ch); 1638 sc->sc_wd_timer = 0; 1639 ifp->if_flags &= ~IFF_RUNNING; 1640 if (!sc->sc_invalid) { 1641 if (sc->sc_softled) { 1642 callout_stop(&sc->sc_ledtimer); 1643 ath_hal_gpioset(ah, sc->sc_ledpin, 1644 !sc->sc_ledon); 1645 sc->sc_blinking = 0; 1646 } 1647 ath_hal_intrset(ah, 0); 1648 } 1649 ath_draintxq(sc); 1650 if (!sc->sc_invalid) { 1651 ath_stoprecv(sc); 1652 ath_hal_phydisable(ah); 1653 } else 1654 sc->sc_rxlink = NULL; 1655 ath_beacon_free(sc); /* XXX not needed */ 1656 } 1657 } 1658 1659 static void 1660 ath_stop(struct ifnet *ifp) 1661 { 1662 struct ath_softc *sc __unused = ifp->if_softc; 1663 1664 ath_stop_locked(ifp); 1665 } 1666 1667 /* 1668 * Reset the hardware w/o losing operational state. This is 1669 * basically a more efficient way of doing ath_stop, ath_init, 1670 * followed by state transitions to the current 802.11 1671 * operational state. Used to recover from various errors and 1672 * to reset or reload hardware state. 1673 */ 1674 static int 1675 ath_reset(struct ifnet *ifp) 1676 { 1677 struct ath_softc *sc = ifp->if_softc; 1678 struct ieee80211com *ic = ifp->if_l2com; 1679 struct ath_hal *ah = sc->sc_ah; 1680 HAL_STATUS status; 1681 1682 ath_hal_intrset(ah, 0); /* disable interrupts */ 1683 ath_draintxq(sc); /* stop xmit side */ 1684 ath_stoprecv(sc); /* stop recv side */ 1685 ath_settkipmic(sc); /* configure TKIP MIC handling */ 1686 /* NB: indicate channel change so we do a full reset */ 1687 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status)) 1688 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1689 __func__, status); 1690 sc->sc_diversity = ath_hal_getdiversity(ah); 1691 if (ath_startrecv(sc) != 0) /* restart recv */ 1692 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1693 /* 1694 * We may be doing a reset in response to an ioctl 1695 * that changes the channel so update any state that 1696 * might change as a result. 1697 */ 1698 ath_chan_change(sc, ic->ic_curchan); 1699 if (sc->sc_beacons) { /* restart beacons */ 1700 #ifdef IEEE80211_SUPPORT_TDMA 1701 if (sc->sc_tdma) 1702 ath_tdma_config(sc, NULL); 1703 else 1704 #endif 1705 ath_beacon_config(sc, NULL); 1706 } 1707 ath_hal_intrset(ah, sc->sc_imask); 1708 1709 if_devstart(ifp); /* restart xmit */ 1710 return 0; 1711 } 1712 1713 static int 1714 ath_reset_vap(struct ieee80211vap *vap, u_long cmd) 1715 { 1716 struct ieee80211com *ic = vap->iv_ic; 1717 struct ifnet *ifp = ic->ic_ifp; 1718 struct ath_softc *sc = ifp->if_softc; 1719 struct ath_hal *ah = sc->sc_ah; 1720 1721 switch (cmd) { 1722 case IEEE80211_IOC_TXPOWER: 1723 /* 1724 * If per-packet TPC is enabled, then we have nothing 1725 * to do; otherwise we need to force the global limit. 1726 * All this can happen directly; no need to reset. 1727 */ 1728 if (!ath_hal_gettpc(ah)) 1729 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 1730 return 0; 1731 } 1732 return ath_reset(ifp); 1733 } 1734 1735 static struct ath_buf * 1736 _ath_getbuf_locked(struct ath_softc *sc) 1737 { 1738 struct ath_buf *bf; 1739 1740 bf = STAILQ_FIRST(&sc->sc_txbuf); 1741 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) 1742 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1743 else 1744 bf = NULL; 1745 if (bf == NULL) { 1746 kprintf("ath: ran out of descriptors\n"); 1747 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__, 1748 STAILQ_FIRST(&sc->sc_txbuf) == NULL ? 1749 "out of xmit buffers" : "xmit buffer busy"); 1750 } 1751 return bf; 1752 } 1753 1754 static struct ath_buf * 1755 ath_getbuf(struct ath_softc *sc) 1756 { 1757 struct ath_buf *bf; 1758 1759 bf = _ath_getbuf_locked(sc); 1760 if (bf == NULL) { 1761 struct ifnet *ifp = sc->sc_ifp; 1762 1763 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1764 sc->sc_stats.ast_tx_qstop++; 1765 ifq_set_oactive(&ifp->if_snd); 1766 } 1767 return bf; 1768 } 1769 1770 /* 1771 * Cleanup driver resources when we run out of buffers 1772 * while processing fragments; return the tx buffers 1773 * allocated and drop node references. 1774 */ 1775 static void 1776 ath_txfrag_cleanup(struct ath_softc *sc, 1777 ath_bufhead *frags, struct ieee80211_node *ni) 1778 { 1779 struct ath_buf *bf, *next; 1780 1781 STAILQ_FOREACH_MUTABLE(bf, frags, bf_list, next) { 1782 /* NB: bf assumed clean */ 1783 STAILQ_REMOVE_HEAD(frags, bf_list); 1784 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1785 ieee80211_node_decref(ni); 1786 } 1787 } 1788 1789 /* 1790 * Setup xmit of a fragmented frame. Allocate a buffer 1791 * for each frag and bump the node reference count to 1792 * reflect the held reference to be setup by ath_tx_start. 1793 */ 1794 static int 1795 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 1796 struct mbuf *m0, struct ieee80211_node *ni) 1797 { 1798 struct mbuf *m; 1799 struct ath_buf *bf; 1800 1801 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1802 bf = _ath_getbuf_locked(sc); 1803 if (bf == NULL) { /* out of buffers, cleanup */ 1804 ath_txfrag_cleanup(sc, frags, ni); 1805 break; 1806 } 1807 ieee80211_node_incref(ni); 1808 STAILQ_INSERT_TAIL(frags, bf, bf_list); 1809 } 1810 1811 return !STAILQ_EMPTY(frags); 1812 } 1813 1814 static void 1815 ath_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1816 { 1817 struct ath_softc *sc = ifp->if_softc; 1818 struct ieee80211_node *ni; 1819 struct ath_buf *bf; 1820 struct mbuf *m, *next; 1821 ath_bufhead frags; 1822 1823 wlan_assert_serialized(); 1824 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1825 1826 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 1827 ifq_purge(&ifp->if_snd); 1828 return; 1829 } 1830 for (;;) { 1831 /* 1832 * Grab a TX buffer and associated resources. 1833 */ 1834 bf = ath_getbuf(sc); 1835 if (bf == NULL) 1836 break; 1837 1838 m = ifq_dequeue(&ifp->if_snd); 1839 if (m == NULL) { 1840 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1841 break; 1842 } 1843 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1844 /* 1845 * Check for fragmentation. If this frame 1846 * has been broken up verify we have enough 1847 * buffers to send all the fragments so all 1848 * go out or none... 1849 */ 1850 STAILQ_INIT(&frags); 1851 if ((m->m_flags & M_FRAG) && 1852 !ath_txfrag_setup(sc, &frags, m, ni)) { 1853 DPRINTF(sc, ATH_DEBUG_XMIT, 1854 "%s: out of txfrag buffers\n", __func__); 1855 sc->sc_stats.ast_tx_nofrag++; 1856 IFNET_STAT_INC(ifp, oerrors, 1); 1857 ath_freetx(m); 1858 goto bad; 1859 } 1860 IFNET_STAT_INC(ifp, opackets, 1); 1861 nextfrag: 1862 /* 1863 * Pass the frame to the h/w for transmission. 1864 * Fragmented frames have each frag chained together 1865 * with m_nextpkt. We know there are sufficient ath_buf's 1866 * to send all the frags because of work done by 1867 * ath_txfrag_setup. We leave m_nextpkt set while 1868 * calling ath_tx_start so it can use it to extend the 1869 * the tx duration to cover the subsequent frag and 1870 * so it can reclaim all the mbufs in case of an error; 1871 * ath_tx_start clears m_nextpkt once it commits to 1872 * handing the frame to the hardware. 1873 */ 1874 next = m->m_nextpkt; 1875 if (ath_tx_start(sc, ni, bf, m)) { 1876 bad: 1877 IFNET_STAT_INC(ifp, oerrors, 1); 1878 reclaim: 1879 bf->bf_m = NULL; 1880 bf->bf_node = NULL; 1881 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 1882 ath_txfrag_cleanup(sc, &frags, ni); 1883 if (ni != NULL) 1884 ieee80211_free_node(ni); 1885 continue; 1886 } 1887 if (next != NULL) { 1888 /* 1889 * Beware of state changing between frags. 1890 * XXX check sta power-save state? 1891 */ 1892 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1893 DPRINTF(sc, ATH_DEBUG_XMIT, 1894 "%s: flush fragmented packet, state %s\n", 1895 __func__, 1896 ieee80211_state_name[ni->ni_vap->iv_state]); 1897 ath_freetx(next); 1898 goto reclaim; 1899 } 1900 m = next; 1901 bf = STAILQ_FIRST(&frags); 1902 KASSERT(bf != NULL, ("no buf for txfrag")); 1903 STAILQ_REMOVE_HEAD(&frags, bf_list); 1904 goto nextfrag; 1905 } 1906 1907 sc->sc_wd_timer = 5; 1908 } 1909 } 1910 1911 static int 1912 ath_media_change(struct ifnet *ifp) 1913 { 1914 int error = ieee80211_media_change(ifp); 1915 /* NB: only the fixed rate can change and that doesn't need a reset */ 1916 return (error == ENETRESET ? 0 : error); 1917 } 1918 1919 #ifdef ATH_DEBUG 1920 static void 1921 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix, 1922 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1923 { 1924 static const char *ciphers[] = { 1925 "WEP", 1926 "AES-OCB", 1927 "AES-CCM", 1928 "CKIP", 1929 "TKIP", 1930 "CLR", 1931 }; 1932 char ethstr[ETHER_ADDRSTRLEN + 1]; 1933 int i, n; 1934 1935 kprintf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1936 for (i = 0, n = hk->kv_len; i < n; i++) 1937 kprintf("%02x", hk->kv_val[i]); 1938 kprintf(" mac %s", kether_ntoa(mac, ethstr)); 1939 if (hk->kv_type == HAL_CIPHER_TKIP) { 1940 kprintf(" %s ", sc->sc_splitmic ? "mic" : "rxmic"); 1941 for (i = 0; i < sizeof(hk->kv_mic); i++) 1942 kprintf("%02x", hk->kv_mic[i]); 1943 if (!sc->sc_splitmic) { 1944 kprintf(" txmic "); 1945 for (i = 0; i < sizeof(hk->kv_txmic); i++) 1946 kprintf("%02x", hk->kv_txmic[i]); 1947 } 1948 } 1949 kprintf("\n"); 1950 } 1951 #endif 1952 1953 /* 1954 * Set a TKIP key into the hardware. This handles the 1955 * potential distribution of key state to multiple key 1956 * cache slots for TKIP. 1957 */ 1958 static int 1959 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1960 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1961 { 1962 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1963 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1964 struct ath_hal *ah = sc->sc_ah; 1965 1966 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1967 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1968 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1969 if (sc->sc_splitmic) { 1970 /* 1971 * TX key goes at first index, RX key at the rx index. 1972 * The hal handles the MIC keys at index+64. 1973 */ 1974 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1975 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1976 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1977 return 0; 1978 1979 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1980 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1981 /* XXX delete tx key on failure? */ 1982 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1983 } else { 1984 /* 1985 * Room for both TX+RX MIC keys in one key cache 1986 * slot, just set key at the first index; the hal 1987 * will handle the rest. 1988 */ 1989 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1990 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 1991 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1992 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1993 } 1994 } else if (k->wk_flags & IEEE80211_KEY_XMIT) { 1995 if (sc->sc_splitmic) { 1996 /* 1997 * NB: must pass MIC key in expected location when 1998 * the keycache only holds one MIC key per entry. 1999 */ 2000 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic)); 2001 } else 2002 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic)); 2003 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2004 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2005 } else if (k->wk_flags & IEEE80211_KEY_RECV) { 2006 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 2007 KEYPRINTF(sc, k->wk_keyix, hk, mac); 2008 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 2009 } 2010 return 0; 2011 #undef IEEE80211_KEY_XR 2012 } 2013 2014 /* 2015 * Set a net80211 key into the hardware. This handles the 2016 * potential distribution of key state to multiple key 2017 * cache slots for TKIP with hardware MIC support. 2018 */ 2019 static int 2020 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 2021 struct ieee80211_node *bss) 2022 { 2023 static const u_int8_t ciphermap[] = { 2024 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 2025 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 2026 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 2027 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 2028 (u_int8_t) -1, /* 4 is not allocated */ 2029 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 2030 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 2031 }; 2032 struct ath_hal *ah = sc->sc_ah; 2033 const struct ieee80211_cipher *cip = k->wk_cipher; 2034 u_int8_t gmac[IEEE80211_ADDR_LEN]; 2035 const u_int8_t *mac; 2036 HAL_KEYVAL hk; 2037 2038 memset(&hk, 0, sizeof(hk)); 2039 /* 2040 * Software crypto uses a "clear key" so non-crypto 2041 * state kept in the key cache are maintained and 2042 * so that rx frames have an entry to match. 2043 */ 2044 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 2045 KASSERT(cip->ic_cipher < NELEM(ciphermap), 2046 ("invalid cipher type %u", cip->ic_cipher)); 2047 hk.kv_type = ciphermap[cip->ic_cipher]; 2048 hk.kv_len = k->wk_keylen; 2049 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 2050 } else 2051 hk.kv_type = HAL_CIPHER_CLR; 2052 2053 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 2054 /* 2055 * Group keys on hardware that supports multicast frame 2056 * key search use a MAC that is the sender's address with 2057 * the high bit set instead of the app-specified address. 2058 */ 2059 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 2060 gmac[0] |= 0x80; 2061 mac = gmac; 2062 } else 2063 mac = k->wk_macaddr; 2064 2065 if (hk.kv_type == HAL_CIPHER_TKIP && 2066 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2067 return ath_keyset_tkip(sc, k, &hk, mac); 2068 } else { 2069 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 2070 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 2071 } 2072 } 2073 2074 /* 2075 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2076 * each key, one for decrypt/encrypt and the other for the MIC. 2077 */ 2078 static u_int16_t 2079 key_alloc_2pair(struct ath_softc *sc, 2080 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2081 { 2082 u_int i, keyix; 2083 2084 KASSERT(sc->sc_splitmic, ("key cache !split")); 2085 /* XXX could optimize */ 2086 for (i = 0; i < NELEM(sc->sc_keymap)/4; i++) { 2087 u_int8_t b = sc->sc_keymap[i]; 2088 if (b != 0xff) { 2089 /* 2090 * One or more slots in this byte are free. 2091 */ 2092 keyix = i*NBBY; 2093 while (b & 1) { 2094 again: 2095 keyix++; 2096 b >>= 1; 2097 } 2098 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 2099 if (isset(sc->sc_keymap, keyix+32) || 2100 isset(sc->sc_keymap, keyix+64) || 2101 isset(sc->sc_keymap, keyix+32+64)) { 2102 /* full pair unavailable */ 2103 /* XXX statistic */ 2104 if (keyix == (i+1)*NBBY) { 2105 /* no slots were appropriate, advance */ 2106 continue; 2107 } 2108 goto again; 2109 } 2110 setbit(sc->sc_keymap, keyix); 2111 setbit(sc->sc_keymap, keyix+64); 2112 setbit(sc->sc_keymap, keyix+32); 2113 setbit(sc->sc_keymap, keyix+32+64); 2114 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2115 "%s: key pair %u,%u %u,%u\n", 2116 __func__, keyix, keyix+64, 2117 keyix+32, keyix+32+64); 2118 *txkeyix = keyix; 2119 *rxkeyix = keyix+32; 2120 return 1; 2121 } 2122 } 2123 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2124 return 0; 2125 } 2126 2127 /* 2128 * Allocate tx/rx key slots for TKIP. We allocate two slots for 2129 * each key, one for decrypt/encrypt and the other for the MIC. 2130 */ 2131 static u_int16_t 2132 key_alloc_pair(struct ath_softc *sc, 2133 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2134 { 2135 u_int i, keyix; 2136 2137 KASSERT(!sc->sc_splitmic, ("key cache split")); 2138 /* XXX could optimize */ 2139 for (i = 0; i < NELEM(sc->sc_keymap)/4; i++) { 2140 u_int8_t b = sc->sc_keymap[i]; 2141 if (b != 0xff) { 2142 /* 2143 * One or more slots in this byte are free. 2144 */ 2145 keyix = i*NBBY; 2146 while (b & 1) { 2147 again: 2148 keyix++; 2149 b >>= 1; 2150 } 2151 if (isset(sc->sc_keymap, keyix+64)) { 2152 /* full pair unavailable */ 2153 /* XXX statistic */ 2154 if (keyix == (i+1)*NBBY) { 2155 /* no slots were appropriate, advance */ 2156 continue; 2157 } 2158 goto again; 2159 } 2160 setbit(sc->sc_keymap, keyix); 2161 setbit(sc->sc_keymap, keyix+64); 2162 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2163 "%s: key pair %u,%u\n", 2164 __func__, keyix, keyix+64); 2165 *txkeyix = *rxkeyix = keyix; 2166 return 1; 2167 } 2168 } 2169 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 2170 return 0; 2171 } 2172 2173 /* 2174 * Allocate a single key cache slot. 2175 */ 2176 static int 2177 key_alloc_single(struct ath_softc *sc, 2178 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 2179 { 2180 u_int i, keyix; 2181 2182 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 2183 for (i = 0; i < NELEM(sc->sc_keymap); i++) { 2184 u_int8_t b = sc->sc_keymap[i]; 2185 if (b != 0xff) { 2186 /* 2187 * One or more slots are free. 2188 */ 2189 keyix = i*NBBY; 2190 while (b & 1) 2191 keyix++, b >>= 1; 2192 setbit(sc->sc_keymap, keyix); 2193 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 2194 __func__, keyix); 2195 *txkeyix = *rxkeyix = keyix; 2196 return 1; 2197 } 2198 } 2199 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 2200 return 0; 2201 } 2202 2203 /* 2204 * Allocate one or more key cache slots for a uniacst key. The 2205 * key itself is needed only to identify the cipher. For hardware 2206 * TKIP with split cipher+MIC keys we allocate two key cache slot 2207 * pairs so that we can setup separate TX and RX MIC keys. Note 2208 * that the MIC key for a TKIP key at slot i is assumed by the 2209 * hardware to be at slot i+64. This limits TKIP keys to the first 2210 * 64 entries. 2211 */ 2212 static int 2213 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k, 2214 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 2215 { 2216 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2217 2218 /* 2219 * Group key allocation must be handled specially for 2220 * parts that do not support multicast key cache search 2221 * functionality. For those parts the key id must match 2222 * the h/w key index so lookups find the right key. On 2223 * parts w/ the key search facility we install the sender's 2224 * mac address (with the high bit set) and let the hardware 2225 * find the key w/o using the key id. This is preferred as 2226 * it permits us to support multiple users for adhoc and/or 2227 * multi-station operation. 2228 */ 2229 if (k->wk_keyix != IEEE80211_KEYIX_NONE) { 2230 /* 2231 * Only global keys should have key index assigned. 2232 */ 2233 if (!(&vap->iv_nw_keys[0] <= k && 2234 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) { 2235 /* should not happen */ 2236 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 2237 "%s: bogus group key\n", __func__); 2238 return 0; 2239 } 2240 if (vap->iv_opmode != IEEE80211_M_HOSTAP || 2241 !(k->wk_flags & IEEE80211_KEY_GROUP) || 2242 !sc->sc_mcastkey) { 2243 /* 2244 * XXX we pre-allocate the global keys so 2245 * have no way to check if they've already 2246 * been allocated. 2247 */ 2248 *keyix = *rxkeyix = k - vap->iv_nw_keys; 2249 return 1; 2250 } 2251 /* 2252 * Group key and device supports multicast key search. 2253 */ 2254 k->wk_keyix = IEEE80211_KEYIX_NONE; 2255 } 2256 2257 /* 2258 * We allocate two pair for TKIP when using the h/w to do 2259 * the MIC. For everything else, including software crypto, 2260 * we allocate a single entry. Note that s/w crypto requires 2261 * a pass-through slot on the 5211 and 5212. The 5210 does 2262 * not support pass-through cache entries and we map all 2263 * those requests to slot 0. 2264 */ 2265 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 2266 return key_alloc_single(sc, keyix, rxkeyix); 2267 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 2268 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2269 if (sc->sc_splitmic) 2270 return key_alloc_2pair(sc, keyix, rxkeyix); 2271 else 2272 return key_alloc_pair(sc, keyix, rxkeyix); 2273 } else { 2274 return key_alloc_single(sc, keyix, rxkeyix); 2275 } 2276 } 2277 2278 /* 2279 * Delete an entry in the key cache allocated by ath_key_alloc. 2280 */ 2281 static int 2282 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k) 2283 { 2284 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2285 struct ath_hal *ah = sc->sc_ah; 2286 const struct ieee80211_cipher *cip = k->wk_cipher; 2287 u_int keyix = k->wk_keyix; 2288 2289 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 2290 2291 ath_hal_keyreset(ah, keyix); 2292 /* 2293 * Handle split tx/rx keying required for TKIP with h/w MIC. 2294 */ 2295 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2296 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 2297 ath_hal_keyreset(ah, keyix+32); /* RX key */ 2298 if (keyix >= IEEE80211_WEP_NKID) { 2299 /* 2300 * Don't touch keymap entries for global keys so 2301 * they are never considered for dynamic allocation. 2302 */ 2303 clrbit(sc->sc_keymap, keyix); 2304 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 2305 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 2306 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 2307 if (sc->sc_splitmic) { 2308 /* +32 for RX key, +32+64 for RX key MIC */ 2309 clrbit(sc->sc_keymap, keyix+32); 2310 clrbit(sc->sc_keymap, keyix+32+64); 2311 } 2312 } 2313 } 2314 return 1; 2315 } 2316 2317 /* 2318 * Set the key cache contents for the specified key. Key cache 2319 * slot(s) must already have been allocated by ath_key_alloc. 2320 */ 2321 static int 2322 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k, 2323 const u_int8_t mac[IEEE80211_ADDR_LEN]) 2324 { 2325 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 2326 2327 return ath_keyset(sc, k, vap->iv_bss); 2328 } 2329 2330 /* 2331 * Block/unblock tx+rx processing while a key change is done. 2332 * We assume the caller serializes key management operations 2333 * so we only need to worry about synchronization with other 2334 * uses that originate in the driver. 2335 */ 2336 static void 2337 ath_key_update_begin(struct ieee80211vap *vap) 2338 { 2339 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2340 struct ath_softc *sc = ifp->if_softc; 2341 2342 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2343 taskqueue_block(sc->sc_tq); 2344 } 2345 2346 static void 2347 ath_key_update_end(struct ieee80211vap *vap) 2348 { 2349 struct ifnet *ifp = vap->iv_ic->ic_ifp; 2350 struct ath_softc *sc = ifp->if_softc; 2351 2352 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 2353 taskqueue_unblock(sc->sc_tq); 2354 } 2355 2356 /* 2357 * Calculate the receive filter according to the 2358 * operating mode and state: 2359 * 2360 * o always accept unicast, broadcast, and multicast traffic 2361 * o accept PHY error frames when hardware doesn't have MIB support 2362 * to count and we need them for ANI (sta mode only until recently) 2363 * and we are not scanning (ANI is disabled) 2364 * NB: older hal's add rx filter bits out of sight and we need to 2365 * blindly preserve them 2366 * o probe request frames are accepted only when operating in 2367 * hostap, adhoc, mesh, or monitor modes 2368 * o enable promiscuous mode 2369 * - when in monitor mode 2370 * - if interface marked PROMISC (assumes bridge setting is filtered) 2371 * o accept beacons: 2372 * - when operating in station mode for collecting rssi data when 2373 * the station is otherwise quiet, or 2374 * - when operating in adhoc mode so the 802.11 layer creates 2375 * node table entries for peers, 2376 * - when scanning 2377 * - when doing s/w beacon miss (e.g. for ap+sta) 2378 * - when operating in ap mode in 11g to detect overlapping bss that 2379 * require protection 2380 * - when operating in mesh mode to detect neighbors 2381 * o accept control frames: 2382 * - when in monitor mode 2383 * XXX BAR frames for 11n 2384 * XXX HT protection for 11n 2385 */ 2386 static u_int32_t 2387 ath_calcrxfilter(struct ath_softc *sc) 2388 { 2389 struct ifnet *ifp = sc->sc_ifp; 2390 struct ieee80211com *ic = ifp->if_l2com; 2391 u_int32_t rfilt; 2392 2393 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 2394 if (!sc->sc_needmib && !sc->sc_scanning) 2395 rfilt |= HAL_RX_FILTER_PHYERR; 2396 if (ic->ic_opmode != IEEE80211_M_STA) 2397 rfilt |= HAL_RX_FILTER_PROBEREQ; 2398 /* XXX ic->ic_monvaps != 0? */ 2399 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 2400 rfilt |= HAL_RX_FILTER_PROM; 2401 if (ic->ic_opmode == IEEE80211_M_STA || 2402 ic->ic_opmode == IEEE80211_M_IBSS || 2403 sc->sc_swbmiss || sc->sc_scanning) 2404 rfilt |= HAL_RX_FILTER_BEACON; 2405 /* 2406 * NB: We don't recalculate the rx filter when 2407 * ic_protmode changes; otherwise we could do 2408 * this only when ic_protmode != NONE. 2409 */ 2410 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 2411 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 2412 rfilt |= HAL_RX_FILTER_BEACON; 2413 if (sc->sc_nmeshvaps) { 2414 rfilt |= HAL_RX_FILTER_BEACON; 2415 if (sc->sc_hasbmatch) 2416 rfilt |= HAL_RX_FILTER_BSSID; 2417 else 2418 rfilt |= HAL_RX_FILTER_PROM; 2419 } 2420 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2421 rfilt |= HAL_RX_FILTER_CONTROL; 2422 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 2423 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 2424 return rfilt; 2425 } 2426 2427 static void 2428 ath_update_promisc(struct ifnet *ifp) 2429 { 2430 struct ath_softc *sc = ifp->if_softc; 2431 u_int32_t rfilt; 2432 2433 /* configure rx filter */ 2434 rfilt = ath_calcrxfilter(sc); 2435 ath_hal_setrxfilter(sc->sc_ah, rfilt); 2436 2437 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt); 2438 } 2439 2440 static void 2441 ath_update_mcast(struct ifnet *ifp) 2442 { 2443 struct ath_softc *sc = ifp->if_softc; 2444 u_int32_t mfilt[2]; 2445 2446 /* calculate and install multicast filter */ 2447 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2448 struct ifmultiaddr *ifma; 2449 /* 2450 * Merge multicast addresses to form the hardware filter. 2451 */ 2452 mfilt[0] = mfilt[1] = 0; 2453 #ifdef __FreeBSD__ 2454 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */ 2455 #endif 2456 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2457 caddr_t dl; 2458 u_int32_t val; 2459 u_int8_t pos; 2460 2461 /* calculate XOR of eight 6bit values */ 2462 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 2463 val = LE_READ_4(dl + 0); 2464 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2465 val = LE_READ_4(dl + 3); 2466 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2467 pos &= 0x3f; 2468 mfilt[pos / 32] |= (1 << (pos % 32)); 2469 } 2470 #ifdef __FreeBSD__ 2471 if_maddr_runlock(ifp); 2472 #endif 2473 } else 2474 mfilt[0] = mfilt[1] = ~0; 2475 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]); 2476 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n", 2477 __func__, mfilt[0], mfilt[1]); 2478 } 2479 2480 static void 2481 ath_mode_init(struct ath_softc *sc) 2482 { 2483 struct ifnet *ifp = sc->sc_ifp; 2484 struct ath_hal *ah = sc->sc_ah; 2485 u_int32_t rfilt; 2486 2487 /* configure rx filter */ 2488 rfilt = ath_calcrxfilter(sc); 2489 ath_hal_setrxfilter(ah, rfilt); 2490 2491 /* configure operational mode */ 2492 ath_hal_setopmode(ah); 2493 2494 /* handle any link-level address change */ 2495 ath_hal_setmac(ah, IF_LLADDR(ifp)); 2496 2497 /* calculate and install multicast filter */ 2498 ath_update_mcast(ifp); 2499 } 2500 2501 /* 2502 * Set the slot time based on the current setting. 2503 */ 2504 static void 2505 ath_setslottime(struct ath_softc *sc) 2506 { 2507 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2508 struct ath_hal *ah = sc->sc_ah; 2509 u_int usec; 2510 2511 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan)) 2512 usec = 13; 2513 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan)) 2514 usec = 21; 2515 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 2516 /* honor short/long slot time only in 11g */ 2517 /* XXX shouldn't honor on pure g or turbo g channel */ 2518 if (ic->ic_flags & IEEE80211_F_SHSLOT) 2519 usec = HAL_SLOT_TIME_9; 2520 else 2521 usec = HAL_SLOT_TIME_20; 2522 } else 2523 usec = HAL_SLOT_TIME_9; 2524 2525 DPRINTF(sc, ATH_DEBUG_RESET, 2526 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n", 2527 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags, 2528 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec); 2529 2530 ath_hal_setslottime(ah, usec); 2531 sc->sc_updateslot = OK; 2532 } 2533 2534 /* 2535 * Callback from the 802.11 layer to update the 2536 * slot time based on the current setting. 2537 */ 2538 static void 2539 ath_updateslot(struct ifnet *ifp) 2540 { 2541 struct ath_softc *sc = ifp->if_softc; 2542 struct ieee80211com *ic = ifp->if_l2com; 2543 2544 /* 2545 * When not coordinating the BSS, change the hardware 2546 * immediately. For other operation we defer the change 2547 * until beacon updates have propagated to the stations. 2548 */ 2549 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2550 ic->ic_opmode == IEEE80211_M_MBSS) 2551 sc->sc_updateslot = UPDATE; 2552 else 2553 ath_setslottime(sc); 2554 } 2555 2556 /* 2557 * Setup a h/w transmit queue for beacons. 2558 */ 2559 static int 2560 ath_beaconq_setup(struct ath_hal *ah) 2561 { 2562 HAL_TXQ_INFO qi; 2563 2564 memset(&qi, 0, sizeof(qi)); 2565 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2566 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2567 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2568 /* NB: for dynamic turbo, don't enable any other interrupts */ 2569 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 2570 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 2571 } 2572 2573 /* 2574 * Setup the transmit queue parameters for the beacon queue. 2575 */ 2576 static int 2577 ath_beaconq_config(struct ath_softc *sc) 2578 { 2579 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 2580 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2581 struct ath_hal *ah = sc->sc_ah; 2582 HAL_TXQ_INFO qi; 2583 2584 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 2585 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 2586 ic->ic_opmode == IEEE80211_M_MBSS) { 2587 /* 2588 * Always burst out beacon and CAB traffic. 2589 */ 2590 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 2591 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 2592 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 2593 } else { 2594 struct wmeParams *wmep = 2595 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 2596 /* 2597 * Adhoc mode; important thing is to use 2x cwmin. 2598 */ 2599 qi.tqi_aifs = wmep->wmep_aifsn; 2600 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2601 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2602 } 2603 2604 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 2605 device_printf(sc->sc_dev, "unable to update parameters for " 2606 "beacon hardware queue!\n"); 2607 return 0; 2608 } else { 2609 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 2610 return 1; 2611 } 2612 #undef ATH_EXPONENT_TO_VALUE 2613 } 2614 2615 /* 2616 * Allocate and setup an initial beacon frame. 2617 */ 2618 static int 2619 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 2620 { 2621 struct ieee80211vap *vap = ni->ni_vap; 2622 struct ath_vap *avp = ATH_VAP(vap); 2623 struct ath_buf *bf; 2624 struct mbuf *m; 2625 int error; 2626 2627 bf = avp->av_bcbuf; 2628 if (bf->bf_m != NULL) { 2629 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2630 m_freem(bf->bf_m); 2631 bf->bf_m = NULL; 2632 } 2633 if (bf->bf_node != NULL) { 2634 ieee80211_free_node(bf->bf_node); 2635 bf->bf_node = NULL; 2636 } 2637 2638 /* 2639 * NB: the beacon data buffer must be 32-bit aligned; 2640 * we assume the mbuf routines will return us something 2641 * with this alignment (perhaps should assert). 2642 */ 2643 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 2644 if (m == NULL) { 2645 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 2646 sc->sc_stats.ast_be_nombuf++; 2647 return ENOMEM; 2648 } 2649 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2650 bf->bf_segs, 1, &bf->bf_nseg, 2651 BUS_DMA_NOWAIT); 2652 if (error != 0) { 2653 device_printf(sc->sc_dev, 2654 "%s: cannot map mbuf, bus_dmamap_load_mbuf_segment returns %d\n", 2655 __func__, error); 2656 m_freem(m); 2657 return error; 2658 } 2659 2660 /* 2661 * Calculate a TSF adjustment factor required for staggered 2662 * beacons. Note that we assume the format of the beacon 2663 * frame leaves the tstamp field immediately following the 2664 * header. 2665 */ 2666 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 2667 uint64_t tsfadjust; 2668 struct ieee80211_frame *wh; 2669 2670 /* 2671 * The beacon interval is in TU's; the TSF is in usecs. 2672 * We figure out how many TU's to add to align the timestamp 2673 * then convert to TSF units and handle byte swapping before 2674 * inserting it in the frame. The hardware will then add this 2675 * each time a beacon frame is sent. Note that we align vap's 2676 * 1..N and leave vap 0 untouched. This means vap 0 has a 2677 * timestamp in one beacon interval while the others get a 2678 * timstamp aligned to the next interval. 2679 */ 2680 tsfadjust = ni->ni_intval * 2681 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 2682 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 2683 2684 DPRINTF(sc, ATH_DEBUG_BEACON, 2685 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 2686 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 2687 avp->av_bslot, ni->ni_intval, 2688 (unsigned long long) le64toh(tsfadjust)); 2689 2690 wh = mtod(m, struct ieee80211_frame *); 2691 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 2692 } 2693 bf->bf_m = m; 2694 bf->bf_node = ieee80211_ref_node(ni); 2695 2696 return 0; 2697 } 2698 2699 /* 2700 * Setup the beacon frame for transmit. 2701 */ 2702 static void 2703 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 2704 { 2705 #define USE_SHPREAMBLE(_ic) \ 2706 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 2707 == IEEE80211_F_SHPREAMBLE) 2708 struct ieee80211_node *ni = bf->bf_node; 2709 struct ieee80211com *ic = ni->ni_ic; 2710 struct mbuf *m = bf->bf_m; 2711 struct ath_hal *ah = sc->sc_ah; 2712 struct ath_desc *ds; 2713 int flags, antenna; 2714 const HAL_RATE_TABLE *rt; 2715 u_int8_t rix, rate; 2716 2717 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 2718 __func__, m, m->m_len); 2719 2720 /* setup descriptors */ 2721 ds = bf->bf_desc; 2722 2723 flags = HAL_TXDESC_NOACK; 2724 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 2725 ds->ds_link = bf->bf_daddr; /* self-linked */ 2726 flags |= HAL_TXDESC_VEOL; 2727 /* 2728 * Let hardware handle antenna switching. 2729 */ 2730 antenna = sc->sc_txantenna; 2731 } else { 2732 ds->ds_link = 0; 2733 /* 2734 * Switch antenna every 4 beacons. 2735 * XXX assumes two antenna 2736 */ 2737 if (sc->sc_txantenna != 0) 2738 antenna = sc->sc_txantenna; 2739 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 2740 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 2741 else 2742 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 2743 } 2744 2745 KASSERT(bf->bf_nseg == 1, 2746 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 2747 ds->ds_data = bf->bf_segs[0].ds_addr; 2748 /* 2749 * Calculate rate code. 2750 * XXX everything at min xmit rate 2751 */ 2752 rix = 0; 2753 rt = sc->sc_currates; 2754 rate = rt->info[rix].rateCode; 2755 if (USE_SHPREAMBLE(ic)) 2756 rate |= rt->info[rix].shortPreamble; 2757 ath_hal_setuptxdesc(ah, ds 2758 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 2759 , sizeof(struct ieee80211_frame)/* header length */ 2760 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 2761 , ni->ni_txpower /* txpower XXX */ 2762 , rate, 1 /* series 0 rate/tries */ 2763 , HAL_TXKEYIX_INVALID /* no encryption */ 2764 , antenna /* antenna mode */ 2765 , flags /* no ack, veol for beacons */ 2766 , 0 /* rts/cts rate */ 2767 , 0 /* rts/cts duration */ 2768 ); 2769 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 2770 ath_hal_filltxdesc(ah, ds 2771 , roundup(m->m_len, 4) /* buffer length */ 2772 , AH_TRUE /* first segment */ 2773 , AH_TRUE /* last segment */ 2774 , ds /* first descriptor */ 2775 ); 2776 #if 0 2777 ath_desc_swap(ds); 2778 #endif 2779 #undef USE_SHPREAMBLE 2780 } 2781 2782 static void 2783 ath_beacon_update(struct ieee80211vap *vap, int item) 2784 { 2785 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 2786 2787 setbit(bo->bo_flags, item); 2788 } 2789 2790 /* 2791 * Append the contents of src to dst; both queues 2792 * are assumed to be locked. 2793 */ 2794 static void 2795 ath_txqmove(struct ath_txq *dst, struct ath_txq *src) 2796 { 2797 STAILQ_CONCAT(&dst->axq_q, &src->axq_q); 2798 if (src->axq_depth) 2799 dst->axq_link = src->axq_link; 2800 src->axq_link = NULL; 2801 dst->axq_depth += src->axq_depth; 2802 src->axq_depth = 0; 2803 } 2804 2805 /* 2806 * Transmit a beacon frame at SWBA. Dynamic updates to the 2807 * frame contents are done as needed and the slot time is 2808 * also adjusted based on current state. 2809 */ 2810 static void 2811 ath_beacon_proc(void *arg, int pending) 2812 { 2813 struct ath_softc *sc = arg; 2814 struct ath_hal *ah = sc->sc_ah; 2815 struct ieee80211vap *vap; 2816 struct ath_buf *bf; 2817 int slot, otherant; 2818 uint32_t bfaddr; 2819 2820 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 2821 __func__, pending); 2822 /* 2823 * Check if the previous beacon has gone out. If 2824 * not don't try to post another, skip this period 2825 * and wait for the next. Missed beacons indicate 2826 * a problem and should not occur. If we miss too 2827 * many consecutive beacons reset the device. 2828 */ 2829 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 2830 sc->sc_bmisscount++; 2831 DPRINTF(sc, ATH_DEBUG_BEACON, 2832 "%s: missed %u consecutive beacons\n", 2833 __func__, sc->sc_bmisscount); 2834 if (sc->sc_bmisscount >= ath_bstuck_threshold) 2835 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 2836 return; 2837 } 2838 if (sc->sc_bmisscount != 0) { 2839 DPRINTF(sc, ATH_DEBUG_BEACON, 2840 "%s: resume beacon xmit after %u misses\n", 2841 __func__, sc->sc_bmisscount); 2842 sc->sc_bmisscount = 0; 2843 } 2844 2845 /* 2846 * Stop any current dma before messing with the beacon linkages. 2847 */ 2848 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 2849 DPRINTF(sc, ATH_DEBUG_ANY, 2850 "%s: beacon queue %u did not stop?\n", 2851 __func__, sc->sc_bhalq); 2852 } 2853 2854 if (sc->sc_stagbeacons) { /* staggered beacons */ 2855 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2856 uint32_t tsftu; 2857 2858 tsftu = ath_hal_gettsf32(ah) >> 10; 2859 /* XXX lintval */ 2860 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 2861 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 2862 bfaddr = 0; 2863 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2864 bf = ath_beacon_generate(sc, vap); 2865 if (bf != NULL) 2866 bfaddr = bf->bf_daddr; 2867 } 2868 } else { /* burst'd beacons */ 2869 uint32_t *bflink = &bfaddr; 2870 2871 for (slot = 0; slot < ATH_BCBUF; slot++) { 2872 vap = sc->sc_bslot[slot]; 2873 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 2874 bf = ath_beacon_generate(sc, vap); 2875 if (bf != NULL) { 2876 *bflink = bf->bf_daddr; 2877 bflink = &bf->bf_desc->ds_link; 2878 } 2879 } 2880 } 2881 *bflink = 0; /* terminate list */ 2882 } 2883 2884 /* 2885 * Handle slot time change when a non-ERP station joins/leaves 2886 * an 11g network. The 802.11 layer notifies us via callback, 2887 * we mark updateslot, then wait one beacon before effecting 2888 * the change. This gives associated stations at least one 2889 * beacon interval to note the state change. 2890 */ 2891 /* XXX locking */ 2892 if (sc->sc_updateslot == UPDATE) { 2893 sc->sc_updateslot = COMMIT; /* commit next beacon */ 2894 sc->sc_slotupdate = slot; 2895 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 2896 ath_setslottime(sc); /* commit change to h/w */ 2897 2898 /* 2899 * Check recent per-antenna transmit statistics and flip 2900 * the default antenna if noticeably more frames went out 2901 * on the non-default antenna. 2902 * XXX assumes 2 anntenae 2903 */ 2904 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 2905 otherant = sc->sc_defant & 1 ? 2 : 1; 2906 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 2907 ath_setdefantenna(sc, otherant); 2908 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 2909 } 2910 2911 if (bfaddr != 0) { 2912 /* NB: cabq traffic should already be queued and primed */ 2913 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 2914 sc->sc_stats.ast_be_xmit++; 2915 ath_hal_txstart(ah, sc->sc_bhalq); 2916 } 2917 /* else no beacon will be generated */ 2918 } 2919 2920 static struct ath_buf * 2921 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 2922 { 2923 struct ath_vap *avp = ATH_VAP(vap); 2924 struct ath_txq *cabq = sc->sc_cabq; 2925 struct ath_buf *bf; 2926 struct mbuf *m; 2927 int nmcastq, error; 2928 2929 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 2930 ("not running, state %d", vap->iv_state)); 2931 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 2932 2933 /* 2934 * Update dynamic beacon contents. If this returns 2935 * non-zero then we need to remap the memory because 2936 * the beacon frame changed size (probably because 2937 * of the TIM bitmap). 2938 */ 2939 bf = avp->av_bcbuf; 2940 m = bf->bf_m; 2941 nmcastq = avp->av_mcastq.axq_depth; 2942 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 2943 /* XXX too conservative? */ 2944 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2945 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 2946 bf->bf_segs, 1, &bf->bf_nseg, 2947 BUS_DMA_NOWAIT); 2948 if (error != 0) { 2949 if_printf(vap->iv_ifp, 2950 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 2951 __func__, error); 2952 return NULL; 2953 } 2954 } 2955 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 2956 DPRINTF(sc, ATH_DEBUG_BEACON, 2957 "%s: cabq did not drain, mcastq %u cabq %u\n", 2958 __func__, nmcastq, cabq->axq_depth); 2959 sc->sc_stats.ast_cabq_busy++; 2960 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 2961 /* 2962 * CABQ traffic from a previous vap is still pending. 2963 * We must drain the q before this beacon frame goes 2964 * out as otherwise this vap's stations will get cab 2965 * frames from a different vap. 2966 * XXX could be slow causing us to miss DBA 2967 */ 2968 ath_tx_draintxq(sc, cabq); 2969 } 2970 } 2971 ath_beacon_setup(sc, bf); 2972 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 2973 2974 /* 2975 * Enable the CAB queue before the beacon queue to 2976 * insure cab frames are triggered by this beacon. 2977 */ 2978 if (avp->av_boff.bo_tim[4] & 1) { 2979 struct ath_hal *ah = sc->sc_ah; 2980 2981 /* NB: only at DTIM */ 2982 if (nmcastq) { 2983 struct ath_buf *bfm; 2984 int qbusy; 2985 2986 /* 2987 * Move frames from the s/w mcast q to the h/w cab q. 2988 * XXX MORE_DATA bit 2989 */ 2990 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q); 2991 qbusy = ath_hal_txqenabled(ah, cabq->axq_qnum); 2992 if (qbusy == 0) { 2993 if (cabq->axq_link != NULL) { 2994 cpu_sfence(); 2995 *cabq->axq_link = bfm->bf_daddr; 2996 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 2997 } else { 2998 cpu_sfence(); 2999 ath_hal_puttxbuf(ah, cabq->axq_qnum, 3000 bfm->bf_daddr); 3001 } 3002 } else { 3003 if (cabq->axq_link != NULL) { 3004 cpu_sfence(); 3005 *cabq->axq_link = bfm->bf_daddr; 3006 } 3007 cabq->axq_flags |= ATH_TXQ_PUTPENDING; 3008 } 3009 ath_txqmove(cabq, &avp->av_mcastq); 3010 3011 sc->sc_stats.ast_cabq_xmit += nmcastq; 3012 } 3013 /* NB: gated by beacon so safe to start here */ 3014 ath_hal_txstart(ah, cabq->axq_qnum); 3015 } 3016 return bf; 3017 } 3018 3019 static void 3020 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 3021 { 3022 struct ath_vap *avp = ATH_VAP(vap); 3023 struct ath_hal *ah = sc->sc_ah; 3024 struct ath_buf *bf; 3025 struct mbuf *m; 3026 int error; 3027 3028 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 3029 3030 /* 3031 * Update dynamic beacon contents. If this returns 3032 * non-zero then we need to remap the memory because 3033 * the beacon frame changed size (probably because 3034 * of the TIM bitmap). 3035 */ 3036 bf = avp->av_bcbuf; 3037 m = bf->bf_m; 3038 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 3039 /* XXX too conservative? */ 3040 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3041 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 3042 bf->bf_segs, 1, &bf->bf_nseg, 3043 BUS_DMA_NOWAIT); 3044 if (error != 0) { 3045 if_printf(vap->iv_ifp, 3046 "%s: bus_dmamap_load_mbuf_segment failed, error %u\n", 3047 __func__, error); 3048 return; 3049 } 3050 } 3051 ath_beacon_setup(sc, bf); 3052 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3053 3054 /* NB: caller is known to have already stopped tx dma */ 3055 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 3056 ath_hal_txstart(ah, sc->sc_bhalq); 3057 } 3058 3059 /* 3060 * Reset the hardware after detecting beacons have stopped. 3061 */ 3062 static void 3063 ath_bstuck_task(void *arg, int pending) 3064 { 3065 struct ath_softc *sc = arg; 3066 struct ifnet *ifp = sc->sc_ifp; 3067 3068 wlan_serialize_enter(); 3069 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 3070 sc->sc_bmisscount); 3071 sc->sc_stats.ast_bstuck++; 3072 ath_reset(ifp); 3073 wlan_serialize_exit(); 3074 } 3075 3076 /* 3077 * Reclaim beacon resources and return buffer to the pool. 3078 */ 3079 static void 3080 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 3081 { 3082 3083 if (bf->bf_m != NULL) { 3084 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3085 m_freem(bf->bf_m); 3086 bf->bf_m = NULL; 3087 } 3088 if (bf->bf_node != NULL) { 3089 ieee80211_free_node(bf->bf_node); 3090 bf->bf_node = NULL; 3091 } 3092 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 3093 } 3094 3095 /* 3096 * Reclaim beacon resources. 3097 */ 3098 static void 3099 ath_beacon_free(struct ath_softc *sc) 3100 { 3101 struct ath_buf *bf; 3102 3103 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 3104 if (bf->bf_m != NULL) { 3105 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3106 m_freem(bf->bf_m); 3107 bf->bf_m = NULL; 3108 } 3109 if (bf->bf_node != NULL) { 3110 ieee80211_free_node(bf->bf_node); 3111 bf->bf_node = NULL; 3112 } 3113 } 3114 } 3115 3116 /* 3117 * Configure the beacon and sleep timers. 3118 * 3119 * When operating as an AP this resets the TSF and sets 3120 * up the hardware to notify us when we need to issue beacons. 3121 * 3122 * When operating in station mode this sets up the beacon 3123 * timers according to the timestamp of the last received 3124 * beacon and the current TSF, configures PCF and DTIM 3125 * handling, programs the sleep registers so the hardware 3126 * will wakeup in time to receive beacons, and configures 3127 * the beacon miss handling so we'll receive a BMISS 3128 * interrupt when we stop seeing beacons from the AP 3129 * we've associated with. 3130 */ 3131 static void 3132 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 3133 { 3134 #define TSF_TO_TU(_h,_l) \ 3135 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 3136 #define FUDGE 2 3137 struct ath_hal *ah = sc->sc_ah; 3138 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3139 struct ieee80211_node *ni; 3140 u_int32_t nexttbtt, intval, tsftu; 3141 u_int64_t tsf; 3142 3143 if (vap == NULL) 3144 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 3145 ni = vap->iv_bss; 3146 3147 /* extract tstamp from last beacon and convert to TU */ 3148 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 3149 LE_READ_4(ni->ni_tstamp.data)); 3150 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3151 ic->ic_opmode == IEEE80211_M_MBSS) { 3152 /* 3153 * For multi-bss ap/mesh support beacons are either staggered 3154 * evenly over N slots or burst together. For the former 3155 * arrange for the SWBA to be delivered for each slot. 3156 * Slots that are not occupied will generate nothing. 3157 */ 3158 /* NB: the beacon interval is kept internally in TU's */ 3159 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3160 if (sc->sc_stagbeacons) 3161 intval /= ATH_BCBUF; 3162 } else { 3163 /* NB: the beacon interval is kept internally in TU's */ 3164 intval = ni->ni_intval & HAL_BEACON_PERIOD; 3165 } 3166 if (nexttbtt == 0) /* e.g. for ap mode */ 3167 nexttbtt = intval; 3168 else if (intval) /* NB: can be 0 for monitor mode */ 3169 nexttbtt = roundup(nexttbtt, intval); 3170 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 3171 __func__, nexttbtt, intval, ni->ni_intval); 3172 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 3173 HAL_BEACON_STATE bs; 3174 int dtimperiod, dtimcount; 3175 int cfpperiod, cfpcount; 3176 3177 /* 3178 * Setup dtim and cfp parameters according to 3179 * last beacon we received (which may be none). 3180 */ 3181 dtimperiod = ni->ni_dtim_period; 3182 if (dtimperiod <= 0) /* NB: 0 if not known */ 3183 dtimperiod = 1; 3184 dtimcount = ni->ni_dtim_count; 3185 if (dtimcount >= dtimperiod) /* NB: sanity check */ 3186 dtimcount = 0; /* XXX? */ 3187 cfpperiod = 1; /* NB: no PCF support yet */ 3188 cfpcount = 0; 3189 /* 3190 * Pull nexttbtt forward to reflect the current 3191 * TSF and calculate dtim+cfp state for the result. 3192 */ 3193 tsf = ath_hal_gettsf64(ah); 3194 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3195 do { 3196 nexttbtt += intval; 3197 if (--dtimcount < 0) { 3198 dtimcount = dtimperiod - 1; 3199 if (--cfpcount < 0) 3200 cfpcount = cfpperiod - 1; 3201 } 3202 } while (nexttbtt < tsftu); 3203 memset(&bs, 0, sizeof(bs)); 3204 bs.bs_intval = intval; 3205 bs.bs_nexttbtt = nexttbtt; 3206 bs.bs_dtimperiod = dtimperiod*intval; 3207 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 3208 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 3209 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 3210 bs.bs_cfpmaxduration = 0; 3211 #if 0 3212 /* 3213 * The 802.11 layer records the offset to the DTIM 3214 * bitmap while receiving beacons; use it here to 3215 * enable h/w detection of our AID being marked in 3216 * the bitmap vector (to indicate frames for us are 3217 * pending at the AP). 3218 * XXX do DTIM handling in s/w to WAR old h/w bugs 3219 * XXX enable based on h/w rev for newer chips 3220 */ 3221 bs.bs_timoffset = ni->ni_timoff; 3222 #endif 3223 /* 3224 * Calculate the number of consecutive beacons to miss 3225 * before taking a BMISS interrupt. 3226 * Note that we clamp the result to at most 10 beacons. 3227 */ 3228 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 3229 if (bs.bs_bmissthreshold > 10) 3230 bs.bs_bmissthreshold = 10; 3231 else if (bs.bs_bmissthreshold <= 0) 3232 bs.bs_bmissthreshold = 1; 3233 3234 /* 3235 * Calculate sleep duration. The configuration is 3236 * given in ms. We insure a multiple of the beacon 3237 * period is used. Also, if the sleep duration is 3238 * greater than the DTIM period then it makes senses 3239 * to make it a multiple of that. 3240 * 3241 * XXX fixed at 100ms 3242 */ 3243 bs.bs_sleepduration = 3244 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 3245 if (bs.bs_sleepduration > bs.bs_dtimperiod) 3246 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 3247 3248 DPRINTF(sc, ATH_DEBUG_BEACON, 3249 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 3250 , __func__ 3251 , tsf, tsftu 3252 , bs.bs_intval 3253 , bs.bs_nexttbtt 3254 , bs.bs_dtimperiod 3255 , bs.bs_nextdtim 3256 , bs.bs_bmissthreshold 3257 , bs.bs_sleepduration 3258 , bs.bs_cfpperiod 3259 , bs.bs_cfpmaxduration 3260 , bs.bs_cfpnext 3261 , bs.bs_timoffset 3262 ); 3263 ath_hal_intrset(ah, 0); 3264 ath_hal_beacontimers(ah, &bs); 3265 sc->sc_imask |= HAL_INT_BMISS; 3266 ath_hal_intrset(ah, sc->sc_imask); 3267 } else { 3268 ath_hal_intrset(ah, 0); 3269 if (nexttbtt == intval) 3270 intval |= HAL_BEACON_RESET_TSF; 3271 if (ic->ic_opmode == IEEE80211_M_IBSS) { 3272 /* 3273 * In IBSS mode enable the beacon timers but only 3274 * enable SWBA interrupts if we need to manually 3275 * prepare beacon frames. Otherwise we use a 3276 * self-linked tx descriptor and let the hardware 3277 * deal with things. 3278 */ 3279 intval |= HAL_BEACON_ENA; 3280 if (!sc->sc_hasveol) 3281 sc->sc_imask |= HAL_INT_SWBA; 3282 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 3283 /* 3284 * Pull nexttbtt forward to reflect 3285 * the current TSF. 3286 */ 3287 tsf = ath_hal_gettsf64(ah); 3288 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 3289 do { 3290 nexttbtt += intval; 3291 } while (nexttbtt < tsftu); 3292 } 3293 ath_beaconq_config(sc); 3294 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3295 ic->ic_opmode == IEEE80211_M_MBSS) { 3296 /* 3297 * In AP/mesh mode we enable the beacon timers 3298 * and SWBA interrupts to prepare beacon frames. 3299 */ 3300 intval |= HAL_BEACON_ENA; 3301 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 3302 ath_beaconq_config(sc); 3303 } 3304 ath_hal_beaconinit(ah, nexttbtt, intval); 3305 sc->sc_bmisscount = 0; 3306 ath_hal_intrset(ah, sc->sc_imask); 3307 /* 3308 * When using a self-linked beacon descriptor in 3309 * ibss mode load it once here. 3310 */ 3311 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 3312 ath_beacon_start_adhoc(sc, vap); 3313 } 3314 sc->sc_syncbeacon = 0; 3315 #undef FUDGE 3316 #undef TSF_TO_TU 3317 } 3318 3319 static void 3320 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3321 { 3322 bus_addr_t *paddr = (bus_addr_t*) arg; 3323 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 3324 *paddr = segs->ds_addr; 3325 } 3326 3327 static int 3328 ath_descdma_setup(struct ath_softc *sc, 3329 struct ath_descdma *dd, ath_bufhead *head, 3330 const char *name, int nbuf, int ndesc) 3331 { 3332 #define DS2PHYS(_dd, _ds) \ 3333 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 3334 struct ifnet *ifp = sc->sc_ifp; 3335 struct ath_desc *ds; 3336 struct ath_buf *bf; 3337 int i, bsize, error; 3338 3339 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 3340 __func__, name, nbuf, ndesc); 3341 3342 dd->dd_name = name; 3343 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 3344 3345 /* 3346 * Setup DMA descriptor area. 3347 */ 3348 error = bus_dma_tag_create(dd->dd_dmat, /* parent */ 3349 PAGE_SIZE, 0, /* alignment, bounds */ 3350 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 3351 BUS_SPACE_MAXADDR, /* highaddr */ 3352 NULL, NULL, /* filter, filterarg */ 3353 dd->dd_desc_len, /* maxsize */ 3354 1, /* nsegments */ 3355 dd->dd_desc_len, /* maxsegsize */ 3356 BUS_DMA_ALLOCNOW, /* flags */ 3357 &dd->dd_dmat); 3358 if (error != 0) { 3359 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 3360 return error; 3361 } 3362 3363 /* allocate descriptors */ 3364 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 3365 if (error != 0) { 3366 if_printf(ifp, "unable to create dmamap for %s descriptors, " 3367 "error %u\n", dd->dd_name, error); 3368 goto fail0; 3369 } 3370 3371 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 3372 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 3373 &dd->dd_dmamap); 3374 if (error != 0) { 3375 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 3376 "error %u\n", nbuf * ndesc, dd->dd_name, error); 3377 goto fail1; 3378 } 3379 3380 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 3381 dd->dd_desc, dd->dd_desc_len, 3382 ath_load_cb, &dd->dd_desc_paddr, 3383 BUS_DMA_NOWAIT); 3384 if (error != 0) { 3385 if_printf(ifp, "unable to map %s descriptors, error %u\n", 3386 dd->dd_name, error); 3387 goto fail2; 3388 } 3389 3390 ds = dd->dd_desc; 3391 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 3392 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 3393 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 3394 3395 /* allocate rx buffers */ 3396 bsize = sizeof(struct ath_buf) * nbuf; 3397 bf = kmalloc(bsize, M_ATHDEV, M_INTWAIT | M_ZERO); 3398 dd->dd_bufptr = bf; 3399 3400 STAILQ_INIT(head); 3401 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 3402 bf->bf_desc = ds; 3403 bf->bf_daddr = DS2PHYS(dd, ds); 3404 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 3405 &bf->bf_dmamap); 3406 if (error != 0) { 3407 if_printf(ifp, "unable to create dmamap for %s " 3408 "buffer %u, error %u\n", dd->dd_name, i, error); 3409 ath_descdma_cleanup(sc, dd, head); 3410 return error; 3411 } 3412 STAILQ_INSERT_TAIL(head, bf, bf_list); 3413 } 3414 return 0; 3415 fail2: 3416 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3417 fail1: 3418 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3419 fail0: 3420 bus_dma_tag_destroy(dd->dd_dmat); 3421 memset(dd, 0, sizeof(*dd)); 3422 return error; 3423 #undef DS2PHYS 3424 } 3425 3426 static void 3427 ath_descdma_cleanup(struct ath_softc *sc, 3428 struct ath_descdma *dd, ath_bufhead *head) 3429 { 3430 struct ath_buf *bf; 3431 struct ieee80211_node *ni; 3432 3433 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 3434 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 3435 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 3436 bus_dma_tag_destroy(dd->dd_dmat); 3437 3438 STAILQ_FOREACH(bf, head, bf_list) { 3439 if (bf->bf_m) { 3440 m_freem(bf->bf_m); 3441 bf->bf_m = NULL; 3442 } 3443 if (bf->bf_dmamap != NULL) { 3444 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 3445 bf->bf_dmamap = NULL; 3446 } 3447 ni = bf->bf_node; 3448 bf->bf_node = NULL; 3449 if (ni != NULL) { 3450 /* 3451 * Reclaim node reference. 3452 */ 3453 ieee80211_free_node(ni); 3454 } 3455 } 3456 3457 STAILQ_INIT(head); 3458 kfree(dd->dd_bufptr, M_ATHDEV); 3459 memset(dd, 0, sizeof(*dd)); 3460 } 3461 3462 static int 3463 ath_desc_alloc(struct ath_softc *sc) 3464 { 3465 int error; 3466 3467 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 3468 "rx", ath_rxbuf, 1); 3469 if (error != 0) 3470 return error; 3471 3472 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 3473 "tx", ath_txbuf, ATH_TXDESC); 3474 if (error != 0) { 3475 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3476 return error; 3477 } 3478 3479 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 3480 "beacon", ATH_BCBUF, 1); 3481 if (error != 0) { 3482 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3483 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3484 return error; 3485 } 3486 return 0; 3487 } 3488 3489 static void 3490 ath_desc_free(struct ath_softc *sc) 3491 { 3492 3493 if (sc->sc_bdma.dd_desc_len != 0) 3494 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 3495 if (sc->sc_txdma.dd_desc_len != 0) 3496 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 3497 if (sc->sc_rxdma.dd_desc_len != 0) 3498 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 3499 } 3500 3501 static struct ieee80211_node * 3502 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 3503 { 3504 struct ieee80211com *ic = vap->iv_ic; 3505 struct ath_softc *sc = ic->ic_ifp->if_softc; 3506 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 3507 struct ath_node *an; 3508 3509 an = kmalloc(space, M_80211_NODE, M_INTWAIT|M_ZERO); 3510 ath_rate_node_init(sc, an); 3511 3512 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 3513 return &an->an_node; 3514 } 3515 3516 static void 3517 ath_node_free(struct ieee80211_node *ni) 3518 { 3519 struct ieee80211com *ic = ni->ni_ic; 3520 struct ath_softc *sc = ic->ic_ifp->if_softc; 3521 3522 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 3523 3524 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 3525 sc->sc_node_free(ni); 3526 } 3527 3528 static void 3529 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) 3530 { 3531 struct ieee80211com *ic = ni->ni_ic; 3532 struct ath_softc *sc = ic->ic_ifp->if_softc; 3533 struct ath_hal *ah = sc->sc_ah; 3534 3535 *rssi = ic->ic_node_getrssi(ni); 3536 if (ni->ni_chan != IEEE80211_CHAN_ANYC) 3537 *noise = ath_hal_getchannoise(ah, ni->ni_chan); 3538 else 3539 *noise = -95; /* nominally correct */ 3540 } 3541 3542 static int 3543 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 3544 { 3545 struct ath_hal *ah = sc->sc_ah; 3546 int error; 3547 struct mbuf *m; 3548 struct ath_desc *ds; 3549 3550 m = bf->bf_m; 3551 if (m == NULL) { 3552 /* 3553 * NB: by assigning a page to the rx dma buffer we 3554 * implicitly satisfy the Atheros requirement that 3555 * this buffer be cache-line-aligned and sized to be 3556 * multiple of the cache line size. Not doing this 3557 * causes weird stuff to happen (for the 5210 at least). 3558 */ 3559 m = m_getcl(MB_WAIT, MT_DATA, M_PKTHDR); 3560 if (m == NULL) { 3561 kprintf("ath_rxbuf_init: no mbuf\n"); 3562 DPRINTF(sc, ATH_DEBUG_ANY, 3563 "%s: no mbuf/cluster\n", __func__); 3564 sc->sc_stats.ast_rx_nombuf++; 3565 return ENOMEM; 3566 } 3567 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 3568 3569 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 3570 bf->bf_dmamap, m, 3571 bf->bf_segs, 1, &bf->bf_nseg, 3572 BUS_DMA_NOWAIT); 3573 if (error != 0) { 3574 DPRINTF(sc, ATH_DEBUG_ANY, 3575 "%s: bus_dmamap_load_mbuf_segment failed; error %d\n", 3576 __func__, error); 3577 sc->sc_stats.ast_rx_busdma++; 3578 m_freem(m); 3579 return error; 3580 } 3581 KASSERT(bf->bf_nseg == 1, 3582 ("multi-segment packet; nseg %u", bf->bf_nseg)); 3583 bf->bf_m = m; 3584 } 3585 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 3586 3587 /* 3588 * Setup descriptors. For receive we always terminate 3589 * the descriptor list with a self-linked entry so we'll 3590 * not get overrun under high load (as can happen with a 3591 * 5212 when ANI processing enables PHY error frames). 3592 * 3593 * To insure the last descriptor is self-linked we create 3594 * each descriptor as self-linked and add it to the end. As 3595 * each additional descriptor is added the previous self-linked 3596 * entry is ``fixed'' naturally. This should be safe even 3597 * if DMA is happening. When processing RX interrupts we 3598 * never remove/process the last, self-linked, entry on the 3599 * descriptor list. This insures the hardware always has 3600 * someplace to write a new frame. 3601 */ 3602 ds = bf->bf_desc; 3603 ds->ds_link = bf->bf_daddr; /* link to self */ 3604 ds->ds_data = bf->bf_segs[0].ds_addr; 3605 ath_hal_setuprxdesc(ah, ds 3606 , m->m_len /* buffer size */ 3607 , 0 3608 ); 3609 3610 if (sc->sc_rxlink != NULL) 3611 *sc->sc_rxlink = bf->bf_daddr; 3612 sc->sc_rxlink = &ds->ds_link; 3613 return 0; 3614 } 3615 3616 /* 3617 * Extend 15-bit time stamp from rx descriptor to 3618 * a full 64-bit TSF using the specified TSF. 3619 */ 3620 static __inline u_int64_t 3621 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 3622 { 3623 if ((tsf & 0x7fff) < rstamp) 3624 tsf -= 0x8000; 3625 return ((tsf &~ 0x7fff) | rstamp); 3626 } 3627 3628 /* 3629 * Intercept management frames to collect beacon rssi data 3630 * and to do ibss merges. 3631 */ 3632 static void 3633 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 3634 int subtype, int rssi, int nf) 3635 { 3636 struct ieee80211vap *vap = ni->ni_vap; 3637 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 3638 3639 /* 3640 * Call up first so subsequent work can use information 3641 * potentially stored in the node (e.g. for ibss merge). 3642 */ 3643 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 3644 switch (subtype) { 3645 case IEEE80211_FC0_SUBTYPE_BEACON: 3646 /* update rssi statistics for use by the hal */ 3647 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 3648 if (sc->sc_syncbeacon && 3649 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 3650 /* 3651 * Resync beacon timers using the tsf of the beacon 3652 * frame we just received. 3653 */ 3654 ath_beacon_config(sc, vap); 3655 } 3656 /* fall thru... */ 3657 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 3658 if (vap->iv_opmode == IEEE80211_M_IBSS && 3659 vap->iv_state == IEEE80211_S_RUN) { 3660 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 3661 u_int64_t tsf = ath_extend_tsf(rstamp, 3662 ath_hal_gettsf64(sc->sc_ah)); 3663 /* 3664 * Handle ibss merge as needed; check the tsf on the 3665 * frame before attempting the merge. The 802.11 spec 3666 * says the station should change it's bssid to match 3667 * the oldest station with the same ssid, where oldest 3668 * is determined by the tsf. Note that hardware 3669 * reconfiguration happens through callback to 3670 * ath_newstate as the state machine will go from 3671 * RUN -> RUN when this happens. 3672 */ 3673 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 3674 DPRINTF(sc, ATH_DEBUG_STATE, 3675 "ibss merge, rstamp %u tsf %ju " 3676 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 3677 (uintmax_t)ni->ni_tstamp.tsf); 3678 (void) ieee80211_ibss_merge(ni); 3679 } 3680 } 3681 break; 3682 } 3683 } 3684 3685 /* 3686 * Set the default antenna. 3687 */ 3688 static void 3689 ath_setdefantenna(struct ath_softc *sc, u_int antenna) 3690 { 3691 struct ath_hal *ah = sc->sc_ah; 3692 3693 /* XXX block beacon interrupts */ 3694 ath_hal_setdefantenna(ah, antenna); 3695 if (sc->sc_defant != antenna) 3696 sc->sc_stats.ast_ant_defswitch++; 3697 sc->sc_defant = antenna; 3698 sc->sc_rxotherant = 0; 3699 } 3700 3701 static void 3702 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 3703 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 3704 { 3705 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 3706 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 3707 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 3708 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 3709 struct ath_softc *sc = ifp->if_softc; 3710 const HAL_RATE_TABLE *rt; 3711 uint8_t rix; 3712 3713 rt = sc->sc_currates; 3714 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3715 rix = rt->rateCodeToIndex[rs->rs_rate]; 3716 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 3717 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 3718 #ifdef AH_SUPPORT_AR5416 3719 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 3720 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 3721 struct ieee80211com *ic = ifp->if_l2com; 3722 3723 if ((rs->rs_flags & HAL_RX_2040) == 0) 3724 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 3725 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 3726 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 3727 else 3728 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 3729 if ((rs->rs_flags & HAL_RX_GI) == 0) 3730 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 3731 } 3732 #endif 3733 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf)); 3734 if (rs->rs_status & HAL_RXERR_CRC) 3735 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 3736 /* XXX propagate other error flags from descriptor */ 3737 sc->sc_rx_th.wr_antnoise = nf; 3738 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 3739 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 3740 #undef CHAN_HT 3741 #undef CHAN_HT20 3742 #undef CHAN_HT40U 3743 #undef CHAN_HT40D 3744 } 3745 3746 static void 3747 ath_handle_micerror(struct ieee80211com *ic, 3748 struct ieee80211_frame *wh, int keyix) 3749 { 3750 struct ieee80211_node *ni; 3751 3752 /* XXX recheck MIC to deal w/ chips that lie */ 3753 /* XXX discard MIC errors on !data frames */ 3754 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 3755 if (ni != NULL) { 3756 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 3757 ieee80211_free_node(ni); 3758 } 3759 } 3760 3761 static void 3762 ath_rx_task(void *arg, int npending) 3763 { 3764 #define PA2DESC(_sc, _pa) \ 3765 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3766 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3767 struct ath_softc *sc = arg; 3768 struct ath_buf *bf; 3769 struct ifnet *ifp; 3770 struct ieee80211com *ic; 3771 struct ath_hal *ah; 3772 struct ath_desc *ds; 3773 struct ath_rx_status *rs; 3774 struct mbuf *m; 3775 struct ieee80211_node *ni; 3776 int len, type, ngood; 3777 u_int phyerr; 3778 HAL_STATUS status; 3779 int16_t nf; 3780 u_int64_t tsf; 3781 3782 wlan_serialize_enter(); 3783 ifp = sc->sc_ifp; 3784 ic = ifp->if_l2com; 3785 ah = sc->sc_ah; 3786 3787 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 3788 ngood = 0; 3789 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 3790 sc->sc_stats.ast_rx_noise = nf; 3791 tsf = ath_hal_gettsf64(ah); 3792 do { 3793 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3794 if (bf == NULL) { /* NB: shouldn't happen */ 3795 if_printf(ifp, "%s: no buffer!\n", __func__); 3796 break; 3797 } 3798 m = bf->bf_m; 3799 if (m == NULL) { /* NB: shouldn't happen */ 3800 /* 3801 * If mbuf allocation failed previously there 3802 * will be no mbuf; try again to re-populate it. 3803 */ 3804 /* XXX make debug msg */ 3805 if_printf(ifp, "%s: no mbuf!\n", __func__); 3806 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3807 goto rx_next; 3808 } 3809 ds = bf->bf_desc; 3810 if (ds->ds_link == bf->bf_daddr) { 3811 /* NB: never process the self-linked entry at the end */ 3812 break; 3813 } 3814 /* XXX sync descriptor memory */ 3815 /* 3816 * Must provide the virtual address of the current 3817 * descriptor, the physical address, and the virtual 3818 * address of the next descriptor in the h/w chain. 3819 * This allows the HAL to look ahead to see if the 3820 * hardware is done with a descriptor by checking the 3821 * done bit in the following descriptor and the address 3822 * of the current descriptor the DMA engine is working 3823 * on. All this is necessary because of our use of 3824 * a self-linked list to avoid rx overruns. 3825 */ 3826 rs = &bf->bf_status.ds_rxstat; 3827 status = ath_hal_rxprocdesc(ah, ds, 3828 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 3829 #ifdef ATH_DEBUG 3830 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 3831 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 3832 #endif 3833 if (status == HAL_EINPROGRESS) 3834 break; 3835 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 3836 if (rs->rs_status != 0) { 3837 if (rs->rs_status & HAL_RXERR_CRC) 3838 sc->sc_stats.ast_rx_crcerr++; 3839 if (rs->rs_status & HAL_RXERR_FIFO) 3840 sc->sc_stats.ast_rx_fifoerr++; 3841 if (rs->rs_status & HAL_RXERR_PHY) { 3842 sc->sc_stats.ast_rx_phyerr++; 3843 phyerr = rs->rs_phyerr & 0x1f; 3844 sc->sc_stats.ast_rx_phy[phyerr]++; 3845 goto rx_error; /* NB: don't count in ierrors */ 3846 } 3847 if (rs->rs_status & HAL_RXERR_DECRYPT) { 3848 /* 3849 * Decrypt error. If the error occurred 3850 * because there was no hardware key, then 3851 * let the frame through so the upper layers 3852 * can process it. This is necessary for 5210 3853 * parts which have no way to setup a ``clear'' 3854 * key cache entry. 3855 * 3856 * XXX do key cache faulting 3857 */ 3858 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 3859 goto rx_accept; 3860 sc->sc_stats.ast_rx_badcrypt++; 3861 } 3862 if (rs->rs_status & HAL_RXERR_MIC) { 3863 sc->sc_stats.ast_rx_badmic++; 3864 /* 3865 * Do minimal work required to hand off 3866 * the 802.11 header for notification. 3867 */ 3868 /* XXX frag's and qos frames */ 3869 len = rs->rs_datalen; 3870 if (len >= sizeof (struct ieee80211_frame)) { 3871 bus_dmamap_sync(sc->sc_dmat, 3872 bf->bf_dmamap, 3873 BUS_DMASYNC_POSTREAD); 3874 ath_handle_micerror(ic, 3875 mtod(m, struct ieee80211_frame *), 3876 sc->sc_splitmic ? 3877 rs->rs_keyix-32 : rs->rs_keyix); 3878 } 3879 } 3880 IFNET_STAT_INC(ifp, ierrors, 1); 3881 rx_error: 3882 /* 3883 * Cleanup any pending partial frame. 3884 */ 3885 if (sc->sc_rxpending != NULL) { 3886 m_freem(sc->sc_rxpending); 3887 sc->sc_rxpending = NULL; 3888 } 3889 /* 3890 * When a tap is present pass error frames 3891 * that have been requested. By default we 3892 * pass decrypt+mic errors but others may be 3893 * interesting (e.g. crc). 3894 */ 3895 if (ieee80211_radiotap_active(ic) && 3896 (rs->rs_status & sc->sc_monpass)) { 3897 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3898 BUS_DMASYNC_POSTREAD); 3899 /* NB: bpf needs the mbuf length setup */ 3900 len = rs->rs_datalen; 3901 m->m_pkthdr.len = m->m_len = len; 3902 ath_rx_tap(ifp, m, rs, tsf, nf); 3903 ieee80211_radiotap_rx_all(ic, m); 3904 } 3905 /* XXX pass MIC errors up for s/w reclaculation */ 3906 goto rx_next; 3907 } 3908 rx_accept: 3909 /* 3910 * Sync and unmap the frame. At this point we're 3911 * committed to passing the mbuf somewhere so clear 3912 * bf_m; this means a new mbuf must be allocated 3913 * when the rx descriptor is setup again to receive 3914 * another frame. 3915 */ 3916 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3917 BUS_DMASYNC_POSTREAD); 3918 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3919 bf->bf_m = NULL; 3920 3921 len = rs->rs_datalen; 3922 m->m_len = len; 3923 3924 if (rs->rs_more) { 3925 /* 3926 * Frame spans multiple descriptors; save 3927 * it for the next completed descriptor, it 3928 * will be used to construct a jumbogram. 3929 */ 3930 if (sc->sc_rxpending != NULL) { 3931 /* NB: max frame size is currently 2 clusters */ 3932 sc->sc_stats.ast_rx_toobig++; 3933 m_freem(sc->sc_rxpending); 3934 } 3935 m->m_pkthdr.rcvif = ifp; 3936 m->m_pkthdr.len = len; 3937 sc->sc_rxpending = m; 3938 goto rx_next; 3939 } else if (sc->sc_rxpending != NULL) { 3940 /* 3941 * This is the second part of a jumbogram, 3942 * chain it to the first mbuf, adjust the 3943 * frame length, and clear the rxpending state. 3944 */ 3945 sc->sc_rxpending->m_next = m; 3946 sc->sc_rxpending->m_pkthdr.len += len; 3947 m = sc->sc_rxpending; 3948 sc->sc_rxpending = NULL; 3949 } else { 3950 /* 3951 * Normal single-descriptor receive; setup 3952 * the rcvif and packet length. 3953 */ 3954 m->m_pkthdr.rcvif = ifp; 3955 m->m_pkthdr.len = len; 3956 } 3957 3958 IFNET_STAT_INC(ifp, ipackets, 1); 3959 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 3960 3961 /* 3962 * Populate the rx status block. When there are bpf 3963 * listeners we do the additional work to provide 3964 * complete status. Otherwise we fill in only the 3965 * material required by ieee80211_input. Note that 3966 * noise setting is filled in above. 3967 */ 3968 if (ieee80211_radiotap_active(ic)) 3969 ath_rx_tap(ifp, m, rs, tsf, nf); 3970 3971 /* 3972 * From this point on we assume the frame is at least 3973 * as large as ieee80211_frame_min; verify that. 3974 */ 3975 if (len < IEEE80211_MIN_LEN) { 3976 if (!ieee80211_radiotap_active(ic)) { 3977 DPRINTF(sc, ATH_DEBUG_RECV, 3978 "%s: short packet %d\n", __func__, len); 3979 sc->sc_stats.ast_rx_tooshort++; 3980 } else { 3981 /* NB: in particular this captures ack's */ 3982 ieee80211_radiotap_rx_all(ic, m); 3983 } 3984 m_freem(m); 3985 goto rx_next; 3986 } 3987 3988 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 3989 const HAL_RATE_TABLE *rt = sc->sc_currates; 3990 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 3991 3992 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 3993 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 3994 } 3995 3996 m_adj(m, -IEEE80211_CRC_LEN); 3997 3998 /* 3999 * Locate the node for sender, track state, and then 4000 * pass the (referenced) node up to the 802.11 layer 4001 * for its use. 4002 */ 4003 ni = ieee80211_find_rxnode_withkey(ic, 4004 mtod(m, const struct ieee80211_frame_min *), 4005 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 4006 IEEE80211_KEYIX_NONE : rs->rs_keyix); 4007 if (ni != NULL) { 4008 /* 4009 * Sending station is known, dispatch directly. 4010 */ 4011 sc->sc_lastrs = rs; 4012 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 4013 ieee80211_free_node(ni); 4014 /* 4015 * Arrange to update the last rx timestamp only for 4016 * frames from our ap when operating in station mode. 4017 * This assumes the rx key is always setup when 4018 * associated. 4019 */ 4020 if (ic->ic_opmode == IEEE80211_M_STA && 4021 rs->rs_keyix != HAL_RXKEYIX_INVALID) 4022 ngood++; 4023 } else { 4024 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 4025 } 4026 /* 4027 * Track rx rssi and do any rx antenna management. 4028 */ 4029 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 4030 if (sc->sc_diversity) { 4031 /* 4032 * When using fast diversity, change the default rx 4033 * antenna if diversity chooses the other antenna 3 4034 * times in a row. 4035 */ 4036 if (sc->sc_defant != rs->rs_antenna) { 4037 if (++sc->sc_rxotherant >= 3) 4038 ath_setdefantenna(sc, rs->rs_antenna); 4039 } else 4040 sc->sc_rxotherant = 0; 4041 } 4042 if (sc->sc_softled) { 4043 /* 4044 * Blink for any data frame. Otherwise do a 4045 * heartbeat-style blink when idle. The latter 4046 * is mainly for station mode where we depend on 4047 * periodic beacon frames to trigger the poll event. 4048 */ 4049 if (type == IEEE80211_FC0_TYPE_DATA) { 4050 const HAL_RATE_TABLE *rt = sc->sc_currates; 4051 ath_led_event(sc, 4052 rt->rateCodeToIndex[rs->rs_rate]); 4053 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 4054 ath_led_event(sc, 0); 4055 } 4056 rx_next: 4057 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 4058 } while (ath_rxbuf_init(sc, bf) == 0); 4059 4060 /* rx signal state monitoring */ 4061 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 4062 if (ngood) 4063 sc->sc_lastrx = tsf; 4064 4065 if (!ifq_is_oactive(&ifp->if_snd)) { 4066 #ifdef IEEE80211_SUPPORT_SUPERG 4067 ieee80211_ff_age_all(ic, 100); 4068 #endif 4069 if (!ifq_is_empty(&ifp->if_snd)) 4070 if_devstart(ifp); 4071 } 4072 wlan_serialize_exit(); 4073 #undef PA2DESC 4074 } 4075 4076 static void 4077 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum) 4078 { 4079 txq->axq_qnum = qnum; 4080 txq->axq_ac = 0; 4081 txq->axq_depth = 0; 4082 txq->axq_intrcnt = 0; 4083 txq->axq_link = NULL; 4084 STAILQ_INIT(&txq->axq_q); 4085 } 4086 4087 /* 4088 * Setup a h/w transmit queue. 4089 */ 4090 static struct ath_txq * 4091 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 4092 { 4093 struct ath_hal *ah = sc->sc_ah; 4094 HAL_TXQ_INFO qi; 4095 int qnum; 4096 4097 memset(&qi, 0, sizeof(qi)); 4098 qi.tqi_subtype = subtype; 4099 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 4100 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 4101 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 4102 /* 4103 * Enable interrupts only for EOL and DESC conditions. 4104 * We mark tx descriptors to receive a DESC interrupt 4105 * when a tx queue gets deep; otherwise waiting for the 4106 * EOL to reap descriptors. Note that this is done to 4107 * reduce interrupt load and this only defers reaping 4108 * descriptors, never transmitting frames. Aside from 4109 * reducing interrupts this also permits more concurrency. 4110 * The only potential downside is if the tx queue backs 4111 * up in which case the top half of the kernel may backup 4112 * due to a lack of tx descriptors. 4113 */ 4114 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE; 4115 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 4116 if (qnum == -1) { 4117 /* 4118 * NB: don't print a message, this happens 4119 * normally on parts with too few tx queues 4120 */ 4121 return NULL; 4122 } 4123 if (qnum >= NELEM(sc->sc_txq)) { 4124 device_printf(sc->sc_dev, 4125 "hal qnum %u out of range, max %zu!\n", 4126 qnum, NELEM(sc->sc_txq)); 4127 ath_hal_releasetxqueue(ah, qnum); 4128 return NULL; 4129 } 4130 if (!ATH_TXQ_SETUP(sc, qnum)) { 4131 ath_txq_init(sc, &sc->sc_txq[qnum], qnum); 4132 sc->sc_txqsetup |= 1<<qnum; 4133 } 4134 return &sc->sc_txq[qnum]; 4135 } 4136 4137 /* 4138 * Setup a hardware data transmit queue for the specified 4139 * access control. The hal may not support all requested 4140 * queues in which case it will return a reference to a 4141 * previously setup queue. We record the mapping from ac's 4142 * to h/w queues for use by ath_tx_start and also track 4143 * the set of h/w queues being used to optimize work in the 4144 * transmit interrupt handler and related routines. 4145 */ 4146 static int 4147 ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 4148 { 4149 struct ath_txq *txq; 4150 4151 if (ac >= NELEM(sc->sc_ac2q)) { 4152 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 4153 ac, NELEM(sc->sc_ac2q)); 4154 return 0; 4155 } 4156 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 4157 if (txq != NULL) { 4158 txq->axq_ac = ac; 4159 sc->sc_ac2q[ac] = txq; 4160 return 1; 4161 } else 4162 return 0; 4163 } 4164 4165 /* 4166 * Update WME parameters for a transmit queue. 4167 */ 4168 static int 4169 ath_txq_update(struct ath_softc *sc, int ac) 4170 { 4171 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 4172 #define ATH_TXOP_TO_US(v) (v<<5) 4173 struct ifnet *ifp = sc->sc_ifp; 4174 struct ieee80211com *ic = ifp->if_l2com; 4175 struct ath_txq *txq = sc->sc_ac2q[ac]; 4176 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 4177 struct ath_hal *ah = sc->sc_ah; 4178 HAL_TXQ_INFO qi; 4179 4180 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 4181 #ifdef IEEE80211_SUPPORT_TDMA 4182 if (sc->sc_tdma) { 4183 /* 4184 * AIFS is zero so there's no pre-transmit wait. The 4185 * burst time defines the slot duration and is configured 4186 * through net80211. The QCU is setup to not do post-xmit 4187 * back off, lockout all lower-priority QCU's, and fire 4188 * off the DMA beacon alert timer which is setup based 4189 * on the slot configuration. 4190 */ 4191 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4192 | HAL_TXQ_TXERRINT_ENABLE 4193 | HAL_TXQ_TXURNINT_ENABLE 4194 | HAL_TXQ_TXEOLINT_ENABLE 4195 | HAL_TXQ_DBA_GATED 4196 | HAL_TXQ_BACKOFF_DISABLE 4197 | HAL_TXQ_ARB_LOCKOUT_GLOBAL 4198 ; 4199 qi.tqi_aifs = 0; 4200 /* XXX +dbaprep? */ 4201 qi.tqi_readyTime = sc->sc_tdmaslotlen; 4202 qi.tqi_burstTime = qi.tqi_readyTime; 4203 } else { 4204 #endif 4205 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE 4206 | HAL_TXQ_TXERRINT_ENABLE 4207 | HAL_TXQ_TXDESCINT_ENABLE 4208 | HAL_TXQ_TXURNINT_ENABLE 4209 ; 4210 qi.tqi_aifs = wmep->wmep_aifsn; 4211 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 4212 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 4213 qi.tqi_readyTime = 0; 4214 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 4215 #ifdef IEEE80211_SUPPORT_TDMA 4216 } 4217 #endif 4218 4219 DPRINTF(sc, ATH_DEBUG_RESET, 4220 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n", 4221 __func__, txq->axq_qnum, qi.tqi_qflags, 4222 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime); 4223 4224 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 4225 if_printf(ifp, "unable to update hardware queue " 4226 "parameters for %s traffic!\n", 4227 ieee80211_wme_acnames[ac]); 4228 return 0; 4229 } else { 4230 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 4231 return 1; 4232 } 4233 #undef ATH_TXOP_TO_US 4234 #undef ATH_EXPONENT_TO_VALUE 4235 } 4236 4237 /* 4238 * Callback from the 802.11 layer to update WME parameters. 4239 */ 4240 static int 4241 ath_wme_update(struct ieee80211com *ic) 4242 { 4243 struct ath_softc *sc = ic->ic_ifp->if_softc; 4244 4245 return !ath_txq_update(sc, WME_AC_BE) || 4246 !ath_txq_update(sc, WME_AC_BK) || 4247 !ath_txq_update(sc, WME_AC_VI) || 4248 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 4249 } 4250 4251 /* 4252 * Reclaim resources for a setup queue. 4253 */ 4254 static void 4255 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 4256 { 4257 4258 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 4259 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 4260 } 4261 4262 /* 4263 * Reclaim all tx queue resources. 4264 */ 4265 static void 4266 ath_tx_cleanup(struct ath_softc *sc) 4267 { 4268 int i; 4269 4270 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 4271 if (ATH_TXQ_SETUP(sc, i)) 4272 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 4273 } 4274 4275 /* 4276 * Return h/w rate index for an IEEE rate (w/o basic rate bit) 4277 * using the current rates in sc_rixmap. 4278 */ 4279 static __inline int 4280 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate) 4281 { 4282 int rix = sc->sc_rixmap[rate]; 4283 /* NB: return lowest rix for invalid rate */ 4284 return (rix == 0xff ? 0 : rix); 4285 } 4286 4287 /* 4288 * Reclaim mbuf resources. For fragmented frames we 4289 * need to claim each frag chained with m_nextpkt. 4290 */ 4291 static void 4292 ath_freetx(struct mbuf *m) 4293 { 4294 struct mbuf *next; 4295 4296 do { 4297 next = m->m_nextpkt; 4298 m->m_nextpkt = NULL; 4299 m_freem(m); 4300 } while ((m = next) != NULL); 4301 } 4302 4303 static int 4304 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 4305 { 4306 int error; 4307 4308 /* 4309 * 4310 * Load the DMA map so any coalescing is done. This 4311 * also calculates the number of descriptors we need. 4312 */ 4313 error = bus_dmamap_load_mbuf_defrag(sc->sc_dmat, bf->bf_dmamap, &m0, 4314 bf->bf_segs, ATH_TXDESC, 4315 &bf->bf_nseg, BUS_DMA_NOWAIT); 4316 if (error != 0) { 4317 sc->sc_stats.ast_tx_busdma++; 4318 ath_freetx(m0); 4319 return error; 4320 } 4321 4322 /* 4323 * Discard null packets. 4324 */ 4325 if (bf->bf_nseg == 0) { /* null packet, discard */ 4326 sc->sc_stats.ast_tx_nodata++; 4327 ath_freetx(m0); 4328 return EIO; 4329 } 4330 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 4331 __func__, m0, m0->m_pkthdr.len); 4332 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 4333 bf->bf_m = m0; 4334 4335 return 0; 4336 } 4337 4338 static void 4339 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf) 4340 { 4341 struct ath_hal *ah = sc->sc_ah; 4342 struct ath_desc *ds, *ds0; 4343 int i; 4344 4345 /* 4346 * Fillin the remainder of the descriptor info. 4347 */ 4348 ds0 = ds = bf->bf_desc; 4349 for (i = 0; i < bf->bf_nseg; i++, ds++) { 4350 ds->ds_data = bf->bf_segs[i].ds_addr; 4351 if (i == bf->bf_nseg - 1) 4352 ds->ds_link = 0; 4353 else 4354 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 4355 ath_hal_filltxdesc(ah, ds 4356 , bf->bf_segs[i].ds_len /* segment length */ 4357 , i == 0 /* first segment */ 4358 , i == bf->bf_nseg - 1 /* last segment */ 4359 , ds0 /* first descriptor */ 4360 ); 4361 DPRINTF(sc, ATH_DEBUG_XMIT, 4362 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 4363 __func__, i, ds->ds_link, ds->ds_data, 4364 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 4365 } 4366 /* 4367 * Insert the frame on the outbound list and pass it on 4368 * to the hardware. Multicast frames buffered for power 4369 * save stations and transmit from the CAB queue are stored 4370 * on a s/w only queue and loaded on to the CAB queue in 4371 * the SWBA handler since frames only go out on DTIM and 4372 * to avoid possible races. 4373 */ 4374 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 4375 ("busy status 0x%x", bf->bf_flags)); 4376 if (txq->axq_qnum != ATH_TXQ_SWQ) { 4377 #ifdef IEEE80211_SUPPORT_TDMA 4378 /* 4379 * Supporting transmit dma. If the queue is busy it is 4380 * impossible to determine if we've won the race against 4381 * the chipset checking the link field or not, so we don't 4382 * try. Instead we let the TX interrupt detect the case 4383 * and restart the transmitter. 4384 * 4385 * If the queue is not busy we can start things rolling 4386 * right here. 4387 */ 4388 int qbusy; 4389 4390 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4391 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4392 4393 if (qbusy == 0) { 4394 if (txq->axq_link != NULL) { 4395 /* 4396 * We had already started one previously but 4397 * not yet processed the TX interrupt. Don't 4398 * try to race a restart because we do not 4399 * know where it stopped, let the TX interrupt 4400 * restart us when it figures out where we 4401 * stopped. 4402 */ 4403 cpu_sfence(); 4404 *txq->axq_link = bf->bf_daddr; 4405 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4406 } else { 4407 /* 4408 * We are first in line, we can safely start 4409 * at this address. 4410 */ 4411 cpu_sfence(); 4412 ath_hal_puttxbuf(ah, txq->axq_qnum, 4413 bf->bf_daddr); 4414 } 4415 } else { 4416 /* 4417 * The queue is busy, go ahead and link us in but 4418 * do not try to start/restart the tx. We just 4419 * don't know whether it will pick up our link 4420 * or not and we don't want to double-xmit. 4421 */ 4422 if (txq->axq_link != NULL) { 4423 cpu_sfence(); 4424 *txq->axq_link = bf->bf_daddr; 4425 } 4426 txq->axq_flags |= ATH_TXQ_PUTPENDING; 4427 } 4428 #if 0 4429 ath_hal_puttxbuf(ah, txq->axq_qnum, 4430 STAILQ_FIRST(&txq->axq_q)->bf_daddr); 4431 #endif 4432 #else 4433 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4434 if (txq->axq_link == NULL) { 4435 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 4436 DPRINTF(sc, ATH_DEBUG_XMIT, 4437 "%s: TXDP[%u] = %p (%p) depth %d\n", 4438 __func__, txq->axq_qnum, 4439 (caddr_t)bf->bf_daddr, bf->bf_desc, 4440 txq->axq_depth); 4441 } else { 4442 *txq->axq_link = bf->bf_daddr; 4443 DPRINTF(sc, ATH_DEBUG_XMIT, 4444 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 4445 txq->axq_qnum, txq->axq_link, 4446 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 4447 } 4448 #endif /* IEEE80211_SUPPORT_TDMA */ 4449 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4450 ath_hal_txstart(ah, txq->axq_qnum); 4451 } else { 4452 if (txq->axq_link != NULL) { 4453 struct ath_buf *last = ATH_TXQ_LAST(txq); 4454 struct ieee80211_frame *wh; 4455 4456 /* mark previous frame */ 4457 wh = mtod(last->bf_m, struct ieee80211_frame *); 4458 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 4459 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 4460 BUS_DMASYNC_PREWRITE); 4461 4462 /* link descriptor */ 4463 *txq->axq_link = bf->bf_daddr; 4464 } 4465 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 4466 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 4467 } 4468 } 4469 4470 static int 4471 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 4472 struct mbuf *m0) 4473 { 4474 struct ieee80211vap *vap = ni->ni_vap; 4475 struct ath_vap *avp = ATH_VAP(vap); 4476 struct ath_hal *ah = sc->sc_ah; 4477 struct ifnet *ifp = sc->sc_ifp; 4478 struct ieee80211com *ic = ifp->if_l2com; 4479 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 4480 int error, iswep, ismcast, isfrag, ismrr; 4481 int keyix, hdrlen, pktlen, try0; 4482 u_int8_t rix, txrate, ctsrate; 4483 u_int8_t cix = 0xff; /* NB: silence compiler */ 4484 struct ath_desc *ds; 4485 struct ath_txq *txq; 4486 struct ieee80211_frame *wh; 4487 u_int subtype, flags, ctsduration; 4488 HAL_PKT_TYPE atype; 4489 const HAL_RATE_TABLE *rt; 4490 HAL_BOOL shortPreamble; 4491 struct ath_node *an; 4492 u_int pri; 4493 4494 wh = mtod(m0, struct ieee80211_frame *); 4495 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 4496 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 4497 isfrag = m0->m_flags & M_FRAG; 4498 hdrlen = ieee80211_anyhdrsize(wh); 4499 /* 4500 * Packet length must not include any 4501 * pad bytes; deduct them here. 4502 */ 4503 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 4504 4505 if (iswep) { 4506 const struct ieee80211_cipher *cip; 4507 struct ieee80211_key *k; 4508 4509 /* 4510 * Construct the 802.11 header+trailer for an encrypted 4511 * frame. The only reason this can fail is because of an 4512 * unknown or unsupported cipher/key type. 4513 */ 4514 k = ieee80211_crypto_encap(ni, m0); 4515 if (k == NULL) { 4516 /* 4517 * This can happen when the key is yanked after the 4518 * frame was queued. Just discard the frame; the 4519 * 802.11 layer counts failures and provides 4520 * debugging/diagnostics. 4521 */ 4522 ath_freetx(m0); 4523 return EIO; 4524 } 4525 /* 4526 * Adjust the packet + header lengths for the crypto 4527 * additions and calculate the h/w key index. When 4528 * a s/w mic is done the frame will have had any mic 4529 * added to it prior to entry so m0->m_pkthdr.len will 4530 * account for it. Otherwise we need to add it to the 4531 * packet length. 4532 */ 4533 cip = k->wk_cipher; 4534 hdrlen += cip->ic_header; 4535 pktlen += cip->ic_header + cip->ic_trailer; 4536 /* NB: frags always have any TKIP MIC done in s/w */ 4537 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 4538 pktlen += cip->ic_miclen; 4539 keyix = k->wk_keyix; 4540 4541 /* packet header may have moved, reset our local pointer */ 4542 wh = mtod(m0, struct ieee80211_frame *); 4543 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 4544 /* 4545 * Use station key cache slot, if assigned. 4546 */ 4547 keyix = ni->ni_ucastkey.wk_keyix; 4548 if (keyix == IEEE80211_KEYIX_NONE) 4549 keyix = HAL_TXKEYIX_INVALID; 4550 } else 4551 keyix = HAL_TXKEYIX_INVALID; 4552 4553 pktlen += IEEE80211_CRC_LEN; 4554 4555 /* 4556 * Load the DMA map so any coalescing is done. This 4557 * also calculates the number of descriptors we need. 4558 */ 4559 error = ath_tx_dmasetup(sc, bf, m0); 4560 if (error != 0) { 4561 return error; 4562 } 4563 bf->bf_node = ni; /* NB: held reference */ 4564 m0 = bf->bf_m; /* NB: may have changed */ 4565 wh = mtod(m0, struct ieee80211_frame *); 4566 4567 /* setup descriptors */ 4568 ds = bf->bf_desc; 4569 rt = sc->sc_currates; 4570 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 4571 4572 /* 4573 * NB: the 802.11 layer marks whether or not we should 4574 * use short preamble based on the current mode and 4575 * negotiated parameters. 4576 */ 4577 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 4578 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 4579 shortPreamble = AH_TRUE; 4580 sc->sc_stats.ast_tx_shortpre++; 4581 } else { 4582 shortPreamble = AH_FALSE; 4583 } 4584 4585 an = ATH_NODE(ni); 4586 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 4587 ismrr = 0; /* default no multi-rate retry*/ 4588 pri = M_WME_GETAC(m0); /* honor classification */ 4589 /* XXX use txparams instead of fixed values */ 4590 /* 4591 * Calculate Atheros packet type from IEEE80211 packet header, 4592 * setup for rate calculations, and select h/w transmit queue. 4593 */ 4594 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 4595 case IEEE80211_FC0_TYPE_MGT: 4596 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4597 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 4598 atype = HAL_PKT_TYPE_BEACON; 4599 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4600 atype = HAL_PKT_TYPE_PROBE_RESP; 4601 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 4602 atype = HAL_PKT_TYPE_ATIM; 4603 else 4604 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 4605 rix = an->an_mgmtrix; 4606 txrate = rt->info[rix].rateCode; 4607 if (shortPreamble) 4608 txrate |= rt->info[rix].shortPreamble; 4609 try0 = ATH_TXMGTTRY; 4610 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4611 break; 4612 case IEEE80211_FC0_TYPE_CTL: 4613 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 4614 rix = an->an_mgmtrix; 4615 txrate = rt->info[rix].rateCode; 4616 if (shortPreamble) 4617 txrate |= rt->info[rix].shortPreamble; 4618 try0 = ATH_TXMGTTRY; 4619 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 4620 break; 4621 case IEEE80211_FC0_TYPE_DATA: 4622 atype = HAL_PKT_TYPE_NORMAL; /* default */ 4623 /* 4624 * Data frames: multicast frames go out at a fixed rate, 4625 * EAPOL frames use the mgmt frame rate; otherwise consult 4626 * the rate control module for the rate to use. 4627 */ 4628 if (ismcast) { 4629 rix = an->an_mcastrix; 4630 txrate = rt->info[rix].rateCode; 4631 if (shortPreamble) 4632 txrate |= rt->info[rix].shortPreamble; 4633 try0 = 1; 4634 } else if (m0->m_flags & M_EAPOL) { 4635 /* XXX? maybe always use long preamble? */ 4636 rix = an->an_mgmtrix; 4637 txrate = rt->info[rix].rateCode; 4638 if (shortPreamble) 4639 txrate |= rt->info[rix].shortPreamble; 4640 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 4641 } else { 4642 ath_rate_findrate(sc, an, shortPreamble, pktlen, 4643 &rix, &try0, &txrate); 4644 sc->sc_txrix = rix; /* for LED blinking */ 4645 sc->sc_lastdatarix = rix; /* for fast frames */ 4646 if (try0 != ATH_TXMAXTRY) 4647 ismrr = 1; 4648 } 4649 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 4650 flags |= HAL_TXDESC_NOACK; 4651 break; 4652 default: 4653 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 4654 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 4655 /* XXX statistic */ 4656 ath_freetx(m0); 4657 return EIO; 4658 } 4659 txq = sc->sc_ac2q[pri]; 4660 4661 /* 4662 * When servicing one or more stations in power-save mode 4663 * (or) if there is some mcast data waiting on the mcast 4664 * queue (to prevent out of order delivery) multicast 4665 * frames must be buffered until after the beacon. 4666 */ 4667 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) 4668 txq = &avp->av_mcastq; 4669 4670 /* 4671 * Calculate miscellaneous flags. 4672 */ 4673 if (ismcast) { 4674 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 4675 } else if (pktlen > vap->iv_rtsthreshold && 4676 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 4677 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 4678 cix = rt->info[rix].controlRate; 4679 sc->sc_stats.ast_tx_rts++; 4680 } 4681 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 4682 sc->sc_stats.ast_tx_noack++; 4683 #ifdef IEEE80211_SUPPORT_TDMA 4684 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 4685 DPRINTF(sc, ATH_DEBUG_TDMA, 4686 "%s: discard frame, ACK required w/ TDMA\n", __func__); 4687 sc->sc_stats.ast_tdma_ack++; 4688 ath_freetx(m0); 4689 return EIO; 4690 } 4691 #endif 4692 4693 /* 4694 * If 802.11g protection is enabled, determine whether 4695 * to use RTS/CTS or just CTS. Note that this is only 4696 * done for OFDM unicast frames. 4697 */ 4698 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 4699 rt->info[rix].phy == IEEE80211_T_OFDM && 4700 (flags & HAL_TXDESC_NOACK) == 0) { 4701 /* XXX fragments must use CCK rates w/ protection */ 4702 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4703 flags |= HAL_TXDESC_RTSENA; 4704 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4705 flags |= HAL_TXDESC_CTSENA; 4706 if (isfrag) { 4707 /* 4708 * For frags it would be desirable to use the 4709 * highest CCK rate for RTS/CTS. But stations 4710 * farther away may detect it at a lower CCK rate 4711 * so use the configured protection rate instead 4712 * (for now). 4713 */ 4714 cix = rt->info[sc->sc_protrix].controlRate; 4715 } else 4716 cix = rt->info[sc->sc_protrix].controlRate; 4717 sc->sc_stats.ast_tx_protect++; 4718 } 4719 4720 /* 4721 * Calculate duration. This logically belongs in the 802.11 4722 * layer but it lacks sufficient information to calculate it. 4723 */ 4724 if ((flags & HAL_TXDESC_NOACK) == 0 && 4725 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 4726 u_int16_t dur; 4727 if (shortPreamble) 4728 dur = rt->info[rix].spAckDuration; 4729 else 4730 dur = rt->info[rix].lpAckDuration; 4731 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 4732 dur += dur; /* additional SIFS+ACK */ 4733 KASSERT(m0->m_nextpkt != NULL, ("no fragment")); 4734 /* 4735 * Include the size of next fragment so NAV is 4736 * updated properly. The last fragment uses only 4737 * the ACK duration 4738 */ 4739 dur += ath_hal_computetxtime(ah, rt, 4740 m0->m_nextpkt->m_pkthdr.len, 4741 rix, shortPreamble); 4742 } 4743 if (isfrag) { 4744 /* 4745 * Force hardware to use computed duration for next 4746 * fragment by disabling multi-rate retry which updates 4747 * duration based on the multi-rate duration table. 4748 */ 4749 ismrr = 0; 4750 try0 = ATH_TXMGTTRY; /* XXX? */ 4751 } 4752 *(u_int16_t *)wh->i_dur = htole16(dur); 4753 } 4754 4755 /* 4756 * Calculate RTS/CTS rate and duration if needed. 4757 */ 4758 ctsduration = 0; 4759 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 4760 /* 4761 * CTS transmit rate is derived from the transmit rate 4762 * by looking in the h/w rate table. We must also factor 4763 * in whether or not a short preamble is to be used. 4764 */ 4765 /* NB: cix is set above where RTS/CTS is enabled */ 4766 KASSERT(cix != 0xff, ("cix not setup")); 4767 ctsrate = rt->info[cix].rateCode; 4768 /* 4769 * Compute the transmit duration based on the frame 4770 * size and the size of an ACK frame. We call into the 4771 * HAL to do the computation since it depends on the 4772 * characteristics of the actual PHY being used. 4773 * 4774 * NB: CTS is assumed the same size as an ACK so we can 4775 * use the precalculated ACK durations. 4776 */ 4777 if (shortPreamble) { 4778 ctsrate |= rt->info[cix].shortPreamble; 4779 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4780 ctsduration += rt->info[cix].spAckDuration; 4781 ctsduration += ath_hal_computetxtime(ah, 4782 rt, pktlen, rix, AH_TRUE); 4783 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4784 ctsduration += rt->info[rix].spAckDuration; 4785 } else { 4786 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 4787 ctsduration += rt->info[cix].lpAckDuration; 4788 ctsduration += ath_hal_computetxtime(ah, 4789 rt, pktlen, rix, AH_FALSE); 4790 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 4791 ctsduration += rt->info[rix].lpAckDuration; 4792 } 4793 /* 4794 * Must disable multi-rate retry when using RTS/CTS. 4795 */ 4796 ismrr = 0; 4797 try0 = ATH_TXMGTTRY; /* XXX */ 4798 } else 4799 ctsrate = 0; 4800 4801 /* 4802 * At this point we are committed to sending the frame 4803 * and we don't need to look at m_nextpkt; clear it in 4804 * case this frame is part of frag chain. 4805 */ 4806 m0->m_nextpkt = NULL; 4807 4808 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 4809 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 4810 sc->sc_hwmap[rix].ieeerate, -1); 4811 4812 if (ieee80211_radiotap_active_vap(vap)) { 4813 u_int64_t tsf = ath_hal_gettsf64(ah); 4814 4815 sc->sc_tx_th.wt_tsf = htole64(tsf); 4816 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 4817 if (iswep) 4818 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4819 if (isfrag) 4820 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 4821 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 4822 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 4823 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 4824 4825 ieee80211_radiotap_tx(vap, m0); 4826 } 4827 4828 /* 4829 * Determine if a tx interrupt should be generated for 4830 * this descriptor. We take a tx interrupt to reap 4831 * descriptors when the h/w hits an EOL condition or 4832 * when the descriptor is specifically marked to generate 4833 * an interrupt. We periodically mark descriptors in this 4834 * way to insure timely replenishing of the supply needed 4835 * for sending frames. Defering interrupts reduces system 4836 * load and potentially allows more concurrent work to be 4837 * done but if done to aggressively can cause senders to 4838 * backup. 4839 * 4840 * NB: use >= to deal with sc_txintrperiod changing 4841 * dynamically through sysctl. 4842 */ 4843 if (flags & HAL_TXDESC_INTREQ) { 4844 txq->axq_intrcnt = 0; 4845 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 4846 flags |= HAL_TXDESC_INTREQ; 4847 txq->axq_intrcnt = 0; 4848 } 4849 4850 /* 4851 * Formulate first tx descriptor with tx controls. 4852 */ 4853 /* XXX check return value? */ 4854 ath_hal_setuptxdesc(ah, ds 4855 , pktlen /* packet length */ 4856 , hdrlen /* header length */ 4857 , atype /* Atheros packet type */ 4858 , ni->ni_txpower /* txpower */ 4859 , txrate, try0 /* series 0 rate/tries */ 4860 , keyix /* key cache index */ 4861 , sc->sc_txantenna /* antenna mode */ 4862 , flags /* flags */ 4863 , ctsrate /* rts/cts rate */ 4864 , ctsduration /* rts/cts duration */ 4865 ); 4866 bf->bf_txflags = flags; 4867 /* 4868 * Setup the multi-rate retry state only when we're 4869 * going to use it. This assumes ath_hal_setuptxdesc 4870 * initializes the descriptors (so we don't have to) 4871 * when the hardware supports multi-rate retry and 4872 * we don't use it. 4873 */ 4874 if (ismrr) 4875 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 4876 4877 ath_tx_handoff(sc, txq, bf); 4878 return 0; 4879 } 4880 4881 /* 4882 * Process completed xmit descriptors from the specified queue. 4883 */ 4884 static int 4885 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 4886 { 4887 struct ath_hal *ah = sc->sc_ah; 4888 struct ifnet *ifp = sc->sc_ifp; 4889 struct ieee80211com *ic = ifp->if_l2com; 4890 struct ath_buf *bf, *last; 4891 struct ath_desc *ds; 4892 struct ath_tx_status *ts; 4893 struct ieee80211_node *ni; 4894 struct ath_node *an; 4895 int sr, lr, pri, nacked; 4896 HAL_STATUS status; 4897 4898 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 4899 __func__, txq->axq_qnum, 4900 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 4901 txq->axq_link); 4902 nacked = 0; 4903 for (;;) { 4904 int qbusy; 4905 4906 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 4907 bf = STAILQ_FIRST(&txq->axq_q); 4908 if (bf == NULL) 4909 break; 4910 ds = &bf->bf_desc[bf->bf_nseg - 1]; 4911 ts = &bf->bf_status.ds_txstat; 4912 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 4913 status = ath_hal_txprocdesc(ah, ds, ts); 4914 #ifdef ATH_DEBUG 4915 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 4916 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 4917 status == HAL_OK); 4918 #endif 4919 if (status == HAL_EINPROGRESS) { 4920 #ifdef IEEE80211_SUPPORT_TDMA 4921 /* 4922 * If not done and the queue is not busy then the 4923 * transmitter raced the hardware on the link field 4924 * and we have to restart it. 4925 */ 4926 if (!qbusy) { 4927 cpu_sfence(); 4928 ath_hal_puttxbuf(ah, txq->axq_qnum, 4929 bf->bf_daddr); 4930 ath_hal_txstart(ah, txq->axq_qnum); 4931 } 4932 #endif 4933 break; 4934 } 4935 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 4936 #ifdef IEEE80211_SUPPORT_TDMA 4937 if (txq->axq_depth > 0) { 4938 /* 4939 * More frames follow. Mark the buffer busy 4940 * so it's not re-used while the hardware may 4941 * still re-read the link field in the descriptor. 4942 */ 4943 bf->bf_flags |= ATH_BUF_BUSY; 4944 } else 4945 #else 4946 if (txq->axq_depth == 0) 4947 #endif 4948 txq->axq_link = NULL; 4949 4950 ni = bf->bf_node; 4951 if (ni != NULL) { 4952 an = ATH_NODE(ni); 4953 if (ts->ts_status == 0) { 4954 u_int8_t txant = ts->ts_antenna; 4955 sc->sc_stats.ast_ant_tx[txant]++; 4956 sc->sc_ant_tx[txant]++; 4957 if (ts->ts_finaltsi != 0) 4958 sc->sc_stats.ast_tx_altrate++; 4959 pri = M_WME_GETAC(bf->bf_m); 4960 if (pri >= WME_AC_VO) 4961 ic->ic_wme.wme_hipri_traffic++; 4962 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0) 4963 ni->ni_inact = ni->ni_inact_reload; 4964 } else { 4965 if (ts->ts_status & HAL_TXERR_XRETRY) 4966 sc->sc_stats.ast_tx_xretries++; 4967 if (ts->ts_status & HAL_TXERR_FIFO) 4968 sc->sc_stats.ast_tx_fifoerr++; 4969 if (ts->ts_status & HAL_TXERR_FILT) 4970 sc->sc_stats.ast_tx_filtered++; 4971 if (bf->bf_m->m_flags & M_FF) 4972 sc->sc_stats.ast_ff_txerr++; 4973 } 4974 sr = ts->ts_shortretry; 4975 lr = ts->ts_longretry; 4976 sc->sc_stats.ast_tx_shortretry += sr; 4977 sc->sc_stats.ast_tx_longretry += lr; 4978 /* 4979 * Hand the descriptor to the rate control algorithm. 4980 */ 4981 if ((ts->ts_status & HAL_TXERR_FILT) == 0 && 4982 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) { 4983 /* 4984 * If frame was ack'd update statistics, 4985 * including the last rx time used to 4986 * workaround phantom bmiss interrupts. 4987 */ 4988 if (ts->ts_status == 0) { 4989 nacked++; 4990 sc->sc_stats.ast_tx_rssi = ts->ts_rssi; 4991 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 4992 ts->ts_rssi); 4993 } 4994 ath_rate_tx_complete(sc, an, bf); 4995 } 4996 /* 4997 * Do any tx complete callback. Note this must 4998 * be done before releasing the node reference. 4999 */ 5000 if (bf->bf_m->m_flags & M_TXCB) 5001 ieee80211_process_callback(ni, bf->bf_m, 5002 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ? 5003 ts->ts_status : HAL_TXERR_XRETRY); 5004 ieee80211_free_node(ni); 5005 } 5006 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 5007 BUS_DMASYNC_POSTWRITE); 5008 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5009 5010 m_freem(bf->bf_m); 5011 bf->bf_m = NULL; 5012 bf->bf_node = NULL; 5013 5014 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5015 if (last != NULL) 5016 last->bf_flags &= ~ATH_BUF_BUSY; 5017 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5018 } 5019 #ifdef IEEE80211_SUPPORT_SUPERG 5020 /* 5021 * Flush fast-frame staging queue when traffic slows. 5022 */ 5023 if (txq->axq_depth <= 1) 5024 ieee80211_ff_flush(ic, txq->axq_ac); 5025 #endif 5026 return nacked; 5027 } 5028 5029 static __inline int 5030 txqactive(struct ath_hal *ah, int qnum) 5031 { 5032 u_int32_t txqs = 1<<qnum; 5033 ath_hal_gettxintrtxqs(ah, &txqs); 5034 return (txqs & (1<<qnum)); 5035 } 5036 5037 /* 5038 * Deferred processing of transmit interrupt; special-cased 5039 * for a single hardware transmit queue (e.g. 5210 and 5211). 5040 */ 5041 static void 5042 ath_tx_task_q0(void *arg, int npending) 5043 { 5044 struct ath_softc *sc = arg; 5045 struct ifnet *ifp = sc->sc_ifp; 5046 5047 wlan_serialize_enter(); 5048 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0])) 5049 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5050 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5051 ath_tx_processq(sc, sc->sc_cabq); 5052 ifq_clr_oactive(&ifp->if_snd); 5053 sc->sc_wd_timer = 0; 5054 5055 if (sc->sc_softled) 5056 ath_led_event(sc, sc->sc_txrix); 5057 5058 if_devstart(ifp); 5059 wlan_serialize_exit(); 5060 } 5061 5062 /* 5063 * Deferred processing of transmit interrupt; special-cased 5064 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 5065 */ 5066 static void 5067 ath_tx_task_q0123(void *arg, int npending) 5068 { 5069 struct ath_softc *sc = arg; 5070 struct ifnet *ifp = sc->sc_ifp; 5071 int nacked; 5072 5073 wlan_serialize_enter(); 5074 /* 5075 * Process each active queue. 5076 */ 5077 nacked = 0; 5078 if (txqactive(sc->sc_ah, 0)) 5079 nacked += ath_tx_processq(sc, &sc->sc_txq[0]); 5080 if (txqactive(sc->sc_ah, 1)) 5081 nacked += ath_tx_processq(sc, &sc->sc_txq[1]); 5082 if (txqactive(sc->sc_ah, 2)) 5083 nacked += ath_tx_processq(sc, &sc->sc_txq[2]); 5084 if (txqactive(sc->sc_ah, 3)) 5085 nacked += ath_tx_processq(sc, &sc->sc_txq[3]); 5086 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum)) 5087 ath_tx_processq(sc, sc->sc_cabq); 5088 if (nacked) 5089 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5090 5091 ifq_clr_oactive(&ifp->if_snd); 5092 sc->sc_wd_timer = 0; 5093 5094 if (sc->sc_softled) 5095 ath_led_event(sc, sc->sc_txrix); 5096 5097 if_devstart(ifp); 5098 wlan_serialize_exit(); 5099 } 5100 5101 /* 5102 * Deferred processing of transmit interrupt. 5103 */ 5104 static void 5105 ath_tx_task(void *arg, int npending) 5106 { 5107 struct ath_softc *sc = arg; 5108 struct ifnet *ifp = sc->sc_ifp; 5109 int i, nacked; 5110 5111 wlan_serialize_enter(); 5112 5113 /* 5114 * Process each active queue. 5115 */ 5116 nacked = 0; 5117 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 5118 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i)) 5119 nacked += ath_tx_processq(sc, &sc->sc_txq[i]); 5120 } 5121 if (nacked) 5122 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah); 5123 5124 ifq_clr_oactive(&ifp->if_snd); 5125 sc->sc_wd_timer = 0; 5126 5127 if (sc->sc_softled) 5128 ath_led_event(sc, sc->sc_txrix); 5129 5130 if_devstart(ifp); 5131 wlan_serialize_exit(); 5132 } 5133 5134 static void 5135 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 5136 { 5137 #ifdef ATH_DEBUG 5138 struct ath_hal *ah = sc->sc_ah; 5139 #endif 5140 struct ieee80211_node *ni; 5141 struct ath_buf *bf; 5142 u_int ix; 5143 5144 /* 5145 * NB: this assumes output has been stopped and 5146 * we do not need to block ath_tx_proc 5147 */ 5148 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list); 5149 if (bf != NULL) 5150 bf->bf_flags &= ~ATH_BUF_BUSY; 5151 for (ix = 0;; ix++) { 5152 bf = STAILQ_FIRST(&txq->axq_q); 5153 if (bf == NULL) { 5154 txq->axq_link = NULL; 5155 break; 5156 } 5157 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 5158 #ifdef ATH_DEBUG 5159 if (sc->sc_debug & ATH_DEBUG_RESET) { 5160 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 5161 5162 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, 5163 ath_hal_txprocdesc(ah, bf->bf_desc, 5164 &bf->bf_status.ds_txstat) == HAL_OK); 5165 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *), 5166 bf->bf_m->m_len, 0, -1); 5167 } 5168 #endif /* ATH_DEBUG */ 5169 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 5170 ni = bf->bf_node; 5171 bf->bf_node = NULL; 5172 if (ni != NULL) { 5173 /* 5174 * Do any callback and reclaim the node reference. 5175 */ 5176 if (bf->bf_m->m_flags & M_TXCB) 5177 ieee80211_process_callback(ni, bf->bf_m, -1); 5178 ieee80211_free_node(ni); 5179 } 5180 m_freem(bf->bf_m); 5181 bf->bf_m = NULL; 5182 bf->bf_flags &= ~ATH_BUF_BUSY; 5183 5184 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 5185 } 5186 } 5187 5188 static void 5189 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 5190 { 5191 struct ath_hal *ah = sc->sc_ah; 5192 5193 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5194 __func__, txq->axq_qnum, 5195 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 5196 txq->axq_link); 5197 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 5198 } 5199 5200 /* 5201 * Drain the transmit queues and reclaim resources. 5202 */ 5203 static void 5204 ath_draintxq(struct ath_softc *sc) 5205 { 5206 struct ath_hal *ah = sc->sc_ah; 5207 struct ifnet *ifp = sc->sc_ifp; 5208 int i; 5209 5210 /* XXX return value */ 5211 if (!sc->sc_invalid) { 5212 /* don't touch the hardware if marked invalid */ 5213 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 5214 __func__, sc->sc_bhalq, 5215 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq), 5216 NULL); 5217 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 5218 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5219 if (ATH_TXQ_SETUP(sc, i)) 5220 ath_tx_stopdma(sc, &sc->sc_txq[i]); 5221 } 5222 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 5223 if (ATH_TXQ_SETUP(sc, i)) 5224 ath_tx_draintxq(sc, &sc->sc_txq[i]); 5225 #ifdef ATH_DEBUG 5226 if (sc->sc_debug & ATH_DEBUG_RESET) { 5227 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 5228 if (bf != NULL && bf->bf_m != NULL) { 5229 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0, 5230 ath_hal_txprocdesc(ah, bf->bf_desc, 5231 &bf->bf_status.ds_txstat) == HAL_OK); 5232 ieee80211_dump_pkt(ifp->if_l2com, 5233 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len, 5234 0, -1); 5235 } 5236 } 5237 #endif /* ATH_DEBUG */ 5238 ifq_clr_oactive(&ifp->if_snd); 5239 sc->sc_wd_timer = 0; 5240 } 5241 5242 /* 5243 * Disable the receive h/w in preparation for a reset. 5244 */ 5245 static void 5246 ath_stoprecv(struct ath_softc *sc) 5247 { 5248 #define PA2DESC(_sc, _pa) \ 5249 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 5250 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 5251 struct ath_hal *ah = sc->sc_ah; 5252 5253 ath_hal_stoppcurecv(ah); /* disable PCU */ 5254 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 5255 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 5256 DELAY(3000); /* 3ms is long enough for 1 frame */ 5257 #ifdef ATH_DEBUG 5258 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 5259 struct ath_buf *bf; 5260 u_int ix; 5261 5262 kprintf("%s: rx queue %p, link %p\n", __func__, 5263 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 5264 ix = 0; 5265 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5266 struct ath_desc *ds = bf->bf_desc; 5267 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 5268 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 5269 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 5270 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 5271 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 5272 ix++; 5273 } 5274 } 5275 #endif 5276 if (sc->sc_rxpending != NULL) { 5277 m_freem(sc->sc_rxpending); 5278 sc->sc_rxpending = NULL; 5279 } 5280 sc->sc_rxlink = NULL; /* just in case */ 5281 #undef PA2DESC 5282 } 5283 5284 /* 5285 * Enable the receive h/w following a reset. 5286 */ 5287 static int 5288 ath_startrecv(struct ath_softc *sc) 5289 { 5290 struct ath_hal *ah = sc->sc_ah; 5291 struct ath_buf *bf; 5292 5293 sc->sc_rxlink = NULL; 5294 sc->sc_rxpending = NULL; 5295 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 5296 int error = ath_rxbuf_init(sc, bf); 5297 if (error != 0) { 5298 DPRINTF(sc, ATH_DEBUG_RECV, 5299 "%s: ath_rxbuf_init failed %d\n", 5300 __func__, error); 5301 return error; 5302 } 5303 } 5304 5305 bf = STAILQ_FIRST(&sc->sc_rxbuf); 5306 ath_hal_putrxbuf(ah, bf->bf_daddr); 5307 ath_hal_rxena(ah); /* enable recv descriptors */ 5308 ath_mode_init(sc); /* set filters, etc. */ 5309 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 5310 return 0; 5311 } 5312 5313 /* 5314 * Update internal state after a channel change. 5315 */ 5316 static void 5317 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 5318 { 5319 enum ieee80211_phymode mode; 5320 5321 /* 5322 * Change channels and update the h/w rate map 5323 * if we're switching; e.g. 11a to 11b/g. 5324 */ 5325 mode = ieee80211_chan2mode(chan); 5326 if (mode != sc->sc_curmode) 5327 ath_setcurmode(sc, mode); 5328 sc->sc_curchan = chan; 5329 } 5330 5331 /* 5332 * Set/change channels. If the channel is really being changed, 5333 * it's done by reseting the chip. To accomplish this we must 5334 * first cleanup any pending DMA, then restart stuff after a la 5335 * ath_init. 5336 */ 5337 static int 5338 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 5339 { 5340 struct ifnet *ifp = sc->sc_ifp; 5341 struct ieee80211com *ic = ifp->if_l2com; 5342 struct ath_hal *ah = sc->sc_ah; 5343 5344 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n", 5345 __func__, ieee80211_chan2ieee(ic, chan), 5346 chan->ic_freq, chan->ic_flags); 5347 if (chan != sc->sc_curchan) { 5348 HAL_STATUS status; 5349 /* 5350 * To switch channels clear any pending DMA operations; 5351 * wait long enough for the RX fifo to drain, reset the 5352 * hardware at the new frequency, and then re-enable 5353 * the relevant bits of the h/w. 5354 */ 5355 ath_hal_intrset(ah, 0); /* disable interrupts */ 5356 ath_draintxq(sc); /* clear pending tx frames */ 5357 ath_stoprecv(sc); /* turn off frame recv */ 5358 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) { 5359 if_printf(ifp, "%s: unable to reset " 5360 "channel %u (%u MHz, flags 0x%x), hal status %u\n", 5361 __func__, ieee80211_chan2ieee(ic, chan), 5362 chan->ic_freq, chan->ic_flags, status); 5363 return EIO; 5364 } 5365 sc->sc_diversity = ath_hal_getdiversity(ah); 5366 5367 /* 5368 * Re-enable rx framework. 5369 */ 5370 if (ath_startrecv(sc) != 0) { 5371 if_printf(ifp, "%s: unable to restart recv logic\n", 5372 __func__); 5373 return EIO; 5374 } 5375 5376 /* 5377 * Change channels and update the h/w rate map 5378 * if we're switching; e.g. 11a to 11b/g. 5379 */ 5380 ath_chan_change(sc, chan); 5381 5382 /* 5383 * Re-enable interrupts. 5384 */ 5385 ath_hal_intrset(ah, sc->sc_imask); 5386 } 5387 return 0; 5388 } 5389 5390 /* 5391 * Periodically recalibrate the PHY to account 5392 * for temperature/environment changes. 5393 */ 5394 static void 5395 ath_calibrate_callout(void *arg) 5396 { 5397 struct ath_softc *sc = arg; 5398 struct ath_hal *ah = sc->sc_ah; 5399 struct ifnet *ifp = sc->sc_ifp; 5400 struct ieee80211com *ic = ifp->if_l2com; 5401 HAL_BOOL longCal, isCalDone; 5402 int nextcal; 5403 5404 wlan_serialize_enter(); 5405 5406 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */ 5407 goto restart; 5408 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz); 5409 if (longCal) { 5410 sc->sc_stats.ast_per_cal++; 5411 sc->sc_lastlongcal = ticks; 5412 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 5413 /* 5414 * Rfgain is out of bounds, reset the chip 5415 * to load new gain values. 5416 */ 5417 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5418 "%s: rfgain change\n", __func__); 5419 sc->sc_stats.ast_per_rfgain++; 5420 ath_reset(ifp); 5421 } 5422 /* 5423 * If this long cal is after an idle period, then 5424 * reset the data collection state so we start fresh. 5425 */ 5426 if (sc->sc_resetcal) { 5427 (void) ath_hal_calreset(ah, sc->sc_curchan); 5428 sc->sc_lastcalreset = ticks; 5429 sc->sc_resetcal = 0; 5430 } 5431 } 5432 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) { 5433 if (longCal) { 5434 /* 5435 * Calibrate noise floor data again in case of change. 5436 */ 5437 ath_hal_process_noisefloor(ah); 5438 } 5439 } else { 5440 DPRINTF(sc, ATH_DEBUG_ANY, 5441 "%s: calibration of channel %u failed\n", 5442 __func__, sc->sc_curchan->ic_freq); 5443 sc->sc_stats.ast_per_calfail++; 5444 } 5445 if (!isCalDone) { 5446 restart: 5447 /* 5448 * Use a shorter interval to potentially collect multiple 5449 * data samples required to complete calibration. Once 5450 * we're told the work is done we drop back to a longer 5451 * interval between requests. We're more aggressive doing 5452 * work when operating as an AP to improve operation right 5453 * after startup. 5454 */ 5455 nextcal = (1000*ath_shortcalinterval)/hz; 5456 if (sc->sc_opmode != HAL_M_HOSTAP) 5457 nextcal *= 10; 5458 } else { 5459 nextcal = ath_longcalinterval*hz; 5460 if (sc->sc_lastcalreset == 0) 5461 sc->sc_lastcalreset = sc->sc_lastlongcal; 5462 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz) 5463 sc->sc_resetcal = 1; /* setup reset next trip */ 5464 } 5465 5466 if (nextcal != 0) { 5467 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n", 5468 __func__, nextcal, isCalDone ? "" : "!"); 5469 callout_reset(&sc->sc_cal_ch, nextcal, 5470 ath_calibrate_callout, sc); 5471 } else { 5472 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n", 5473 __func__); 5474 /* NB: don't rearm timer */ 5475 } 5476 wlan_serialize_exit(); 5477 } 5478 5479 static void 5480 ath_scan_start(struct ieee80211com *ic) 5481 { 5482 struct ifnet *ifp = ic->ic_ifp; 5483 struct ath_softc *sc = ifp->if_softc; 5484 struct ath_hal *ah = sc->sc_ah; 5485 #ifdef ATH_DEBUG 5486 char ethstr[ETHER_ADDRSTRLEN + 1]; 5487 #endif 5488 u_int32_t rfilt; 5489 5490 /* XXX calibration timer? */ 5491 5492 sc->sc_scanning = 1; 5493 sc->sc_syncbeacon = 0; 5494 rfilt = ath_calcrxfilter(sc); 5495 ath_hal_setrxfilter(ah, rfilt); 5496 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0); 5497 5498 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n", 5499 __func__, rfilt, kether_ntoa(ifp->if_broadcastaddr, ethstr)); 5500 } 5501 5502 static void 5503 ath_scan_end(struct ieee80211com *ic) 5504 { 5505 struct ifnet *ifp = ic->ic_ifp; 5506 struct ath_softc *sc = ifp->if_softc; 5507 struct ath_hal *ah = sc->sc_ah; 5508 #ifdef ATH_DEBUG 5509 char ethstr[ETHER_ADDRSTRLEN + 1]; 5510 #endif 5511 u_int32_t rfilt; 5512 5513 sc->sc_scanning = 0; 5514 rfilt = ath_calcrxfilter(sc); 5515 ath_hal_setrxfilter(ah, rfilt); 5516 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5517 5518 ath_hal_process_noisefloor(ah); 5519 5520 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5521 __func__, rfilt, kether_ntoa(sc->sc_curbssid, ethstr), 5522 sc->sc_curaid); 5523 } 5524 5525 static void 5526 ath_set_channel(struct ieee80211com *ic) 5527 { 5528 struct ifnet *ifp = ic->ic_ifp; 5529 struct ath_softc *sc = ifp->if_softc; 5530 5531 (void) ath_chan_set(sc, ic->ic_curchan); 5532 /* 5533 * If we are returning to our bss channel then mark state 5534 * so the next recv'd beacon's tsf will be used to sync the 5535 * beacon timers. Note that since we only hear beacons in 5536 * sta/ibss mode this has no effect in other operating modes. 5537 */ 5538 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan) 5539 sc->sc_syncbeacon = 1; 5540 } 5541 5542 /* 5543 * Walk the vap list and check if there any vap's in RUN state. 5544 */ 5545 static int 5546 ath_isanyrunningvaps(struct ieee80211vap *this) 5547 { 5548 struct ieee80211com *ic = this->iv_ic; 5549 struct ieee80211vap *vap; 5550 5551 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) { 5552 if (vap != this && vap->iv_state >= IEEE80211_S_RUN) 5553 return 1; 5554 } 5555 return 0; 5556 } 5557 5558 static int 5559 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 5560 { 5561 struct ieee80211com *ic = vap->iv_ic; 5562 struct ath_softc *sc = ic->ic_ifp->if_softc; 5563 struct ath_vap *avp = ATH_VAP(vap); 5564 struct ath_hal *ah = sc->sc_ah; 5565 struct ieee80211_node *ni = NULL; 5566 int i, error, stamode; 5567 u_int32_t rfilt; 5568 #ifdef ATH_DEBUG 5569 char ethstr[ETHER_ADDRSTRLEN + 1]; 5570 #endif 5571 static const HAL_LED_STATE leds[] = { 5572 HAL_LED_INIT, /* IEEE80211_S_INIT */ 5573 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 5574 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 5575 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 5576 HAL_LED_RUN, /* IEEE80211_S_CAC */ 5577 HAL_LED_RUN, /* IEEE80211_S_RUN */ 5578 HAL_LED_RUN, /* IEEE80211_S_CSA */ 5579 HAL_LED_RUN, /* IEEE80211_S_SLEEP */ 5580 }; 5581 5582 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 5583 ieee80211_state_name[vap->iv_state], 5584 ieee80211_state_name[nstate]); 5585 5586 callout_stop(&sc->sc_cal_ch); 5587 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 5588 5589 if (nstate == IEEE80211_S_SCAN) { 5590 /* 5591 * Scanning: turn off beacon miss and don't beacon. 5592 * Mark beacon state so when we reach RUN state we'll 5593 * [re]setup beacons. Unblock the task q thread so 5594 * deferred interrupt processing is done. 5595 */ 5596 ath_hal_intrset(ah, 5597 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 5598 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5599 sc->sc_beacons = 0; 5600 taskqueue_unblock(sc->sc_tq); 5601 } 5602 5603 ni = vap->iv_bss; 5604 rfilt = ath_calcrxfilter(sc); 5605 stamode = (vap->iv_opmode == IEEE80211_M_STA || 5606 vap->iv_opmode == IEEE80211_M_AHDEMO || 5607 vap->iv_opmode == IEEE80211_M_IBSS); 5608 if (stamode && nstate == IEEE80211_S_RUN) { 5609 sc->sc_curaid = ni->ni_associd; 5610 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid); 5611 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid); 5612 } 5613 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n", 5614 __func__, rfilt, kether_ntoa(sc->sc_curbssid, ethstr), sc->sc_curaid); 5615 ath_hal_setrxfilter(ah, rfilt); 5616 5617 /* XXX is this to restore keycache on resume? */ 5618 if (vap->iv_opmode != IEEE80211_M_STA && 5619 (vap->iv_flags & IEEE80211_F_PRIVACY)) { 5620 for (i = 0; i < IEEE80211_WEP_NKID; i++) 5621 if (ath_hal_keyisvalid(ah, i)) 5622 ath_hal_keysetmac(ah, i, ni->ni_bssid); 5623 } 5624 5625 /* 5626 * Invoke the parent method to do net80211 work. 5627 */ 5628 error = avp->av_newstate(vap, nstate, arg); 5629 if (error != 0) 5630 goto bad; 5631 5632 if (nstate == IEEE80211_S_RUN) { 5633 /* NB: collect bss node again, it may have changed */ 5634 ni = vap->iv_bss; 5635 5636 DPRINTF(sc, ATH_DEBUG_STATE, 5637 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s " 5638 "capinfo 0x%04x chan %d\n", __func__, 5639 vap->iv_flags, ni->ni_intval, kether_ntoa(ni->ni_bssid, ethstr), 5640 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan)); 5641 5642 switch (vap->iv_opmode) { 5643 #ifdef IEEE80211_SUPPORT_TDMA 5644 case IEEE80211_M_AHDEMO: 5645 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0) 5646 break; 5647 /* fall thru... */ 5648 #endif 5649 case IEEE80211_M_HOSTAP: 5650 case IEEE80211_M_IBSS: 5651 case IEEE80211_M_MBSS: 5652 /* 5653 * Allocate and setup the beacon frame. 5654 * 5655 * Stop any previous beacon DMA. This may be 5656 * necessary, for example, when an ibss merge 5657 * causes reconfiguration; there will be a state 5658 * transition from RUN->RUN that means we may 5659 * be called with beacon transmission active. 5660 */ 5661 ath_hal_stoptxdma(ah, sc->sc_bhalq); 5662 5663 error = ath_beacon_alloc(sc, ni); 5664 if (error != 0) 5665 goto bad; 5666 /* 5667 * If joining an adhoc network defer beacon timer 5668 * configuration to the next beacon frame so we 5669 * have a current TSF to use. Otherwise we're 5670 * starting an ibss/bss so there's no need to delay; 5671 * if this is the first vap moving to RUN state, then 5672 * beacon state needs to be [re]configured. 5673 */ 5674 if (vap->iv_opmode == IEEE80211_M_IBSS && 5675 ni->ni_tstamp.tsf != 0) { 5676 sc->sc_syncbeacon = 1; 5677 } else if (!sc->sc_beacons) { 5678 #ifdef IEEE80211_SUPPORT_TDMA 5679 if (vap->iv_caps & IEEE80211_C_TDMA) 5680 ath_tdma_config(sc, vap); 5681 else 5682 #endif 5683 ath_beacon_config(sc, vap); 5684 sc->sc_beacons = 1; 5685 } 5686 break; 5687 case IEEE80211_M_STA: 5688 /* 5689 * Defer beacon timer configuration to the next 5690 * beacon frame so we have a current TSF to use 5691 * (any TSF collected when scanning is likely old). 5692 */ 5693 sc->sc_syncbeacon = 1; 5694 break; 5695 case IEEE80211_M_MONITOR: 5696 /* 5697 * Monitor mode vaps have only INIT->RUN and RUN->RUN 5698 * transitions so we must re-enable interrupts here to 5699 * handle the case of a single monitor mode vap. 5700 */ 5701 ath_hal_intrset(ah, sc->sc_imask); 5702 break; 5703 case IEEE80211_M_WDS: 5704 break; 5705 default: 5706 break; 5707 } 5708 /* 5709 * Let the hal process statistics collected during a 5710 * scan so it can provide calibrated noise floor data. 5711 */ 5712 ath_hal_process_noisefloor(ah); 5713 /* 5714 * Reset rssi stats; maybe not the best place... 5715 */ 5716 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 5717 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 5718 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 5719 /* 5720 * Finally, start any timers and the task q thread 5721 * (in case we didn't go through SCAN state). 5722 */ 5723 if (ath_longcalinterval != 0) { 5724 /* start periodic recalibration timer */ 5725 callout_reset(&sc->sc_cal_ch, 1, 5726 ath_calibrate_callout, sc); 5727 } else { 5728 DPRINTF(sc, ATH_DEBUG_CALIBRATE, 5729 "%s: calibration disabled\n", __func__); 5730 } 5731 taskqueue_unblock(sc->sc_tq); 5732 } else if (nstate == IEEE80211_S_INIT) { 5733 /* 5734 * If there are no vaps left in RUN state then 5735 * shutdown host/driver operation: 5736 * o disable interrupts 5737 * o disable the task queue thread 5738 * o mark beacon processing as stopped 5739 */ 5740 if (!ath_isanyrunningvaps(vap)) { 5741 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 5742 /* disable interrupts */ 5743 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 5744 taskqueue_block(sc->sc_tq); 5745 sc->sc_beacons = 0; 5746 } 5747 #ifdef IEEE80211_SUPPORT_TDMA 5748 ath_hal_setcca(ah, AH_TRUE); 5749 #endif 5750 } 5751 bad: 5752 return error; 5753 } 5754 5755 /* 5756 * Allocate a key cache slot to the station so we can 5757 * setup a mapping from key index to node. The key cache 5758 * slot is needed for managing antenna state and for 5759 * compression when stations do not use crypto. We do 5760 * it uniliaterally here; if crypto is employed this slot 5761 * will be reassigned. 5762 */ 5763 static void 5764 ath_setup_stationkey(struct ieee80211_node *ni) 5765 { 5766 struct ieee80211vap *vap = ni->ni_vap; 5767 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5768 ieee80211_keyix keyix, rxkeyix; 5769 5770 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 5771 /* 5772 * Key cache is full; we'll fall back to doing 5773 * the more expensive lookup in software. Note 5774 * this also means no h/w compression. 5775 */ 5776 /* XXX msg+statistic */ 5777 } else { 5778 /* XXX locking? */ 5779 ni->ni_ucastkey.wk_keyix = keyix; 5780 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 5781 /* NB: must mark device key to get called back on delete */ 5782 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY; 5783 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr); 5784 /* NB: this will create a pass-thru key entry */ 5785 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss); 5786 } 5787 } 5788 5789 /* 5790 * Setup driver-specific state for a newly associated node. 5791 * Note that we're called also on a re-associate, the isnew 5792 * param tells us if this is the first time or not. 5793 */ 5794 static void 5795 ath_newassoc(struct ieee80211_node *ni, int isnew) 5796 { 5797 struct ath_node *an = ATH_NODE(ni); 5798 struct ieee80211vap *vap = ni->ni_vap; 5799 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 5800 const struct ieee80211_txparam *tp = ni->ni_txparms; 5801 5802 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate); 5803 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate); 5804 5805 ath_rate_newassoc(sc, an, isnew); 5806 if (isnew && 5807 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey && 5808 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 5809 ath_setup_stationkey(ni); 5810 } 5811 5812 static int 5813 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg, 5814 int nchans, struct ieee80211_channel chans[]) 5815 { 5816 struct ath_softc *sc = ic->ic_ifp->if_softc; 5817 struct ath_hal *ah = sc->sc_ah; 5818 HAL_STATUS status; 5819 5820 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5821 "%s: rd %u cc %u location %c%s\n", 5822 __func__, reg->regdomain, reg->country, reg->location, 5823 reg->ecm ? " ecm" : ""); 5824 5825 status = ath_hal_set_channels(ah, chans, nchans, 5826 reg->country, reg->regdomain); 5827 if (status != HAL_OK) { 5828 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n", 5829 __func__, status); 5830 return EINVAL; /* XXX */ 5831 } 5832 return 0; 5833 } 5834 5835 static void 5836 ath_getradiocaps(struct ieee80211com *ic, 5837 int maxchans, int *nchans, struct ieee80211_channel chans[]) 5838 { 5839 struct ath_softc *sc = ic->ic_ifp->if_softc; 5840 struct ath_hal *ah = sc->sc_ah; 5841 5842 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n", 5843 __func__, SKU_DEBUG, CTRY_DEFAULT); 5844 5845 /* XXX check return */ 5846 (void) ath_hal_getchannels(ah, chans, maxchans, nchans, 5847 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE); 5848 5849 } 5850 5851 static int 5852 ath_getchannels(struct ath_softc *sc) 5853 { 5854 struct ifnet *ifp = sc->sc_ifp; 5855 struct ieee80211com *ic = ifp->if_l2com; 5856 struct ath_hal *ah = sc->sc_ah; 5857 HAL_STATUS status; 5858 5859 /* 5860 * Collect channel set based on EEPROM contents. 5861 */ 5862 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX, 5863 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE); 5864 if (status != HAL_OK) { 5865 if_printf(ifp, "%s: unable to collect channel list from hal, " 5866 "status %d\n", __func__, status); 5867 return EINVAL; 5868 } 5869 (void) ath_hal_getregdomain(ah, &sc->sc_eerd); 5870 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */ 5871 /* XXX map Atheros sku's to net80211 SKU's */ 5872 /* XXX net80211 types too small */ 5873 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd; 5874 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc; 5875 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */ 5876 ic->ic_regdomain.isocc[1] = ' '; 5877 5878 ic->ic_regdomain.ecm = 1; 5879 ic->ic_regdomain.location = 'I'; 5880 5881 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, 5882 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n", 5883 __func__, sc->sc_eerd, sc->sc_eecc, 5884 ic->ic_regdomain.regdomain, ic->ic_regdomain.country, 5885 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : ""); 5886 return 0; 5887 } 5888 5889 static void 5890 ath_led_done_callout(void *arg) 5891 { 5892 struct ath_softc *sc = arg; 5893 5894 wlan_serialize_enter(); 5895 sc->sc_blinking = 0; 5896 wlan_serialize_exit(); 5897 } 5898 5899 /* 5900 * Turn the LED off: flip the pin and then set a timer so no 5901 * update will happen for the specified duration. 5902 */ 5903 static void 5904 ath_led_off_callout(void *arg) 5905 { 5906 struct ath_softc *sc = arg; 5907 5908 wlan_serialize_enter(); 5909 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 5910 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, 5911 ath_led_done_callout, sc); 5912 wlan_serialize_exit(); 5913 } 5914 5915 /* 5916 * Blink the LED according to the specified on/off times. 5917 */ 5918 static void 5919 ath_led_blink(struct ath_softc *sc, int on, int off) 5920 { 5921 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 5922 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 5923 sc->sc_blinking = 1; 5924 sc->sc_ledoff = off; 5925 callout_reset(&sc->sc_ledtimer, on, ath_led_off_callout, sc); 5926 } 5927 5928 static void 5929 ath_led_event(struct ath_softc *sc, int rix) 5930 { 5931 sc->sc_ledevent = ticks; /* time of last event */ 5932 if (sc->sc_blinking) /* don't interrupt active blink */ 5933 return; 5934 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff); 5935 } 5936 5937 static int 5938 ath_rate_setup(struct ath_softc *sc, u_int mode) 5939 { 5940 struct ath_hal *ah = sc->sc_ah; 5941 const HAL_RATE_TABLE *rt; 5942 5943 switch (mode) { 5944 case IEEE80211_MODE_11A: 5945 rt = ath_hal_getratetable(ah, HAL_MODE_11A); 5946 break; 5947 case IEEE80211_MODE_HALF: 5948 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE); 5949 break; 5950 case IEEE80211_MODE_QUARTER: 5951 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE); 5952 break; 5953 case IEEE80211_MODE_11B: 5954 rt = ath_hal_getratetable(ah, HAL_MODE_11B); 5955 break; 5956 case IEEE80211_MODE_11G: 5957 rt = ath_hal_getratetable(ah, HAL_MODE_11G); 5958 break; 5959 case IEEE80211_MODE_TURBO_A: 5960 rt = ath_hal_getratetable(ah, HAL_MODE_108A); 5961 break; 5962 case IEEE80211_MODE_TURBO_G: 5963 rt = ath_hal_getratetable(ah, HAL_MODE_108G); 5964 break; 5965 case IEEE80211_MODE_STURBO_A: 5966 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO); 5967 break; 5968 case IEEE80211_MODE_11NA: 5969 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20); 5970 break; 5971 case IEEE80211_MODE_11NG: 5972 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20); 5973 break; 5974 default: 5975 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 5976 __func__, mode); 5977 return 0; 5978 } 5979 sc->sc_rates[mode] = rt; 5980 return (rt != NULL); 5981 } 5982 5983 static void 5984 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 5985 { 5986 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 5987 static const struct { 5988 u_int rate; /* tx/rx 802.11 rate */ 5989 u_int16_t timeOn; /* LED on time (ms) */ 5990 u_int16_t timeOff; /* LED off time (ms) */ 5991 } blinkrates[] = { 5992 { 108, 40, 10 }, 5993 { 96, 44, 11 }, 5994 { 72, 50, 13 }, 5995 { 48, 57, 14 }, 5996 { 36, 67, 16 }, 5997 { 24, 80, 20 }, 5998 { 22, 100, 25 }, 5999 { 18, 133, 34 }, 6000 { 12, 160, 40 }, 6001 { 10, 200, 50 }, 6002 { 6, 240, 58 }, 6003 { 4, 267, 66 }, 6004 { 2, 400, 100 }, 6005 { 0, 500, 130 }, 6006 /* XXX half/quarter rates */ 6007 }; 6008 const HAL_RATE_TABLE *rt; 6009 int i, j; 6010 6011 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 6012 rt = sc->sc_rates[mode]; 6013 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 6014 for (i = 0; i < rt->rateCount; i++) { 6015 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6016 if (rt->info[i].phy != IEEE80211_T_HT) 6017 sc->sc_rixmap[ieeerate] = i; 6018 else 6019 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i; 6020 } 6021 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 6022 for (i = 0; i < NELEM(sc->sc_hwmap); i++) { 6023 if (i >= rt->rateCount) { 6024 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 6025 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 6026 continue; 6027 } 6028 sc->sc_hwmap[i].ieeerate = 6029 rt->info[i].dot11Rate & IEEE80211_RATE_VAL; 6030 if (rt->info[i].phy == IEEE80211_T_HT) 6031 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS; 6032 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 6033 if (rt->info[i].shortPreamble || 6034 rt->info[i].phy == IEEE80211_T_OFDM) 6035 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6036 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags; 6037 for (j = 0; j < NELEM(blinkrates)-1; j++) 6038 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 6039 break; 6040 /* NB: this uses the last entry if the rate isn't found */ 6041 /* XXX beware of overlow */ 6042 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 6043 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 6044 } 6045 sc->sc_currates = rt; 6046 sc->sc_curmode = mode; 6047 /* 6048 * All protection frames are transmited at 2Mb/s for 6049 * 11g, otherwise at 1Mb/s. 6050 */ 6051 if (mode == IEEE80211_MODE_11G) 6052 sc->sc_protrix = ath_tx_findrix(sc, 2*2); 6053 else 6054 sc->sc_protrix = ath_tx_findrix(sc, 2*1); 6055 /* NB: caller is responsible for reseting rate control state */ 6056 } 6057 6058 #ifdef ATH_DEBUG 6059 static void 6060 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6061 u_int ix, int done) 6062 { 6063 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 6064 struct ath_hal *ah = sc->sc_ah; 6065 const struct ath_desc *ds; 6066 int i; 6067 6068 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6069 kprintf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n" 6070 " %08x %08x %08x %08x\n", 6071 ix, ds, (const struct ath_desc *)bf->bf_daddr + i, 6072 ds->ds_link, ds->ds_data, 6073 !done ? "" : (rs->rs_status == 0) ? " *" : " !", 6074 ds->ds_ctl0, ds->ds_ctl1, 6075 ds->ds_hw[0], ds->ds_hw[1]); 6076 if (ah->ah_magic == 0x20065416) { 6077 kprintf(" %08x %08x %08x %08x %08x %08x %08x\n", 6078 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4], 6079 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7], 6080 ds->ds_hw[8]); 6081 } 6082 } 6083 } 6084 6085 static void 6086 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf, 6087 u_int qnum, u_int ix, int done) 6088 { 6089 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 6090 struct ath_hal *ah = sc->sc_ah; 6091 const struct ath_desc *ds; 6092 int i; 6093 6094 kprintf("Q%u[%3u]", qnum, ix); 6095 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 6096 kprintf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n" 6097 " %08x %08x %08x %08x %08x %08x\n", 6098 ds, (const struct ath_desc *)bf->bf_daddr + i, 6099 ds->ds_link, ds->ds_data, bf->bf_txflags, 6100 !done ? "" : (ts->ts_status == 0) ? " *" : " !", 6101 ds->ds_ctl0, ds->ds_ctl1, 6102 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]); 6103 if (ah->ah_magic == 0x20065416) { 6104 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6105 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6], 6106 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9], 6107 ds->ds_hw[10],ds->ds_hw[11]); 6108 kprintf(" %08x %08x %08x %08x %08x %08x %08x %08x\n", 6109 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14], 6110 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17], 6111 ds->ds_hw[18], ds->ds_hw[19]); 6112 } 6113 } 6114 } 6115 #endif /* ATH_DEBUG */ 6116 6117 static void 6118 ath_watchdog_callout(void *arg) 6119 { 6120 struct ath_softc *sc = arg; 6121 6122 wlan_serialize_enter(); 6123 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) { 6124 struct ifnet *ifp = sc->sc_ifp; 6125 uint32_t hangs; 6126 6127 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && 6128 hangs != 0) { 6129 if_printf(ifp, "%s hang detected (0x%x)\n", 6130 hangs & 0xff ? "bb" : "mac", hangs); 6131 } else 6132 if_printf(ifp, "device timeout\n"); 6133 ath_reset(ifp); 6134 IFNET_STAT_INC(ifp, oerrors, 1); 6135 sc->sc_stats.ast_watchdog++; 6136 } 6137 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog_callout, sc); 6138 wlan_serialize_exit(); 6139 } 6140 6141 #ifdef ATH_DIAGAPI 6142 /* 6143 * Diagnostic interface to the HAL. This is used by various 6144 * tools to do things like retrieve register contents for 6145 * debugging. The mechanism is intentionally opaque so that 6146 * it can change frequently w/o concern for compatiblity. 6147 */ 6148 static int 6149 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 6150 { 6151 struct ath_hal *ah = sc->sc_ah; 6152 u_int id = ad->ad_id & ATH_DIAG_ID; 6153 void *indata = NULL; 6154 void *outdata = NULL; 6155 u_int32_t insize = ad->ad_in_size; 6156 u_int32_t outsize = ad->ad_out_size; 6157 int error = 0; 6158 6159 if (ad->ad_id & ATH_DIAG_IN) { 6160 /* 6161 * Copy in data. 6162 */ 6163 indata = kmalloc(insize, M_TEMP, M_INTWAIT); 6164 error = copyin(ad->ad_in_data, indata, insize); 6165 if (error) 6166 goto bad; 6167 } 6168 if (ad->ad_id & ATH_DIAG_DYN) { 6169 /* 6170 * Allocate a buffer for the results (otherwise the HAL 6171 * returns a pointer to a buffer where we can read the 6172 * results). Note that we depend on the HAL leaving this 6173 * pointer for us to use below in reclaiming the buffer; 6174 * may want to be more defensive. 6175 */ 6176 outdata = kmalloc(outsize, M_TEMP, M_INTWAIT); 6177 } 6178 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 6179 if (outsize < ad->ad_out_size) 6180 ad->ad_out_size = outsize; 6181 if (outdata != NULL) 6182 error = copyout(outdata, ad->ad_out_data, 6183 ad->ad_out_size); 6184 } else { 6185 error = EINVAL; 6186 } 6187 bad: 6188 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 6189 kfree(indata, M_TEMP); 6190 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 6191 kfree(outdata, M_TEMP); 6192 return error; 6193 } 6194 #endif /* ATH_DIAGAPI */ 6195 6196 static int 6197 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 6198 { 6199 #define IS_RUNNING(ifp) \ 6200 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING)) 6201 struct ath_softc *sc = ifp->if_softc; 6202 struct ieee80211com *ic = ifp->if_l2com; 6203 struct ifreq *ifr = (struct ifreq *)data; 6204 const HAL_RATE_TABLE *rt; 6205 int error = 0; 6206 6207 wlan_assert_serialized(); 6208 6209 switch (cmd) { 6210 case SIOCSIFFLAGS: 6211 if (IS_RUNNING(ifp)) { 6212 /* 6213 * To avoid rescanning another access point, 6214 * do not call ath_init() here. Instead, 6215 * only reflect promisc mode settings. 6216 */ 6217 ath_mode_init(sc); 6218 } else if (ifp->if_flags & IFF_UP) { 6219 /* 6220 * Beware of being called during attach/detach 6221 * to reset promiscuous mode. In that case we 6222 * will still be marked UP but not RUNNING. 6223 * However trying to re-init the interface 6224 * is the wrong thing to do as we've already 6225 * torn down much of our state. There's 6226 * probably a better way to deal with this. 6227 */ 6228 if (!sc->sc_invalid) 6229 ath_init(sc); /* XXX lose error */ 6230 } else { 6231 ath_stop_locked(ifp); 6232 #ifdef notyet 6233 /* XXX must wakeup in places like ath_vap_delete */ 6234 if (!sc->sc_invalid) 6235 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP); 6236 #endif 6237 } 6238 break; 6239 case SIOCGIFMEDIA: 6240 case SIOCSIFMEDIA: 6241 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 6242 break; 6243 case SIOCGATHSTATS: 6244 /* NB: embed these numbers to get a consistent view */ 6245 IFNET_STAT_GET(ifp, opackets, sc->sc_stats.ast_tx_packets); 6246 IFNET_STAT_GET(ifp, ipackets, sc->sc_stats.ast_rx_packets); 6247 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi); 6248 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi); 6249 #ifdef IEEE80211_SUPPORT_TDMA 6250 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap); 6251 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam); 6252 #endif 6253 rt = sc->sc_currates; 6254 /* XXX HT rates */ 6255 sc->sc_stats.ast_tx_rate = 6256 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC; 6257 return copyout(&sc->sc_stats, 6258 ifr->ifr_data, sizeof (sc->sc_stats)); 6259 case SIOCZATHSTATS: 6260 error = priv_check(curthread, PRIV_DRIVER); 6261 if (error == 0) 6262 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 6263 break; 6264 #ifdef ATH_DIAGAPI 6265 case SIOCGATHDIAG: 6266 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 6267 break; 6268 #endif 6269 case SIOCGIFADDR: 6270 error = ether_ioctl(ifp, cmd, data); 6271 break; 6272 default: 6273 error = EINVAL; 6274 break; 6275 } 6276 return error; 6277 #undef IS_RUNNING 6278 } 6279 6280 static int 6281 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 6282 { 6283 struct ath_softc *sc = arg1; 6284 u_int slottime; 6285 int error; 6286 6287 wlan_serialize_enter(); 6288 slottime = ath_hal_getslottime(sc->sc_ah); 6289 error = sysctl_handle_int(oidp, &slottime, 0, req); 6290 if (error == 0 && req->newptr) { 6291 if (!ath_hal_setslottime(sc->sc_ah, slottime)) 6292 error = EINVAL; 6293 } 6294 wlan_serialize_exit(); 6295 return error; 6296 } 6297 6298 static int 6299 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 6300 { 6301 struct ath_softc *sc = arg1; 6302 u_int acktimeout; 6303 int error; 6304 6305 wlan_serialize_enter(); 6306 acktimeout = ath_hal_getacktimeout(sc->sc_ah); 6307 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 6308 if (error == 0 && req->newptr) { 6309 if (!ath_hal_setacktimeout(sc->sc_ah, acktimeout)) 6310 error = EINVAL; 6311 } 6312 wlan_serialize_exit(); 6313 return error; 6314 } 6315 6316 static int 6317 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 6318 { 6319 struct ath_softc *sc = arg1; 6320 u_int ctstimeout; 6321 int error; 6322 6323 wlan_serialize_enter(); 6324 ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 6325 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 6326 if (error == 0 && req->newptr) { 6327 if (!ath_hal_setctstimeout(sc->sc_ah, ctstimeout)) 6328 error = EINVAL; 6329 } 6330 wlan_serialize_exit(); 6331 return error; 6332 } 6333 6334 static int 6335 ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 6336 { 6337 struct ath_softc *sc = arg1; 6338 int softled = sc->sc_softled; 6339 int error; 6340 6341 error = sysctl_handle_int(oidp, &softled, 0, req); 6342 if (error || !req->newptr) 6343 return error; 6344 wlan_serialize_enter(); 6345 softled = (softled != 0); 6346 if (softled != sc->sc_softled) { 6347 if (softled) { 6348 /* NB: handle any sc_ledpin change */ 6349 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6350 HAL_GPIO_MUX_MAC_NETWORK_LED); 6351 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6352 !sc->sc_ledon); 6353 } 6354 sc->sc_softled = softled; 6355 } 6356 wlan_serialize_exit(); 6357 return 0; 6358 } 6359 6360 static int 6361 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS) 6362 { 6363 struct ath_softc *sc = arg1; 6364 int ledpin = sc->sc_ledpin; 6365 int error; 6366 6367 error = sysctl_handle_int(oidp, &ledpin, 0, req); 6368 if (error || !req->newptr) 6369 return error; 6370 wlan_serialize_enter(); 6371 if (ledpin != sc->sc_ledpin) { 6372 sc->sc_ledpin = ledpin; 6373 if (sc->sc_softled) { 6374 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin, 6375 HAL_GPIO_MUX_MAC_NETWORK_LED); 6376 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 6377 !sc->sc_ledon); 6378 } 6379 } 6380 wlan_serialize_exit(); 6381 return 0; 6382 } 6383 6384 static int 6385 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS) 6386 { 6387 struct ath_softc *sc = arg1; 6388 u_int txantenna; 6389 int error; 6390 6391 wlan_serialize_enter(); 6392 txantenna = ath_hal_getantennaswitch(sc->sc_ah); 6393 error = sysctl_handle_int(oidp, &txantenna, 0, req); 6394 6395 if (!error && req->newptr) { 6396 /* XXX assumes 2 antenna ports */ 6397 if (txantenna < HAL_ANT_VARIABLE || 6398 txantenna > HAL_ANT_FIXED_B) { 6399 error = EINVAL; 6400 } else { 6401 ath_hal_setantennaswitch(sc->sc_ah, txantenna); 6402 /* 6403 * NB: with the switch locked this isn't meaningful, 6404 * but set it anyway so things like radiotap get 6405 * consistent info in their data. 6406 */ 6407 sc->sc_txantenna = txantenna; 6408 } 6409 } 6410 wlan_serialize_exit(); 6411 return error; 6412 } 6413 6414 static int 6415 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 6416 { 6417 struct ath_softc *sc = arg1; 6418 u_int defantenna; 6419 int error; 6420 6421 wlan_serialize_enter(); 6422 defantenna = ath_hal_getdefantenna(sc->sc_ah); 6423 error = sysctl_handle_int(oidp, &defantenna, 0, req); 6424 if (error == 0 && req->newptr) 6425 ath_hal_setdefantenna(sc->sc_ah, defantenna); 6426 wlan_serialize_exit(); 6427 return error; 6428 } 6429 6430 static int 6431 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 6432 { 6433 struct ath_softc *sc = arg1; 6434 u_int diversity; 6435 int error; 6436 6437 wlan_serialize_enter(); 6438 diversity = ath_hal_getdiversity(sc->sc_ah); 6439 error = sysctl_handle_int(oidp, &diversity, 0, req); 6440 if (error == 0 && req->newptr) { 6441 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 6442 error = EINVAL; 6443 else 6444 sc->sc_diversity = diversity; 6445 } 6446 wlan_serialize_exit(); 6447 return error; 6448 } 6449 6450 static int 6451 ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 6452 { 6453 struct ath_softc *sc = arg1; 6454 u_int32_t diag; 6455 int error; 6456 6457 wlan_serialize_enter(); 6458 if (!ath_hal_getdiag(sc->sc_ah, &diag)) { 6459 error = EINVAL; 6460 } else { 6461 error = sysctl_handle_int(oidp, &diag, 0, req); 6462 if (error == 0 && req->newptr) { 6463 if (!ath_hal_setdiag(sc->sc_ah, diag)) 6464 error = EINVAL; 6465 } 6466 } 6467 wlan_serialize_exit(); 6468 return error; 6469 } 6470 6471 static int 6472 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 6473 { 6474 struct ath_softc *sc = arg1; 6475 struct ifnet *ifp = sc->sc_ifp; 6476 u_int32_t scale; 6477 int error; 6478 6479 wlan_serialize_enter(); 6480 (void)ath_hal_gettpscale(sc->sc_ah, &scale); 6481 error = sysctl_handle_int(oidp, &scale, 0, req); 6482 if (error == 0 && req->newptr) { 6483 if (!ath_hal_settpscale(sc->sc_ah, scale)) 6484 error = EINVAL; 6485 else if (ifp->if_flags & IFF_RUNNING) 6486 error = ath_reset(ifp); 6487 } 6488 wlan_serialize_exit(); 6489 return error; 6490 } 6491 6492 static int 6493 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 6494 { 6495 struct ath_softc *sc = arg1; 6496 u_int tpc; 6497 int error; 6498 6499 wlan_serialize_enter(); 6500 tpc = ath_hal_gettpc(sc->sc_ah); 6501 error = sysctl_handle_int(oidp, &tpc, 0, req); 6502 if (error == 0 && req->newptr) { 6503 if (!ath_hal_settpc(sc->sc_ah, tpc)) 6504 error = EINVAL; 6505 } 6506 wlan_serialize_exit(); 6507 return error; 6508 } 6509 6510 static int 6511 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS) 6512 { 6513 struct ath_softc *sc = arg1; 6514 struct ifnet *ifp; 6515 struct ath_hal *ah; 6516 u_int rfkill; 6517 int error; 6518 6519 wlan_serialize_enter(); 6520 ifp = sc->sc_ifp; 6521 ah = sc->sc_ah; 6522 rfkill = ath_hal_getrfkill(ah); 6523 6524 error = sysctl_handle_int(oidp, &rfkill, 0, req); 6525 if (error == 0 && req->newptr) { 6526 if (rfkill != ath_hal_getrfkill(ah)) { 6527 if (!ath_hal_setrfkill(ah, rfkill)) 6528 error = EINVAL; 6529 else if (ifp->if_flags & IFF_RUNNING) 6530 error = ath_reset(ifp); 6531 } 6532 } 6533 wlan_serialize_exit(); 6534 return error; 6535 } 6536 6537 static int 6538 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS) 6539 { 6540 struct ath_softc *sc = arg1; 6541 u_int rfsilent; 6542 int error; 6543 6544 wlan_serialize_enter(); 6545 (void)ath_hal_getrfsilent(sc->sc_ah, &rfsilent); 6546 error = sysctl_handle_int(oidp, &rfsilent, 0, req); 6547 if (error == 0 && req->newptr) { 6548 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) { 6549 error = EINVAL; 6550 } else { 6551 sc->sc_rfsilentpin = rfsilent & 0x1c; 6552 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0; 6553 } 6554 } 6555 wlan_serialize_exit(); 6556 return error; 6557 } 6558 6559 static int 6560 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS) 6561 { 6562 struct ath_softc *sc = arg1; 6563 u_int32_t tpack; 6564 int error; 6565 6566 wlan_serialize_enter(); 6567 (void)ath_hal_gettpack(sc->sc_ah, &tpack); 6568 error = sysctl_handle_int(oidp, &tpack, 0, req); 6569 if (error == 0 && req->newptr) { 6570 if (!ath_hal_settpack(sc->sc_ah, tpack)) 6571 error = EINVAL; 6572 } 6573 wlan_serialize_exit(); 6574 return error; 6575 } 6576 6577 static int 6578 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS) 6579 { 6580 struct ath_softc *sc = arg1; 6581 u_int32_t tpcts; 6582 int error; 6583 6584 wlan_serialize_enter(); 6585 (void)ath_hal_gettpcts(sc->sc_ah, &tpcts); 6586 error = sysctl_handle_int(oidp, &tpcts, 0, req); 6587 if (error == 0 && req->newptr) { 6588 if (!ath_hal_settpcts(sc->sc_ah, tpcts)) 6589 error = EINVAL; 6590 } 6591 wlan_serialize_exit(); 6592 return error; 6593 } 6594 6595 static int 6596 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS) 6597 { 6598 struct ath_softc *sc = arg1; 6599 int intmit, error; 6600 6601 wlan_serialize_enter(); 6602 intmit = ath_hal_getintmit(sc->sc_ah); 6603 error = sysctl_handle_int(oidp, &intmit, 0, req); 6604 if (error == 0 && req->newptr) { 6605 if (!ath_hal_setintmit(sc->sc_ah, intmit)) 6606 error = EINVAL; 6607 } 6608 wlan_serialize_exit(); 6609 return error; 6610 } 6611 6612 #ifdef IEEE80211_SUPPORT_TDMA 6613 static int 6614 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS) 6615 { 6616 struct ath_softc *sc = arg1; 6617 int setcca, error; 6618 6619 wlan_serialize_enter(); 6620 setcca = sc->sc_setcca; 6621 error = sysctl_handle_int(oidp, &setcca, 0, req); 6622 if (error == 0 && req->newptr) 6623 sc->sc_setcca = (setcca != 0); 6624 wlan_serialize_exit(); 6625 return error; 6626 } 6627 #endif /* IEEE80211_SUPPORT_TDMA */ 6628 6629 static void 6630 ath_sysctlattach(struct ath_softc *sc) 6631 { 6632 struct sysctl_ctx_list *ctx; 6633 struct sysctl_oid *tree; 6634 struct ath_hal *ah = sc->sc_ah; 6635 6636 ctx = &sc->sc_sysctl_ctx; 6637 tree = sc->sc_sysctl_tree; 6638 if (tree == NULL) { 6639 device_printf(sc->sc_dev, "can't add sysctl node\n"); 6640 return; 6641 } 6642 6643 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6644 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0, 6645 "EEPROM country code"); 6646 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6647 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0, 6648 "EEPROM regdomain code"); 6649 #ifdef ATH_DEBUG 6650 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6651 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 6652 "control debugging printfs"); 6653 #endif 6654 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6655 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6656 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 6657 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6658 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6659 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 6660 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6661 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6662 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 6663 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6664 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6665 ath_sysctl_softled, "I", "enable/disable software LED support"); 6666 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6667 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6668 ath_sysctl_ledpin, "I", "GPIO pin connected to LED"); 6669 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6670 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 6671 "setting to turn LED on"); 6672 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6673 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 6674 "idle time for inactivity LED (ticks)"); 6675 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6676 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6677 ath_sysctl_txantenna, "I", "antenna switch"); 6678 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6679 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6680 ath_sysctl_rxantenna, "I", "default/rx antenna"); 6681 if (ath_hal_hasdiversity(ah)) 6682 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6683 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6684 ath_sysctl_diversity, "I", "antenna diversity"); 6685 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 6686 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6687 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 6688 "tx descriptor batching"); 6689 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6690 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6691 ath_sysctl_diag, "I", "h/w diagnostic control"); 6692 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6693 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6694 ath_sysctl_tpscale, "I", "tx power scaling"); 6695 if (ath_hal_hastpc(ah)) { 6696 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6697 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6698 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 6699 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6700 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6701 ath_sysctl_tpack, "I", "tx power for ack frames"); 6702 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6703 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6704 ath_sysctl_tpcts, "I", "tx power for cts frames"); 6705 } 6706 if (ath_hal_hasrfsilent(ah)) { 6707 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6708 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6709 ath_sysctl_rfsilent, "I", "h/w RF silent config"); 6710 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6711 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6712 ath_sysctl_rfkill, "I", "enable/disable RF kill switch"); 6713 } 6714 if (ath_hal_hasintmit(ah)) { 6715 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6716 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6717 ath_sysctl_intmit, "I", "interference mitigation"); 6718 } 6719 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 6720 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6721 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 6722 "mask of error frames to pass when monitoring"); 6723 #ifdef IEEE80211_SUPPORT_TDMA 6724 if (ath_hal_macversion(ah) > 0x78) { 6725 sc->sc_tdmadbaprep = 2; 6726 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6727 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0, 6728 "TDMA DBA preparation time"); 6729 sc->sc_tdmaswbaprep = 10; 6730 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6731 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0, 6732 "TDMA SWBA preparation time"); 6733 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6734 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0, 6735 "TDMA slot guard time"); 6736 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6737 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0, 6738 "TDMA calculated super frame"); 6739 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 6740 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 6741 ath_sysctl_setcca, "I", "enable CCA control"); 6742 } 6743 #endif 6744 } 6745 6746 static int 6747 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 6748 struct ath_buf *bf, struct mbuf *m0, 6749 const struct ieee80211_bpf_params *params) 6750 { 6751 struct ifnet *ifp = sc->sc_ifp; 6752 struct ieee80211com *ic = ifp->if_l2com; 6753 struct ath_hal *ah = sc->sc_ah; 6754 struct ieee80211vap *vap = ni->ni_vap; 6755 int error, ismcast, ismrr; 6756 int keyix, hdrlen, pktlen, try0, txantenna; 6757 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3; 6758 struct ieee80211_frame *wh; 6759 u_int flags, ctsduration; 6760 HAL_PKT_TYPE atype; 6761 const HAL_RATE_TABLE *rt; 6762 struct ath_desc *ds; 6763 u_int pri; 6764 6765 wh = mtod(m0, struct ieee80211_frame *); 6766 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6767 hdrlen = ieee80211_anyhdrsize(wh); 6768 /* 6769 * Packet length must not include any 6770 * pad bytes; deduct them here. 6771 */ 6772 /* XXX honor IEEE80211_BPF_DATAPAD */ 6773 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 6774 6775 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) { 6776 const struct ieee80211_cipher *cip; 6777 struct ieee80211_key *k; 6778 6779 /* 6780 * Construct the 802.11 header+trailer for an encrypted 6781 * frame. The only reason this can fail is because of an 6782 * unknown or unsupported cipher/key type. 6783 */ 6784 k = ieee80211_crypto_encap(ni, m0); 6785 if (k == NULL) { 6786 /* 6787 * This can happen when the key is yanked after the 6788 * frame was queued. Just discard the frame; the 6789 * 802.11 layer counts failures and provides 6790 * debugging/diagnostics. 6791 */ 6792 ath_freetx(m0); 6793 return EIO; 6794 } 6795 /* 6796 * Adjust the packet + header lengths for the crypto 6797 * additions and calculate the h/w key index. When 6798 * a s/w mic is done the frame will have had any mic 6799 * added to it prior to entry so m0->m_pkthdr.len will 6800 * account for it. Otherwise we need to add it to the 6801 * packet length. 6802 */ 6803 cip = k->wk_cipher; 6804 hdrlen += cip->ic_header; 6805 pktlen += cip->ic_header + cip->ic_trailer; 6806 /* NB: frags always have any TKIP MIC done in s/w */ 6807 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 6808 pktlen += cip->ic_miclen; 6809 keyix = k->wk_keyix; 6810 6811 /* packet header may have moved, reset our local pointer */ 6812 wh = mtod(m0, struct ieee80211_frame *); 6813 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 6814 /* 6815 * Use station key cache slot, if assigned. 6816 */ 6817 keyix = ni->ni_ucastkey.wk_keyix; 6818 if (keyix == IEEE80211_KEYIX_NONE) 6819 keyix = HAL_TXKEYIX_INVALID; 6820 } else 6821 keyix = HAL_TXKEYIX_INVALID; 6822 6823 error = ath_tx_dmasetup(sc, bf, m0); 6824 if (error != 0) 6825 return error; 6826 m0 = bf->bf_m; /* NB: may have changed */ 6827 wh = mtod(m0, struct ieee80211_frame *); 6828 bf->bf_node = ni; /* NB: held reference */ 6829 6830 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 6831 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 6832 if (params->ibp_flags & IEEE80211_BPF_RTS) 6833 flags |= HAL_TXDESC_RTSENA; 6834 else if (params->ibp_flags & IEEE80211_BPF_CTS) 6835 flags |= HAL_TXDESC_CTSENA; 6836 /* XXX leave ismcast to injector? */ 6837 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 6838 flags |= HAL_TXDESC_NOACK; 6839 6840 rt = sc->sc_currates; 6841 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 6842 rix = ath_tx_findrix(sc, params->ibp_rate0); 6843 txrate = rt->info[rix].rateCode; 6844 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6845 txrate |= rt->info[rix].shortPreamble; 6846 sc->sc_txrix = rix; 6847 try0 = params->ibp_try0; 6848 ismrr = (params->ibp_try1 != 0); 6849 txantenna = params->ibp_pri >> 2; 6850 if (txantenna == 0) /* XXX? */ 6851 txantenna = sc->sc_txantenna; 6852 ctsduration = 0; 6853 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { 6854 cix = ath_tx_findrix(sc, params->ibp_ctsrate); 6855 ctsrate = rt->info[cix].rateCode; 6856 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) { 6857 ctsrate |= rt->info[cix].shortPreamble; 6858 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6859 ctsduration += rt->info[cix].spAckDuration; 6860 ctsduration += ath_hal_computetxtime(ah, 6861 rt, pktlen, rix, AH_TRUE); 6862 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6863 ctsduration += rt->info[rix].spAckDuration; 6864 } else { 6865 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 6866 ctsduration += rt->info[cix].lpAckDuration; 6867 ctsduration += ath_hal_computetxtime(ah, 6868 rt, pktlen, rix, AH_FALSE); 6869 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 6870 ctsduration += rt->info[rix].lpAckDuration; 6871 } 6872 ismrr = 0; /* XXX */ 6873 } else 6874 ctsrate = 0; 6875 pri = params->ibp_pri & 3; 6876 /* 6877 * NB: we mark all packets as type PSPOLL so the h/w won't 6878 * set the sequence number, duration, etc. 6879 */ 6880 atype = HAL_PKT_TYPE_PSPOLL; 6881 6882 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 6883 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 6884 sc->sc_hwmap[rix].ieeerate, -1); 6885 6886 if (ieee80211_radiotap_active_vap(vap)) { 6887 u_int64_t tsf = ath_hal_gettsf64(ah); 6888 6889 sc->sc_tx_th.wt_tsf = htole64(tsf); 6890 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 6891 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 6892 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6893 if (m0->m_flags & M_FRAG) 6894 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 6895 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 6896 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 6897 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 6898 6899 ieee80211_radiotap_tx(vap, m0); 6900 } 6901 6902 /* 6903 * Formulate first tx descriptor with tx controls. 6904 */ 6905 ds = bf->bf_desc; 6906 /* XXX check return value? */ 6907 ath_hal_setuptxdesc(ah, ds 6908 , pktlen /* packet length */ 6909 , hdrlen /* header length */ 6910 , atype /* Atheros packet type */ 6911 , params->ibp_power /* txpower */ 6912 , txrate, try0 /* series 0 rate/tries */ 6913 , keyix /* key cache index */ 6914 , txantenna /* antenna mode */ 6915 , flags /* flags */ 6916 , ctsrate /* rts/cts rate */ 6917 , ctsduration /* rts/cts duration */ 6918 ); 6919 bf->bf_txflags = flags; 6920 6921 if (ismrr) { 6922 rix = ath_tx_findrix(sc, params->ibp_rate1); 6923 rate1 = rt->info[rix].rateCode; 6924 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6925 rate1 |= rt->info[rix].shortPreamble; 6926 if (params->ibp_try2) { 6927 rix = ath_tx_findrix(sc, params->ibp_rate2); 6928 rate2 = rt->info[rix].rateCode; 6929 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6930 rate2 |= rt->info[rix].shortPreamble; 6931 } else 6932 rate2 = 0; 6933 if (params->ibp_try3) { 6934 rix = ath_tx_findrix(sc, params->ibp_rate3); 6935 rate3 = rt->info[rix].rateCode; 6936 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 6937 rate3 |= rt->info[rix].shortPreamble; 6938 } else 6939 rate3 = 0; 6940 ath_hal_setupxtxdesc(ah, ds 6941 , rate1, params->ibp_try1 /* series 1 */ 6942 , rate2, params->ibp_try2 /* series 2 */ 6943 , rate3, params->ibp_try3 /* series 3 */ 6944 ); 6945 } 6946 6947 /* NB: no buffered multicast in power save support */ 6948 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf); 6949 return 0; 6950 } 6951 6952 static int 6953 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 6954 const struct ieee80211_bpf_params *params) 6955 { 6956 struct ieee80211com *ic = ni->ni_ic; 6957 struct ifnet *ifp = ic->ic_ifp; 6958 struct ath_softc *sc = ifp->if_softc; 6959 struct ath_buf *bf; 6960 int error; 6961 6962 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) { 6963 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 6964 (ifp->if_flags & IFF_RUNNING) == 0 ? 6965 "!running" : "invalid"); 6966 m_freem(m); 6967 error = ENETDOWN; 6968 goto bad; 6969 } 6970 /* 6971 * Grab a TX buffer and associated resources. 6972 */ 6973 bf = ath_getbuf(sc); 6974 if (bf == NULL) { 6975 sc->sc_stats.ast_tx_nobuf++; 6976 m_freem(m); 6977 error = ENOBUFS; 6978 goto bad; 6979 } 6980 6981 if (params == NULL) { 6982 /* 6983 * Legacy path; interpret frame contents to decide 6984 * precisely how to send the frame. 6985 */ 6986 if (ath_tx_start(sc, ni, bf, m)) { 6987 error = EIO; /* XXX */ 6988 goto bad2; 6989 } 6990 } else { 6991 /* 6992 * Caller supplied explicit parameters to use in 6993 * sending the frame. 6994 */ 6995 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 6996 error = EIO; /* XXX */ 6997 goto bad2; 6998 } 6999 } 7000 sc->sc_wd_timer = 5; 7001 IFNET_STAT_INC(ifp, opackets, 1); 7002 sc->sc_stats.ast_tx_raw++; 7003 7004 return 0; 7005 bad2: 7006 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list); 7007 bad: 7008 IFNET_STAT_INC(ifp, oerrors, 1); 7009 sc->sc_stats.ast_tx_raw_fail++; 7010 ieee80211_free_node(ni); 7011 return error; 7012 } 7013 7014 /* 7015 * Announce various information on device/driver attach. 7016 */ 7017 static void 7018 ath_announce(struct ath_softc *sc) 7019 { 7020 struct ifnet *ifp = sc->sc_ifp; 7021 struct ath_hal *ah = sc->sc_ah; 7022 7023 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n", 7024 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev, 7025 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 7026 if (bootverbose) { 7027 int i; 7028 for (i = 0; i <= WME_AC_VO; i++) { 7029 struct ath_txq *txq = sc->sc_ac2q[i]; 7030 if_printf(ifp, "Use hw queue %u for %s traffic\n", 7031 txq->axq_qnum, ieee80211_wme_acnames[i]); 7032 } 7033 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 7034 sc->sc_cabq->axq_qnum); 7035 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 7036 } 7037 if (ath_rxbuf != ATH_RXBUF) 7038 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf); 7039 if (ath_txbuf != ATH_TXBUF) 7040 if_printf(ifp, "using %u tx buffers\n", ath_txbuf); 7041 if (sc->sc_mcastkey && bootverbose) 7042 if_printf(ifp, "using multicast key search\n"); 7043 } 7044 7045 #ifdef IEEE80211_SUPPORT_TDMA 7046 static __inline uint32_t 7047 ath_hal_getnexttbtt(struct ath_hal *ah) 7048 { 7049 #define AR_TIMER0 0x8028 7050 return OS_REG_READ(ah, AR_TIMER0); 7051 } 7052 7053 static __inline void 7054 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta) 7055 { 7056 /* XXX handle wrap/overflow */ 7057 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta); 7058 } 7059 7060 static void 7061 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 7062 { 7063 struct ath_hal *ah = sc->sc_ah; 7064 HAL_BEACON_TIMERS bt; 7065 7066 bt.bt_intval = bintval | HAL_BEACON_ENA; 7067 bt.bt_nexttbtt = nexttbtt; 7068 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 7069 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 7070 bt.bt_nextatim = nexttbtt+1; 7071 ath_hal_beaconsettimers(ah, &bt); 7072 } 7073 7074 /* 7075 * Calculate the beacon interval. This is periodic in the 7076 * superframe for the bss. We assume each station is configured 7077 * identically wrt transmit rate so the guard time we calculate 7078 * above will be the same on all stations. Note we need to 7079 * factor in the xmit time because the hardware will schedule 7080 * a frame for transmit if the start of the frame is within 7081 * the burst time. When we get hardware that properly kills 7082 * frames in the PCU we can reduce/eliminate the guard time. 7083 * 7084 * Roundup to 1024 is so we have 1 TU buffer in the guard time 7085 * to deal with the granularity of the nexttbtt timer. 11n MAC's 7086 * with 1us timer granularity should allow us to reduce/eliminate 7087 * this. 7088 */ 7089 static void 7090 ath_tdma_bintvalsetup(struct ath_softc *sc, 7091 const struct ieee80211_tdma_state *tdma) 7092 { 7093 /* copy from vap state (XXX check all vaps have same value?) */ 7094 sc->sc_tdmaslotlen = tdma->tdma_slotlen; 7095 7096 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 7097 tdma->tdma_slotcnt, 1024); 7098 sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 7099 if (sc->sc_tdmabintval & 1) 7100 sc->sc_tdmabintval++; 7101 7102 if (tdma->tdma_slot == 0) { 7103 /* 7104 * Only slot 0 beacons; other slots respond. 7105 */ 7106 sc->sc_imask |= HAL_INT_SWBA; 7107 sc->sc_tdmaswba = 0; /* beacon immediately */ 7108 } else { 7109 /* XXX all vaps must be slot 0 or slot !0 */ 7110 sc->sc_imask &= ~HAL_INT_SWBA; 7111 } 7112 } 7113 7114 /* 7115 * Max 802.11 overhead. This assumes no 4-address frames and 7116 * the encapsulation done by ieee80211_encap (llc). We also 7117 * include potential crypto overhead. 7118 */ 7119 #define IEEE80211_MAXOVERHEAD \ 7120 (sizeof(struct ieee80211_qosframe) \ 7121 + sizeof(struct llc) \ 7122 + IEEE80211_ADDR_LEN \ 7123 + IEEE80211_WEP_IVLEN \ 7124 + IEEE80211_WEP_KIDLEN \ 7125 + IEEE80211_WEP_CRCLEN \ 7126 + IEEE80211_WEP_MICLEN \ 7127 + IEEE80211_CRC_LEN) 7128 7129 /* 7130 * Setup initially for tdma operation. Start the beacon 7131 * timers and enable SWBA if we are slot 0. Otherwise 7132 * we wait for slot 0 to arrive so we can sync up before 7133 * starting to transmit. 7134 */ 7135 static void 7136 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 7137 { 7138 struct ath_hal *ah = sc->sc_ah; 7139 struct ifnet *ifp = sc->sc_ifp; 7140 struct ieee80211com *ic = ifp->if_l2com; 7141 const struct ieee80211_txparam *tp; 7142 const struct ieee80211_tdma_state *tdma = NULL; 7143 int rix; 7144 7145 if (vap == NULL) { 7146 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 7147 if (vap == NULL) { 7148 if_printf(ifp, "%s: no vaps?\n", __func__); 7149 return; 7150 } 7151 } 7152 tp = vap->iv_bss->ni_txparms; 7153 /* 7154 * Calculate the guard time for each slot. This is the 7155 * time to send a maximal-size frame according to the 7156 * fixed/lowest transmit rate. Note that the interface 7157 * mtu does not include the 802.11 overhead so we must 7158 * tack that on (ath_hal_computetxtime includes the 7159 * preamble and plcp in it's calculation). 7160 */ 7161 tdma = vap->iv_tdma; 7162 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 7163 rix = ath_tx_findrix(sc, tp->ucastrate); 7164 else 7165 rix = ath_tx_findrix(sc, tp->mcastrate); 7166 /* XXX short preamble assumed */ 7167 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 7168 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 7169 7170 ath_hal_intrset(ah, 0); 7171 7172 ath_beaconq_config(sc); /* setup h/w beacon q */ 7173 if (sc->sc_setcca) 7174 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 7175 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 7176 ath_tdma_settimers(sc, sc->sc_tdmabintval, 7177 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 7178 sc->sc_syncbeacon = 0; 7179 7180 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 7181 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 7182 7183 ath_hal_intrset(ah, sc->sc_imask); 7184 7185 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 7186 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 7187 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 7188 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 7189 sc->sc_tdmadbaprep); 7190 } 7191 7192 /* 7193 * Update tdma operation. Called from the 802.11 layer 7194 * when a beacon is received from the TDMA station operating 7195 * in the slot immediately preceding us in the bss. Use 7196 * the rx timestamp for the beacon frame to update our 7197 * beacon timers so we follow their schedule. Note that 7198 * by using the rx timestamp we implicitly include the 7199 * propagation delay in our schedule. 7200 */ 7201 static void 7202 ath_tdma_update(struct ieee80211_node *ni, 7203 const struct ieee80211_tdma_param *tdma, int changed) 7204 { 7205 #define TSF_TO_TU(_h,_l) \ 7206 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 7207 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 7208 struct ieee80211vap *vap = ni->ni_vap; 7209 struct ieee80211com *ic = ni->ni_ic; 7210 struct ath_softc *sc = ic->ic_ifp->if_softc; 7211 struct ath_hal *ah = sc->sc_ah; 7212 const HAL_RATE_TABLE *rt = sc->sc_currates; 7213 u_int64_t tsf, rstamp, nextslot; 7214 u_int32_t txtime, nextslottu, timer0; 7215 int32_t tudelta, tsfdelta; 7216 const struct ath_rx_status *rs; 7217 int rix; 7218 7219 sc->sc_stats.ast_tdma_update++; 7220 7221 /* 7222 * Check for and adopt configuration changes. 7223 */ 7224 if (changed != 0) { 7225 const struct ieee80211_tdma_state *ts = vap->iv_tdma; 7226 7227 ath_tdma_bintvalsetup(sc, ts); 7228 if (changed & TDMA_UPDATE_SLOTLEN) 7229 ath_wme_update(ic); 7230 7231 DPRINTF(sc, ATH_DEBUG_TDMA, 7232 "%s: adopt slot %u slotcnt %u slotlen %u us " 7233 "bintval %u TU\n", __func__, 7234 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 7235 sc->sc_tdmabintval); 7236 7237 /* XXX right? */ 7238 ath_hal_intrset(ah, sc->sc_imask); 7239 /* NB: beacon timers programmed below */ 7240 } 7241 7242 /* extend rx timestamp to 64 bits */ 7243 rs = sc->sc_lastrs; 7244 tsf = ath_hal_gettsf64(ah); 7245 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf); 7246 /* 7247 * The rx timestamp is set by the hardware on completing 7248 * reception (at the point where the rx descriptor is DMA'd 7249 * to the host). To find the start of our next slot we 7250 * must adjust this time by the time required to send 7251 * the packet just received. 7252 */ 7253 rix = rt->rateCodeToIndex[rs->rs_rate]; 7254 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 7255 rt->info[rix].shortPreamble); 7256 /* NB: << 9 is to cvt to TU and /2 */ 7257 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 7258 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD; 7259 7260 /* 7261 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert 7262 * to usecs and calculate the difference between what the 7263 * other station thinks and what we have programmed. This 7264 * lets us figure how to adjust our timers to match. The 7265 * adjustments are done by pulling the TSF forward and possibly 7266 * rewriting the beacon timers. 7267 */ 7268 timer0 = ath_hal_getnexttbtt(ah); 7269 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0)); 7270 7271 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7272 "tsfdelta %d avg +%d/-%d\n", tsfdelta, 7273 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 7274 7275 if (tsfdelta < 0) { 7276 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7277 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 7278 tsfdelta = -tsfdelta % 1024; 7279 nextslottu++; 7280 } else if (tsfdelta > 0) { 7281 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 7282 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7283 tsfdelta = 1024 - (tsfdelta % 1024); 7284 nextslottu++; 7285 } else { 7286 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 7287 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 7288 } 7289 tudelta = nextslottu - timer0; 7290 7291 /* 7292 * Copy sender's timetstamp into tdma ie so they can 7293 * calculate roundtrip time. We submit a beacon frame 7294 * below after any timer adjustment. The frame goes out 7295 * at the next TBTT so the sender can calculate the 7296 * roundtrip by inspecting the tdma ie in our beacon frame. 7297 * 7298 * NB: This tstamp is subtlely preserved when 7299 * IEEE80211_BEACON_TDMA is marked (e.g. when the 7300 * slot position changes) because ieee80211_add_tdma 7301 * skips over the data. 7302 */ 7303 memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 7304 __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 7305 &ni->ni_tstamp.data, 8); 7306 #if 0 7307 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 7308 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n", 7309 (unsigned long long) tsf, (unsigned long long) nextslot, 7310 (int)(nextslot - tsf), tsfdelta, 7311 nextslottu, timer0, tudelta); 7312 #endif 7313 /* 7314 * Adjust the beacon timers only when pulling them forward 7315 * or when going back by less than the beacon interval. 7316 * Negative jumps larger than the beacon interval seem to 7317 * cause the timers to stop and generally cause instability. 7318 * This basically filters out jumps due to missed beacons. 7319 */ 7320 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 7321 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 7322 sc->sc_stats.ast_tdma_timers++; 7323 } 7324 if (tsfdelta > 0) { 7325 ath_hal_adjusttsf(ah, tsfdelta); 7326 sc->sc_stats.ast_tdma_tsf++; 7327 } 7328 ath_tdma_beacon_send(sc, vap); /* prepare response */ 7329 #undef TU_TO_TSF 7330 #undef TSF_TO_TU 7331 } 7332 7333 /* 7334 * Transmit a beacon frame at SWBA. Dynamic updates 7335 * to the frame contents are done as needed. 7336 */ 7337 static void 7338 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 7339 { 7340 struct ath_hal *ah = sc->sc_ah; 7341 struct ath_buf *bf; 7342 int otherant; 7343 7344 /* 7345 * Check if the previous beacon has gone out. If 7346 * not don't try to post another, skip this period 7347 * and wait for the next. Missed beacons indicate 7348 * a problem and should not occur. If we miss too 7349 * many consecutive beacons reset the device. 7350 */ 7351 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 7352 sc->sc_bmisscount++; 7353 DPRINTF(sc, ATH_DEBUG_BEACON, 7354 "%s: missed %u consecutive beacons\n", 7355 __func__, sc->sc_bmisscount); 7356 if (sc->sc_bmisscount >= ath_bstuck_threshold) 7357 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 7358 return; 7359 } 7360 if (sc->sc_bmisscount != 0) { 7361 DPRINTF(sc, ATH_DEBUG_BEACON, 7362 "%s: resume beacon xmit after %u misses\n", 7363 __func__, sc->sc_bmisscount); 7364 sc->sc_bmisscount = 0; 7365 } 7366 7367 /* 7368 * Check recent per-antenna transmit statistics and flip 7369 * the default antenna if noticeably more frames went out 7370 * on the non-default antenna. 7371 * XXX assumes 2 anntenae 7372 */ 7373 if (!sc->sc_diversity) { 7374 otherant = sc->sc_defant & 1 ? 2 : 1; 7375 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 7376 ath_setdefantenna(sc, otherant); 7377 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 7378 } 7379 7380 /* 7381 * Stop any current dma before messing with the beacon linkages. 7382 * 7383 * This should never fail since we check above that no frames 7384 * are still pending on the queue. 7385 */ 7386 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 7387 DPRINTF(sc, ATH_DEBUG_ANY, 7388 "%s: beacon queue %u did not stop?\n", 7389 __func__, sc->sc_bhalq); 7390 /* NB: the HAL still stops DMA, so proceed */ 7391 } 7392 bf = ath_beacon_generate(sc, vap); 7393 if (bf != NULL) { 7394 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 7395 ath_hal_txstart(ah, sc->sc_bhalq); 7396 7397 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 7398 7399 /* 7400 * Record local TSF for our last send for use 7401 * in arbitrating slot collisions. 7402 */ 7403 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 7404 } else { 7405 device_printf(sc->sc_dev, "tdma beacon gen failed!\n"); 7406 } 7407 } 7408 #endif /* IEEE80211_SUPPORT_TDMA */ 7409 7410 static int 7411 ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS) 7412 { 7413 struct ath_softc *sc = arg1; 7414 int val = 0; 7415 int error; 7416 7417 error = sysctl_handle_int(oidp, &val, 0, req); 7418 if (error || !req->newptr) 7419 return error; 7420 if (val == 0) 7421 return 0; /* Not clearing the stats is still valid */ 7422 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats)); 7423 val = 0; 7424 return 0; 7425 } 7426 7427 static void 7428 ath_sysctl_stats_attach(struct ath_softc *sc) 7429 { 7430 struct sysctl_oid *tree; 7431 struct sysctl_ctx_list *ctx; 7432 struct sysctl_oid_list *child; 7433 7434 ctx = &sc->sc_sysctl_ctx; 7435 tree = sc->sc_sysctl_tree; 7436 child = SYSCTL_CHILDREN(tree); 7437 7438 /* Create "clear" node */ 7439 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 7440 "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 7441 ath_sysctl_clearstats, "I", "clear stats"); 7442 7443 /* Create stats node */ 7444 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 7445 NULL, "Statistics"); 7446 child = SYSCTL_CHILDREN(tree); 7447 7448 /* This was generated from if_athioctl.h */ 7449 7450 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD, 7451 &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog"); 7452 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD, 7453 &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts"); 7454 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD, 7455 &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts"); 7456 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD, 7457 &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts"); 7458 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD, 7459 &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts"); 7460 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD, 7461 &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts"); 7462 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD, 7463 &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts"); 7464 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD, 7465 &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts"); 7466 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD, 7467 &sc->sc_stats.ast_mib, 0, "mib interrupts"); 7468 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD, 7469 &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced"); 7470 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD, 7471 &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface"); 7472 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD, 7473 &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted"); 7474 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD, 7475 &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc"); 7476 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD, 7477 &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer"); 7478 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD, 7479 &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed"); 7480 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD, 7481 &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node"); 7482 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD, 7483 &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf"); 7484 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD, 7485 &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster"); 7486 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD, 7487 &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster"); 7488 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD, 7489 &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame"); 7490 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD, 7491 &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs"); 7492 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD, 7493 &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries"); 7494 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD, 7495 &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun"); 7496 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD, 7497 &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered"); 7498 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD, 7499 &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)"); 7500 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD, 7501 &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)"); 7502 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD, 7503 &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate"); 7504 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD, 7505 &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked"); 7506 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD, 7507 &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled"); 7508 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD, 7509 &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled"); 7510 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD, 7511 &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble"); 7512 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD, 7513 &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate"); 7514 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD, 7515 &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection"); 7516 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD, 7517 &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting"); 7518 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD, 7519 &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension"); 7520 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD, 7521 &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf"); 7522 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD, 7523 &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs"); 7524 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD, 7525 &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun"); 7526 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD, 7527 &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC"); 7528 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD, 7529 &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun"); 7530 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD, 7531 &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption"); 7532 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD, 7533 &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure"); 7534 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD, 7535 &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err"); 7536 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD, 7537 &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short"); 7538 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD, 7539 &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large"); 7540 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD, 7541 &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface"); 7542 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD, 7543 &sc->sc_stats.ast_rx_mgt, 0, "management frames received"); 7544 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD, 7545 &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame"); 7546 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD, 7547 &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted"); 7548 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD, 7549 &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf"); 7550 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD, 7551 &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls"); 7552 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD, 7553 &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed"); 7554 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD, 7555 &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset"); 7556 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD, 7557 &sc->sc_stats.ast_rate_calls, 0, "rate control checks"); 7558 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD, 7559 &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate"); 7560 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD, 7561 &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate"); 7562 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD, 7563 &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches"); 7564 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD, 7565 &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches"); 7566 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD, 7567 &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted"); 7568 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD, 7569 &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy"); 7570 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD, 7571 &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api"); 7572 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD, 7573 &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully"); 7574 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD, 7575 &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error"); 7576 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD, 7577 &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd"); 7578 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD, 7579 &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q"); 7580 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD, 7581 &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit"); 7582 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD, 7583 &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer"); 7584 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD, 7585 &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates"); 7586 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD, 7587 &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers"); 7588 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD, 7589 &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF"); 7590 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD, 7591 &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required"); 7592 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD, 7593 &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down"); 7594 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD, 7595 &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer"); 7596 #if 0 7597 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD, 7598 &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons"); 7599 #endif 7600 } 7601