1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 72 #if defined(__DragonFly__) 73 /* empty */ 74 #else 75 #include <sys/smp.h> /* for mp_ncpus */ 76 #include <machine/bus.h> 77 #endif 78 79 #include <net/if.h> 80 #include <net/if_var.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_arp.h> 85 #include <net/ethernet.h> 86 #include <net/if_llc.h> 87 88 #include <netproto/802_11/ieee80211_var.h> 89 #include <netproto/802_11/ieee80211_regdomain.h> 90 #ifdef IEEE80211_SUPPORT_SUPERG 91 #include <netproto/802_11/ieee80211_superg.h> 92 #endif 93 94 #include <net/bpf.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_ether.h> 99 #endif 100 101 #include <dev/netif/ath/ath/if_athvar.h> 102 103 #include <dev/netif/ath/ath/if_ath_debug.h> 104 #include <dev/netif/ath/ath/if_ath_misc.h> 105 #include <dev/netif/ath/ath/if_ath_tx.h> 106 #include <dev/netif/ath/ath/if_ath_beacon.h> 107 108 #ifdef ATH_TX99_DIAG 109 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h> 110 #endif 111 112 /* 113 * Setup a h/w transmit queue for beacons. 114 */ 115 int 116 ath_beaconq_setup(struct ath_softc *sc) 117 { 118 struct ath_hal *ah = sc->sc_ah; 119 HAL_TXQ_INFO qi; 120 121 memset(&qi, 0, sizeof(qi)); 122 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 123 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 124 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 125 /* NB: for dynamic turbo, don't enable any other interrupts */ 126 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 127 if (sc->sc_isedma) 128 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 129 HAL_TXQ_TXERRINT_ENABLE; 130 131 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 132 } 133 134 /* 135 * Setup the transmit queue parameters for the beacon queue. 136 */ 137 int 138 ath_beaconq_config(struct ath_softc *sc) 139 { 140 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 141 struct ieee80211com *ic = &sc->sc_ic; 142 struct ath_hal *ah = sc->sc_ah; 143 HAL_TXQ_INFO qi; 144 145 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 146 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 147 ic->ic_opmode == IEEE80211_M_MBSS) { 148 /* 149 * Always burst out beacon and CAB traffic. 150 */ 151 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 152 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 153 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 154 } else { 155 struct wmeParams *wmep = 156 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 157 /* 158 * Adhoc mode; important thing is to use 2x cwmin. 159 */ 160 qi.tqi_aifs = wmep->wmep_aifsn; 161 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 162 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 163 } 164 165 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 166 device_printf(sc->sc_dev, "unable to update parameters for " 167 "beacon hardware queue!\n"); 168 return 0; 169 } else { 170 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 171 return 1; 172 } 173 #undef ATH_EXPONENT_TO_VALUE 174 } 175 176 /* 177 * Allocate and setup an initial beacon frame. 178 */ 179 int 180 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 181 { 182 struct ieee80211vap *vap = ni->ni_vap; 183 struct ath_vap *avp = ATH_VAP(vap); 184 struct ath_buf *bf; 185 struct mbuf *m; 186 int error; 187 188 bf = avp->av_bcbuf; 189 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 190 __func__, bf->bf_m, bf->bf_node); 191 if (bf->bf_m != NULL) { 192 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 193 m_freem(bf->bf_m); 194 bf->bf_m = NULL; 195 } 196 if (bf->bf_node != NULL) { 197 ieee80211_free_node(bf->bf_node); 198 bf->bf_node = NULL; 199 } 200 201 /* 202 * NB: the beacon data buffer must be 32-bit aligned; 203 * we assume the mbuf routines will return us something 204 * with this alignment (perhaps should assert). 205 */ 206 m = ieee80211_beacon_alloc(ni); 207 if (m == NULL) { 208 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 209 sc->sc_stats.ast_be_nombuf++; 210 return ENOMEM; 211 } 212 #if defined(__DragonFly__) 213 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 214 bf->bf_segs, 1, &bf->bf_nseg, 215 BUS_DMA_NOWAIT); 216 #else 217 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 218 bf->bf_segs, &bf->bf_nseg, 219 BUS_DMA_NOWAIT); 220 #endif 221 if (error != 0) { 222 device_printf(sc->sc_dev, 223 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 224 __func__, error); 225 m_freem(m); 226 return error; 227 } 228 229 /* 230 * Calculate a TSF adjustment factor required for staggered 231 * beacons. Note that we assume the format of the beacon 232 * frame leaves the tstamp field immediately following the 233 * header. 234 */ 235 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 236 uint64_t tsfadjust; 237 struct ieee80211_frame *wh; 238 239 /* 240 * The beacon interval is in TU's; the TSF is in usecs. 241 * We figure out how many TU's to add to align the timestamp 242 * then convert to TSF units and handle byte swapping before 243 * inserting it in the frame. The hardware will then add this 244 * each time a beacon frame is sent. Note that we align vap's 245 * 1..N and leave vap 0 untouched. This means vap 0 has a 246 * timestamp in one beacon interval while the others get a 247 * timstamp aligned to the next interval. 248 */ 249 tsfadjust = ni->ni_intval * 250 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 251 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 252 253 DPRINTF(sc, ATH_DEBUG_BEACON, 254 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 255 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 256 avp->av_bslot, ni->ni_intval, 257 (long long unsigned) le64toh(tsfadjust)); 258 259 wh = mtod(m, struct ieee80211_frame *); 260 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 261 } 262 bf->bf_m = m; 263 bf->bf_node = ieee80211_ref_node(ni); 264 265 return 0; 266 } 267 268 /* 269 * Setup the beacon frame for transmit. 270 */ 271 static void 272 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 273 { 274 #define USE_SHPREAMBLE(_ic) \ 275 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 276 == IEEE80211_F_SHPREAMBLE) 277 struct ieee80211_node *ni = bf->bf_node; 278 struct ieee80211com *ic = ni->ni_ic; 279 struct mbuf *m = bf->bf_m; 280 struct ath_hal *ah = sc->sc_ah; 281 struct ath_desc *ds; 282 int flags, antenna; 283 const HAL_RATE_TABLE *rt; 284 u_int8_t rix, rate; 285 HAL_DMA_ADDR bufAddrList[4]; 286 uint32_t segLenList[4]; 287 HAL_11N_RATE_SERIES rc[4]; 288 289 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 290 __func__, m, m->m_len); 291 292 /* setup descriptors */ 293 ds = bf->bf_desc; 294 bf->bf_last = bf; 295 bf->bf_lastds = ds; 296 297 flags = HAL_TXDESC_NOACK; 298 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 299 /* self-linked descriptor */ 300 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 301 flags |= HAL_TXDESC_VEOL; 302 /* 303 * Let hardware handle antenna switching. 304 */ 305 antenna = sc->sc_txantenna; 306 } else { 307 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 308 /* 309 * Switch antenna every 4 beacons. 310 * XXX assumes two antenna 311 */ 312 if (sc->sc_txantenna != 0) 313 antenna = sc->sc_txantenna; 314 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 315 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 316 else 317 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 318 } 319 320 KASSERT(bf->bf_nseg == 1, 321 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 322 323 /* 324 * Calculate rate code. 325 * XXX everything at min xmit rate 326 */ 327 rix = 0; 328 rt = sc->sc_currates; 329 rate = rt->info[rix].rateCode; 330 if (USE_SHPREAMBLE(ic)) 331 rate |= rt->info[rix].shortPreamble; 332 ath_hal_setuptxdesc(ah, ds 333 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 334 , sizeof(struct ieee80211_frame)/* header length */ 335 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 336 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 337 , rate, 1 /* series 0 rate/tries */ 338 , HAL_TXKEYIX_INVALID /* no encryption */ 339 , antenna /* antenna mode */ 340 , flags /* no ack, veol for beacons */ 341 , 0 /* rts/cts rate */ 342 , 0 /* rts/cts duration */ 343 ); 344 345 /* 346 * The EDMA HAL currently assumes that _all_ rate control 347 * settings are done in ath_hal_set11nratescenario(), rather 348 * than in ath_hal_setuptxdesc(). 349 */ 350 if (sc->sc_isedma) { 351 memset(&rc, 0, sizeof(rc)); 352 353 rc[0].ChSel = sc->sc_txchainmask; 354 rc[0].Tries = 1; 355 rc[0].Rate = rt->info[rix].rateCode; 356 rc[0].RateIndex = rix; 357 rc[0].tx_power_cap = 0x3f; 358 rc[0].PktDuration = 359 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 360 rix, 0); 361 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 362 } 363 364 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 365 segLenList[0] = roundup(m->m_len, 4); 366 segLenList[1] = segLenList[2] = segLenList[3] = 0; 367 bufAddrList[0] = bf->bf_segs[0].ds_addr; 368 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 369 ath_hal_filltxdesc(ah, ds 370 , bufAddrList 371 , segLenList 372 , 0 /* XXX desc id */ 373 , sc->sc_bhalq /* hardware TXQ */ 374 , AH_TRUE /* first segment */ 375 , AH_TRUE /* last segment */ 376 , ds /* first descriptor */ 377 ); 378 #if 0 379 ath_desc_swap(ds); 380 #endif 381 #undef USE_SHPREAMBLE 382 } 383 384 void 385 ath_beacon_update(struct ieee80211vap *vap, int item) 386 { 387 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off; 388 389 setbit(bo->bo_flags, item); 390 } 391 392 /* 393 * Handle a beacon miss. 394 */ 395 void 396 ath_beacon_miss(struct ath_softc *sc) 397 { 398 HAL_SURVEY_SAMPLE hs; 399 HAL_BOOL ret; 400 uint32_t hangs; 401 402 bzero(&hs, sizeof(hs)); 403 404 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 405 406 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 407 DPRINTF(sc, ATH_DEBUG_BEACON, 408 "%s: hang=0x%08x\n", 409 __func__, 410 hangs); 411 } 412 413 #ifdef ATH_DEBUG_ALQ 414 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 415 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 416 #endif 417 418 DPRINTF(sc, ATH_DEBUG_BEACON, 419 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 420 "extchanbusy=%u, cyclecount=%u\n", 421 __func__, 422 ret, 423 hs.tx_busy, 424 hs.rx_busy, 425 hs.chan_busy, 426 hs.ext_chan_busy, 427 hs.cycle_count); 428 } 429 430 /* 431 * Transmit a beacon frame at SWBA. Dynamic updates to the 432 * frame contents are done as needed and the slot time is 433 * also adjusted based on current state. 434 */ 435 void 436 ath_beacon_proc(void *arg, int pending) 437 { 438 struct ath_softc *sc = arg; 439 struct ath_hal *ah = sc->sc_ah; 440 struct ieee80211vap *vap; 441 struct ath_buf *bf; 442 int slot, otherant; 443 uint32_t bfaddr; 444 445 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 446 __func__, pending); 447 /* 448 * Check if the previous beacon has gone out. If 449 * not don't try to post another, skip this period 450 * and wait for the next. Missed beacons indicate 451 * a problem and should not occur. If we miss too 452 * many consecutive beacons reset the device. 453 */ 454 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 455 sc->sc_bmisscount++; 456 sc->sc_stats.ast_be_missed++; 457 ath_beacon_miss(sc); 458 DPRINTF(sc, ATH_DEBUG_BEACON, 459 "%s: missed %u consecutive beacons\n", 460 __func__, sc->sc_bmisscount); 461 if (sc->sc_bmisscount >= ath_bstuck_threshold) 462 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 463 return; 464 } 465 if (sc->sc_bmisscount != 0) { 466 DPRINTF(sc, ATH_DEBUG_BEACON, 467 "%s: resume beacon xmit after %u misses\n", 468 __func__, sc->sc_bmisscount); 469 sc->sc_bmisscount = 0; 470 #ifdef ATH_DEBUG_ALQ 471 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 472 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 473 #endif 474 } 475 476 if (sc->sc_stagbeacons) { /* staggered beacons */ 477 struct ieee80211com *ic = &sc->sc_ic; 478 uint32_t tsftu; 479 480 tsftu = ath_hal_gettsf32(ah) >> 10; 481 /* XXX lintval */ 482 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 483 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 484 bfaddr = 0; 485 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 486 bf = ath_beacon_generate(sc, vap); 487 if (bf != NULL) 488 bfaddr = bf->bf_daddr; 489 } 490 } else { /* burst'd beacons */ 491 uint32_t *bflink = &bfaddr; 492 493 for (slot = 0; slot < ATH_BCBUF; slot++) { 494 vap = sc->sc_bslot[slot]; 495 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 496 bf = ath_beacon_generate(sc, vap); 497 /* 498 * XXX TODO: this should use settxdesclinkptr() 499 * otherwise it won't work for EDMA chipsets! 500 */ 501 if (bf != NULL) { 502 /* XXX should do this using the ds */ 503 *bflink = bf->bf_daddr; 504 ath_hal_gettxdesclinkptr(sc->sc_ah, 505 bf->bf_desc, &bflink); 506 } 507 } 508 } 509 /* 510 * XXX TODO: this should use settxdesclinkptr() 511 * otherwise it won't work for EDMA chipsets! 512 */ 513 *bflink = 0; /* terminate list */ 514 } 515 516 /* 517 * Handle slot time change when a non-ERP station joins/leaves 518 * an 11g network. The 802.11 layer notifies us via callback, 519 * we mark updateslot, then wait one beacon before effecting 520 * the change. This gives associated stations at least one 521 * beacon interval to note the state change. 522 */ 523 /* XXX locking */ 524 if (sc->sc_updateslot == UPDATE) { 525 sc->sc_updateslot = COMMIT; /* commit next beacon */ 526 sc->sc_slotupdate = slot; 527 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 528 ath_setslottime(sc); /* commit change to h/w */ 529 530 /* 531 * Check recent per-antenna transmit statistics and flip 532 * the default antenna if noticeably more frames went out 533 * on the non-default antenna. 534 * XXX assumes 2 anntenae 535 */ 536 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 537 otherant = sc->sc_defant & 1 ? 2 : 1; 538 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 539 ath_setdefantenna(sc, otherant); 540 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 541 } 542 543 /* Program the CABQ with the contents of the CABQ txq and start it */ 544 ATH_TXQ_LOCK(sc->sc_cabq); 545 ath_beacon_cabq_start(sc); 546 ATH_TXQ_UNLOCK(sc->sc_cabq); 547 548 /* Program the new beacon frame if we have one for this interval */ 549 if (bfaddr != 0) { 550 /* 551 * Stop any current dma and put the new frame on the queue. 552 * This should never fail since we check above that no frames 553 * are still pending on the queue. 554 */ 555 if (! sc->sc_isedma) { 556 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 557 DPRINTF(sc, ATH_DEBUG_ANY, 558 "%s: beacon queue %u did not stop?\n", 559 __func__, sc->sc_bhalq); 560 } 561 } 562 /* NB: cabq traffic should already be queued and primed */ 563 564 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 565 ath_hal_txstart(ah, sc->sc_bhalq); 566 567 sc->sc_stats.ast_be_xmit++; 568 } 569 } 570 571 static void 572 ath_beacon_cabq_start_edma(struct ath_softc *sc) 573 { 574 struct ath_buf *bf, *bf_last; 575 struct ath_txq *cabq = sc->sc_cabq; 576 #if 0 577 struct ath_buf *bfi; 578 int i = 0; 579 #endif 580 581 ATH_TXQ_LOCK_ASSERT(cabq); 582 583 if (TAILQ_EMPTY(&cabq->axq_q)) 584 return; 585 bf = TAILQ_FIRST(&cabq->axq_q); 586 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 587 588 /* 589 * This is a dirty, dirty hack to push the contents of 590 * the cabq staging queue into the FIFO. 591 * 592 * This ideally should live in the EDMA code file 593 * and only push things into the CABQ if there's a FIFO 594 * slot. 595 * 596 * We can't treat this like a normal TX queue because 597 * in the case of multi-VAP traffic, we may have to flush 598 * the CABQ each new (staggered) beacon that goes out. 599 * But for non-staggered beacons, we could in theory 600 * handle multicast traffic for all VAPs in one FIFO 601 * push. Just keep all of this in mind if you're wondering 602 * how to correctly/better handle multi-VAP CABQ traffic 603 * with EDMA. 604 */ 605 606 /* 607 * Is the CABQ FIFO free? If not, complain loudly and 608 * don't queue anything. Maybe we'll flush the CABQ 609 * traffic, maybe we won't. But that'll happen next 610 * beacon interval. 611 */ 612 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 613 device_printf(sc->sc_dev, 614 "%s: Q%d: CAB FIFO queue=%d?\n", 615 __func__, 616 cabq->axq_qnum, 617 cabq->axq_fifo_depth); 618 return; 619 } 620 621 /* 622 * Ok, so here's the gymnastics reqiured to make this 623 * all sensible. 624 */ 625 626 /* 627 * Tag the first/last buffer appropriately. 628 */ 629 bf->bf_flags |= ATH_BUF_FIFOPTR; 630 bf_last->bf_flags |= ATH_BUF_FIFOEND; 631 632 #if 0 633 i = 0; 634 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 635 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 636 i++; 637 } 638 #endif 639 640 /* 641 * We now need to push this set of frames onto the tail 642 * of the FIFO queue. We don't adjust the aggregate 643 * count, only the queue depth counter(s). 644 * We also need to blank the link pointer now. 645 */ 646 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 647 cabq->axq_link = NULL; 648 cabq->fifo.axq_depth += cabq->axq_depth; 649 cabq->axq_depth = 0; 650 651 /* Bump FIFO queue */ 652 cabq->axq_fifo_depth++; 653 654 /* Push the first entry into the hardware */ 655 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 656 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 657 658 /* NB: gated by beacon so safe to start here */ 659 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 660 661 } 662 663 static void 664 ath_beacon_cabq_start_legacy(struct ath_softc *sc) 665 { 666 struct ath_buf *bf; 667 struct ath_txq *cabq = sc->sc_cabq; 668 669 ATH_TXQ_LOCK_ASSERT(cabq); 670 if (TAILQ_EMPTY(&cabq->axq_q)) 671 return; 672 bf = TAILQ_FIRST(&cabq->axq_q); 673 674 /* Push the first entry into the hardware */ 675 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 676 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 677 678 /* NB: gated by beacon so safe to start here */ 679 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 680 } 681 682 /* 683 * Start CABQ transmission - this assumes that all frames are prepped 684 * and ready in the CABQ. 685 */ 686 void 687 ath_beacon_cabq_start(struct ath_softc *sc) 688 { 689 struct ath_txq *cabq = sc->sc_cabq; 690 691 ATH_TXQ_LOCK_ASSERT(cabq); 692 693 if (TAILQ_EMPTY(&cabq->axq_q)) 694 return; 695 696 if (sc->sc_isedma) 697 ath_beacon_cabq_start_edma(sc); 698 else 699 ath_beacon_cabq_start_legacy(sc); 700 } 701 702 struct ath_buf * 703 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 704 { 705 struct ath_vap *avp = ATH_VAP(vap); 706 struct ath_txq *cabq = sc->sc_cabq; 707 struct ath_buf *bf; 708 struct mbuf *m; 709 int nmcastq, error; 710 711 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 712 ("not running, state %d", vap->iv_state)); 713 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 714 715 /* 716 * Update dynamic beacon contents. If this returns 717 * non-zero then we need to remap the memory because 718 * the beacon frame changed size (probably because 719 * of the TIM bitmap). 720 */ 721 bf = avp->av_bcbuf; 722 m = bf->bf_m; 723 /* XXX lock mcastq? */ 724 nmcastq = avp->av_mcastq.axq_depth; 725 726 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) { 727 /* XXX too conservative? */ 728 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 729 #if defined(__DragonFly__) 730 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 731 bf->bf_dmamap, m, 732 bf->bf_segs, 1, &bf->bf_nseg, 733 BUS_DMA_NOWAIT); 734 #else 735 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 736 bf->bf_segs, &bf->bf_nseg, 737 BUS_DMA_NOWAIT); 738 #endif 739 if (error != 0) { 740 if_printf(vap->iv_ifp, 741 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 742 __func__, error); 743 return NULL; 744 } 745 } 746 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) { 747 DPRINTF(sc, ATH_DEBUG_BEACON, 748 "%s: cabq did not drain, mcastq %u cabq %u\n", 749 __func__, nmcastq, cabq->axq_depth); 750 sc->sc_stats.ast_cabq_busy++; 751 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 752 /* 753 * CABQ traffic from a previous vap is still pending. 754 * We must drain the q before this beacon frame goes 755 * out as otherwise this vap's stations will get cab 756 * frames from a different vap. 757 * XXX could be slow causing us to miss DBA 758 */ 759 /* 760 * XXX TODO: this doesn't stop CABQ DMA - it assumes 761 * that since we're about to transmit a beacon, we've 762 * already stopped transmitting on the CABQ. But this 763 * doesn't at all mean that the CABQ DMA QCU will 764 * accept a new TXDP! So what, should we do a DMA 765 * stop? What if it fails? 766 * 767 * More thought is required here. 768 */ 769 /* 770 * XXX can we even stop TX DMA here? Check what the 771 * reference driver does for cabq for beacons, given 772 * that stopping TX requires RX is paused. 773 */ 774 ath_tx_draintxq(sc, cabq); 775 } 776 } 777 ath_beacon_setup(sc, bf); 778 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 779 780 /* 781 * Enable the CAB queue before the beacon queue to 782 * insure cab frames are triggered by this beacon. 783 */ 784 if (vap->iv_bcn_off.bo_tim[4] & 1) { 785 786 /* NB: only at DTIM */ 787 ATH_TXQ_LOCK(&avp->av_mcastq); 788 if (nmcastq) { 789 struct ath_buf *bfm, *bfc_last; 790 791 /* 792 * Move frames from the s/w mcast q to the h/w cab q. 793 * 794 * XXX TODO: if we chain together multiple VAPs 795 * worth of CABQ traffic, should we keep the 796 * MORE data bit set on the last frame of each 797 * intermediary VAP (ie, only clear the MORE 798 * bit of the last frame on the last vap?) 799 */ 800 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 801 ATH_TXQ_LOCK(cabq); 802 803 /* 804 * If there's already a frame on the CABQ, we 805 * need to link to the end of the last frame. 806 * We can't use axq_link here because 807 * EDMA descriptors require some recalculation 808 * (checksum) to occur. 809 */ 810 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 811 if (bfc_last != NULL) { 812 ath_hal_settxdesclink(sc->sc_ah, 813 bfc_last->bf_lastds, 814 bfm->bf_daddr); 815 } 816 ath_txqmove(cabq, &avp->av_mcastq); 817 ATH_TXQ_UNLOCK(cabq); 818 /* 819 * XXX not entirely accurate, in case a mcast 820 * queue frame arrived before we grabbed the TX 821 * lock. 822 */ 823 sc->sc_stats.ast_cabq_xmit += nmcastq; 824 } 825 ATH_TXQ_UNLOCK(&avp->av_mcastq); 826 } 827 return bf; 828 } 829 830 void 831 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 832 { 833 struct ath_vap *avp = ATH_VAP(vap); 834 struct ath_hal *ah = sc->sc_ah; 835 struct ath_buf *bf; 836 struct mbuf *m; 837 int error; 838 839 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 840 841 /* 842 * Update dynamic beacon contents. If this returns 843 * non-zero then we need to remap the memory because 844 * the beacon frame changed size (probably because 845 * of the TIM bitmap). 846 */ 847 bf = avp->av_bcbuf; 848 m = bf->bf_m; 849 if (ieee80211_beacon_update(bf->bf_node, m, 0)) { 850 /* XXX too conservative? */ 851 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 852 #if defined(__DragonFly__) 853 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 854 bf->bf_dmamap, m, 855 bf->bf_segs, 1, &bf->bf_nseg, 856 BUS_DMA_NOWAIT); 857 #else 858 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 859 bf->bf_segs, &bf->bf_nseg, 860 BUS_DMA_NOWAIT); 861 #endif 862 if (error != 0) { 863 if_printf(vap->iv_ifp, 864 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 865 __func__, error); 866 return; 867 } 868 } 869 ath_beacon_setup(sc, bf); 870 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 871 872 /* NB: caller is known to have already stopped tx dma */ 873 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 874 ath_hal_txstart(ah, sc->sc_bhalq); 875 } 876 877 /* 878 * Reclaim beacon resources and return buffer to the pool. 879 */ 880 void 881 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 882 { 883 884 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 885 __func__, bf, bf->bf_m, bf->bf_node); 886 if (bf->bf_m != NULL) { 887 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 888 m_freem(bf->bf_m); 889 bf->bf_m = NULL; 890 } 891 if (bf->bf_node != NULL) { 892 ieee80211_free_node(bf->bf_node); 893 bf->bf_node = NULL; 894 } 895 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 896 } 897 898 /* 899 * Reclaim beacon resources. 900 */ 901 void 902 ath_beacon_free(struct ath_softc *sc) 903 { 904 struct ath_buf *bf; 905 906 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 907 DPRINTF(sc, ATH_DEBUG_NODE, 908 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 909 __func__, bf, bf->bf_m, bf->bf_node); 910 if (bf->bf_m != NULL) { 911 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 912 m_freem(bf->bf_m); 913 bf->bf_m = NULL; 914 } 915 if (bf->bf_node != NULL) { 916 ieee80211_free_node(bf->bf_node); 917 bf->bf_node = NULL; 918 } 919 } 920 } 921 922 /* 923 * Configure the beacon and sleep timers. 924 * 925 * When operating as an AP this resets the TSF and sets 926 * up the hardware to notify us when we need to issue beacons. 927 * 928 * When operating in station mode this sets up the beacon 929 * timers according to the timestamp of the last received 930 * beacon and the current TSF, configures PCF and DTIM 931 * handling, programs the sleep registers so the hardware 932 * will wakeup in time to receive beacons, and configures 933 * the beacon miss handling so we'll receive a BMISS 934 * interrupt when we stop seeing beacons from the AP 935 * we've associated with. 936 */ 937 void 938 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 939 { 940 #define TSF_TO_TU(_h,_l) \ 941 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 942 #define FUDGE 2 943 struct ath_hal *ah = sc->sc_ah; 944 struct ieee80211com *ic = &sc->sc_ic; 945 struct ieee80211_node *ni; 946 u_int32_t nexttbtt, intval, tsftu; 947 u_int32_t nexttbtt_u8, intval_u8; 948 u_int64_t tsf, tsf_beacon; 949 950 if (vap == NULL) 951 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 952 /* 953 * Just ensure that we aren't being called when the last 954 * VAP is destroyed. 955 */ 956 if (vap == NULL) { 957 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 958 __func__); 959 return; 960 } 961 962 ni = ieee80211_ref_node(vap->iv_bss); 963 964 ATH_LOCK(sc); 965 ath_power_set_power_state(sc, HAL_PM_AWAKE); 966 ATH_UNLOCK(sc); 967 968 /* extract tstamp from last beacon and convert to TU */ 969 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4), 970 le32dec(ni->ni_tstamp.data)); 971 972 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 973 tsf_beacon |= le32dec(ni->ni_tstamp.data); 974 975 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 976 ic->ic_opmode == IEEE80211_M_MBSS) { 977 /* 978 * For multi-bss ap/mesh support beacons are either staggered 979 * evenly over N slots or burst together. For the former 980 * arrange for the SWBA to be delivered for each slot. 981 * Slots that are not occupied will generate nothing. 982 */ 983 /* NB: the beacon interval is kept internally in TU's */ 984 intval = ni->ni_intval & HAL_BEACON_PERIOD; 985 if (sc->sc_stagbeacons) 986 intval /= ATH_BCBUF; 987 } else { 988 /* NB: the beacon interval is kept internally in TU's */ 989 intval = ni->ni_intval & HAL_BEACON_PERIOD; 990 } 991 if (nexttbtt == 0) /* e.g. for ap mode */ 992 nexttbtt = intval; 993 else if (intval) /* NB: can be 0 for monitor mode */ 994 nexttbtt = roundup(nexttbtt, intval); 995 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 996 __func__, nexttbtt, intval, ni->ni_intval); 997 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 998 HAL_BEACON_STATE bs; 999 int dtimperiod, dtimcount; 1000 int cfpperiod, cfpcount; 1001 1002 /* 1003 * Setup dtim and cfp parameters according to 1004 * last beacon we received (which may be none). 1005 */ 1006 dtimperiod = ni->ni_dtim_period; 1007 if (dtimperiod <= 0) /* NB: 0 if not known */ 1008 dtimperiod = 1; 1009 dtimcount = ni->ni_dtim_count; 1010 if (dtimcount >= dtimperiod) /* NB: sanity check */ 1011 dtimcount = 0; /* XXX? */ 1012 cfpperiod = 1; /* NB: no PCF support yet */ 1013 cfpcount = 0; 1014 /* 1015 * Pull nexttbtt forward to reflect the current 1016 * TSF and calculate dtim+cfp state for the result. 1017 */ 1018 tsf = ath_hal_gettsf64(ah); 1019 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1020 1021 DPRINTF(sc, ATH_DEBUG_BEACON, 1022 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 1023 __func__, 1024 (unsigned long long) tsf_beacon, 1025 (unsigned long long) tsf, 1026 nexttbtt, 1027 tsftu); 1028 DPRINTF(sc, ATH_DEBUG_BEACON, 1029 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 1030 __func__, 1031 (unsigned long long) tsf_beacon, 1032 (unsigned long long) tsf, 1033 (long long) tsf - 1034 (long long) tsf_beacon); 1035 1036 DPRINTF(sc, ATH_DEBUG_BEACON, 1037 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1038 __func__, 1039 (unsigned long long) nexttbtt, 1040 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1041 1042 /* XXX cfpcount? */ 1043 1044 if (nexttbtt > tsftu) { 1045 uint32_t countdiff, oldtbtt, remainder; 1046 1047 oldtbtt = nexttbtt; 1048 remainder = (nexttbtt - tsftu) % intval; 1049 nexttbtt = tsftu + remainder; 1050 1051 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1052 if (dtimcount > countdiff) { 1053 dtimcount -= countdiff; 1054 } else { 1055 dtimcount += dtimperiod - countdiff; 1056 } 1057 } else { //nexttbtt <= tsftu 1058 uint32_t countdiff, oldtbtt, remainder; 1059 1060 oldtbtt = nexttbtt; 1061 remainder = (tsftu - nexttbtt) % intval; 1062 nexttbtt = tsftu - remainder + intval; 1063 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1064 if (dtimcount > countdiff) { 1065 dtimcount -= countdiff; 1066 } else { 1067 dtimcount += dtimperiod - countdiff; 1068 } 1069 } 1070 1071 DPRINTF(sc, ATH_DEBUG_BEACON, 1072 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1073 __func__, 1074 (unsigned long long) nexttbtt, 1075 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1076 1077 memset(&bs, 0, sizeof(bs)); 1078 bs.bs_intval = intval; 1079 bs.bs_nexttbtt = nexttbtt; 1080 bs.bs_dtimperiod = dtimperiod*intval; 1081 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1082 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1083 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1084 bs.bs_cfpmaxduration = 0; 1085 #if 0 1086 /* 1087 * The 802.11 layer records the offset to the DTIM 1088 * bitmap while receiving beacons; use it here to 1089 * enable h/w detection of our AID being marked in 1090 * the bitmap vector (to indicate frames for us are 1091 * pending at the AP). 1092 * XXX do DTIM handling in s/w to WAR old h/w bugs 1093 * XXX enable based on h/w rev for newer chips 1094 */ 1095 bs.bs_timoffset = ni->ni_timoff; 1096 #endif 1097 /* 1098 * Calculate the number of consecutive beacons to miss 1099 * before taking a BMISS interrupt. 1100 * Note that we clamp the result to at most 10 beacons. 1101 */ 1102 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1103 if (bs.bs_bmissthreshold > 10) 1104 bs.bs_bmissthreshold = 10; 1105 else if (bs.bs_bmissthreshold <= 0) 1106 bs.bs_bmissthreshold = 1; 1107 1108 /* 1109 * Calculate sleep duration. The configuration is 1110 * given in ms. We insure a multiple of the beacon 1111 * period is used. Also, if the sleep duration is 1112 * greater than the DTIM period then it makes senses 1113 * to make it a multiple of that. 1114 * 1115 * XXX fixed at 100ms 1116 */ 1117 bs.bs_sleepduration = 1118 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1119 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1120 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1121 1122 DPRINTF(sc, ATH_DEBUG_BEACON, 1123 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1124 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1125 "maxdur %u next %u timoffset %u\n" 1126 , __func__ 1127 , tsf 1128 , tsftu 1129 , bs.bs_intval 1130 , bs.bs_nexttbtt 1131 , bs.bs_dtimperiod 1132 , bs.bs_nextdtim 1133 , bs.bs_bmissthreshold 1134 , bs.bs_sleepduration 1135 , bs.bs_cfpperiod 1136 , bs.bs_cfpmaxduration 1137 , bs.bs_cfpnext 1138 , bs.bs_timoffset 1139 ); 1140 ath_hal_intrset(ah, 0); 1141 ath_hal_beacontimers(ah, &bs); 1142 sc->sc_imask |= HAL_INT_BMISS; 1143 ath_hal_intrset(ah, sc->sc_imask); 1144 } else { 1145 ath_hal_intrset(ah, 0); 1146 if (nexttbtt == intval) 1147 intval |= HAL_BEACON_RESET_TSF; 1148 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1149 /* 1150 * In IBSS mode enable the beacon timers but only 1151 * enable SWBA interrupts if we need to manually 1152 * prepare beacon frames. Otherwise we use a 1153 * self-linked tx descriptor and let the hardware 1154 * deal with things. 1155 */ 1156 intval |= HAL_BEACON_ENA; 1157 if (!sc->sc_hasveol) 1158 sc->sc_imask |= HAL_INT_SWBA; 1159 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1160 /* 1161 * Pull nexttbtt forward to reflect 1162 * the current TSF. 1163 */ 1164 tsf = ath_hal_gettsf64(ah); 1165 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1166 do { 1167 nexttbtt += intval; 1168 } while (nexttbtt < tsftu); 1169 } 1170 ath_beaconq_config(sc); 1171 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1172 ic->ic_opmode == IEEE80211_M_MBSS) { 1173 /* 1174 * In AP/mesh mode we enable the beacon timers 1175 * and SWBA interrupts to prepare beacon frames. 1176 */ 1177 intval |= HAL_BEACON_ENA; 1178 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1179 ath_beaconq_config(sc); 1180 } 1181 1182 /* 1183 * Now dirty things because for now, the EDMA HAL has 1184 * nexttbtt and intval is TU/8. 1185 */ 1186 if (sc->sc_isedma) { 1187 nexttbtt_u8 = (nexttbtt << 3); 1188 intval_u8 = (intval << 3); 1189 if (intval & HAL_BEACON_ENA) 1190 intval_u8 |= HAL_BEACON_ENA; 1191 if (intval & HAL_BEACON_RESET_TSF) 1192 intval_u8 |= HAL_BEACON_RESET_TSF; 1193 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1194 } else 1195 ath_hal_beaconinit(ah, nexttbtt, intval); 1196 sc->sc_bmisscount = 0; 1197 ath_hal_intrset(ah, sc->sc_imask); 1198 /* 1199 * When using a self-linked beacon descriptor in 1200 * ibss mode load it once here. 1201 */ 1202 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1203 ath_beacon_start_adhoc(sc, vap); 1204 } 1205 ieee80211_free_node(ni); 1206 1207 ATH_LOCK(sc); 1208 ath_power_restore_power_state(sc); 1209 ATH_UNLOCK(sc); 1210 #undef FUDGE 1211 #undef TSF_TO_TU 1212 } 1213