1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 32 /* 33 * Driver for the Atheros Wireless LAN controller. 34 * 35 * This software is derived from work of Atsushi Onoe; his contribution 36 * is greatly appreciated. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ath.h" 41 /* 42 * This is needed for register operations which are performed 43 * by the driver - eg, calls to ath_hal_gettsf32(). 44 * 45 * It's also required for any AH_DEBUG checks in here, eg the 46 * module dependencies. 47 */ 48 #include "opt_ah.h" 49 #include "opt_wlan.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysctl.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/sockio.h> 61 #include <sys/errno.h> 62 #include <sys/callout.h> 63 #include <sys/bus.h> 64 #include <sys/endian.h> 65 #include <sys/kthread.h> 66 #include <sys/taskqueue.h> 67 #include <sys/priv.h> 68 #include <sys/module.h> 69 #include <sys/ktr.h> 70 71 #include <net/if.h> 72 #include <net/if_var.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_llc.h> 79 80 #include <netproto/802_11/ieee80211_var.h> 81 #include <netproto/802_11/ieee80211_regdomain.h> 82 #ifdef IEEE80211_SUPPORT_SUPERG 83 #include <netproto/802_11/ieee80211_superg.h> 84 #endif 85 86 #include <net/bpf.h> 87 88 #ifdef INET 89 #include <netinet/in.h> 90 #include <netinet/if_ether.h> 91 #endif 92 93 #include <dev/netif/ath/ath/if_athvar.h> 94 95 #include <dev/netif/ath/ath/if_ath_debug.h> 96 #include <dev/netif/ath/ath/if_ath_misc.h> 97 #include <dev/netif/ath/ath/if_ath_tx.h> 98 #include <dev/netif/ath/ath/if_ath_beacon.h> 99 100 #ifdef ATH_TX99_DIAG 101 #include <dev/netif/ath/ath_tx99/ath_tx99.h> 102 #endif 103 104 /* 105 * Setup a h/w transmit queue for beacons. 106 */ 107 int 108 ath_beaconq_setup(struct ath_softc *sc) 109 { 110 struct ath_hal *ah = sc->sc_ah; 111 HAL_TXQ_INFO qi; 112 113 memset(&qi, 0, sizeof(qi)); 114 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 115 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 116 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 117 /* NB: for dynamic turbo, don't enable any other interrupts */ 118 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 119 if (sc->sc_isedma) 120 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 121 HAL_TXQ_TXERRINT_ENABLE; 122 123 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 124 } 125 126 /* 127 * Setup the transmit queue parameters for the beacon queue. 128 */ 129 int 130 ath_beaconq_config(struct ath_softc *sc) 131 { 132 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 133 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 134 struct ath_hal *ah = sc->sc_ah; 135 HAL_TXQ_INFO qi; 136 137 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 138 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 139 ic->ic_opmode == IEEE80211_M_MBSS) { 140 /* 141 * Always burst out beacon and CAB traffic. 142 */ 143 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 144 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 145 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 146 } else { 147 struct wmeParams *wmep = 148 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 149 /* 150 * Adhoc mode; important thing is to use 2x cwmin. 151 */ 152 qi.tqi_aifs = wmep->wmep_aifsn; 153 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 154 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 155 } 156 157 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 158 device_printf(sc->sc_dev, "unable to update parameters for " 159 "beacon hardware queue!\n"); 160 return 0; 161 } else { 162 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 163 return 1; 164 } 165 #undef ATH_EXPONENT_TO_VALUE 166 } 167 168 /* 169 * Allocate and setup an initial beacon frame. 170 */ 171 int 172 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 173 { 174 struct ieee80211vap *vap = ni->ni_vap; 175 struct ath_vap *avp = ATH_VAP(vap); 176 struct ath_buf *bf; 177 struct mbuf *m; 178 int error; 179 180 bf = avp->av_bcbuf; 181 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 182 __func__, bf->bf_m, bf->bf_node); 183 if (bf->bf_m != NULL) { 184 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 185 m_freem(bf->bf_m); 186 bf->bf_m = NULL; 187 } 188 if (bf->bf_node != NULL) { 189 ieee80211_free_node(bf->bf_node); 190 bf->bf_node = NULL; 191 } 192 193 /* 194 * NB: the beacon data buffer must be 32-bit aligned; 195 * we assume the mbuf routines will return us something 196 * with this alignment (perhaps should assert). 197 */ 198 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 199 if (m == NULL) { 200 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 201 sc->sc_stats.ast_be_nombuf++; 202 return ENOMEM; 203 } 204 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 205 bf->bf_segs, 1, &bf->bf_nseg, 206 BUS_DMA_NOWAIT); 207 if (error != 0) { 208 device_printf(sc->sc_dev, 209 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 210 __func__, error); 211 m_freem(m); 212 return error; 213 } 214 215 /* 216 * Calculate a TSF adjustment factor required for staggered 217 * beacons. Note that we assume the format of the beacon 218 * frame leaves the tstamp field immediately following the 219 * header. 220 */ 221 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 222 uint64_t tsfadjust; 223 struct ieee80211_frame *wh; 224 225 /* 226 * The beacon interval is in TU's; the TSF is in usecs. 227 * We figure out how many TU's to add to align the timestamp 228 * then convert to TSF units and handle byte swapping before 229 * inserting it in the frame. The hardware will then add this 230 * each time a beacon frame is sent. Note that we align vap's 231 * 1..N and leave vap 0 untouched. This means vap 0 has a 232 * timestamp in one beacon interval while the others get a 233 * timstamp aligned to the next interval. 234 */ 235 tsfadjust = ni->ni_intval * 236 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 237 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 238 239 DPRINTF(sc, ATH_DEBUG_BEACON, 240 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 241 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 242 avp->av_bslot, ni->ni_intval, 243 (unsigned long long) le64toh(tsfadjust)); 244 245 wh = mtod(m, struct ieee80211_frame *); 246 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 247 } 248 bf->bf_m = m; 249 bf->bf_node = ieee80211_ref_node(ni); 250 251 return 0; 252 } 253 254 /* 255 * Setup the beacon frame for transmit. 256 */ 257 static void 258 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 259 { 260 #define USE_SHPREAMBLE(_ic) \ 261 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 262 == IEEE80211_F_SHPREAMBLE) 263 struct ieee80211_node *ni = bf->bf_node; 264 struct ieee80211com *ic = ni->ni_ic; 265 struct mbuf *m = bf->bf_m; 266 struct ath_hal *ah = sc->sc_ah; 267 struct ath_desc *ds; 268 int flags, antenna; 269 const HAL_RATE_TABLE *rt; 270 u_int8_t rix, rate; 271 HAL_DMA_ADDR bufAddrList[4]; 272 uint32_t segLenList[4]; 273 HAL_11N_RATE_SERIES rc[4]; 274 275 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 276 __func__, m, m->m_len); 277 278 /* setup descriptors */ 279 ds = bf->bf_desc; 280 bf->bf_last = bf; 281 bf->bf_lastds = ds; 282 283 flags = HAL_TXDESC_NOACK; 284 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 285 /* self-linked descriptor */ 286 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 287 flags |= HAL_TXDESC_VEOL; 288 /* 289 * Let hardware handle antenna switching. 290 */ 291 antenna = sc->sc_txantenna; 292 } else { 293 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 294 /* 295 * Switch antenna every 4 beacons. 296 * XXX assumes two antenna 297 */ 298 if (sc->sc_txantenna != 0) 299 antenna = sc->sc_txantenna; 300 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 301 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 302 else 303 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 304 } 305 306 KASSERT(bf->bf_nseg == 1, 307 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 308 309 /* 310 * Calculate rate code. 311 * XXX everything at min xmit rate 312 */ 313 rix = 0; 314 rt = sc->sc_currates; 315 rate = rt->info[rix].rateCode; 316 if (USE_SHPREAMBLE(ic)) 317 rate |= rt->info[rix].shortPreamble; 318 ath_hal_setuptxdesc(ah, ds 319 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 320 , sizeof(struct ieee80211_frame)/* header length */ 321 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 322 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 323 , rate, 1 /* series 0 rate/tries */ 324 , HAL_TXKEYIX_INVALID /* no encryption */ 325 , antenna /* antenna mode */ 326 , flags /* no ack, veol for beacons */ 327 , 0 /* rts/cts rate */ 328 , 0 /* rts/cts duration */ 329 ); 330 331 /* 332 * The EDMA HAL currently assumes that _all_ rate control 333 * settings are done in ath_hal_set11nratescenario(), rather 334 * than in ath_hal_setuptxdesc(). 335 */ 336 if (sc->sc_isedma) { 337 memset(&rc, 0, sizeof(rc)); 338 339 rc[0].ChSel = sc->sc_txchainmask; 340 rc[0].Tries = 1; 341 rc[0].Rate = rt->info[rix].rateCode; 342 rc[0].RateIndex = rix; 343 rc[0].tx_power_cap = 0x3f; 344 rc[0].PktDuration = 345 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 346 rix, 0); 347 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 348 } 349 350 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 351 segLenList[0] = roundup(m->m_len, 4); 352 segLenList[1] = segLenList[2] = segLenList[3] = 0; 353 bufAddrList[0] = bf->bf_segs[0].ds_addr; 354 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 355 ath_hal_filltxdesc(ah, ds 356 , bufAddrList 357 , segLenList 358 , 0 /* XXX desc id */ 359 , sc->sc_bhalq /* hardware TXQ */ 360 , AH_TRUE /* first segment */ 361 , AH_TRUE /* last segment */ 362 , ds /* first descriptor */ 363 ); 364 #if 0 365 ath_desc_swap(ds); 366 #endif 367 #undef USE_SHPREAMBLE 368 } 369 370 void 371 ath_beacon_update(struct ieee80211vap *vap, int item) 372 { 373 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 374 375 setbit(bo->bo_flags, item); 376 } 377 378 /* 379 * Handle a beacon miss. 380 */ 381 void 382 ath_beacon_miss(struct ath_softc *sc) 383 { 384 HAL_SURVEY_SAMPLE hs; 385 HAL_BOOL ret; 386 uint32_t hangs; 387 388 bzero(&hs, sizeof(hs)); 389 390 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 391 392 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 393 DPRINTF(sc, ATH_DEBUG_BEACON, 394 "%s: hang=0x%08x\n", 395 __func__, 396 hangs); 397 } 398 399 #ifdef ATH_DEBUG_ALQ 400 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 401 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 402 #endif 403 404 DPRINTF(sc, ATH_DEBUG_BEACON, 405 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 406 "extchanbusy=%u, cyclecount=%u\n", 407 __func__, 408 ret, 409 hs.tx_busy, 410 hs.rx_busy, 411 hs.chan_busy, 412 hs.ext_chan_busy, 413 hs.cycle_count); 414 } 415 416 /* 417 * Transmit a beacon frame at SWBA. Dynamic updates to the 418 * frame contents are done as needed and the slot time is 419 * also adjusted based on current state. 420 */ 421 void 422 ath_beacon_proc(void *arg, int pending) 423 { 424 struct ath_softc *sc = arg; 425 struct ath_hal *ah = sc->sc_ah; 426 struct ieee80211vap *vap; 427 struct ath_buf *bf; 428 int slot, otherant; 429 uint32_t bfaddr; 430 431 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 432 __func__, pending); 433 /* 434 * Check if the previous beacon has gone out. If 435 * not don't try to post another, skip this period 436 * and wait for the next. Missed beacons indicate 437 * a problem and should not occur. If we miss too 438 * many consecutive beacons reset the device. 439 */ 440 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 441 sc->sc_bmisscount++; 442 sc->sc_stats.ast_be_missed++; 443 ath_beacon_miss(sc); 444 DPRINTF(sc, ATH_DEBUG_BEACON, 445 "%s: missed %u consecutive beacons\n", 446 __func__, sc->sc_bmisscount); 447 if (sc->sc_bmisscount >= ath_bstuck_threshold) 448 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 449 return; 450 } 451 if (sc->sc_bmisscount != 0) { 452 DPRINTF(sc, ATH_DEBUG_BEACON, 453 "%s: resume beacon xmit after %u misses\n", 454 __func__, sc->sc_bmisscount); 455 sc->sc_bmisscount = 0; 456 #ifdef ATH_DEBUG_ALQ 457 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 458 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 459 #endif 460 } 461 462 if (sc->sc_stagbeacons) { /* staggered beacons */ 463 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 464 uint32_t tsftu; 465 466 tsftu = ath_hal_gettsf32(ah) >> 10; 467 /* XXX lintval */ 468 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 469 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 470 bfaddr = 0; 471 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 472 bf = ath_beacon_generate(sc, vap); 473 if (bf != NULL) 474 bfaddr = bf->bf_daddr; 475 } 476 } else { /* burst'd beacons */ 477 uint32_t *bflink = &bfaddr; 478 479 for (slot = 0; slot < ATH_BCBUF; slot++) { 480 vap = sc->sc_bslot[slot]; 481 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 482 bf = ath_beacon_generate(sc, vap); 483 /* 484 * XXX TODO: this should use settxdesclinkptr() 485 * otherwise it won't work for EDMA chipsets! 486 */ 487 if (bf != NULL) { 488 /* XXX should do this using the ds */ 489 *bflink = bf->bf_daddr; 490 ath_hal_gettxdesclinkptr(sc->sc_ah, 491 bf->bf_desc, &bflink); 492 } 493 } 494 } 495 /* 496 * XXX TODO: this should use settxdesclinkptr() 497 * otherwise it won't work for EDMA chipsets! 498 */ 499 *bflink = 0; /* terminate list */ 500 } 501 502 /* 503 * Handle slot time change when a non-ERP station joins/leaves 504 * an 11g network. The 802.11 layer notifies us via callback, 505 * we mark updateslot, then wait one beacon before effecting 506 * the change. This gives associated stations at least one 507 * beacon interval to note the state change. 508 */ 509 /* XXX locking */ 510 if (sc->sc_updateslot == UPDATE) { 511 sc->sc_updateslot = COMMIT; /* commit next beacon */ 512 sc->sc_slotupdate = slot; 513 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 514 ath_setslottime(sc); /* commit change to h/w */ 515 516 /* 517 * Check recent per-antenna transmit statistics and flip 518 * the default antenna if noticeably more frames went out 519 * on the non-default antenna. 520 * XXX assumes 2 anntenae 521 */ 522 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 523 otherant = sc->sc_defant & 1 ? 2 : 1; 524 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 525 ath_setdefantenna(sc, otherant); 526 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 527 } 528 529 /* Program the CABQ with the contents of the CABQ txq and start it */ 530 ATH_TXQ_LOCK(sc->sc_cabq); 531 ath_beacon_cabq_start(sc); 532 ATH_TXQ_UNLOCK(sc->sc_cabq); 533 534 /* Program the new beacon frame if we have one for this interval */ 535 if (bfaddr != 0) { 536 /* 537 * Stop any current dma and put the new frame on the queue. 538 * This should never fail since we check above that no frames 539 * are still pending on the queue. 540 */ 541 if (! sc->sc_isedma) { 542 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 543 DPRINTF(sc, ATH_DEBUG_ANY, 544 "%s: beacon queue %u did not stop?\n", 545 __func__, sc->sc_bhalq); 546 } 547 } 548 /* NB: cabq traffic should already be queued and primed */ 549 550 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 551 ath_hal_txstart(ah, sc->sc_bhalq); 552 553 sc->sc_stats.ast_be_xmit++; 554 } 555 } 556 557 static void 558 ath_beacon_cabq_start_edma(struct ath_softc *sc) 559 { 560 struct ath_buf *bf, *bf_last; 561 struct ath_txq *cabq = sc->sc_cabq; 562 #if 0 563 struct ath_buf *bfi; 564 int i = 0; 565 #endif 566 567 ATH_TXQ_LOCK_ASSERT(cabq); 568 569 if (TAILQ_EMPTY(&cabq->axq_q)) 570 return; 571 bf = TAILQ_FIRST(&cabq->axq_q); 572 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 573 574 /* 575 * This is a dirty, dirty hack to push the contents of 576 * the cabq staging queue into the FIFO. 577 * 578 * This ideally should live in the EDMA code file 579 * and only push things into the CABQ if there's a FIFO 580 * slot. 581 * 582 * We can't treat this like a normal TX queue because 583 * in the case of multi-VAP traffic, we may have to flush 584 * the CABQ each new (staggered) beacon that goes out. 585 * But for non-staggered beacons, we could in theory 586 * handle multicast traffic for all VAPs in one FIFO 587 * push. Just keep all of this in mind if you're wondering 588 * how to correctly/better handle multi-VAP CABQ traffic 589 * with EDMA. 590 */ 591 592 /* 593 * Is the CABQ FIFO free? If not, complain loudly and 594 * don't queue anything. Maybe we'll flush the CABQ 595 * traffic, maybe we won't. But that'll happen next 596 * beacon interval. 597 */ 598 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 599 device_printf(sc->sc_dev, 600 "%s: Q%d: CAB FIFO queue=%d?\n", 601 __func__, 602 cabq->axq_qnum, 603 cabq->axq_fifo_depth); 604 return; 605 } 606 607 /* 608 * Ok, so here's the gymnastics reqiured to make this 609 * all sensible. 610 */ 611 612 /* 613 * Tag the first/last buffer appropriately. 614 */ 615 bf->bf_flags |= ATH_BUF_FIFOPTR; 616 bf_last->bf_flags |= ATH_BUF_FIFOEND; 617 618 #if 0 619 i = 0; 620 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 621 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 622 i++; 623 } 624 #endif 625 626 /* 627 * We now need to push this set of frames onto the tail 628 * of the FIFO queue. We don't adjust the aggregate 629 * count, only the queue depth counter(s). 630 * We also need to blank the link pointer now. 631 */ 632 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 633 cabq->axq_link = NULL; 634 cabq->fifo.axq_depth += cabq->axq_depth; 635 cabq->axq_depth = 0; 636 637 /* Bump FIFO queue */ 638 cabq->axq_fifo_depth++; 639 640 /* Push the first entry into the hardware */ 641 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 642 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 643 644 /* NB: gated by beacon so safe to start here */ 645 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 646 647 } 648 649 static void 650 ath_beacon_cabq_start_legacy(struct ath_softc *sc) 651 { 652 struct ath_buf *bf; 653 struct ath_txq *cabq = sc->sc_cabq; 654 655 ATH_TXQ_LOCK_ASSERT(cabq); 656 if (TAILQ_EMPTY(&cabq->axq_q)) 657 return; 658 bf = TAILQ_FIRST(&cabq->axq_q); 659 660 /* Push the first entry into the hardware */ 661 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 662 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 663 664 /* NB: gated by beacon so safe to start here */ 665 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 666 } 667 668 /* 669 * Start CABQ transmission - this assumes that all frames are prepped 670 * and ready in the CABQ. 671 */ 672 void 673 ath_beacon_cabq_start(struct ath_softc *sc) 674 { 675 struct ath_txq *cabq = sc->sc_cabq; 676 677 ATH_TXQ_LOCK_ASSERT(cabq); 678 679 if (TAILQ_EMPTY(&cabq->axq_q)) 680 return; 681 682 if (sc->sc_isedma) 683 ath_beacon_cabq_start_edma(sc); 684 else 685 ath_beacon_cabq_start_legacy(sc); 686 } 687 688 struct ath_buf * 689 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 690 { 691 struct ath_vap *avp = ATH_VAP(vap); 692 struct ath_txq *cabq = sc->sc_cabq; 693 struct ath_buf *bf; 694 struct mbuf *m; 695 int nmcastq, error; 696 697 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 698 ("not running, state %d", vap->iv_state)); 699 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 700 701 /* 702 * Update dynamic beacon contents. If this returns 703 * non-zero then we need to remap the memory because 704 * the beacon frame changed size (probably because 705 * of the TIM bitmap). 706 */ 707 bf = avp->av_bcbuf; 708 m = bf->bf_m; 709 /* XXX lock mcastq? */ 710 nmcastq = avp->av_mcastq.axq_depth; 711 712 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 713 /* XXX too conservative? */ 714 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 715 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 716 bf->bf_dmamap, m, 717 bf->bf_segs, 1, &bf->bf_nseg, 718 BUS_DMA_NOWAIT); 719 if (error != 0) { 720 if_printf(vap->iv_ifp, 721 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 722 __func__, error); 723 return NULL; 724 } 725 } 726 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 727 DPRINTF(sc, ATH_DEBUG_BEACON, 728 "%s: cabq did not drain, mcastq %u cabq %u\n", 729 __func__, nmcastq, cabq->axq_depth); 730 sc->sc_stats.ast_cabq_busy++; 731 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 732 /* 733 * CABQ traffic from a previous vap is still pending. 734 * We must drain the q before this beacon frame goes 735 * out as otherwise this vap's stations will get cab 736 * frames from a different vap. 737 * XXX could be slow causing us to miss DBA 738 */ 739 /* 740 * XXX TODO: this doesn't stop CABQ DMA - it assumes 741 * that since we're about to transmit a beacon, we've 742 * already stopped transmitting on the CABQ. But this 743 * doesn't at all mean that the CABQ DMA QCU will 744 * accept a new TXDP! So what, should we do a DMA 745 * stop? What if it fails? 746 * 747 * More thought is required here. 748 */ 749 ath_tx_draintxq(sc, cabq); 750 } 751 } 752 ath_beacon_setup(sc, bf); 753 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 754 755 /* 756 * Enable the CAB queue before the beacon queue to 757 * insure cab frames are triggered by this beacon. 758 */ 759 if (avp->av_boff.bo_tim[4] & 1) { 760 761 /* NB: only at DTIM */ 762 ATH_TXQ_LOCK(&avp->av_mcastq); 763 if (nmcastq) { 764 struct ath_buf *bfm, *bfc_last; 765 766 /* 767 * Move frames from the s/w mcast q to the h/w cab q. 768 * 769 * XXX TODO: if we chain together multiple VAPs 770 * worth of CABQ traffic, should we keep the 771 * MORE data bit set on the last frame of each 772 * intermediary VAP (ie, only clear the MORE 773 * bit of the last frame on the last vap?) 774 */ 775 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 776 ATH_TXQ_LOCK(cabq); 777 778 /* 779 * If there's already a frame on the CABQ, we 780 * need to link to the end of the last frame. 781 * We can't use axq_link here because 782 * EDMA descriptors require some recalculation 783 * (checksum) to occur. 784 */ 785 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 786 if (bfc_last != NULL) { 787 ath_hal_settxdesclink(sc->sc_ah, 788 bfc_last->bf_lastds, 789 bfm->bf_daddr); 790 } 791 ath_txqmove(cabq, &avp->av_mcastq); 792 ATH_TXQ_UNLOCK(cabq); 793 /* 794 * XXX not entirely accurate, in case a mcast 795 * queue frame arrived before we grabbed the TX 796 * lock. 797 */ 798 sc->sc_stats.ast_cabq_xmit += nmcastq; 799 } 800 ATH_TXQ_UNLOCK(&avp->av_mcastq); 801 } 802 return bf; 803 } 804 805 void 806 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 807 { 808 struct ath_vap *avp = ATH_VAP(vap); 809 struct ath_hal *ah = sc->sc_ah; 810 struct ath_buf *bf; 811 struct mbuf *m; 812 int error; 813 814 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 815 816 /* 817 * Update dynamic beacon contents. If this returns 818 * non-zero then we need to remap the memory because 819 * the beacon frame changed size (probably because 820 * of the TIM bitmap). 821 */ 822 bf = avp->av_bcbuf; 823 m = bf->bf_m; 824 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 825 /* XXX too conservative? */ 826 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 827 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 828 bf->bf_dmamap, m, 829 bf->bf_segs, 1, &bf->bf_nseg, 830 BUS_DMA_NOWAIT); 831 if (error != 0) { 832 if_printf(vap->iv_ifp, 833 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 834 __func__, error); 835 return; 836 } 837 } 838 ath_beacon_setup(sc, bf); 839 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 840 841 /* NB: caller is known to have already stopped tx dma */ 842 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 843 ath_hal_txstart(ah, sc->sc_bhalq); 844 } 845 846 /* 847 * Reclaim beacon resources and return buffer to the pool. 848 */ 849 void 850 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 851 { 852 853 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 854 __func__, bf, bf->bf_m, bf->bf_node); 855 if (bf->bf_m != NULL) { 856 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 857 m_freem(bf->bf_m); 858 bf->bf_m = NULL; 859 } 860 if (bf->bf_node != NULL) { 861 ieee80211_free_node(bf->bf_node); 862 bf->bf_node = NULL; 863 } 864 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 865 } 866 867 /* 868 * Reclaim beacon resources. 869 */ 870 void 871 ath_beacon_free(struct ath_softc *sc) 872 { 873 struct ath_buf *bf; 874 875 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 876 DPRINTF(sc, ATH_DEBUG_NODE, 877 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 878 __func__, bf, bf->bf_m, bf->bf_node); 879 if (bf->bf_m != NULL) { 880 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 881 m_freem(bf->bf_m); 882 bf->bf_m = NULL; 883 } 884 if (bf->bf_node != NULL) { 885 ieee80211_free_node(bf->bf_node); 886 bf->bf_node = NULL; 887 } 888 } 889 } 890 891 /* 892 * Configure the beacon and sleep timers. 893 * 894 * When operating as an AP this resets the TSF and sets 895 * up the hardware to notify us when we need to issue beacons. 896 * 897 * When operating in station mode this sets up the beacon 898 * timers according to the timestamp of the last received 899 * beacon and the current TSF, configures PCF and DTIM 900 * handling, programs the sleep registers so the hardware 901 * will wakeup in time to receive beacons, and configures 902 * the beacon miss handling so we'll receive a BMISS 903 * interrupt when we stop seeing beacons from the AP 904 * we've associated with. 905 */ 906 void 907 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 908 { 909 #define TSF_TO_TU(_h,_l) \ 910 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 911 #define FUDGE 2 912 struct ath_hal *ah = sc->sc_ah; 913 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 914 struct ieee80211_node *ni; 915 u_int32_t nexttbtt, intval, tsftu; 916 u_int32_t nexttbtt_u8, intval_u8; 917 u_int64_t tsf, tsf_beacon; 918 919 if (vap == NULL) 920 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 921 /* 922 * Just ensure that we aren't being called when the last 923 * VAP is destroyed. 924 */ 925 if (vap == NULL) { 926 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 927 __func__); 928 return; 929 } 930 931 ni = ieee80211_ref_node(vap->iv_bss); 932 933 ath_power_set_power_state(sc, HAL_PM_AWAKE); 934 935 /* extract tstamp from last beacon and convert to TU */ 936 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 937 LE_READ_4(ni->ni_tstamp.data)); 938 939 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 940 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 941 942 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 943 ic->ic_opmode == IEEE80211_M_MBSS) { 944 /* 945 * For multi-bss ap/mesh support beacons are either staggered 946 * evenly over N slots or burst together. For the former 947 * arrange for the SWBA to be delivered for each slot. 948 * Slots that are not occupied will generate nothing. 949 */ 950 /* NB: the beacon interval is kept internally in TU's */ 951 intval = ni->ni_intval & HAL_BEACON_PERIOD; 952 if (sc->sc_stagbeacons) 953 intval /= ATH_BCBUF; 954 } else { 955 /* NB: the beacon interval is kept internally in TU's */ 956 intval = ni->ni_intval & HAL_BEACON_PERIOD; 957 } 958 if (nexttbtt == 0) /* e.g. for ap mode */ 959 nexttbtt = intval; 960 else if (intval) /* NB: can be 0 for monitor mode */ 961 nexttbtt = roundup(nexttbtt, intval); 962 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 963 __func__, nexttbtt, intval, ni->ni_intval); 964 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 965 HAL_BEACON_STATE bs; 966 int dtimperiod, dtimcount; 967 int cfpperiod, cfpcount; 968 969 /* 970 * Setup dtim and cfp parameters according to 971 * last beacon we received (which may be none). 972 */ 973 dtimperiod = ni->ni_dtim_period; 974 if (dtimperiod <= 0) /* NB: 0 if not known */ 975 dtimperiod = 1; 976 dtimcount = ni->ni_dtim_count; 977 if (dtimcount >= dtimperiod) /* NB: sanity check */ 978 dtimcount = 0; /* XXX? */ 979 cfpperiod = 1; /* NB: no PCF support yet */ 980 cfpcount = 0; 981 /* 982 * Pull nexttbtt forward to reflect the current 983 * TSF and calculate dtim+cfp state for the result. 984 */ 985 tsf = ath_hal_gettsf64(ah); 986 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 987 988 DPRINTF(sc, ATH_DEBUG_BEACON, 989 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 990 __func__, 991 (unsigned long long) tsf_beacon, 992 (unsigned long long) tsf, 993 nexttbtt, 994 tsftu); 995 DPRINTF(sc, ATH_DEBUG_BEACON, 996 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 997 __func__, 998 (unsigned long long) tsf_beacon, 999 (unsigned long long) tsf, 1000 (long long) tsf - 1001 (long long) tsf_beacon); 1002 1003 DPRINTF(sc, ATH_DEBUG_BEACON, 1004 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1005 __func__, 1006 (unsigned long long) nexttbtt, 1007 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1008 1009 /* XXX cfpcount? */ 1010 1011 if (nexttbtt > tsftu) { 1012 uint32_t countdiff, oldtbtt, remainder; 1013 1014 oldtbtt = nexttbtt; 1015 remainder = (nexttbtt - tsftu) % intval; 1016 nexttbtt = tsftu + remainder; 1017 1018 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1019 if (dtimcount > countdiff) { 1020 dtimcount -= countdiff; 1021 } else { 1022 dtimcount += dtimperiod - countdiff; 1023 } 1024 } else { //nexttbtt <= tsftu 1025 uint32_t countdiff, oldtbtt, remainder; 1026 1027 oldtbtt = nexttbtt; 1028 remainder = (tsftu - nexttbtt) % intval; 1029 nexttbtt = tsftu - remainder + intval; 1030 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1031 if (dtimcount > countdiff) { 1032 dtimcount -= countdiff; 1033 } else { 1034 dtimcount += dtimperiod - countdiff; 1035 } 1036 } 1037 1038 DPRINTF(sc, ATH_DEBUG_BEACON, 1039 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1040 __func__, 1041 (unsigned long long) nexttbtt, 1042 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1043 1044 memset(&bs, 0, sizeof(bs)); 1045 bs.bs_intval = intval; 1046 bs.bs_nexttbtt = nexttbtt; 1047 bs.bs_dtimperiod = dtimperiod*intval; 1048 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1049 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1050 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1051 bs.bs_cfpmaxduration = 0; 1052 #if 0 1053 /* 1054 * The 802.11 layer records the offset to the DTIM 1055 * bitmap while receiving beacons; use it here to 1056 * enable h/w detection of our AID being marked in 1057 * the bitmap vector (to indicate frames for us are 1058 * pending at the AP). 1059 * XXX do DTIM handling in s/w to WAR old h/w bugs 1060 * XXX enable based on h/w rev for newer chips 1061 */ 1062 bs.bs_timoffset = ni->ni_timoff; 1063 #endif 1064 /* 1065 * Calculate the number of consecutive beacons to miss 1066 * before taking a BMISS interrupt. 1067 * Note that we clamp the result to at most 10 beacons. 1068 */ 1069 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1070 if (bs.bs_bmissthreshold > 10) 1071 bs.bs_bmissthreshold = 10; 1072 else if (bs.bs_bmissthreshold <= 0) 1073 bs.bs_bmissthreshold = 1; 1074 1075 /* 1076 * Calculate sleep duration. The configuration is 1077 * given in ms. We insure a multiple of the beacon 1078 * period is used. Also, if the sleep duration is 1079 * greater than the DTIM period then it makes senses 1080 * to make it a multiple of that. 1081 * 1082 * XXX fixed at 100ms 1083 */ 1084 bs.bs_sleepduration = 1085 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1086 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1087 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1088 1089 DPRINTF(sc, ATH_DEBUG_BEACON, 1090 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1091 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1092 "maxdur %u next %u timoffset %u\n" 1093 , __func__ 1094 , tsf 1095 , tsftu 1096 , bs.bs_intval 1097 , bs.bs_nexttbtt 1098 , bs.bs_dtimperiod 1099 , bs.bs_nextdtim 1100 , bs.bs_bmissthreshold 1101 , bs.bs_sleepduration 1102 , bs.bs_cfpperiod 1103 , bs.bs_cfpmaxduration 1104 , bs.bs_cfpnext 1105 , bs.bs_timoffset 1106 ); 1107 ath_hal_intrset(ah, 0); 1108 ath_hal_beacontimers(ah, &bs); 1109 sc->sc_imask |= HAL_INT_BMISS; 1110 ath_hal_intrset(ah, sc->sc_imask); 1111 } else { 1112 ath_hal_intrset(ah, 0); 1113 if (nexttbtt == intval) 1114 intval |= HAL_BEACON_RESET_TSF; 1115 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1116 /* 1117 * In IBSS mode enable the beacon timers but only 1118 * enable SWBA interrupts if we need to manually 1119 * prepare beacon frames. Otherwise we use a 1120 * self-linked tx descriptor and let the hardware 1121 * deal with things. 1122 */ 1123 intval |= HAL_BEACON_ENA; 1124 if (!sc->sc_hasveol) 1125 sc->sc_imask |= HAL_INT_SWBA; 1126 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1127 /* 1128 * Pull nexttbtt forward to reflect 1129 * the current TSF. 1130 */ 1131 tsf = ath_hal_gettsf64(ah); 1132 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1133 do { 1134 nexttbtt += intval; 1135 } while (nexttbtt < tsftu); 1136 } 1137 ath_beaconq_config(sc); 1138 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1139 ic->ic_opmode == IEEE80211_M_MBSS) { 1140 /* 1141 * In AP/mesh mode we enable the beacon timers 1142 * and SWBA interrupts to prepare beacon frames. 1143 */ 1144 intval |= HAL_BEACON_ENA; 1145 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1146 ath_beaconq_config(sc); 1147 } 1148 1149 /* 1150 * Now dirty things because for now, the EDMA HAL has 1151 * nexttbtt and intval is TU/8. 1152 */ 1153 if (sc->sc_isedma) { 1154 nexttbtt_u8 = (nexttbtt << 3); 1155 intval_u8 = (intval << 3); 1156 if (intval & HAL_BEACON_ENA) 1157 intval_u8 |= HAL_BEACON_ENA; 1158 if (intval & HAL_BEACON_RESET_TSF) 1159 intval_u8 |= HAL_BEACON_RESET_TSF; 1160 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1161 } else 1162 ath_hal_beaconinit(ah, nexttbtt, intval); 1163 sc->sc_bmisscount = 0; 1164 ath_hal_intrset(ah, sc->sc_imask); 1165 /* 1166 * When using a self-linked beacon descriptor in 1167 * ibss mode load it once here. 1168 */ 1169 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1170 ath_beacon_start_adhoc(sc, vap); 1171 } 1172 ieee80211_free_node(ni); 1173 1174 ath_power_restore_power_state(sc); 1175 #undef FUDGE 1176 #undef TSF_TO_TU 1177 } 1178