1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 72 73 #include <net/if.h> 74 #include <net/if_var.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_arp.h> 79 #include <net/ethernet.h> 80 #include <net/if_llc.h> 81 82 #include <netproto/802_11/ieee80211_var.h> 83 #include <netproto/802_11/ieee80211_regdomain.h> 84 #ifdef IEEE80211_SUPPORT_SUPERG 85 #include <netproto/802_11/ieee80211_superg.h> 86 #endif 87 88 #include <net/bpf.h> 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #include <netinet/if_ether.h> 93 #endif 94 95 #include <dev/netif/ath/ath/if_athvar.h> 96 97 #include <dev/netif/ath/ath/if_ath_debug.h> 98 #include <dev/netif/ath/ath/if_ath_misc.h> 99 #include <dev/netif/ath/ath/if_ath_tx.h> 100 #include <dev/netif/ath/ath/if_ath_beacon.h> 101 102 #ifdef ATH_TX99_DIAG 103 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h> 104 #endif 105 106 /* 107 * Setup a h/w transmit queue for beacons. 108 */ 109 int 110 ath_beaconq_setup(struct ath_softc *sc) 111 { 112 struct ath_hal *ah = sc->sc_ah; 113 HAL_TXQ_INFO qi; 114 115 memset(&qi, 0, sizeof(qi)); 116 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 117 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 118 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 119 /* NB: for dynamic turbo, don't enable any other interrupts */ 120 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE; 121 if (sc->sc_isedma) 122 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE | 123 HAL_TXQ_TXERRINT_ENABLE; 124 125 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 126 } 127 128 /* 129 * Setup the transmit queue parameters for the beacon queue. 130 */ 131 int 132 ath_beaconq_config(struct ath_softc *sc) 133 { 134 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 135 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 136 struct ath_hal *ah = sc->sc_ah; 137 HAL_TXQ_INFO qi; 138 139 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 140 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 141 ic->ic_opmode == IEEE80211_M_MBSS) { 142 /* 143 * Always burst out beacon and CAB traffic. 144 */ 145 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 146 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 147 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 148 } else { 149 struct wmeParams *wmep = 150 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 151 /* 152 * Adhoc mode; important thing is to use 2x cwmin. 153 */ 154 qi.tqi_aifs = wmep->wmep_aifsn; 155 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 156 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 157 } 158 159 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 160 device_printf(sc->sc_dev, "unable to update parameters for " 161 "beacon hardware queue!\n"); 162 return 0; 163 } else { 164 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 165 return 1; 166 } 167 #undef ATH_EXPONENT_TO_VALUE 168 } 169 170 /* 171 * Allocate and setup an initial beacon frame. 172 */ 173 int 174 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 175 { 176 struct ieee80211vap *vap = ni->ni_vap; 177 struct ath_vap *avp = ATH_VAP(vap); 178 struct ath_buf *bf; 179 struct mbuf *m; 180 int error; 181 182 bf = avp->av_bcbuf; 183 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n", 184 __func__, bf->bf_m, bf->bf_node); 185 if (bf->bf_m != NULL) { 186 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 187 m_freem(bf->bf_m); 188 bf->bf_m = NULL; 189 } 190 if (bf->bf_node != NULL) { 191 ieee80211_free_node(bf->bf_node); 192 bf->bf_node = NULL; 193 } 194 195 /* 196 * NB: the beacon data buffer must be 32-bit aligned; 197 * we assume the mbuf routines will return us something 198 * with this alignment (perhaps should assert). 199 */ 200 m = ieee80211_beacon_alloc(ni, &avp->av_boff); 201 if (m == NULL) { 202 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__); 203 sc->sc_stats.ast_be_nombuf++; 204 return ENOMEM; 205 } 206 #if defined(__DragonFly__) 207 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m, 208 bf->bf_segs, 1, &bf->bf_nseg, 209 BUS_DMA_NOWAIT); 210 #else 211 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 212 bf->bf_segs, &bf->bf_nseg, 213 BUS_DMA_NOWAIT); 214 #endif 215 if (error != 0) { 216 device_printf(sc->sc_dev, 217 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n", 218 __func__, error); 219 m_freem(m); 220 return error; 221 } 222 223 /* 224 * Calculate a TSF adjustment factor required for staggered 225 * beacons. Note that we assume the format of the beacon 226 * frame leaves the tstamp field immediately following the 227 * header. 228 */ 229 if (sc->sc_stagbeacons && avp->av_bslot > 0) { 230 uint64_t tsfadjust; 231 struct ieee80211_frame *wh; 232 233 /* 234 * The beacon interval is in TU's; the TSF is in usecs. 235 * We figure out how many TU's to add to align the timestamp 236 * then convert to TSF units and handle byte swapping before 237 * inserting it in the frame. The hardware will then add this 238 * each time a beacon frame is sent. Note that we align vap's 239 * 1..N and leave vap 0 untouched. This means vap 0 has a 240 * timestamp in one beacon interval while the others get a 241 * timstamp aligned to the next interval. 242 */ 243 tsfadjust = ni->ni_intval * 244 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF; 245 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */ 246 247 DPRINTF(sc, ATH_DEBUG_BEACON, 248 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n", 249 __func__, sc->sc_stagbeacons ? "stagger" : "burst", 250 avp->av_bslot, ni->ni_intval, 251 (long long unsigned) le64toh(tsfadjust)); 252 253 wh = mtod(m, struct ieee80211_frame *); 254 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust)); 255 } 256 bf->bf_m = m; 257 bf->bf_node = ieee80211_ref_node(ni); 258 259 return 0; 260 } 261 262 /* 263 * Setup the beacon frame for transmit. 264 */ 265 static void 266 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 267 { 268 #define USE_SHPREAMBLE(_ic) \ 269 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 270 == IEEE80211_F_SHPREAMBLE) 271 struct ieee80211_node *ni = bf->bf_node; 272 struct ieee80211com *ic = ni->ni_ic; 273 struct mbuf *m = bf->bf_m; 274 struct ath_hal *ah = sc->sc_ah; 275 struct ath_desc *ds; 276 int flags, antenna; 277 const HAL_RATE_TABLE *rt; 278 u_int8_t rix, rate; 279 HAL_DMA_ADDR bufAddrList[4]; 280 uint32_t segLenList[4]; 281 HAL_11N_RATE_SERIES rc[4]; 282 283 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n", 284 __func__, m, m->m_len); 285 286 /* setup descriptors */ 287 ds = bf->bf_desc; 288 bf->bf_last = bf; 289 bf->bf_lastds = ds; 290 291 flags = HAL_TXDESC_NOACK; 292 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 293 /* self-linked descriptor */ 294 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr); 295 flags |= HAL_TXDESC_VEOL; 296 /* 297 * Let hardware handle antenna switching. 298 */ 299 antenna = sc->sc_txantenna; 300 } else { 301 ath_hal_settxdesclink(sc->sc_ah, ds, 0); 302 /* 303 * Switch antenna every 4 beacons. 304 * XXX assumes two antenna 305 */ 306 if (sc->sc_txantenna != 0) 307 antenna = sc->sc_txantenna; 308 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0) 309 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1); 310 else 311 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 312 } 313 314 KASSERT(bf->bf_nseg == 1, 315 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 316 317 /* 318 * Calculate rate code. 319 * XXX everything at min xmit rate 320 */ 321 rix = 0; 322 rt = sc->sc_currates; 323 rate = rt->info[rix].rateCode; 324 if (USE_SHPREAMBLE(ic)) 325 rate |= rt->info[rix].shortPreamble; 326 ath_hal_setuptxdesc(ah, ds 327 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 328 , sizeof(struct ieee80211_frame)/* header length */ 329 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 330 , ieee80211_get_node_txpower(ni) /* txpower XXX */ 331 , rate, 1 /* series 0 rate/tries */ 332 , HAL_TXKEYIX_INVALID /* no encryption */ 333 , antenna /* antenna mode */ 334 , flags /* no ack, veol for beacons */ 335 , 0 /* rts/cts rate */ 336 , 0 /* rts/cts duration */ 337 ); 338 339 /* 340 * The EDMA HAL currently assumes that _all_ rate control 341 * settings are done in ath_hal_set11nratescenario(), rather 342 * than in ath_hal_setuptxdesc(). 343 */ 344 if (sc->sc_isedma) { 345 memset(&rc, 0, sizeof(rc)); 346 347 rc[0].ChSel = sc->sc_txchainmask; 348 rc[0].Tries = 1; 349 rc[0].Rate = rt->info[rix].rateCode; 350 rc[0].RateIndex = rix; 351 rc[0].tx_power_cap = 0x3f; 352 rc[0].PktDuration = 353 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4), 354 rix, 0); 355 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags); 356 } 357 358 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 359 segLenList[0] = roundup(m->m_len, 4); 360 segLenList[1] = segLenList[2] = segLenList[3] = 0; 361 bufAddrList[0] = bf->bf_segs[0].ds_addr; 362 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 363 ath_hal_filltxdesc(ah, ds 364 , bufAddrList 365 , segLenList 366 , 0 /* XXX desc id */ 367 , sc->sc_bhalq /* hardware TXQ */ 368 , AH_TRUE /* first segment */ 369 , AH_TRUE /* last segment */ 370 , ds /* first descriptor */ 371 ); 372 #if 0 373 ath_desc_swap(ds); 374 #endif 375 #undef USE_SHPREAMBLE 376 } 377 378 void 379 ath_beacon_update(struct ieee80211vap *vap, int item) 380 { 381 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff; 382 383 setbit(bo->bo_flags, item); 384 } 385 386 /* 387 * Handle a beacon miss. 388 */ 389 void 390 ath_beacon_miss(struct ath_softc *sc) 391 { 392 HAL_SURVEY_SAMPLE hs; 393 HAL_BOOL ret; 394 uint32_t hangs; 395 396 bzero(&hs, sizeof(hs)); 397 398 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs); 399 400 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) { 401 DPRINTF(sc, ATH_DEBUG_BEACON, 402 "%s: hang=0x%08x\n", 403 __func__, 404 hangs); 405 } 406 407 #ifdef ATH_DEBUG_ALQ 408 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON)) 409 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL); 410 #endif 411 412 DPRINTF(sc, ATH_DEBUG_BEACON, 413 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, " 414 "extchanbusy=%u, cyclecount=%u\n", 415 __func__, 416 ret, 417 hs.tx_busy, 418 hs.rx_busy, 419 hs.chan_busy, 420 hs.ext_chan_busy, 421 hs.cycle_count); 422 } 423 424 /* 425 * Transmit a beacon frame at SWBA. Dynamic updates to the 426 * frame contents are done as needed and the slot time is 427 * also adjusted based on current state. 428 */ 429 void 430 ath_beacon_proc(void *arg, int pending) 431 { 432 struct ath_softc *sc = arg; 433 struct ath_hal *ah = sc->sc_ah; 434 struct ieee80211vap *vap; 435 struct ath_buf *bf; 436 int slot, otherant; 437 uint32_t bfaddr; 438 439 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 440 __func__, pending); 441 /* 442 * Check if the previous beacon has gone out. If 443 * not don't try to post another, skip this period 444 * and wait for the next. Missed beacons indicate 445 * a problem and should not occur. If we miss too 446 * many consecutive beacons reset the device. 447 */ 448 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 449 sc->sc_bmisscount++; 450 sc->sc_stats.ast_be_missed++; 451 ath_beacon_miss(sc); 452 DPRINTF(sc, ATH_DEBUG_BEACON, 453 "%s: missed %u consecutive beacons\n", 454 __func__, sc->sc_bmisscount); 455 if (sc->sc_bmisscount >= ath_bstuck_threshold) 456 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 457 return; 458 } 459 if (sc->sc_bmisscount != 0) { 460 DPRINTF(sc, ATH_DEBUG_BEACON, 461 "%s: resume beacon xmit after %u misses\n", 462 __func__, sc->sc_bmisscount); 463 sc->sc_bmisscount = 0; 464 #ifdef ATH_DEBUG_ALQ 465 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON)) 466 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL); 467 #endif 468 } 469 470 if (sc->sc_stagbeacons) { /* staggered beacons */ 471 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 472 uint32_t tsftu; 473 474 tsftu = ath_hal_gettsf32(ah) >> 10; 475 /* XXX lintval */ 476 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval; 477 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF]; 478 bfaddr = 0; 479 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 480 bf = ath_beacon_generate(sc, vap); 481 if (bf != NULL) 482 bfaddr = bf->bf_daddr; 483 } 484 } else { /* burst'd beacons */ 485 uint32_t *bflink = &bfaddr; 486 487 for (slot = 0; slot < ATH_BCBUF; slot++) { 488 vap = sc->sc_bslot[slot]; 489 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) { 490 bf = ath_beacon_generate(sc, vap); 491 /* 492 * XXX TODO: this should use settxdesclinkptr() 493 * otherwise it won't work for EDMA chipsets! 494 */ 495 if (bf != NULL) { 496 /* XXX should do this using the ds */ 497 *bflink = bf->bf_daddr; 498 ath_hal_gettxdesclinkptr(sc->sc_ah, 499 bf->bf_desc, &bflink); 500 } 501 } 502 } 503 /* 504 * XXX TODO: this should use settxdesclinkptr() 505 * otherwise it won't work for EDMA chipsets! 506 */ 507 *bflink = 0; /* terminate list */ 508 } 509 510 /* 511 * Handle slot time change when a non-ERP station joins/leaves 512 * an 11g network. The 802.11 layer notifies us via callback, 513 * we mark updateslot, then wait one beacon before effecting 514 * the change. This gives associated stations at least one 515 * beacon interval to note the state change. 516 */ 517 /* XXX locking */ 518 if (sc->sc_updateslot == UPDATE) { 519 sc->sc_updateslot = COMMIT; /* commit next beacon */ 520 sc->sc_slotupdate = slot; 521 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) 522 ath_setslottime(sc); /* commit change to h/w */ 523 524 /* 525 * Check recent per-antenna transmit statistics and flip 526 * the default antenna if noticeably more frames went out 527 * on the non-default antenna. 528 * XXX assumes 2 anntenae 529 */ 530 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) { 531 otherant = sc->sc_defant & 1 ? 2 : 1; 532 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 533 ath_setdefantenna(sc, otherant); 534 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 535 } 536 537 /* Program the CABQ with the contents of the CABQ txq and start it */ 538 ATH_TXQ_LOCK(sc->sc_cabq); 539 ath_beacon_cabq_start(sc); 540 ATH_TXQ_UNLOCK(sc->sc_cabq); 541 542 /* Program the new beacon frame if we have one for this interval */ 543 if (bfaddr != 0) { 544 /* 545 * Stop any current dma and put the new frame on the queue. 546 * This should never fail since we check above that no frames 547 * are still pending on the queue. 548 */ 549 if (! sc->sc_isedma) { 550 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 551 DPRINTF(sc, ATH_DEBUG_ANY, 552 "%s: beacon queue %u did not stop?\n", 553 __func__, sc->sc_bhalq); 554 } 555 } 556 /* NB: cabq traffic should already be queued and primed */ 557 558 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr); 559 ath_hal_txstart(ah, sc->sc_bhalq); 560 561 sc->sc_stats.ast_be_xmit++; 562 } 563 } 564 565 static void 566 ath_beacon_cabq_start_edma(struct ath_softc *sc) 567 { 568 struct ath_buf *bf, *bf_last; 569 struct ath_txq *cabq = sc->sc_cabq; 570 #if 0 571 struct ath_buf *bfi; 572 int i = 0; 573 #endif 574 575 ATH_TXQ_LOCK_ASSERT(cabq); 576 577 if (TAILQ_EMPTY(&cabq->axq_q)) 578 return; 579 bf = TAILQ_FIRST(&cabq->axq_q); 580 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s); 581 582 /* 583 * This is a dirty, dirty hack to push the contents of 584 * the cabq staging queue into the FIFO. 585 * 586 * This ideally should live in the EDMA code file 587 * and only push things into the CABQ if there's a FIFO 588 * slot. 589 * 590 * We can't treat this like a normal TX queue because 591 * in the case of multi-VAP traffic, we may have to flush 592 * the CABQ each new (staggered) beacon that goes out. 593 * But for non-staggered beacons, we could in theory 594 * handle multicast traffic for all VAPs in one FIFO 595 * push. Just keep all of this in mind if you're wondering 596 * how to correctly/better handle multi-VAP CABQ traffic 597 * with EDMA. 598 */ 599 600 /* 601 * Is the CABQ FIFO free? If not, complain loudly and 602 * don't queue anything. Maybe we'll flush the CABQ 603 * traffic, maybe we won't. But that'll happen next 604 * beacon interval. 605 */ 606 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 607 device_printf(sc->sc_dev, 608 "%s: Q%d: CAB FIFO queue=%d?\n", 609 __func__, 610 cabq->axq_qnum, 611 cabq->axq_fifo_depth); 612 return; 613 } 614 615 /* 616 * Ok, so here's the gymnastics reqiured to make this 617 * all sensible. 618 */ 619 620 /* 621 * Tag the first/last buffer appropriately. 622 */ 623 bf->bf_flags |= ATH_BUF_FIFOPTR; 624 bf_last->bf_flags |= ATH_BUF_FIFOEND; 625 626 #if 0 627 i = 0; 628 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) { 629 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0); 630 i++; 631 } 632 #endif 633 634 /* 635 * We now need to push this set of frames onto the tail 636 * of the FIFO queue. We don't adjust the aggregate 637 * count, only the queue depth counter(s). 638 * We also need to blank the link pointer now. 639 */ 640 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list); 641 cabq->axq_link = NULL; 642 cabq->fifo.axq_depth += cabq->axq_depth; 643 cabq->axq_depth = 0; 644 645 /* Bump FIFO queue */ 646 cabq->axq_fifo_depth++; 647 648 /* Push the first entry into the hardware */ 649 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 650 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 651 652 /* NB: gated by beacon so safe to start here */ 653 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 654 655 } 656 657 static void 658 ath_beacon_cabq_start_legacy(struct ath_softc *sc) 659 { 660 struct ath_buf *bf; 661 struct ath_txq *cabq = sc->sc_cabq; 662 663 ATH_TXQ_LOCK_ASSERT(cabq); 664 if (TAILQ_EMPTY(&cabq->axq_q)) 665 return; 666 bf = TAILQ_FIRST(&cabq->axq_q); 667 668 /* Push the first entry into the hardware */ 669 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr); 670 cabq->axq_flags |= ATH_TXQ_PUTRUNNING; 671 672 /* NB: gated by beacon so safe to start here */ 673 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum); 674 } 675 676 /* 677 * Start CABQ transmission - this assumes that all frames are prepped 678 * and ready in the CABQ. 679 */ 680 void 681 ath_beacon_cabq_start(struct ath_softc *sc) 682 { 683 struct ath_txq *cabq = sc->sc_cabq; 684 685 ATH_TXQ_LOCK_ASSERT(cabq); 686 687 if (TAILQ_EMPTY(&cabq->axq_q)) 688 return; 689 690 if (sc->sc_isedma) 691 ath_beacon_cabq_start_edma(sc); 692 else 693 ath_beacon_cabq_start_legacy(sc); 694 } 695 696 struct ath_buf * 697 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap) 698 { 699 struct ath_vap *avp = ATH_VAP(vap); 700 struct ath_txq *cabq = sc->sc_cabq; 701 struct ath_buf *bf; 702 struct mbuf *m; 703 int nmcastq, error; 704 705 KASSERT(vap->iv_state >= IEEE80211_S_RUN, 706 ("not running, state %d", vap->iv_state)); 707 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 708 709 /* 710 * Update dynamic beacon contents. If this returns 711 * non-zero then we need to remap the memory because 712 * the beacon frame changed size (probably because 713 * of the TIM bitmap). 714 */ 715 bf = avp->av_bcbuf; 716 m = bf->bf_m; 717 /* XXX lock mcastq? */ 718 nmcastq = avp->av_mcastq.axq_depth; 719 720 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) { 721 /* XXX too conservative? */ 722 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 723 #if defined(__DragonFly__) 724 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 725 bf->bf_dmamap, m, 726 bf->bf_segs, 1, &bf->bf_nseg, 727 BUS_DMA_NOWAIT); 728 #else 729 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 730 bf->bf_segs, &bf->bf_nseg, 731 BUS_DMA_NOWAIT); 732 #endif 733 if (error != 0) { 734 if_printf(vap->iv_ifp, 735 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 736 __func__, error); 737 return NULL; 738 } 739 } 740 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) { 741 DPRINTF(sc, ATH_DEBUG_BEACON, 742 "%s: cabq did not drain, mcastq %u cabq %u\n", 743 __func__, nmcastq, cabq->axq_depth); 744 sc->sc_stats.ast_cabq_busy++; 745 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) { 746 /* 747 * CABQ traffic from a previous vap is still pending. 748 * We must drain the q before this beacon frame goes 749 * out as otherwise this vap's stations will get cab 750 * frames from a different vap. 751 * XXX could be slow causing us to miss DBA 752 */ 753 /* 754 * XXX TODO: this doesn't stop CABQ DMA - it assumes 755 * that since we're about to transmit a beacon, we've 756 * already stopped transmitting on the CABQ. But this 757 * doesn't at all mean that the CABQ DMA QCU will 758 * accept a new TXDP! So what, should we do a DMA 759 * stop? What if it fails? 760 * 761 * More thought is required here. 762 */ 763 /* 764 * XXX can we even stop TX DMA here? Check what the 765 * reference driver does for cabq for beacons, given 766 * that stopping TX requires RX is paused. 767 */ 768 ath_tx_draintxq(sc, cabq); 769 } 770 } 771 ath_beacon_setup(sc, bf); 772 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 773 774 /* 775 * Enable the CAB queue before the beacon queue to 776 * insure cab frames are triggered by this beacon. 777 */ 778 if (avp->av_boff.bo_tim[4] & 1) { 779 780 /* NB: only at DTIM */ 781 ATH_TXQ_LOCK(&avp->av_mcastq); 782 if (nmcastq) { 783 struct ath_buf *bfm, *bfc_last; 784 785 /* 786 * Move frames from the s/w mcast q to the h/w cab q. 787 * 788 * XXX TODO: if we chain together multiple VAPs 789 * worth of CABQ traffic, should we keep the 790 * MORE data bit set on the last frame of each 791 * intermediary VAP (ie, only clear the MORE 792 * bit of the last frame on the last vap?) 793 */ 794 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q); 795 ATH_TXQ_LOCK(cabq); 796 797 /* 798 * If there's already a frame on the CABQ, we 799 * need to link to the end of the last frame. 800 * We can't use axq_link here because 801 * EDMA descriptors require some recalculation 802 * (checksum) to occur. 803 */ 804 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s); 805 if (bfc_last != NULL) { 806 ath_hal_settxdesclink(sc->sc_ah, 807 bfc_last->bf_lastds, 808 bfm->bf_daddr); 809 } 810 ath_txqmove(cabq, &avp->av_mcastq); 811 ATH_TXQ_UNLOCK(cabq); 812 /* 813 * XXX not entirely accurate, in case a mcast 814 * queue frame arrived before we grabbed the TX 815 * lock. 816 */ 817 sc->sc_stats.ast_cabq_xmit += nmcastq; 818 } 819 ATH_TXQ_UNLOCK(&avp->av_mcastq); 820 } 821 return bf; 822 } 823 824 void 825 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap) 826 { 827 struct ath_vap *avp = ATH_VAP(vap); 828 struct ath_hal *ah = sc->sc_ah; 829 struct ath_buf *bf; 830 struct mbuf *m; 831 int error; 832 833 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer")); 834 835 /* 836 * Update dynamic beacon contents. If this returns 837 * non-zero then we need to remap the memory because 838 * the beacon frame changed size (probably because 839 * of the TIM bitmap). 840 */ 841 bf = avp->av_bcbuf; 842 m = bf->bf_m; 843 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) { 844 /* XXX too conservative? */ 845 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 846 #if defined(__DragonFly__) 847 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 848 bf->bf_dmamap, m, 849 bf->bf_segs, 1, &bf->bf_nseg, 850 BUS_DMA_NOWAIT); 851 #else 852 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 853 bf->bf_segs, &bf->bf_nseg, 854 BUS_DMA_NOWAIT); 855 #endif 856 if (error != 0) { 857 if_printf(vap->iv_ifp, 858 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 859 __func__, error); 860 return; 861 } 862 } 863 ath_beacon_setup(sc, bf); 864 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 865 866 /* NB: caller is known to have already stopped tx dma */ 867 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 868 ath_hal_txstart(ah, sc->sc_bhalq); 869 } 870 871 /* 872 * Reclaim beacon resources and return buffer to the pool. 873 */ 874 void 875 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf) 876 { 877 878 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 879 __func__, bf, bf->bf_m, bf->bf_node); 880 if (bf->bf_m != NULL) { 881 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 882 m_freem(bf->bf_m); 883 bf->bf_m = NULL; 884 } 885 if (bf->bf_node != NULL) { 886 ieee80211_free_node(bf->bf_node); 887 bf->bf_node = NULL; 888 } 889 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list); 890 } 891 892 /* 893 * Reclaim beacon resources. 894 */ 895 void 896 ath_beacon_free(struct ath_softc *sc) 897 { 898 struct ath_buf *bf; 899 900 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 901 DPRINTF(sc, ATH_DEBUG_NODE, 902 "%s: free bf=%p, bf_m=%p, bf_node=%p\n", 903 __func__, bf, bf->bf_m, bf->bf_node); 904 if (bf->bf_m != NULL) { 905 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 906 m_freem(bf->bf_m); 907 bf->bf_m = NULL; 908 } 909 if (bf->bf_node != NULL) { 910 ieee80211_free_node(bf->bf_node); 911 bf->bf_node = NULL; 912 } 913 } 914 } 915 916 /* 917 * Configure the beacon and sleep timers. 918 * 919 * When operating as an AP this resets the TSF and sets 920 * up the hardware to notify us when we need to issue beacons. 921 * 922 * When operating in station mode this sets up the beacon 923 * timers according to the timestamp of the last received 924 * beacon and the current TSF, configures PCF and DTIM 925 * handling, programs the sleep registers so the hardware 926 * will wakeup in time to receive beacons, and configures 927 * the beacon miss handling so we'll receive a BMISS 928 * interrupt when we stop seeing beacons from the AP 929 * we've associated with. 930 */ 931 void 932 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap) 933 { 934 #define TSF_TO_TU(_h,_l) \ 935 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 936 #define FUDGE 2 937 struct ath_hal *ah = sc->sc_ah; 938 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 939 struct ieee80211_node *ni; 940 u_int32_t nexttbtt, intval, tsftu; 941 u_int32_t nexttbtt_u8, intval_u8; 942 u_int64_t tsf, tsf_beacon; 943 944 if (vap == NULL) 945 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 946 /* 947 * Just ensure that we aren't being called when the last 948 * VAP is destroyed. 949 */ 950 if (vap == NULL) { 951 device_printf(sc->sc_dev, "%s: called with no VAPs\n", 952 __func__); 953 return; 954 } 955 956 ni = ieee80211_ref_node(vap->iv_bss); 957 958 ATH_LOCK(sc); 959 ath_power_set_power_state(sc, HAL_PM_AWAKE); 960 ATH_UNLOCK(sc); 961 962 /* extract tstamp from last beacon and convert to TU */ 963 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 964 LE_READ_4(ni->ni_tstamp.data)); 965 966 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 967 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 968 969 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 970 ic->ic_opmode == IEEE80211_M_MBSS) { 971 /* 972 * For multi-bss ap/mesh support beacons are either staggered 973 * evenly over N slots or burst together. For the former 974 * arrange for the SWBA to be delivered for each slot. 975 * Slots that are not occupied will generate nothing. 976 */ 977 /* NB: the beacon interval is kept internally in TU's */ 978 intval = ni->ni_intval & HAL_BEACON_PERIOD; 979 if (sc->sc_stagbeacons) 980 intval /= ATH_BCBUF; 981 } else { 982 /* NB: the beacon interval is kept internally in TU's */ 983 intval = ni->ni_intval & HAL_BEACON_PERIOD; 984 } 985 if (nexttbtt == 0) /* e.g. for ap mode */ 986 nexttbtt = intval; 987 else if (intval) /* NB: can be 0 for monitor mode */ 988 nexttbtt = roundup(nexttbtt, intval); 989 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 990 __func__, nexttbtt, intval, ni->ni_intval); 991 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) { 992 HAL_BEACON_STATE bs; 993 int dtimperiod, dtimcount; 994 int cfpperiod, cfpcount; 995 996 /* 997 * Setup dtim and cfp parameters according to 998 * last beacon we received (which may be none). 999 */ 1000 dtimperiod = ni->ni_dtim_period; 1001 if (dtimperiod <= 0) /* NB: 0 if not known */ 1002 dtimperiod = 1; 1003 dtimcount = ni->ni_dtim_count; 1004 if (dtimcount >= dtimperiod) /* NB: sanity check */ 1005 dtimcount = 0; /* XXX? */ 1006 cfpperiod = 1; /* NB: no PCF support yet */ 1007 cfpcount = 0; 1008 /* 1009 * Pull nexttbtt forward to reflect the current 1010 * TSF and calculate dtim+cfp state for the result. 1011 */ 1012 tsf = ath_hal_gettsf64(ah); 1013 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1014 1015 DPRINTF(sc, ATH_DEBUG_BEACON, 1016 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n", 1017 __func__, 1018 (unsigned long long) tsf_beacon, 1019 (unsigned long long) tsf, 1020 nexttbtt, 1021 tsftu); 1022 DPRINTF(sc, ATH_DEBUG_BEACON, 1023 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n", 1024 __func__, 1025 (unsigned long long) tsf_beacon, 1026 (unsigned long long) tsf, 1027 (long long) tsf - 1028 (long long) tsf_beacon); 1029 1030 DPRINTF(sc, ATH_DEBUG_BEACON, 1031 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n", 1032 __func__, 1033 (unsigned long long) nexttbtt, 1034 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon); 1035 1036 /* XXX cfpcount? */ 1037 1038 if (nexttbtt > tsftu) { 1039 uint32_t countdiff, oldtbtt, remainder; 1040 1041 oldtbtt = nexttbtt; 1042 remainder = (nexttbtt - tsftu) % intval; 1043 nexttbtt = tsftu + remainder; 1044 1045 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod; 1046 if (dtimcount > countdiff) { 1047 dtimcount -= countdiff; 1048 } else { 1049 dtimcount += dtimperiod - countdiff; 1050 } 1051 } else { //nexttbtt <= tsftu 1052 uint32_t countdiff, oldtbtt, remainder; 1053 1054 oldtbtt = nexttbtt; 1055 remainder = (tsftu - nexttbtt) % intval; 1056 nexttbtt = tsftu - remainder + intval; 1057 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod; 1058 if (dtimcount > countdiff) { 1059 dtimcount -= countdiff; 1060 } else { 1061 dtimcount += dtimperiod - countdiff; 1062 } 1063 } 1064 1065 DPRINTF(sc, ATH_DEBUG_BEACON, 1066 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n", 1067 __func__, 1068 (unsigned long long) nexttbtt, 1069 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf); 1070 1071 memset(&bs, 0, sizeof(bs)); 1072 bs.bs_intval = intval; 1073 bs.bs_nexttbtt = nexttbtt; 1074 bs.bs_dtimperiod = dtimperiod*intval; 1075 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 1076 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 1077 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 1078 bs.bs_cfpmaxduration = 0; 1079 #if 0 1080 /* 1081 * The 802.11 layer records the offset to the DTIM 1082 * bitmap while receiving beacons; use it here to 1083 * enable h/w detection of our AID being marked in 1084 * the bitmap vector (to indicate frames for us are 1085 * pending at the AP). 1086 * XXX do DTIM handling in s/w to WAR old h/w bugs 1087 * XXX enable based on h/w rev for newer chips 1088 */ 1089 bs.bs_timoffset = ni->ni_timoff; 1090 #endif 1091 /* 1092 * Calculate the number of consecutive beacons to miss 1093 * before taking a BMISS interrupt. 1094 * Note that we clamp the result to at most 10 beacons. 1095 */ 1096 bs.bs_bmissthreshold = vap->iv_bmissthreshold; 1097 if (bs.bs_bmissthreshold > 10) 1098 bs.bs_bmissthreshold = 10; 1099 else if (bs.bs_bmissthreshold <= 0) 1100 bs.bs_bmissthreshold = 1; 1101 1102 /* 1103 * Calculate sleep duration. The configuration is 1104 * given in ms. We insure a multiple of the beacon 1105 * period is used. Also, if the sleep duration is 1106 * greater than the DTIM period then it makes senses 1107 * to make it a multiple of that. 1108 * 1109 * XXX fixed at 100ms 1110 */ 1111 bs.bs_sleepduration = 1112 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 1113 if (bs.bs_sleepduration > bs.bs_dtimperiod) 1114 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 1115 1116 DPRINTF(sc, ATH_DEBUG_BEACON, 1117 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u " 1118 "nextdtim %u bmiss %u sleep %u cfp:period %u " 1119 "maxdur %u next %u timoffset %u\n" 1120 , __func__ 1121 , tsf 1122 , tsftu 1123 , bs.bs_intval 1124 , bs.bs_nexttbtt 1125 , bs.bs_dtimperiod 1126 , bs.bs_nextdtim 1127 , bs.bs_bmissthreshold 1128 , bs.bs_sleepduration 1129 , bs.bs_cfpperiod 1130 , bs.bs_cfpmaxduration 1131 , bs.bs_cfpnext 1132 , bs.bs_timoffset 1133 ); 1134 ath_hal_intrset(ah, 0); 1135 ath_hal_beacontimers(ah, &bs); 1136 sc->sc_imask |= HAL_INT_BMISS; 1137 ath_hal_intrset(ah, sc->sc_imask); 1138 } else { 1139 ath_hal_intrset(ah, 0); 1140 if (nexttbtt == intval) 1141 intval |= HAL_BEACON_RESET_TSF; 1142 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1143 /* 1144 * In IBSS mode enable the beacon timers but only 1145 * enable SWBA interrupts if we need to manually 1146 * prepare beacon frames. Otherwise we use a 1147 * self-linked tx descriptor and let the hardware 1148 * deal with things. 1149 */ 1150 intval |= HAL_BEACON_ENA; 1151 if (!sc->sc_hasveol) 1152 sc->sc_imask |= HAL_INT_SWBA; 1153 if ((intval & HAL_BEACON_RESET_TSF) == 0) { 1154 /* 1155 * Pull nexttbtt forward to reflect 1156 * the current TSF. 1157 */ 1158 tsf = ath_hal_gettsf64(ah); 1159 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; 1160 do { 1161 nexttbtt += intval; 1162 } while (nexttbtt < tsftu); 1163 } 1164 ath_beaconq_config(sc); 1165 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1166 ic->ic_opmode == IEEE80211_M_MBSS) { 1167 /* 1168 * In AP/mesh mode we enable the beacon timers 1169 * and SWBA interrupts to prepare beacon frames. 1170 */ 1171 intval |= HAL_BEACON_ENA; 1172 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 1173 ath_beaconq_config(sc); 1174 } 1175 1176 /* 1177 * Now dirty things because for now, the EDMA HAL has 1178 * nexttbtt and intval is TU/8. 1179 */ 1180 if (sc->sc_isedma) { 1181 nexttbtt_u8 = (nexttbtt << 3); 1182 intval_u8 = (intval << 3); 1183 if (intval & HAL_BEACON_ENA) 1184 intval_u8 |= HAL_BEACON_ENA; 1185 if (intval & HAL_BEACON_RESET_TSF) 1186 intval_u8 |= HAL_BEACON_RESET_TSF; 1187 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8); 1188 } else 1189 ath_hal_beaconinit(ah, nexttbtt, intval); 1190 sc->sc_bmisscount = 0; 1191 ath_hal_intrset(ah, sc->sc_imask); 1192 /* 1193 * When using a self-linked beacon descriptor in 1194 * ibss mode load it once here. 1195 */ 1196 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 1197 ath_beacon_start_adhoc(sc, vap); 1198 } 1199 ieee80211_free_node(ni); 1200 1201 ATH_LOCK(sc); 1202 ath_power_restore_power_state(sc); 1203 ATH_UNLOCK(sc); 1204 #undef FUDGE 1205 #undef TSF_TO_TU 1206 } 1207