1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/sockio.h> 61 #include <sys/errno.h> 62 #include <sys/callout.h> 63 #include <sys/bus.h> 64 #include <sys/endian.h> 65 #include <sys/kthread.h> 66 #include <sys/taskqueue.h> 67 #include <sys/caps.h> 68 #include <sys/module.h> 69 #include <sys/ktr.h> 70 71 #if defined(__DragonFly__) 72 /* empty */ 73 #else 74 #include <sys/smp.h> /* for mp_ncpus */ 75 #include <machine/bus.h> 76 #endif 77 78 #include <net/if.h> 79 #include <net/if_var.h> 80 #include <net/if_dl.h> 81 #include <net/if_media.h> 82 #include <net/if_types.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_llc.h> 86 87 #include <netproto/802_11/ieee80211_var.h> 88 #include <netproto/802_11/ieee80211_regdomain.h> 89 #ifdef IEEE80211_SUPPORT_SUPERG 90 #include <netproto/802_11/ieee80211_superg.h> 91 #endif 92 #ifdef IEEE80211_SUPPORT_TDMA 93 #include <netproto/802_11/ieee80211_tdma.h> 94 #endif 95 96 #include <net/bpf.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_ether.h> 101 #endif 102 103 #include <dev/netif/ath/ath/if_athvar.h> 104 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */ 105 #include <dev/netif/ath/ath_hal/ah_diagcodes.h> 106 107 #include <dev/netif/ath/ath/if_ath_debug.h> 108 #include <dev/netif/ath/ath/if_ath_misc.h> 109 #if 0 110 #include <dev/netif/ath/ath/if_ath_tsf.h> 111 #include <dev/netif/ath/ath/if_ath_tx.h> 112 #include <dev/netif/ath/ath/if_ath_sysctl.h> 113 #include <dev/netif/ath/ath/if_ath_led.h> 114 #include <dev/netif/ath/ath/if_ath_keycache.h> 115 #include <dev/netif/ath/ath/if_ath_rx.h> 116 #include <dev/netif/ath/ath/if_ath_rx_edma.h> 117 #include <dev/netif/ath/ath/if_ath_tx_edma.h> 118 #include <dev/netif/ath/ath/if_ath_beacon.h> 119 #include <dev/netif/ath/ath/if_ath_btcoex.h> 120 #include <dev/netif/ath/ath/if_ath_spectral.h> 121 #include <dev/netif/ath/ath/if_ath_lna_div.h> 122 #include <dev/netif/ath/ath/if_athdfs.h> 123 #endif 124 #include <dev/netif/ath/ath/if_ath_descdma.h> 125 126 MALLOC_DECLARE(M_ATHDEV); 127 128 /* 129 * This is the descriptor setup / busdma memory intialisation and 130 * teardown routines. 131 */ 132 133 static void 134 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 135 { 136 bus_addr_t *paddr = (bus_addr_t*) arg; 137 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 138 *paddr = segs->ds_addr; 139 } 140 141 /* 142 * Allocate the descriptors and appropriate DMA tag/setup. 143 * 144 * For some situations (eg EDMA TX completion), there isn't a requirement 145 * for the ath_buf entries to be allocated. 146 */ 147 int 148 ath_descdma_alloc_desc(struct ath_softc *sc, 149 struct ath_descdma *dd, ath_bufhead *head, 150 const char *name, int ds_size, int ndesc) 151 { 152 #define DS2PHYS(_dd, _ds) \ 153 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 154 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 155 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 156 int error; 157 158 dd->dd_descsize = ds_size; 159 160 DPRINTF(sc, ATH_DEBUG_RESET, 161 "%s: %s DMA: %u desc, %d bytes per descriptor\n", 162 __func__, name, ndesc, dd->dd_descsize); 163 164 dd->dd_name = name; 165 dd->dd_desc_len = dd->dd_descsize * ndesc; 166 167 /* 168 * Merlin work-around: 169 * Descriptors that cross the 4KB boundary can't be used. 170 * Assume one skipped descriptor per 4KB page. 171 */ 172 if (! ath_hal_split4ktrans(sc->sc_ah)) { 173 int numpages = dd->dd_desc_len / 4096; 174 dd->dd_desc_len += ds_size * numpages; 175 } 176 177 /* 178 * Setup DMA descriptor area. 179 * 180 * BUS_DMA_ALLOCNOW is not used; we never use bounce 181 * buffers for the descriptors themselves. 182 */ 183 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 184 PAGE_SIZE, 0, /* alignment, bounds */ 185 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 186 BUS_SPACE_MAXADDR, /* highaddr */ 187 #if defined(__DragonFly__) 188 #else 189 NULL, NULL, /* filter, filterarg */ 190 #endif 191 dd->dd_desc_len, /* maxsize */ 192 1, /* nsegments */ 193 dd->dd_desc_len, /* maxsegsize */ 194 0, /* flags */ 195 #if defined(__DragonFly__) 196 #else 197 NULL, /* lockfunc */ 198 NULL, /* lockarg */ 199 #endif 200 &dd->dd_dmat); 201 if (error != 0) { 202 device_printf(sc->sc_dev, 203 "cannot allocate %s DMA tag\n", dd->dd_name); 204 return error; 205 } 206 207 /* allocate descriptors */ 208 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 209 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 210 &dd->dd_dmamap); 211 if (error != 0) { 212 device_printf(sc->sc_dev, 213 "unable to alloc memory for %u %s descriptors, error %u\n", 214 ndesc, dd->dd_name, error); 215 goto fail1; 216 } 217 218 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 219 dd->dd_desc, dd->dd_desc_len, 220 ath_load_cb, &dd->dd_desc_paddr, 221 BUS_DMA_NOWAIT); 222 if (error != 0) { 223 device_printf(sc->sc_dev, 224 "unable to map %s descriptors, error %u\n", 225 dd->dd_name, error); 226 goto fail2; 227 } 228 229 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 230 __func__, dd->dd_name, (uint8_t *) dd->dd_desc, 231 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr, 232 /*XXX*/ (u_long) dd->dd_desc_len); 233 234 return (0); 235 236 fail2: 237 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 238 fail1: 239 bus_dma_tag_destroy(dd->dd_dmat); 240 memset(dd, 0, sizeof(*dd)); 241 return error; 242 #undef DS2PHYS 243 #undef ATH_DESC_4KB_BOUND_CHECK 244 } 245 246 int 247 ath_descdma_setup(struct ath_softc *sc, 248 struct ath_descdma *dd, ath_bufhead *head, 249 const char *name, int ds_size, int nbuf, int ndesc) 250 { 251 #define DS2PHYS(_dd, _ds) \ 252 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 253 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 254 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 255 uint8_t *ds; 256 struct ath_buf *bf; 257 int i, bsize, error; 258 259 /* Allocate descriptors */ 260 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size, 261 nbuf * ndesc); 262 263 /* Assume any errors during allocation were dealt with */ 264 if (error != 0) { 265 return (error); 266 } 267 268 ds = (uint8_t *) dd->dd_desc; 269 270 /* allocate rx buffers */ 271 bsize = sizeof(struct ath_buf) * nbuf; 272 bf = kmalloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 273 if (bf == NULL) { 274 device_printf(sc->sc_dev, 275 "malloc of %s buffers failed, size %u\n", 276 dd->dd_name, bsize); 277 goto fail3; 278 } 279 dd->dd_bufptr = bf; 280 281 TAILQ_INIT(head); 282 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) { 283 bf->bf_desc = (struct ath_desc *) ds; 284 bf->bf_daddr = DS2PHYS(dd, ds); 285 if (! ath_hal_split4ktrans(sc->sc_ah)) { 286 /* 287 * Merlin WAR: Skip descriptor addresses which 288 * cause 4KB boundary crossing along any point 289 * in the descriptor. 290 */ 291 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 292 dd->dd_descsize)) { 293 /* Start at the next page */ 294 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 295 bf->bf_desc = (struct ath_desc *) ds; 296 bf->bf_daddr = DS2PHYS(dd, ds); 297 } 298 } 299 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 300 &bf->bf_dmamap); 301 if (error != 0) { 302 device_printf(sc->sc_dev, "unable to create dmamap " 303 "for %s buffer %u, error %u\n", 304 dd->dd_name, i, error); 305 ath_descdma_cleanup(sc, dd, head); 306 return error; 307 } 308 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 309 TAILQ_INSERT_TAIL(head, bf, bf_list); 310 } 311 312 /* 313 * XXX TODO: ensure that ds doesn't overflow the descriptor 314 * allocation otherwise weird stuff will occur and crash your 315 * machine. 316 */ 317 return 0; 318 /* XXX this should likely just call ath_descdma_cleanup() */ 319 fail3: 320 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 321 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 322 bus_dma_tag_destroy(dd->dd_dmat); 323 memset(dd, 0, sizeof(*dd)); 324 return error; 325 #undef DS2PHYS 326 #undef ATH_DESC_4KB_BOUND_CHECK 327 } 328 329 /* 330 * Allocate ath_buf entries but no descriptor contents. 331 * 332 * This is for RX EDMA where the descriptors are the header part of 333 * the RX buffer. 334 */ 335 int 336 ath_descdma_setup_rx_edma(struct ath_softc *sc, 337 struct ath_descdma *dd, ath_bufhead *head, 338 const char *name, int nbuf, int rx_status_len) 339 { 340 struct ath_buf *bf; 341 int i, bsize, error; 342 343 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n", 344 __func__, name, nbuf); 345 346 dd->dd_name = name; 347 /* 348 * This is (mostly) purely for show. We're not allocating any actual 349 * descriptors here as EDMA RX has the descriptor be part 350 * of the RX buffer. 351 * 352 * However, dd_desc_len is used by ath_descdma_free() to determine 353 * whether we have already freed this DMA mapping. 354 */ 355 dd->dd_desc_len = rx_status_len * nbuf; 356 dd->dd_descsize = rx_status_len; 357 358 /* allocate rx buffers */ 359 bsize = sizeof(struct ath_buf) * nbuf; 360 bf = kmalloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 361 if (bf == NULL) { 362 device_printf(sc->sc_dev, 363 "malloc of %s buffers failed, size %u\n", 364 dd->dd_name, bsize); 365 error = ENOMEM; 366 goto fail3; 367 } 368 dd->dd_bufptr = bf; 369 370 TAILQ_INIT(head); 371 for (i = 0; i < nbuf; i++, bf++) { 372 bf->bf_desc = NULL; 373 bf->bf_daddr = 0; 374 bf->bf_lastds = NULL; /* Just an initial value */ 375 376 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 377 &bf->bf_dmamap); 378 if (error != 0) { 379 device_printf(sc->sc_dev, "unable to create dmamap " 380 "for %s buffer %u, error %u\n", 381 dd->dd_name, i, error); 382 ath_descdma_cleanup(sc, dd, head); 383 return error; 384 } 385 TAILQ_INSERT_TAIL(head, bf, bf_list); 386 } 387 return 0; 388 fail3: 389 memset(dd, 0, sizeof(*dd)); 390 return error; 391 } 392 393 void 394 ath_descdma_cleanup(struct ath_softc *sc, 395 struct ath_descdma *dd, ath_bufhead *head) 396 { 397 struct ath_buf *bf; 398 struct ieee80211_node *ni; 399 int do_warning = 0; 400 401 if (dd->dd_dmamap != 0) { 402 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 403 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 404 bus_dma_tag_destroy(dd->dd_dmat); 405 } 406 407 if (head != NULL) { 408 TAILQ_FOREACH(bf, head, bf_list) { 409 if (bf->bf_m) { 410 /* 411 * XXX warn if there's buffers here. 412 * XXX it should have been freed by the 413 * owner! 414 */ 415 416 if (do_warning == 0) { 417 do_warning = 1; 418 device_printf(sc->sc_dev, 419 "%s: %s: mbuf should've been" 420 " unmapped/freed!\n", 421 __func__, 422 dd->dd_name); 423 } 424 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 425 BUS_DMASYNC_POSTREAD); 426 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 427 m_freem(bf->bf_m); 428 bf->bf_m = NULL; 429 } 430 if (bf->bf_dmamap != NULL) { 431 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 432 bf->bf_dmamap = NULL; 433 } 434 ni = bf->bf_node; 435 bf->bf_node = NULL; 436 if (ni != NULL) { 437 /* 438 * Reclaim node reference. 439 */ 440 ieee80211_free_node(ni); 441 } 442 } 443 } 444 445 if (head != NULL) 446 TAILQ_INIT(head); 447 448 if (dd->dd_bufptr != NULL) 449 kfree(dd->dd_bufptr, M_ATHDEV); 450 memset(dd, 0, sizeof(*dd)); 451 } 452