1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 72 #if defined(__DragonFly__) 73 /* empty */ 74 #else 75 #include <sys/smp.h> /* for mp_ncpus */ 76 #include <machine/bus.h> 77 #endif 78 79 #include <net/if.h> 80 #include <net/if_var.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_arp.h> 85 #include <net/ethernet.h> 86 #include <net/if_llc.h> 87 88 #include <netproto/802_11/ieee80211_var.h> 89 #include <netproto/802_11/ieee80211_regdomain.h> 90 #ifdef IEEE80211_SUPPORT_SUPERG 91 #include <netproto/802_11/ieee80211_superg.h> 92 #endif 93 #ifdef IEEE80211_SUPPORT_TDMA 94 #include <netproto/802_11/ieee80211_tdma.h> 95 #endif 96 97 #include <net/bpf.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_ether.h> 102 #endif 103 104 #include <dev/netif/ath/ath/if_athvar.h> 105 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */ 106 #include <dev/netif/ath/ath_hal/ah_diagcodes.h> 107 108 #include <dev/netif/ath/ath/if_ath_debug.h> 109 #include <dev/netif/ath/ath/if_ath_misc.h> 110 #if 0 111 #include <dev/netif/ath/ath/if_ath_tsf.h> 112 #include <dev/netif/ath/ath/if_ath_tx.h> 113 #include <dev/netif/ath/ath/if_ath_sysctl.h> 114 #include <dev/netif/ath/ath/if_ath_led.h> 115 #include <dev/netif/ath/ath/if_ath_keycache.h> 116 #include <dev/netif/ath/ath/if_ath_rx.h> 117 #include <dev/netif/ath/ath/if_ath_rx_edma.h> 118 #include <dev/netif/ath/ath/if_ath_tx_edma.h> 119 #include <dev/netif/ath/ath/if_ath_beacon.h> 120 #include <dev/netif/ath/ath/if_ath_btcoex.h> 121 #include <dev/netif/ath/ath/if_ath_spectral.h> 122 #include <dev/netif/ath/ath/if_ath_lna_div.h> 123 #include <dev/netif/ath/ath/if_athdfs.h> 124 #endif 125 #include <dev/netif/ath/ath/if_ath_descdma.h> 126 127 MALLOC_DECLARE(M_ATHDEV); 128 129 /* 130 * This is the descriptor setup / busdma memory intialisation and 131 * teardown routines. 132 */ 133 134 static void 135 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 136 { 137 bus_addr_t *paddr = (bus_addr_t*) arg; 138 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 139 *paddr = segs->ds_addr; 140 } 141 142 /* 143 * Allocate the descriptors and appropriate DMA tag/setup. 144 * 145 * For some situations (eg EDMA TX completion), there isn't a requirement 146 * for the ath_buf entries to be allocated. 147 */ 148 int 149 ath_descdma_alloc_desc(struct ath_softc *sc, 150 struct ath_descdma *dd, ath_bufhead *head, 151 const char *name, int ds_size, int ndesc) 152 { 153 #define DS2PHYS(_dd, _ds) \ 154 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 155 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 156 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 157 int error; 158 159 dd->dd_descsize = ds_size; 160 161 DPRINTF(sc, ATH_DEBUG_RESET, 162 "%s: %s DMA: %u desc, %d bytes per descriptor\n", 163 __func__, name, ndesc, dd->dd_descsize); 164 165 dd->dd_name = name; 166 dd->dd_desc_len = dd->dd_descsize * ndesc; 167 168 /* 169 * Merlin work-around: 170 * Descriptors that cross the 4KB boundary can't be used. 171 * Assume one skipped descriptor per 4KB page. 172 */ 173 if (! ath_hal_split4ktrans(sc->sc_ah)) { 174 int numpages = dd->dd_desc_len / 4096; 175 dd->dd_desc_len += ds_size * numpages; 176 } 177 178 /* 179 * Setup DMA descriptor area. 180 * 181 * BUS_DMA_ALLOCNOW is not used; we never use bounce 182 * buffers for the descriptors themselves. 183 */ 184 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 185 PAGE_SIZE, 0, /* alignment, bounds */ 186 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 187 BUS_SPACE_MAXADDR, /* highaddr */ 188 NULL, NULL, /* filter, filterarg */ 189 dd->dd_desc_len, /* maxsize */ 190 1, /* nsegments */ 191 dd->dd_desc_len, /* maxsegsize */ 192 0, /* flags */ 193 #if defined(__DragonFly__) 194 #else 195 NULL, /* lockfunc */ 196 NULL, /* lockarg */ 197 #endif 198 &dd->dd_dmat); 199 if (error != 0) { 200 device_printf(sc->sc_dev, 201 "cannot allocate %s DMA tag\n", dd->dd_name); 202 return error; 203 } 204 205 /* allocate descriptors */ 206 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 207 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 208 &dd->dd_dmamap); 209 if (error != 0) { 210 device_printf(sc->sc_dev, 211 "unable to alloc memory for %u %s descriptors, error %u\n", 212 ndesc, dd->dd_name, error); 213 goto fail1; 214 } 215 216 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 217 dd->dd_desc, dd->dd_desc_len, 218 ath_load_cb, &dd->dd_desc_paddr, 219 BUS_DMA_NOWAIT); 220 if (error != 0) { 221 device_printf(sc->sc_dev, 222 "unable to map %s descriptors, error %u\n", 223 dd->dd_name, error); 224 goto fail2; 225 } 226 227 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 228 __func__, dd->dd_name, (uint8_t *) dd->dd_desc, 229 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr, 230 /*XXX*/ (u_long) dd->dd_desc_len); 231 232 return (0); 233 234 fail2: 235 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 236 fail1: 237 bus_dma_tag_destroy(dd->dd_dmat); 238 memset(dd, 0, sizeof(*dd)); 239 return error; 240 #undef DS2PHYS 241 #undef ATH_DESC_4KB_BOUND_CHECK 242 } 243 244 int 245 ath_descdma_setup(struct ath_softc *sc, 246 struct ath_descdma *dd, ath_bufhead *head, 247 const char *name, int ds_size, int nbuf, int ndesc) 248 { 249 #define DS2PHYS(_dd, _ds) \ 250 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 251 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \ 252 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0) 253 uint8_t *ds; 254 struct ath_buf *bf; 255 int i, bsize, error; 256 257 /* Allocate descriptors */ 258 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size, 259 nbuf * ndesc); 260 261 /* Assume any errors during allocation were dealt with */ 262 if (error != 0) { 263 return (error); 264 } 265 266 ds = (uint8_t *) dd->dd_desc; 267 268 /* allocate rx buffers */ 269 bsize = sizeof(struct ath_buf) * nbuf; 270 bf = kmalloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 271 if (bf == NULL) { 272 device_printf(sc->sc_dev, 273 "malloc of %s buffers failed, size %u\n", 274 dd->dd_name, bsize); 275 goto fail3; 276 } 277 dd->dd_bufptr = bf; 278 279 TAILQ_INIT(head); 280 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) { 281 bf->bf_desc = (struct ath_desc *) ds; 282 bf->bf_daddr = DS2PHYS(dd, ds); 283 if (! ath_hal_split4ktrans(sc->sc_ah)) { 284 /* 285 * Merlin WAR: Skip descriptor addresses which 286 * cause 4KB boundary crossing along any point 287 * in the descriptor. 288 */ 289 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr, 290 dd->dd_descsize)) { 291 /* Start at the next page */ 292 ds += 0x1000 - (bf->bf_daddr & 0xFFF); 293 bf->bf_desc = (struct ath_desc *) ds; 294 bf->bf_daddr = DS2PHYS(dd, ds); 295 } 296 } 297 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 298 &bf->bf_dmamap); 299 if (error != 0) { 300 device_printf(sc->sc_dev, "unable to create dmamap " 301 "for %s buffer %u, error %u\n", 302 dd->dd_name, i, error); 303 ath_descdma_cleanup(sc, dd, head); 304 return error; 305 } 306 bf->bf_lastds = bf->bf_desc; /* Just an initial value */ 307 TAILQ_INSERT_TAIL(head, bf, bf_list); 308 } 309 310 /* 311 * XXX TODO: ensure that ds doesn't overflow the descriptor 312 * allocation otherwise weird stuff will occur and crash your 313 * machine. 314 */ 315 return 0; 316 /* XXX this should likely just call ath_descdma_cleanup() */ 317 fail3: 318 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 319 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 320 bus_dma_tag_destroy(dd->dd_dmat); 321 memset(dd, 0, sizeof(*dd)); 322 return error; 323 #undef DS2PHYS 324 #undef ATH_DESC_4KB_BOUND_CHECK 325 } 326 327 /* 328 * Allocate ath_buf entries but no descriptor contents. 329 * 330 * This is for RX EDMA where the descriptors are the header part of 331 * the RX buffer. 332 */ 333 int 334 ath_descdma_setup_rx_edma(struct ath_softc *sc, 335 struct ath_descdma *dd, ath_bufhead *head, 336 const char *name, int nbuf, int rx_status_len) 337 { 338 struct ath_buf *bf; 339 int i, bsize, error; 340 341 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n", 342 __func__, name, nbuf); 343 344 dd->dd_name = name; 345 /* 346 * This is (mostly) purely for show. We're not allocating any actual 347 * descriptors here as EDMA RX has the descriptor be part 348 * of the RX buffer. 349 * 350 * However, dd_desc_len is used by ath_descdma_free() to determine 351 * whether we have already freed this DMA mapping. 352 */ 353 dd->dd_desc_len = rx_status_len * nbuf; 354 dd->dd_descsize = rx_status_len; 355 356 /* allocate rx buffers */ 357 bsize = sizeof(struct ath_buf) * nbuf; 358 bf = kmalloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 359 if (bf == NULL) { 360 device_printf(sc->sc_dev, 361 "malloc of %s buffers failed, size %u\n", 362 dd->dd_name, bsize); 363 error = ENOMEM; 364 goto fail3; 365 } 366 dd->dd_bufptr = bf; 367 368 TAILQ_INIT(head); 369 for (i = 0; i < nbuf; i++, bf++) { 370 bf->bf_desc = NULL; 371 bf->bf_daddr = 0; 372 bf->bf_lastds = NULL; /* Just an initial value */ 373 374 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 375 &bf->bf_dmamap); 376 if (error != 0) { 377 device_printf(sc->sc_dev, "unable to create dmamap " 378 "for %s buffer %u, error %u\n", 379 dd->dd_name, i, error); 380 ath_descdma_cleanup(sc, dd, head); 381 return error; 382 } 383 TAILQ_INSERT_TAIL(head, bf, bf_list); 384 } 385 return 0; 386 fail3: 387 memset(dd, 0, sizeof(*dd)); 388 return error; 389 } 390 391 void 392 ath_descdma_cleanup(struct ath_softc *sc, 393 struct ath_descdma *dd, ath_bufhead *head) 394 { 395 struct ath_buf *bf; 396 struct ieee80211_node *ni; 397 int do_warning = 0; 398 399 if (dd->dd_dmamap != 0) { 400 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 401 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 402 bus_dma_tag_destroy(dd->dd_dmat); 403 } 404 405 if (head != NULL) { 406 TAILQ_FOREACH(bf, head, bf_list) { 407 if (bf->bf_m) { 408 /* 409 * XXX warn if there's buffers here. 410 * XXX it should have been freed by the 411 * owner! 412 */ 413 414 if (do_warning == 0) { 415 do_warning = 1; 416 device_printf(sc->sc_dev, 417 "%s: %s: mbuf should've been" 418 " unmapped/freed!\n", 419 __func__, 420 dd->dd_name); 421 } 422 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 423 BUS_DMASYNC_POSTREAD); 424 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 425 m_freem(bf->bf_m); 426 bf->bf_m = NULL; 427 } 428 if (bf->bf_dmamap != NULL) { 429 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 430 bf->bf_dmamap = NULL; 431 } 432 ni = bf->bf_node; 433 bf->bf_node = NULL; 434 if (ni != NULL) { 435 /* 436 * Reclaim node reference. 437 */ 438 ieee80211_free_node(ni); 439 } 440 } 441 } 442 443 if (head != NULL) 444 TAILQ_INIT(head); 445 446 if (dd->dd_bufptr != NULL) 447 kfree(dd->dd_bufptr, M_ATHDEV); 448 memset(dd, 0, sizeof(*dd)); 449 } 450