1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 32 /* 33 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver. 34 */ 35 #include "opt_ath.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 #include <sys/errno.h> 45 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 49 #include <sys/socket.h> 50 51 #include <net/if.h> 52 #include <net/if_media.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 56 #include <netproto/802_11/ieee80211_var.h> 57 58 #include <dev/netif/ath/ath/if_athvar.h> 59 60 #include <bus/pci/pcivar.h> 61 #include <bus/pci/pcireg.h> 62 63 /* For EEPROM firmware */ 64 #ifdef ATH_EEPROM_FIRMWARE 65 #include <sys/linker.h> 66 #include <sys/firmware.h> 67 #endif /* ATH_EEPROM_FIRMWARE */ 68 69 /* 70 * PCI glue. 71 */ 72 73 struct ath_pci_softc { 74 struct ath_softc sc_sc; 75 struct resource *sc_sr; /* memory resource */ 76 struct resource *sc_irq; /* irq resource */ 77 void *sc_ih; /* interrupt handler */ 78 }; 79 80 #define BS_BAR 0x10 81 #define PCIR_RETRY_TIMEOUT 0x41 82 #define PCIR_CFG_PMCSR 0x48 83 84 #define DEFAULT_CACHESIZE 32 85 86 static void 87 ath_pci_setup(device_t dev) 88 { 89 uint8_t cz; 90 91 /* XXX TODO: need to override the _system_ saved copies of this */ 92 93 /* 94 * If the cache line size is 0, force it to a reasonable 95 * value. 96 */ 97 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 98 if (cz == 0) { 99 pci_write_config(dev, PCIR_CACHELNSZ, 100 DEFAULT_CACHESIZE / 4, 1); 101 } 102 103 /* Override the system latency timer */ 104 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1); 105 106 /* If a PCI NIC, force wakeup */ 107 #ifdef ATH_PCI_WAKEUP_WAR 108 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */ 109 if (1) { 110 uint16_t pmcsr; 111 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2); 112 pmcsr |= 3; 113 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 114 pmcsr &= ~3; 115 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2); 116 } 117 #endif 118 119 /* 120 * Disable retry timeout to keep PCI Tx retries from 121 * interfering with C3 CPU state. 122 */ 123 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1); 124 } 125 126 static int 127 ath_pci_probe(device_t dev) 128 { 129 const char* devname; 130 131 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev)); 132 if (devname != NULL) { 133 device_set_desc(dev, devname); 134 return BUS_PROBE_DEFAULT; 135 } 136 return ENXIO; 137 } 138 139 static int 140 ath_pci_attach(device_t dev) 141 { 142 struct ath_pci_softc *psc = device_get_softc(dev); 143 struct ath_softc *sc = &psc->sc_sc; 144 int error = ENXIO; 145 int rid; 146 #ifdef ATH_EEPROM_FIRMWARE 147 const struct firmware *fw = NULL; 148 const char *buf; 149 #endif 150 151 sc->sc_dev = dev; 152 153 /* 154 * Enable bus mastering. 155 */ 156 pci_enable_busmaster(dev); 157 158 /* 159 * Setup other PCI bus configuration parameters. 160 */ 161 ath_pci_setup(dev); 162 163 /* 164 * Setup memory-mapping of PCI registers. 165 */ 166 rid = BS_BAR; 167 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 168 RF_ACTIVE); 169 if (psc->sc_sr == NULL) { 170 device_printf(dev, "cannot map register space\n"); 171 goto bad; 172 } 173 /* XXX uintptr_t is a bandaid for ia64; to be fixed */ 174 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr); 175 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr); 176 /* 177 * Mark device invalid so any interrupts (shared or otherwise) 178 * that arrive before the HAL is setup are discarded. 179 */ 180 sc->sc_invalid = 1; 181 182 /* 183 * Arrange interrupt line. 184 */ 185 rid = 0; 186 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 187 RF_SHAREABLE|RF_ACTIVE); 188 if (psc->sc_irq == NULL) { 189 device_printf(dev, "could not map interrupt\n"); 190 goto bad1; 191 } 192 if (bus_setup_intr(dev, psc->sc_irq, 193 INTR_MPSAFE, 194 ath_intr, sc, &psc->sc_ih, 195 &wlan_global_serializer)) { 196 device_printf(dev, "could not establish interrupt\n"); 197 goto bad2; 198 } 199 200 /* 201 * Setup DMA descriptor area. 202 */ 203 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 204 4, 0, /* alignment, bounds */ 205 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 206 BUS_SPACE_MAXADDR, /* highaddr */ 207 NULL, NULL, /* filter, filterarg */ 208 0x3ffff, /* maxsize XXX */ 209 ATH_MAX_SCATTER, /* nsegments */ 210 0x3ffff, /* maxsegsize XXX */ 211 BUS_DMA_ALLOCNOW, /* flags */ 212 &sc->sc_dmat)) { 213 device_printf(dev, "cannot allocate DMA tag\n"); 214 goto bad3; 215 } 216 217 #ifdef ATH_EEPROM_FIRMWARE 218 /* 219 * If there's an EEPROM firmware image, load that in. 220 */ 221 if (resource_string_value(device_get_name(dev), device_get_unit(dev), 222 "eeprom_firmware", &buf) == 0) { 223 if (bootverbose) 224 device_printf(dev, "%s: looking up firmware @ '%s'\n", 225 __func__, buf); 226 227 fw = firmware_get(buf); 228 if (fw == NULL) { 229 device_printf(dev, "%s: couldn't find firmware\n", 230 __func__); 231 goto bad3; 232 } 233 234 device_printf(dev, "%s: EEPROM firmware @ %p\n", 235 __func__, fw->data); 236 sc->sc_eepromdata = 237 kmalloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO); 238 if (! sc->sc_eepromdata) { 239 device_printf(dev, "%s: can't malloc eepromdata\n", 240 __func__); 241 goto bad3; 242 } 243 memcpy(sc->sc_eepromdata, fw->data, fw->datasize); 244 firmware_put(fw, 0); 245 } 246 #endif /* ATH_EEPROM_FIRMWARE */ 247 248 ATH_LOCK_INIT(sc); 249 ATH_PCU_LOCK_INIT(sc); 250 ATH_RX_LOCK_INIT(sc); 251 ATH_TX_LOCK_INIT(sc); 252 ATH_TX_IC_LOCK_INIT(sc); 253 ATH_TXSTATUS_LOCK_INIT(sc); 254 255 wlan_serialize_enter(); 256 error = ath_attach(pci_get_device(dev), sc); 257 wlan_serialize_exit(); 258 if (error == 0) /* success */ 259 return 0; 260 261 ATH_TXSTATUS_LOCK_DESTROY(sc); 262 ATH_PCU_LOCK_DESTROY(sc); 263 ATH_RX_LOCK_DESTROY(sc); 264 ATH_TX_IC_LOCK_DESTROY(sc); 265 ATH_TX_LOCK_DESTROY(sc); 266 ATH_LOCK_DESTROY(sc); 267 bus_dma_tag_destroy(sc->sc_dmat); 268 bad3: 269 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 270 bad2: 271 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 272 bad1: 273 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 274 bad: 275 return (error); 276 } 277 278 static int 279 ath_pci_detach(device_t dev) 280 { 281 struct ath_pci_softc *psc = device_get_softc(dev); 282 struct ath_softc *sc = &psc->sc_sc; 283 284 /* check if device was removed */ 285 sc->sc_invalid = !bus_child_present(dev); 286 287 /* 288 * Do a config read to clear pre-existing pci error status. 289 */ 290 (void) pci_read_config(dev, PCIR_COMMAND, 4); 291 292 ath_detach(sc); 293 294 bus_generic_detach(dev); 295 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih); 296 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq); 297 298 bus_dma_tag_destroy(sc->sc_dmat); 299 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr); 300 301 if (sc->sc_eepromdata) 302 kfree(sc->sc_eepromdata, M_TEMP); 303 304 ATH_TXSTATUS_LOCK_DESTROY(sc); 305 ATH_PCU_LOCK_DESTROY(sc); 306 ATH_RX_LOCK_DESTROY(sc); 307 ATH_TX_IC_LOCK_DESTROY(sc); 308 ATH_TX_LOCK_DESTROY(sc); 309 ATH_LOCK_DESTROY(sc); 310 311 return (0); 312 } 313 314 static int 315 ath_pci_shutdown(device_t dev) 316 { 317 struct ath_pci_softc *psc = device_get_softc(dev); 318 319 ath_shutdown(&psc->sc_sc); 320 return (0); 321 } 322 323 static int 324 ath_pci_suspend(device_t dev) 325 { 326 struct ath_pci_softc *psc = device_get_softc(dev); 327 328 ath_suspend(&psc->sc_sc); 329 330 return (0); 331 } 332 333 static int 334 ath_pci_resume(device_t dev) 335 { 336 struct ath_pci_softc *psc = device_get_softc(dev); 337 338 /* 339 * Suspend/resume resets the PCI configuration space. 340 */ 341 ath_pci_setup(dev); 342 343 ath_resume(&psc->sc_sc); 344 345 return (0); 346 } 347 348 static device_method_t ath_pci_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, ath_pci_probe), 351 DEVMETHOD(device_attach, ath_pci_attach), 352 DEVMETHOD(device_detach, ath_pci_detach), 353 DEVMETHOD(device_shutdown, ath_pci_shutdown), 354 DEVMETHOD(device_suspend, ath_pci_suspend), 355 DEVMETHOD(device_resume, ath_pci_resume), 356 357 { 0,0 } 358 }; 359 static driver_t ath_pci_driver = { 360 "ath", 361 ath_pci_methods, 362 sizeof (struct ath_pci_softc) 363 }; 364 static devclass_t ath_devclass; 365 DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0); 366 MODULE_VERSION(ath_pci, 1); 367 MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */ 368 MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */ 369 MODULE_DEPEND(ath_pci, ath_hal, 1, 1, 1); /* Atheros HAL */ 370 MODULE_DEPEND(ath_pci, ath_rate, 1, 1, 1); /* rate control alg */ 371 MODULE_DEPEND(ath_pci, ath_dfs, 1, 1, 1); /* wtf */ 372