1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 72 #include <net/if.h> 73 #include <net/if_var.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_arp.h> 78 #include <net/ethernet.h> 79 #include <net/if_llc.h> 80 #include <net/ifq_var.h> 81 82 #include <netproto/802_11/ieee80211_var.h> 83 #include <netproto/802_11/ieee80211_regdomain.h> 84 #ifdef IEEE80211_SUPPORT_SUPERG 85 #include <netproto/802_11/ieee80211_superg.h> 86 #endif 87 #ifdef IEEE80211_SUPPORT_TDMA 88 #include <netproto/802_11/ieee80211_tdma.h> 89 #endif 90 91 #include <net/bpf.h> 92 93 #ifdef INET 94 #include <netinet/in.h> 95 #include <netinet/if_ether.h> 96 #endif 97 98 #include <dev/netif/ath/ath/if_athvar.h> 99 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */ 100 #include <dev/netif/ath/ath_hal/ah_diagcodes.h> 101 102 #include <dev/netif/ath/ath/if_ath_debug.h> 103 #include <dev/netif/ath/ath/if_ath_misc.h> 104 #include <dev/netif/ath/ath/if_ath_tsf.h> 105 #include <dev/netif/ath/ath/if_ath_tx.h> 106 #include <dev/netif/ath/ath/if_ath_sysctl.h> 107 #include <dev/netif/ath/ath/if_ath_led.h> 108 #include <dev/netif/ath/ath/if_ath_keycache.h> 109 #include <dev/netif/ath/ath/if_ath_rx.h> 110 #include <dev/netif/ath/ath/if_ath_beacon.h> 111 #include <dev/netif/ath/ath/if_athdfs.h> 112 113 #ifdef ATH_TX99_DIAG 114 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h> 115 #endif 116 117 #ifdef ATH_DEBUG_ALQ 118 #include <dev/netif/ath/ath/if_ath_alq.h> 119 #endif 120 121 #include <dev/netif/ath/ath/if_ath_lna_div.h> 122 123 /* 124 * Calculate the receive filter according to the 125 * operating mode and state: 126 * 127 * o always accept unicast, broadcast, and multicast traffic 128 * o accept PHY error frames when hardware doesn't have MIB support 129 * to count and we need them for ANI (sta mode only until recently) 130 * and we are not scanning (ANI is disabled) 131 * NB: older hal's add rx filter bits out of sight and we need to 132 * blindly preserve them 133 * o probe request frames are accepted only when operating in 134 * hostap, adhoc, mesh, or monitor modes 135 * o enable promiscuous mode 136 * - when in monitor mode 137 * - if interface marked PROMISC (assumes bridge setting is filtered) 138 * o accept beacons: 139 * - when operating in station mode for collecting rssi data when 140 * the station is otherwise quiet, or 141 * - when operating in adhoc mode so the 802.11 layer creates 142 * node table entries for peers, 143 * - when scanning 144 * - when doing s/w beacon miss (e.g. for ap+sta) 145 * - when operating in ap mode in 11g to detect overlapping bss that 146 * require protection 147 * - when operating in mesh mode to detect neighbors 148 * o accept control frames: 149 * - when in monitor mode 150 * XXX HT protection for 11n 151 */ 152 u_int32_t 153 ath_calcrxfilter(struct ath_softc *sc) 154 { 155 struct ifnet *ifp = sc->sc_ifp; 156 struct ieee80211com *ic = ifp->if_l2com; 157 u_int32_t rfilt; 158 159 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 160 if (!sc->sc_needmib && !sc->sc_scanning) 161 rfilt |= HAL_RX_FILTER_PHYERR; 162 if (ic->ic_opmode != IEEE80211_M_STA) 163 rfilt |= HAL_RX_FILTER_PROBEREQ; 164 /* XXX ic->ic_monvaps != 0? */ 165 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 166 rfilt |= HAL_RX_FILTER_PROM; 167 168 /* 169 * Only listen to all beacons if we're scanning. 170 * 171 * Otherwise we only really need to hear beacons from 172 * our own BSSID. 173 */ 174 if (ic->ic_opmode == IEEE80211_M_STA || 175 ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 176 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 177 rfilt |= HAL_RX_FILTER_MYBEACON; 178 } else { /* scanning, non-mybeacon chips */ 179 rfilt |= HAL_RX_FILTER_BEACON; 180 } 181 } 182 183 /* 184 * NB: We don't recalculate the rx filter when 185 * ic_protmode changes; otherwise we could do 186 * this only when ic_protmode != NONE. 187 */ 188 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 189 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 190 rfilt |= HAL_RX_FILTER_BEACON; 191 192 /* 193 * Enable hardware PS-POLL RX only for hostap mode; 194 * STA mode sends PS-POLL frames but never 195 * receives them. 196 */ 197 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 198 0, NULL) == HAL_OK && 199 ic->ic_opmode == IEEE80211_M_HOSTAP) 200 rfilt |= HAL_RX_FILTER_PSPOLL; 201 202 if (sc->sc_nmeshvaps) { 203 rfilt |= HAL_RX_FILTER_BEACON; 204 if (sc->sc_hasbmatch) 205 rfilt |= HAL_RX_FILTER_BSSID; 206 else 207 rfilt |= HAL_RX_FILTER_PROM; 208 } 209 if (ic->ic_opmode == IEEE80211_M_MONITOR) 210 rfilt |= HAL_RX_FILTER_CONTROL; 211 212 /* 213 * Enable RX of compressed BAR frames only when doing 214 * 802.11n. Required for A-MPDU. 215 */ 216 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 217 rfilt |= HAL_RX_FILTER_COMPBAR; 218 219 /* 220 * Enable radar PHY errors if requested by the 221 * DFS module. 222 */ 223 if (sc->sc_dodfs) 224 rfilt |= HAL_RX_FILTER_PHYRADAR; 225 226 /* 227 * Enable spectral PHY errors if requested by the 228 * spectral module. 229 */ 230 if (sc->sc_dospectral) 231 rfilt |= HAL_RX_FILTER_PHYRADAR; 232 233 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 234 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 235 return rfilt; 236 } 237 238 static int 239 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 240 { 241 struct ath_hal *ah = sc->sc_ah; 242 int error; 243 struct mbuf *m; 244 struct ath_desc *ds; 245 246 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 247 248 m = bf->bf_m; 249 if (m == NULL) { 250 /* 251 * NB: by assigning a page to the rx dma buffer we 252 * implicitly satisfy the Atheros requirement that 253 * this buffer be cache-line-aligned and sized to be 254 * multiple of the cache line size. Not doing this 255 * causes weird stuff to happen (for the 5210 at least). 256 */ 257 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 258 if (m == NULL) { 259 DPRINTF(sc, ATH_DEBUG_ANY, 260 "%s: no mbuf/cluster\n", __func__); 261 sc->sc_stats.ast_rx_nombuf++; 262 return ENOMEM; 263 } 264 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 265 266 #if defined(__DragonFly__) 267 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 268 bf->bf_dmamap, m, 269 bf->bf_segs, 1, &bf->bf_nseg, 270 BUS_DMA_NOWAIT); 271 #else 272 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 273 bf->bf_dmamap, m, 274 bf->bf_segs, &bf->bf_nseg, 275 BUS_DMA_NOWAIT); 276 #endif 277 if (error != 0) { 278 DPRINTF(sc, ATH_DEBUG_ANY, 279 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 280 __func__, error); 281 sc->sc_stats.ast_rx_busdma++; 282 m_freem(m); 283 return error; 284 } 285 KASSERT(bf->bf_nseg == 1, 286 ("multi-segment packet; nseg %u", bf->bf_nseg)); 287 bf->bf_m = m; 288 } 289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 290 291 /* 292 * Setup descriptors. For receive we always terminate 293 * the descriptor list with a self-linked entry so we'll 294 * not get overrun under high load (as can happen with a 295 * 5212 when ANI processing enables PHY error frames). 296 * 297 * To insure the last descriptor is self-linked we create 298 * each descriptor as self-linked and add it to the end. As 299 * each additional descriptor is added the previous self-linked 300 * entry is ``fixed'' naturally. This should be safe even 301 * if DMA is happening. When processing RX interrupts we 302 * never remove/process the last, self-linked, entry on the 303 * descriptor list. This insures the hardware always has 304 * someplace to write a new frame. 305 */ 306 /* 307 * 11N: we can no longer afford to self link the last descriptor. 308 * MAC acknowledges BA status as long as it copies frames to host 309 * buffer (or rx fifo). This can incorrectly acknowledge packets 310 * to a sender if last desc is self-linked. 311 */ 312 ds = bf->bf_desc; 313 if (sc->sc_rxslink) 314 ds->ds_link = bf->bf_daddr; /* link to self */ 315 else 316 ds->ds_link = 0; /* terminate the list */ 317 ds->ds_data = bf->bf_segs[0].ds_addr; 318 ath_hal_setuprxdesc(ah, ds 319 , m->m_len /* buffer size */ 320 , 0 321 ); 322 323 if (sc->sc_rxlink != NULL) 324 *sc->sc_rxlink = bf->bf_daddr; 325 sc->sc_rxlink = &ds->ds_link; 326 return 0; 327 } 328 329 /* 330 * Intercept management frames to collect beacon rssi data 331 * and to do ibss merges. 332 */ 333 void 334 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 335 int subtype, int rssi, int nf) 336 { 337 struct ieee80211vap *vap = ni->ni_vap; 338 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 339 uint64_t tsf_beacon_old, tsf_beacon; 340 uint64_t nexttbtt; 341 int64_t tsf_delta; 342 int32_t tsf_delta_bmiss; 343 int32_t tsf_remainder; 344 uint64_t tsf_beacon_target; 345 int tsf_intval; 346 347 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 348 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data); 349 350 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 351 tsf_intval = 1; 352 if (ni->ni_intval > 0) { 353 tsf_intval = TU_TO_TSF(ni->ni_intval); 354 } 355 #undef TU_TO_TSF 356 357 /* 358 * Call up first so subsequent work can use information 359 * potentially stored in the node (e.g. for ibss merge). 360 */ 361 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 362 switch (subtype) { 363 case IEEE80211_FC0_SUBTYPE_BEACON: 364 /* update rssi statistics for use by the hal */ 365 /* XXX unlocked check against vap->iv_bss? */ 366 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 367 368 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 369 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 370 371 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 372 373 /* 374 * Let's calculate the delta and remainder, so we can see 375 * if the beacon timer from the AP is varying by more than 376 * a few TU. (Which would be a huge, huge problem.) 377 */ 378 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 379 380 tsf_delta_bmiss = tsf_delta / tsf_intval; 381 382 /* 383 * If our delta is greater than half the beacon interval, 384 * let's round the bmiss value up to the next beacon 385 * interval. Ie, we're running really, really early 386 * on the next beacon. 387 */ 388 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 389 tsf_delta_bmiss ++; 390 391 tsf_beacon_target = tsf_beacon_old + 392 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 393 394 /* 395 * The remainder using '%' is between 0 .. intval-1. 396 * If we're actually running too fast, then the remainder 397 * will be some large number just under intval-1. 398 * So we need to look at whether we're running 399 * before or after the target beacon interval 400 * and if we are, modify how we do the remainder 401 * calculation. 402 */ 403 if (tsf_beacon < tsf_beacon_target) { 404 tsf_remainder = 405 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 406 } else { 407 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 408 } 409 410 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 411 __func__, 412 (unsigned long long) tsf_beacon_old, 413 (unsigned long long) tsf_beacon, 414 (unsigned long long) tsf_beacon_target, 415 (long long) tsf_delta, 416 tsf_delta_bmiss, 417 tsf_remainder); 418 419 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 420 __func__, 421 (unsigned long long) tsf_beacon, 422 (unsigned long long) nexttbtt, 423 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 424 425 if (sc->sc_syncbeacon && 426 ni == vap->iv_bss && 427 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 428 DPRINTF(sc, ATH_DEBUG_BEACON, 429 "%s: syncbeacon=1; syncing\n", 430 __func__); 431 /* 432 * Resync beacon timers using the tsf of the beacon 433 * frame we just received. 434 */ 435 ath_beacon_config(sc, vap); 436 sc->sc_syncbeacon = 0; 437 } 438 439 440 /* fall thru... */ 441 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 442 if (vap->iv_opmode == IEEE80211_M_IBSS && 443 vap->iv_state == IEEE80211_S_RUN) { 444 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 445 uint64_t tsf = ath_extend_tsf(sc, rstamp, 446 ath_hal_gettsf64(sc->sc_ah)); 447 /* 448 * Handle ibss merge as needed; check the tsf on the 449 * frame before attempting the merge. The 802.11 spec 450 * says the station should change it's bssid to match 451 * the oldest station with the same ssid, where oldest 452 * is determined by the tsf. Note that hardware 453 * reconfiguration happens through callback to 454 * ath_newstate as the state machine will go from 455 * RUN -> RUN when this happens. 456 */ 457 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 458 DPRINTF(sc, ATH_DEBUG_STATE, 459 "ibss merge, rstamp %u tsf %ju " 460 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 461 (uintmax_t)ni->ni_tstamp.tsf); 462 (void) ieee80211_ibss_merge(ni); 463 } 464 } 465 break; 466 } 467 } 468 469 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 470 static void 471 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 472 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 473 { 474 struct ath_softc *sc = ifp->if_softc; 475 476 /* Fill in the extension bitmap */ 477 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 478 479 /* Fill in the vendor header */ 480 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 481 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 482 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 483 484 /* XXX what should this be? */ 485 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 486 sc->sc_rx_th.wr_vh.vh_skip_len = 487 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 488 489 /* General version info */ 490 sc->sc_rx_th.wr_v.vh_version = 1; 491 492 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 493 494 /* rssi */ 495 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 496 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 497 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 498 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 499 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 500 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 501 502 /* evm */ 503 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 504 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 505 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 506 /* These are only populated from the AR9300 or later */ 507 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 508 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 509 510 /* direction */ 511 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 512 513 /* RX rate */ 514 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 515 516 /* RX flags */ 517 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 518 519 if (rs->rs_isaggr) 520 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 521 if (rs->rs_moreaggr) 522 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 523 524 /* phyerr info */ 525 if (rs->rs_status & HAL_RXERR_PHY) { 526 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 527 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 528 } else { 529 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 530 } 531 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 532 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 533 } 534 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 535 536 static void 537 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 538 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 539 { 540 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 541 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 542 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 543 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 544 struct ath_softc *sc = ifp->if_softc; 545 const HAL_RATE_TABLE *rt; 546 uint8_t rix; 547 548 rt = sc->sc_currates; 549 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 550 rix = rt->rateCodeToIndex[rs->rs_rate]; 551 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 552 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 553 #ifdef AH_SUPPORT_AR5416 554 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 555 if (rs->rs_status & HAL_RXERR_PHY) { 556 /* 557 * PHY error - make sure the channel flags 558 * reflect the actual channel configuration, 559 * not the received frame. 560 */ 561 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 562 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 563 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 564 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 565 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 566 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 567 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 568 struct ieee80211com *ic = ifp->if_l2com; 569 570 if ((rs->rs_flags & HAL_RX_2040) == 0) 571 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 572 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 573 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 574 else 575 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 576 if ((rs->rs_flags & HAL_RX_GI) == 0) 577 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 578 } 579 580 #endif 581 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 582 if (rs->rs_status & HAL_RXERR_CRC) 583 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 584 /* XXX propagate other error flags from descriptor */ 585 sc->sc_rx_th.wr_antnoise = nf; 586 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 587 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 588 #undef CHAN_HT 589 #undef CHAN_HT20 590 #undef CHAN_HT40U 591 #undef CHAN_HT40D 592 } 593 594 static void 595 ath_handle_micerror(struct ieee80211com *ic, 596 struct ieee80211_frame *wh, int keyix) 597 { 598 struct ieee80211_node *ni; 599 600 /* XXX recheck MIC to deal w/ chips that lie */ 601 /* XXX discard MIC errors on !data frames */ 602 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 603 if (ni != NULL) { 604 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 605 ieee80211_free_node(ni); 606 } 607 } 608 609 /* 610 * Process a single packet. 611 * 612 * The mbuf must already be synced, unmapped and removed from bf->bf_m 613 * by this stage. 614 * 615 * The mbuf must be consumed by this routine - either passed up the 616 * net80211 stack, put on the holding queue, or freed. 617 */ 618 int 619 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 620 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 621 struct mbuf *m) 622 { 623 uint64_t rstamp; 624 int len, type; 625 struct ifnet *ifp = sc->sc_ifp; 626 struct ieee80211com *ic = ifp->if_l2com; 627 struct ieee80211_node *ni; 628 int is_good = 0; 629 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 630 631 /* 632 * Calculate the correct 64 bit TSF given 633 * the TSF64 register value and rs_tstamp. 634 */ 635 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 636 637 /* These aren't specifically errors */ 638 #ifdef AH_SUPPORT_AR5416 639 if (rs->rs_flags & HAL_RX_GI) 640 sc->sc_stats.ast_rx_halfgi++; 641 if (rs->rs_flags & HAL_RX_2040) 642 sc->sc_stats.ast_rx_2040++; 643 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 644 sc->sc_stats.ast_rx_pre_crc_err++; 645 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 646 sc->sc_stats.ast_rx_post_crc_err++; 647 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 648 sc->sc_stats.ast_rx_decrypt_busy_err++; 649 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 650 sc->sc_stats.ast_rx_hi_rx_chain++; 651 if (rs->rs_flags & HAL_RX_STBC) 652 sc->sc_stats.ast_rx_stbc++; 653 #endif /* AH_SUPPORT_AR5416 */ 654 655 if (rs->rs_status != 0) { 656 if (rs->rs_status & HAL_RXERR_CRC) 657 sc->sc_stats.ast_rx_crcerr++; 658 if (rs->rs_status & HAL_RXERR_FIFO) 659 sc->sc_stats.ast_rx_fifoerr++; 660 if (rs->rs_status & HAL_RXERR_PHY) { 661 sc->sc_stats.ast_rx_phyerr++; 662 /* Process DFS radar events */ 663 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 664 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 665 /* Now pass it to the radar processing code */ 666 ath_dfs_process_phy_err(sc, m, rstamp, rs); 667 } 668 669 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 670 if (rs->rs_phyerr < 64) 671 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 672 goto rx_error; /* NB: don't count in ierrors */ 673 } 674 if (rs->rs_status & HAL_RXERR_DECRYPT) { 675 /* 676 * Decrypt error. If the error occurred 677 * because there was no hardware key, then 678 * let the frame through so the upper layers 679 * can process it. This is necessary for 5210 680 * parts which have no way to setup a ``clear'' 681 * key cache entry. 682 * 683 * XXX do key cache faulting 684 */ 685 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 686 goto rx_accept; 687 sc->sc_stats.ast_rx_badcrypt++; 688 } 689 /* 690 * Similar as above - if the failure was a keymiss 691 * just punt it up to the upper layers for now. 692 */ 693 if (rs->rs_status & HAL_RXERR_KEYMISS) { 694 sc->sc_stats.ast_rx_keymiss++; 695 goto rx_accept; 696 } 697 if (rs->rs_status & HAL_RXERR_MIC) { 698 sc->sc_stats.ast_rx_badmic++; 699 /* 700 * Do minimal work required to hand off 701 * the 802.11 header for notification. 702 */ 703 /* XXX frag's and qos frames */ 704 len = rs->rs_datalen; 705 if (len >= sizeof (struct ieee80211_frame)) { 706 ath_handle_micerror(ic, 707 mtod(m, struct ieee80211_frame *), 708 sc->sc_splitmic ? 709 rs->rs_keyix-32 : rs->rs_keyix); 710 } 711 } 712 #if defined(__DragonFly__) 713 ++ifp->if_ierrors; 714 #else 715 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 716 #endif 717 rx_error: 718 /* 719 * Cleanup any pending partial frame. 720 */ 721 if (re->m_rxpending != NULL) { 722 m_freem(re->m_rxpending); 723 re->m_rxpending = NULL; 724 } 725 /* 726 * When a tap is present pass error frames 727 * that have been requested. By default we 728 * pass decrypt+mic errors but others may be 729 * interesting (e.g. crc). 730 */ 731 if (ieee80211_radiotap_active(ic) && 732 (rs->rs_status & sc->sc_monpass)) { 733 /* NB: bpf needs the mbuf length setup */ 734 len = rs->rs_datalen; 735 m->m_pkthdr.len = m->m_len = len; 736 ath_rx_tap(ifp, m, rs, rstamp, nf); 737 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 738 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 739 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 740 ieee80211_radiotap_rx_all(ic, m); 741 } 742 /* XXX pass MIC errors up for s/w reclaculation */ 743 m_freem(m); m = NULL; 744 goto rx_next; 745 } 746 rx_accept: 747 len = rs->rs_datalen; 748 m->m_len = len; 749 750 if (rs->rs_more) { 751 /* 752 * Frame spans multiple descriptors; save 753 * it for the next completed descriptor, it 754 * will be used to construct a jumbogram. 755 */ 756 if (re->m_rxpending != NULL) { 757 /* NB: max frame size is currently 2 clusters */ 758 sc->sc_stats.ast_rx_toobig++; 759 m_freem(re->m_rxpending); 760 } 761 m->m_pkthdr.rcvif = ifp; 762 m->m_pkthdr.len = len; 763 re->m_rxpending = m; 764 m = NULL; 765 goto rx_next; 766 } else if (re->m_rxpending != NULL) { 767 /* 768 * This is the second part of a jumbogram, 769 * chain it to the first mbuf, adjust the 770 * frame length, and clear the rxpending state. 771 */ 772 re->m_rxpending->m_next = m; 773 re->m_rxpending->m_pkthdr.len += len; 774 m = re->m_rxpending; 775 re->m_rxpending = NULL; 776 } else { 777 /* 778 * Normal single-descriptor receive; setup 779 * the rcvif and packet length. 780 */ 781 m->m_pkthdr.rcvif = ifp; 782 m->m_pkthdr.len = len; 783 } 784 785 /* 786 * Validate rs->rs_antenna. 787 * 788 * Some users w/ AR9285 NICs have reported crashes 789 * here because rs_antenna field is bogusly large. 790 * Let's enforce the maximum antenna limit of 8 791 * (and it shouldn't be hard coded, but that's a 792 * separate problem) and if there's an issue, print 793 * out an error and adjust rs_antenna to something 794 * sensible. 795 * 796 * This code should be removed once the actual 797 * root cause of the issue has been identified. 798 * For example, it may be that the rs_antenna 799 * field is only valid for the lsat frame of 800 * an aggregate and it just happens that it is 801 * "mostly" right. (This is a general statement - 802 * the majority of the statistics are only valid 803 * for the last frame in an aggregate. 804 */ 805 if (rs->rs_antenna > 7) { 806 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 807 __func__, rs->rs_antenna); 808 #ifdef ATH_DEBUG 809 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 810 #endif /* ATH_DEBUG */ 811 rs->rs_antenna = 0; /* XXX better than nothing */ 812 } 813 814 /* 815 * If this is an AR9285/AR9485, then the receive and LNA 816 * configuration is stored in RSSI[2] / EXTRSSI[2]. 817 * We can extract this out to build a much better 818 * receive antenna profile. 819 * 820 * Yes, this just blurts over the above RX antenna field 821 * for now. It's fine, the AR9285 doesn't really use 822 * that. 823 * 824 * Later on we should store away the fine grained LNA 825 * information and keep separate counters just for 826 * that. It'll help when debugging the AR9285/AR9485 827 * combined diversity code. 828 */ 829 if (sc->sc_rx_lnamixer) { 830 rs->rs_antenna = 0; 831 832 /* Bits 0:1 - the LNA configuration used */ 833 rs->rs_antenna |= 834 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 835 >> HAL_RX_LNA_CFG_USED_S); 836 837 /* Bit 2 - the external RX antenna switch */ 838 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 839 rs->rs_antenna |= 0x4; 840 } 841 842 #if defined(__DragonFly__) 843 ++ifp->if_ipackets; 844 #else 845 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 846 #endif 847 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 848 849 /* 850 * Populate the rx status block. When there are bpf 851 * listeners we do the additional work to provide 852 * complete status. Otherwise we fill in only the 853 * material required by ieee80211_input. Note that 854 * noise setting is filled in above. 855 */ 856 if (ieee80211_radiotap_active(ic)) { 857 ath_rx_tap(ifp, m, rs, rstamp, nf); 858 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 859 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 860 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 861 } 862 863 /* 864 * From this point on we assume the frame is at least 865 * as large as ieee80211_frame_min; verify that. 866 */ 867 if (len < IEEE80211_MIN_LEN) { 868 if (!ieee80211_radiotap_active(ic)) { 869 DPRINTF(sc, ATH_DEBUG_RECV, 870 "%s: short packet %d\n", __func__, len); 871 sc->sc_stats.ast_rx_tooshort++; 872 } else { 873 /* NB: in particular this captures ack's */ 874 ieee80211_radiotap_rx_all(ic, m); 875 } 876 m_freem(m); m = NULL; 877 goto rx_next; 878 } 879 880 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 881 const HAL_RATE_TABLE *rt = sc->sc_currates; 882 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 883 884 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 885 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 886 } 887 888 m_adj(m, -IEEE80211_CRC_LEN); 889 890 /* 891 * Locate the node for sender, track state, and then 892 * pass the (referenced) node up to the 802.11 layer 893 * for its use. 894 */ 895 ni = ieee80211_find_rxnode_withkey(ic, 896 mtod(m, const struct ieee80211_frame_min *), 897 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 898 IEEE80211_KEYIX_NONE : rs->rs_keyix); 899 sc->sc_lastrs = rs; 900 901 #ifdef AH_SUPPORT_AR5416 902 if (rs->rs_isaggr) 903 sc->sc_stats.ast_rx_agg++; 904 #endif /* AH_SUPPORT_AR5416 */ 905 906 if (ni != NULL) { 907 /* 908 * Only punt packets for ampdu reorder processing for 909 * 11n nodes; net80211 enforces that M_AMPDU is only 910 * set for 11n nodes. 911 */ 912 if (ni->ni_flags & IEEE80211_NODE_HT) 913 m->m_flags |= M_AMPDU; 914 915 /* 916 * Sending station is known, dispatch directly. 917 */ 918 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 919 ieee80211_free_node(ni); 920 m = NULL; 921 /* 922 * Arrange to update the last rx timestamp only for 923 * frames from our ap when operating in station mode. 924 * This assumes the rx key is always setup when 925 * associated. 926 */ 927 if (ic->ic_opmode == IEEE80211_M_STA && 928 rs->rs_keyix != HAL_RXKEYIX_INVALID) 929 is_good = 1; 930 } else { 931 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 932 m = NULL; 933 } 934 935 /* 936 * At this point we have passed the frame up the stack; thus 937 * the mbuf is no longer ours. 938 */ 939 940 /* 941 * Track rx rssi and do any rx antenna management. 942 */ 943 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 944 if (sc->sc_diversity) { 945 /* 946 * When using fast diversity, change the default rx 947 * antenna if diversity chooses the other antenna 3 948 * times in a row. 949 */ 950 if (sc->sc_defant != rs->rs_antenna) { 951 if (++sc->sc_rxotherant >= 3) 952 ath_setdefantenna(sc, rs->rs_antenna); 953 } else 954 sc->sc_rxotherant = 0; 955 } 956 957 /* Handle slow diversity if enabled */ 958 if (sc->sc_dolnadiv) { 959 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 960 } 961 962 if (sc->sc_softled) { 963 /* 964 * Blink for any data frame. Otherwise do a 965 * heartbeat-style blink when idle. The latter 966 * is mainly for station mode where we depend on 967 * periodic beacon frames to trigger the poll event. 968 */ 969 if (type == IEEE80211_FC0_TYPE_DATA) { 970 const HAL_RATE_TABLE *rt = sc->sc_currates; 971 ath_led_event(sc, 972 rt->rateCodeToIndex[rs->rs_rate]); 973 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 974 ath_led_event(sc, 0); 975 } 976 rx_next: 977 /* 978 * Debugging - complain if we didn't NULL the mbuf pointer 979 * here. 980 */ 981 if (m != NULL) { 982 device_printf(sc->sc_dev, 983 "%s: mbuf %p should've been freed!\n", 984 __func__, 985 m); 986 } 987 return (is_good); 988 } 989 990 #define ATH_RX_MAX 128 991 992 /* 993 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 994 * the EDMA code does. 995 * 996 * XXX TODO: then, do all of the RX list management stuff inside 997 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 998 * code is doing it right. 999 */ 1000 static void 1001 ath_rx_proc(struct ath_softc *sc, int resched) 1002 { 1003 #define PA2DESC(_sc, _pa) \ 1004 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1005 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1006 struct ath_buf *bf; 1007 struct ifnet *ifp = sc->sc_ifp; 1008 struct ath_hal *ah = sc->sc_ah; 1009 #ifdef IEEE80211_SUPPORT_SUPERG 1010 struct ieee80211com *ic = ifp->if_l2com; 1011 #endif 1012 struct ath_desc *ds; 1013 struct ath_rx_status *rs; 1014 struct mbuf *m; 1015 int ngood; 1016 HAL_STATUS status; 1017 int16_t nf; 1018 u_int64_t tsf; 1019 int npkts = 0; 1020 int kickpcu = 0; 1021 int ret; 1022 1023 /* XXX we must not hold the ATH_LOCK here */ 1024 ATH_UNLOCK_ASSERT(sc); 1025 ATH_PCU_UNLOCK_ASSERT(sc); 1026 1027 ATH_PCU_LOCK(sc); 1028 sc->sc_rxproc_cnt++; 1029 kickpcu = sc->sc_kickpcu; 1030 ATH_PCU_UNLOCK(sc); 1031 1032 ATH_LOCK(sc); 1033 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1034 ATH_UNLOCK(sc); 1035 1036 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1037 ngood = 0; 1038 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1039 sc->sc_stats.ast_rx_noise = nf; 1040 tsf = ath_hal_gettsf64(ah); 1041 do { 1042 /* 1043 * Don't process too many packets at a time; give the 1044 * TX thread time to also run - otherwise the TX 1045 * latency can jump by quite a bit, causing throughput 1046 * degredation. 1047 */ 1048 if (!kickpcu && npkts >= ATH_RX_MAX) 1049 break; 1050 1051 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1052 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1053 if_printf(ifp, "%s: no buffer!\n", __func__); 1054 break; 1055 } else if (bf == NULL) { 1056 /* 1057 * End of List: 1058 * this can happen for non-self-linked RX chains 1059 */ 1060 sc->sc_stats.ast_rx_hitqueueend++; 1061 break; 1062 } 1063 m = bf->bf_m; 1064 if (m == NULL) { /* NB: shouldn't happen */ 1065 /* 1066 * If mbuf allocation failed previously there 1067 * will be no mbuf; try again to re-populate it. 1068 */ 1069 /* XXX make debug msg */ 1070 if_printf(ifp, "%s: no mbuf!\n", __func__); 1071 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1072 goto rx_proc_next; 1073 } 1074 ds = bf->bf_desc; 1075 if (ds->ds_link == bf->bf_daddr) { 1076 /* NB: never process the self-linked entry at the end */ 1077 sc->sc_stats.ast_rx_hitqueueend++; 1078 break; 1079 } 1080 /* XXX sync descriptor memory */ 1081 /* 1082 * Must provide the virtual address of the current 1083 * descriptor, the physical address, and the virtual 1084 * address of the next descriptor in the h/w chain. 1085 * This allows the HAL to look ahead to see if the 1086 * hardware is done with a descriptor by checking the 1087 * done bit in the following descriptor and the address 1088 * of the current descriptor the DMA engine is working 1089 * on. All this is necessary because of our use of 1090 * a self-linked list to avoid rx overruns. 1091 */ 1092 rs = &bf->bf_status.ds_rxstat; 1093 status = ath_hal_rxprocdesc(ah, ds, 1094 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1095 #ifdef ATH_DEBUG 1096 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1097 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1098 #endif 1099 1100 #ifdef ATH_DEBUG_ALQ 1101 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1102 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1103 sc->sc_rx_statuslen, (char *) ds); 1104 #endif /* ATH_DEBUG_ALQ */ 1105 1106 if (status == HAL_EINPROGRESS) 1107 break; 1108 1109 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1110 npkts++; 1111 1112 /* 1113 * Process a single frame. 1114 */ 1115 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1116 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1117 bf->bf_m = NULL; 1118 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1119 ngood++; 1120 rx_proc_next: 1121 /* 1122 * If there's a holding buffer, insert that onto 1123 * the RX list; the hardware is now definitely not pointing 1124 * to it now. 1125 */ 1126 ret = 0; 1127 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1128 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1129 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1130 bf_list); 1131 ret = ath_rxbuf_init(sc, 1132 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1133 } 1134 /* 1135 * Next, throw our buffer into the holding entry. The hardware 1136 * may use the descriptor to read the link pointer before 1137 * DMAing the next descriptor in to write out a packet. 1138 */ 1139 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1140 } while (ret == 0); 1141 1142 /* rx signal state monitoring */ 1143 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1144 if (ngood) 1145 sc->sc_lastrx = tsf; 1146 1147 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1148 /* Queue DFS tasklet if needed */ 1149 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1150 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1151 1152 /* 1153 * Now that all the RX frames were handled that 1154 * need to be handled, kick the PCU if there's 1155 * been an RXEOL condition. 1156 */ 1157 if (resched && kickpcu) { 1158 ATH_PCU_LOCK(sc); 1159 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1160 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1161 __func__, npkts); 1162 1163 /* 1164 * Go through the process of fully tearing down 1165 * the RX buffers and reinitialising them. 1166 * 1167 * There's a hardware bug that causes the RX FIFO 1168 * to get confused under certain conditions and 1169 * constantly write over the same frame, leading 1170 * the RX driver code here to get heavily confused. 1171 */ 1172 /* 1173 * XXX Has RX DMA stopped enough here to just call 1174 * ath_startrecv()? 1175 * XXX Do we need to use the holding buffer to restart 1176 * RX DMA by appending entries to the final 1177 * descriptor? Quite likely. 1178 */ 1179 #if 1 1180 ath_startrecv(sc); 1181 #else 1182 /* 1183 * Disabled for now - it'd be nice to be able to do 1184 * this in order to limit the amount of CPU time spent 1185 * reinitialising the RX side (and thus minimise RX 1186 * drops) however there's a hardware issue that 1187 * causes things to get too far out of whack. 1188 */ 1189 /* 1190 * XXX can we hold the PCU lock here? 1191 * Are there any net80211 buffer calls involved? 1192 */ 1193 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1194 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1195 ath_hal_rxena(ah); /* enable recv descriptors */ 1196 ath_mode_init(sc); /* set filters, etc. */ 1197 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1198 #endif 1199 1200 ath_hal_intrset(ah, sc->sc_imask); 1201 sc->sc_kickpcu = 0; 1202 ATH_PCU_UNLOCK(sc); 1203 } 1204 1205 /* XXX check this inside of IF_LOCK? */ 1206 #if defined(__DragonFly__) 1207 if (resched && !ifq_is_oactive(&ifp->if_snd)) { 1208 #else 1209 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1210 #endif 1211 #ifdef IEEE80211_SUPPORT_SUPERG 1212 ieee80211_ff_age_all(ic, 100); 1213 #endif 1214 #if defined(__DragonFly__) 1215 if (!ifq_is_empty(&ifp->if_snd)) 1216 ath_tx_kick(sc); 1217 #else 1218 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1219 ath_tx_kick(sc); 1220 #endif 1221 } 1222 #undef PA2DESC 1223 1224 /* 1225 * Put the hardware to sleep again if we're done with it. 1226 */ 1227 ATH_LOCK(sc); 1228 ath_power_restore_power_state(sc); 1229 ATH_UNLOCK(sc); 1230 1231 /* 1232 * If we hit the maximum number of frames in this round, 1233 * reschedule for another immediate pass. This gives 1234 * the TX and TX completion routines time to run, which 1235 * will reduce latency. 1236 */ 1237 if (npkts >= ATH_RX_MAX) 1238 sc->sc_rx.recv_sched(sc, resched); 1239 1240 ATH_PCU_LOCK(sc); 1241 sc->sc_rxproc_cnt--; 1242 ATH_PCU_UNLOCK(sc); 1243 } 1244 1245 #undef ATH_RX_MAX 1246 1247 /* 1248 * Only run the RX proc if it's not already running. 1249 * Since this may get run as part of the reset/flush path, 1250 * the task can't clash with an existing, running tasklet. 1251 */ 1252 static void 1253 ath_legacy_rx_tasklet(void *arg, int npending) 1254 { 1255 struct ath_softc *sc = arg; 1256 1257 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1258 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1259 ATH_PCU_LOCK(sc); 1260 if (sc->sc_inreset_cnt > 0) { 1261 device_printf(sc->sc_dev, 1262 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1263 ATH_PCU_UNLOCK(sc); 1264 return; 1265 } 1266 ATH_PCU_UNLOCK(sc); 1267 1268 ath_rx_proc(sc, 1); 1269 } 1270 1271 static void 1272 ath_legacy_flushrecv(struct ath_softc *sc) 1273 { 1274 1275 ath_rx_proc(sc, 0); 1276 } 1277 1278 static void 1279 ath_legacy_flush_rxpending(struct ath_softc *sc) 1280 { 1281 1282 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1283 1284 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1285 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1286 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1287 } 1288 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1289 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1290 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1291 } 1292 } 1293 1294 static int 1295 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1296 { 1297 struct ath_buf *bf; 1298 1299 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1300 /* 1301 * If there are RX holding buffers, free them here and return 1302 * them to the list. 1303 * 1304 * XXX should just verify that bf->bf_m is NULL, as it must 1305 * be at this point! 1306 */ 1307 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1308 if (bf != NULL) { 1309 if (bf->bf_m != NULL) 1310 m_freem(bf->bf_m); 1311 bf->bf_m = NULL; 1312 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1313 (void) ath_rxbuf_init(sc, bf); 1314 } 1315 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1316 1317 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1318 if (bf != NULL) { 1319 if (bf->bf_m != NULL) 1320 m_freem(bf->bf_m); 1321 bf->bf_m = NULL; 1322 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1323 (void) ath_rxbuf_init(sc, bf); 1324 } 1325 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1326 1327 return (0); 1328 } 1329 1330 /* 1331 * Disable the receive h/w in preparation for a reset. 1332 */ 1333 static void 1334 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1335 { 1336 #define PA2DESC(_sc, _pa) \ 1337 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1338 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1339 struct ath_hal *ah = sc->sc_ah; 1340 1341 ATH_RX_LOCK(sc); 1342 1343 ath_hal_stoppcurecv(ah); /* disable PCU */ 1344 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1345 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1346 /* 1347 * TODO: see if this particular DELAY() is required; it may be 1348 * masking some missing FIFO flush or DMA sync. 1349 */ 1350 #if 0 1351 if (dodelay) 1352 #endif 1353 DELAY(3000); /* 3ms is long enough for 1 frame */ 1354 #ifdef ATH_DEBUG 1355 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1356 struct ath_buf *bf; 1357 u_int ix; 1358 1359 device_printf(sc->sc_dev, 1360 "%s: rx queue %p, link %p\n", 1361 __func__, 1362 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1363 sc->sc_rxlink); 1364 ix = 0; 1365 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1366 struct ath_desc *ds = bf->bf_desc; 1367 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1368 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1369 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1370 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1371 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1372 ix++; 1373 } 1374 } 1375 #endif 1376 1377 (void) ath_legacy_flush_rxpending(sc); 1378 (void) ath_legacy_flush_rxholdbf(sc); 1379 1380 sc->sc_rxlink = NULL; /* just in case */ 1381 1382 ATH_RX_UNLOCK(sc); 1383 #undef PA2DESC 1384 } 1385 1386 /* 1387 * XXX TODO: something was calling startrecv without calling 1388 * stoprecv. Let's figure out what/why. It was showing up 1389 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1390 */ 1391 1392 /* 1393 * Enable the receive h/w following a reset. 1394 */ 1395 static int 1396 ath_legacy_startrecv(struct ath_softc *sc) 1397 { 1398 struct ath_hal *ah = sc->sc_ah; 1399 struct ath_buf *bf; 1400 1401 ATH_RX_LOCK(sc); 1402 1403 /* 1404 * XXX should verify these are already all NULL! 1405 */ 1406 sc->sc_rxlink = NULL; 1407 (void) ath_legacy_flush_rxpending(sc); 1408 (void) ath_legacy_flush_rxholdbf(sc); 1409 1410 /* 1411 * Re-chain all of the buffers in the RX buffer list. 1412 */ 1413 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1414 int error = ath_rxbuf_init(sc, bf); 1415 if (error != 0) { 1416 DPRINTF(sc, ATH_DEBUG_RECV, 1417 "%s: ath_rxbuf_init failed %d\n", 1418 __func__, error); 1419 return error; 1420 } 1421 } 1422 1423 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1424 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1425 ath_hal_rxena(ah); /* enable recv descriptors */ 1426 ath_mode_init(sc); /* set filters, etc. */ 1427 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1428 1429 ATH_RX_UNLOCK(sc); 1430 return 0; 1431 } 1432 1433 static int 1434 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1435 { 1436 int error; 1437 1438 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1439 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1440 if (error != 0) 1441 return (error); 1442 1443 return (0); 1444 } 1445 1446 static int 1447 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1448 { 1449 1450 if (sc->sc_rxdma.dd_desc_len != 0) 1451 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1452 return (0); 1453 } 1454 1455 static void 1456 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1457 { 1458 1459 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1460 } 1461 1462 static void 1463 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1464 int dosched) 1465 { 1466 1467 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1468 } 1469 1470 void 1471 ath_recv_setup_legacy(struct ath_softc *sc) 1472 { 1473 1474 /* Sensible legacy defaults */ 1475 /* 1476 * XXX this should be changed to properly support the 1477 * exact RX descriptor size for each HAL. 1478 */ 1479 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1480 1481 sc->sc_rx.recv_start = ath_legacy_startrecv; 1482 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1483 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1484 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1485 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1486 1487 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1488 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1489 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1490 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1491 } 1492