1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 32 /* 33 * Driver for the Atheros Wireless LAN controller. 34 * 35 * This software is derived from work of Atsushi Onoe; his contribution 36 * is greatly appreciated. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ath.h" 41 /* 42 * This is needed for register operations which are performed 43 * by the driver - eg, calls to ath_hal_gettsf32(). 44 * 45 * It's also required for any AH_DEBUG checks in here, eg the 46 * module dependencies. 47 */ 48 #include "opt_ah.h" 49 #include "opt_wlan.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/sysctl.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/sockio.h> 61 #include <sys/errno.h> 62 #include <sys/callout.h> 63 #include <sys/bus.h> 64 #include <sys/endian.h> 65 #include <sys/kthread.h> 66 #include <sys/taskqueue.h> 67 #include <sys/priv.h> 68 #include <sys/module.h> 69 #include <sys/ktr.h> 70 71 #include <net/if.h> 72 #include <net/if_var.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_arp.h> 77 #include <net/ethernet.h> 78 #include <net/if_llc.h> 79 #include <net/ifq_var.h> 80 81 #include <netproto/802_11/ieee80211_var.h> 82 #include <netproto/802_11/ieee80211_regdomain.h> 83 #ifdef IEEE80211_SUPPORT_SUPERG 84 #include <netproto/802_11/ieee80211_superg.h> 85 #endif 86 #ifdef IEEE80211_SUPPORT_TDMA 87 #include <netproto/802_11/ieee80211_tdma.h> 88 #endif 89 90 #include <net/bpf.h> 91 92 #ifdef INET 93 #include <netinet/in.h> 94 #include <netinet/if_ether.h> 95 #endif 96 97 #include <dev/netif/ath/ath/if_athvar.h> 98 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */ 99 #include <dev/netif/ath/ath_hal/ah_diagcodes.h> 100 101 #include <dev/netif/ath/ath/if_ath_debug.h> 102 #include <dev/netif/ath/ath/if_ath_misc.h> 103 #include <dev/netif/ath/ath/if_ath_tsf.h> 104 #include <dev/netif/ath/ath/if_ath_tx.h> 105 #include <dev/netif/ath/ath/if_ath_sysctl.h> 106 #include <dev/netif/ath/ath/if_ath_led.h> 107 #include <dev/netif/ath/ath/if_ath_keycache.h> 108 #include <dev/netif/ath/ath/if_ath_rx.h> 109 #include <dev/netif/ath/ath/if_ath_beacon.h> 110 #include <dev/netif/ath/ath/if_athdfs.h> 111 112 #ifdef ATH_TX99_DIAG 113 #include <dev/netif/ath/ath_tx99/ath_tx99.h> 114 #endif 115 116 #ifdef ATH_DEBUG_ALQ 117 #include <dev/netif/ath/ath/if_ath_alq.h> 118 #endif 119 120 #include <dev/netif/ath/ath/if_ath_lna_div.h> 121 122 /* 123 * Calculate the receive filter according to the 124 * operating mode and state: 125 * 126 * o always accept unicast, broadcast, and multicast traffic 127 * o accept PHY error frames when hardware doesn't have MIB support 128 * to count and we need them for ANI (sta mode only until recently) 129 * and we are not scanning (ANI is disabled) 130 * NB: older hal's add rx filter bits out of sight and we need to 131 * blindly preserve them 132 * o probe request frames are accepted only when operating in 133 * hostap, adhoc, mesh, or monitor modes 134 * o enable promiscuous mode 135 * - when in monitor mode 136 * - if interface marked PROMISC (assumes bridge setting is filtered) 137 * o accept beacons: 138 * - when operating in station mode for collecting rssi data when 139 * the station is otherwise quiet, or 140 * - when operating in adhoc mode so the 802.11 layer creates 141 * node table entries for peers, 142 * - when scanning 143 * - when doing s/w beacon miss (e.g. for ap+sta) 144 * - when operating in ap mode in 11g to detect overlapping bss that 145 * require protection 146 * - when operating in mesh mode to detect neighbors 147 * o accept control frames: 148 * - when in monitor mode 149 * XXX HT protection for 11n 150 */ 151 u_int32_t 152 ath_calcrxfilter(struct ath_softc *sc) 153 { 154 struct ifnet *ifp = sc->sc_ifp; 155 struct ieee80211com *ic = ifp->if_l2com; 156 u_int32_t rfilt; 157 158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 159 if (!sc->sc_needmib && !sc->sc_scanning) 160 rfilt |= HAL_RX_FILTER_PHYERR; 161 if (ic->ic_opmode != IEEE80211_M_STA) 162 rfilt |= HAL_RX_FILTER_PROBEREQ; 163 /* XXX ic->ic_monvaps != 0? */ 164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 165 rfilt |= HAL_RX_FILTER_PROM; 166 167 /* 168 * Only listen to all beacons if we're scanning. 169 * 170 * Otherwise we only really need to hear beacons from 171 * our own BSSID. 172 */ 173 if (ic->ic_opmode == IEEE80211_M_STA || 174 ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 175 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 176 rfilt |= HAL_RX_FILTER_MYBEACON; 177 } else { /* scanning, non-mybeacon chips */ 178 rfilt |= HAL_RX_FILTER_BEACON; 179 } 180 } 181 182 /* 183 * NB: We don't recalculate the rx filter when 184 * ic_protmode changes; otherwise we could do 185 * this only when ic_protmode != NONE. 186 */ 187 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 188 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 189 rfilt |= HAL_RX_FILTER_BEACON; 190 191 /* 192 * Enable hardware PS-POLL RX only for hostap mode; 193 * STA mode sends PS-POLL frames but never 194 * receives them. 195 */ 196 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 197 0, NULL) == HAL_OK && 198 ic->ic_opmode == IEEE80211_M_HOSTAP) 199 rfilt |= HAL_RX_FILTER_PSPOLL; 200 201 if (sc->sc_nmeshvaps) { 202 rfilt |= HAL_RX_FILTER_BEACON; 203 if (sc->sc_hasbmatch) 204 rfilt |= HAL_RX_FILTER_BSSID; 205 else 206 rfilt |= HAL_RX_FILTER_PROM; 207 } 208 if (ic->ic_opmode == IEEE80211_M_MONITOR) 209 rfilt |= HAL_RX_FILTER_CONTROL; 210 211 /* 212 * Enable RX of compressed BAR frames only when doing 213 * 802.11n. Required for A-MPDU. 214 */ 215 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 216 rfilt |= HAL_RX_FILTER_COMPBAR; 217 218 /* 219 * Enable radar PHY errors if requested by the 220 * DFS module. 221 */ 222 if (sc->sc_dodfs) 223 rfilt |= HAL_RX_FILTER_PHYRADAR; 224 225 /* 226 * Enable spectral PHY errors if requested by the 227 * spectral module. 228 */ 229 if (sc->sc_dospectral) 230 rfilt |= HAL_RX_FILTER_PHYRADAR; 231 232 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 233 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 234 return rfilt; 235 } 236 237 static int 238 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 239 { 240 struct ath_hal *ah = sc->sc_ah; 241 int error; 242 struct mbuf *m; 243 struct ath_desc *ds; 244 245 m = bf->bf_m; 246 if (m == NULL) { 247 /* 248 * NB: by assigning a page to the rx dma buffer we 249 * implicitly satisfy the Atheros requirement that 250 * this buffer be cache-line-aligned and sized to be 251 * multiple of the cache line size. Not doing this 252 * causes weird stuff to happen (for the 5210 at least). 253 */ 254 m = m_getcl(MB_WAIT, MT_DATA, M_PKTHDR); 255 if (m == NULL) { 256 DPRINTF(sc, ATH_DEBUG_ANY, 257 "%s: no mbuf/cluster\n", __func__); 258 sc->sc_stats.ast_rx_nombuf++; 259 return ENOMEM; 260 } 261 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 262 263 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 264 bf->bf_dmamap, m, 265 bf->bf_segs, 1, &bf->bf_nseg, 266 BUS_DMA_NOWAIT); 267 if (error != 0) { 268 DPRINTF(sc, ATH_DEBUG_ANY, 269 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 270 __func__, error); 271 sc->sc_stats.ast_rx_busdma++; 272 m_freem(m); 273 return error; 274 } 275 KASSERT(bf->bf_nseg == 1, 276 ("multi-segment packet; nseg %u", bf->bf_nseg)); 277 bf->bf_m = m; 278 } 279 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 280 281 /* 282 * Setup descriptors. For receive we always terminate 283 * the descriptor list with a self-linked entry so we'll 284 * not get overrun under high load (as can happen with a 285 * 5212 when ANI processing enables PHY error frames). 286 * 287 * To insure the last descriptor is self-linked we create 288 * each descriptor as self-linked and add it to the end. As 289 * each additional descriptor is added the previous self-linked 290 * entry is ``fixed'' naturally. This should be safe even 291 * if DMA is happening. When processing RX interrupts we 292 * never remove/process the last, self-linked, entry on the 293 * descriptor list. This insures the hardware always has 294 * someplace to write a new frame. 295 */ 296 /* 297 * 11N: we can no longer afford to self link the last descriptor. 298 * MAC acknowledges BA status as long as it copies frames to host 299 * buffer (or rx fifo). This can incorrectly acknowledge packets 300 * to a sender if last desc is self-linked. 301 */ 302 ds = bf->bf_desc; 303 if (sc->sc_rxslink) 304 ds->ds_link = bf->bf_daddr; /* link to self */ 305 else 306 ds->ds_link = 0; /* terminate the list */ 307 ds->ds_data = bf->bf_segs[0].ds_addr; 308 ath_hal_setuprxdesc(ah, ds 309 , m->m_len /* buffer size */ 310 , 0 311 ); 312 313 if (sc->sc_rxlink != NULL) 314 *sc->sc_rxlink = bf->bf_daddr; 315 sc->sc_rxlink = &ds->ds_link; 316 return 0; 317 } 318 319 /* 320 * Intercept management frames to collect beacon rssi data 321 * and to do ibss merges. 322 */ 323 void 324 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 325 int subtype, int rssi, int nf) 326 { 327 struct ieee80211vap *vap = ni->ni_vap; 328 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 329 uint64_t tsf_beacon_old, tsf_beacon; 330 uint64_t nexttbtt; 331 int64_t tsf_delta; 332 int32_t tsf_delta_bmiss; 333 int32_t tsf_remainder; 334 uint64_t tsf_beacon_target; 335 int tsf_intval; 336 337 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 338 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data); 339 340 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 341 tsf_intval = 1; 342 if (ni != NULL && ni->ni_intval > 0) { 343 tsf_intval = TU_TO_TSF(ni->ni_intval); 344 } 345 #undef TU_TO_TSF 346 347 /* 348 * Call up first so subsequent work can use information 349 * potentially stored in the node (e.g. for ibss merge). 350 */ 351 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 352 switch (subtype) { 353 case IEEE80211_FC0_SUBTYPE_BEACON: 354 /* update rssi statistics for use by the hal */ 355 /* XXX unlocked check against vap->iv_bss? */ 356 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 357 358 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32; 359 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data); 360 361 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 362 363 /* 364 * Let's calculate the delta and remainder, so we can see 365 * if the beacon timer from the AP is varying by more than 366 * a few TU. (Which would be a huge, huge problem.) 367 */ 368 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 369 370 tsf_delta_bmiss = tsf_delta / tsf_intval; 371 372 /* 373 * If our delta is greater than half the beacon interval, 374 * let's round the bmiss value up to the next beacon 375 * interval. Ie, we're running really, really early 376 * on the next beacon. 377 */ 378 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 379 tsf_delta_bmiss ++; 380 381 tsf_beacon_target = tsf_beacon_old + 382 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 383 384 /* 385 * The remainder using '%' is between 0 .. intval-1. 386 * If we're actually running too fast, then the remainder 387 * will be some large number just under intval-1. 388 * So we need to look at whether we're running 389 * before or after the target beacon interval 390 * and if we are, modify how we do the remainder 391 * calculation. 392 */ 393 if (tsf_beacon < tsf_beacon_target) { 394 tsf_remainder = 395 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 396 } else { 397 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 398 } 399 400 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 401 __func__, 402 (unsigned long long) tsf_beacon_old, 403 (unsigned long long) tsf_beacon, 404 (unsigned long long) tsf_beacon_target, 405 (long long) tsf_delta, 406 tsf_delta_bmiss, 407 tsf_remainder); 408 409 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 410 __func__, 411 (unsigned long long) tsf_beacon, 412 (unsigned long long) nexttbtt, 413 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 414 415 if (sc->sc_syncbeacon && 416 ni == vap->iv_bss && 417 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 418 DPRINTF(sc, ATH_DEBUG_BEACON, 419 "%s: syncbeacon=1; syncing\n", 420 __func__); 421 /* 422 * Resync beacon timers using the tsf of the beacon 423 * frame we just received. 424 */ 425 ath_beacon_config(sc, vap); 426 sc->sc_syncbeacon = 0; 427 } 428 429 430 /* fall thru... */ 431 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 432 if (vap->iv_opmode == IEEE80211_M_IBSS && 433 vap->iv_state == IEEE80211_S_RUN) { 434 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 435 uint64_t tsf = ath_extend_tsf(sc, rstamp, 436 ath_hal_gettsf64(sc->sc_ah)); 437 /* 438 * Handle ibss merge as needed; check the tsf on the 439 * frame before attempting the merge. The 802.11 spec 440 * says the station should change it's bssid to match 441 * the oldest station with the same ssid, where oldest 442 * is determined by the tsf. Note that hardware 443 * reconfiguration happens through callback to 444 * ath_newstate as the state machine will go from 445 * RUN -> RUN when this happens. 446 */ 447 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 448 DPRINTF(sc, ATH_DEBUG_STATE, 449 "ibss merge, rstamp %u tsf %ju " 450 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 451 (uintmax_t)ni->ni_tstamp.tsf); 452 (void) ieee80211_ibss_merge(ni); 453 } 454 } 455 break; 456 } 457 } 458 459 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 460 static void 461 ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 462 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 463 { 464 struct ath_softc *sc = ifp->if_softc; 465 466 /* Fill in the extension bitmap */ 467 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 468 469 /* Fill in the vendor header */ 470 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 471 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 472 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 473 474 /* XXX what should this be? */ 475 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 476 sc->sc_rx_th.wr_vh.vh_skip_len = 477 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 478 479 /* General version info */ 480 sc->sc_rx_th.wr_v.vh_version = 1; 481 482 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 483 484 /* rssi */ 485 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 486 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 487 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 488 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 489 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 490 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 491 492 /* evm */ 493 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 494 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 495 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 496 /* These are only populated from the AR9300 or later */ 497 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 498 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 499 500 /* direction */ 501 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 502 503 /* RX rate */ 504 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 505 506 /* RX flags */ 507 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 508 509 if (rs->rs_isaggr) 510 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 511 if (rs->rs_moreaggr) 512 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 513 514 /* phyerr info */ 515 if (rs->rs_status & HAL_RXERR_PHY) { 516 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 517 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 518 } else { 519 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 520 } 521 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 522 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 523 } 524 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 525 526 static void 527 ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 528 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 529 { 530 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 531 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 532 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 533 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 534 struct ath_softc *sc = ifp->if_softc; 535 const HAL_RATE_TABLE *rt; 536 uint8_t rix; 537 538 rt = sc->sc_currates; 539 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 540 rix = rt->rateCodeToIndex[rs->rs_rate]; 541 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 542 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 543 #ifdef AH_SUPPORT_AR5416 544 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 545 if (rs->rs_status & HAL_RXERR_PHY) { 546 /* 547 * PHY error - make sure the channel flags 548 * reflect the actual channel configuration, 549 * not the received frame. 550 */ 551 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 552 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 553 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 554 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 555 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 556 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 557 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 558 struct ieee80211com *ic = ifp->if_l2com; 559 560 if ((rs->rs_flags & HAL_RX_2040) == 0) 561 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 562 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 563 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 564 else 565 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 566 if ((rs->rs_flags & HAL_RX_GI) == 0) 567 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 568 } 569 570 #endif 571 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 572 if (rs->rs_status & HAL_RXERR_CRC) 573 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 574 /* XXX propagate other error flags from descriptor */ 575 sc->sc_rx_th.wr_antnoise = nf; 576 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 577 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 578 #undef CHAN_HT 579 #undef CHAN_HT20 580 #undef CHAN_HT40U 581 #undef CHAN_HT40D 582 } 583 584 static void 585 ath_handle_micerror(struct ieee80211com *ic, 586 struct ieee80211_frame *wh, int keyix) 587 { 588 struct ieee80211_node *ni; 589 590 /* XXX recheck MIC to deal w/ chips that lie */ 591 /* XXX discard MIC errors on !data frames */ 592 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 593 if (ni != NULL) { 594 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 595 ieee80211_free_node(ni); 596 } 597 } 598 599 /* 600 * Process a single packet. 601 * 602 * The mbuf must already be synced, unmapped and removed from bf->bf_m 603 * by this stage. 604 * 605 * The mbuf must be consumed by this routine - either passed up the 606 * net80211 stack, put on the holding queue, or freed. 607 */ 608 int 609 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 610 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 611 struct mbuf *m) 612 { 613 uint64_t rstamp; 614 int len, type; 615 struct ifnet *ifp = sc->sc_ifp; 616 struct ieee80211com *ic = ifp->if_l2com; 617 struct ieee80211_node *ni; 618 int is_good = 0; 619 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 620 621 /* 622 * Calculate the correct 64 bit TSF given 623 * the TSF64 register value and rs_tstamp. 624 */ 625 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 626 627 /* These aren't specifically errors */ 628 #ifdef AH_SUPPORT_AR5416 629 if (rs->rs_flags & HAL_RX_GI) 630 sc->sc_stats.ast_rx_halfgi++; 631 if (rs->rs_flags & HAL_RX_2040) 632 sc->sc_stats.ast_rx_2040++; 633 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 634 sc->sc_stats.ast_rx_pre_crc_err++; 635 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 636 sc->sc_stats.ast_rx_post_crc_err++; 637 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 638 sc->sc_stats.ast_rx_decrypt_busy_err++; 639 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 640 sc->sc_stats.ast_rx_hi_rx_chain++; 641 if (rs->rs_flags & HAL_RX_STBC) 642 sc->sc_stats.ast_rx_stbc++; 643 #endif /* AH_SUPPORT_AR5416 */ 644 645 if (rs->rs_status != 0) { 646 if (rs->rs_status & HAL_RXERR_CRC) 647 sc->sc_stats.ast_rx_crcerr++; 648 if (rs->rs_status & HAL_RXERR_FIFO) 649 sc->sc_stats.ast_rx_fifoerr++; 650 if (rs->rs_status & HAL_RXERR_PHY) { 651 sc->sc_stats.ast_rx_phyerr++; 652 /* Process DFS radar events */ 653 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 654 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 655 /* Now pass it to the radar processing code */ 656 ath_dfs_process_phy_err(sc, m, rstamp, rs); 657 } 658 659 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 660 if (rs->rs_phyerr < 64) 661 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 662 goto rx_error; /* NB: don't count in ierrors */ 663 } 664 if (rs->rs_status & HAL_RXERR_DECRYPT) { 665 /* 666 * Decrypt error. If the error occurred 667 * because there was no hardware key, then 668 * let the frame through so the upper layers 669 * can process it. This is necessary for 5210 670 * parts which have no way to setup a ``clear'' 671 * key cache entry. 672 * 673 * XXX do key cache faulting 674 */ 675 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 676 goto rx_accept; 677 sc->sc_stats.ast_rx_badcrypt++; 678 } 679 /* 680 * Similar as above - if the failure was a keymiss 681 * just punt it up to the upper layers for now. 682 */ 683 if (rs->rs_status & HAL_RXERR_KEYMISS) { 684 sc->sc_stats.ast_rx_keymiss++; 685 goto rx_accept; 686 } 687 if (rs->rs_status & HAL_RXERR_MIC) { 688 sc->sc_stats.ast_rx_badmic++; 689 /* 690 * Do minimal work required to hand off 691 * the 802.11 header for notification. 692 */ 693 /* XXX frag's and qos frames */ 694 len = rs->rs_datalen; 695 if (len >= sizeof (struct ieee80211_frame)) { 696 ath_handle_micerror(ic, 697 mtod(m, struct ieee80211_frame *), 698 sc->sc_splitmic ? 699 rs->rs_keyix-32 : rs->rs_keyix); 700 } 701 } 702 ifp->if_ierrors++; 703 rx_error: 704 /* 705 * Cleanup any pending partial frame. 706 */ 707 if (re->m_rxpending != NULL) { 708 m_freem(re->m_rxpending); 709 re->m_rxpending = NULL; 710 } 711 /* 712 * When a tap is present pass error frames 713 * that have been requested. By default we 714 * pass decrypt+mic errors but others may be 715 * interesting (e.g. crc). 716 */ 717 if (ieee80211_radiotap_active(ic) && 718 (rs->rs_status & sc->sc_monpass)) { 719 /* NB: bpf needs the mbuf length setup */ 720 len = rs->rs_datalen; 721 m->m_pkthdr.len = m->m_len = len; 722 ath_rx_tap(ifp, m, rs, rstamp, nf); 723 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 724 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 725 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 726 ieee80211_radiotap_rx_all(ic, m); 727 } 728 /* XXX pass MIC errors up for s/w reclaculation */ 729 m_freem(m); m = NULL; 730 goto rx_next; 731 } 732 rx_accept: 733 len = rs->rs_datalen; 734 m->m_len = len; 735 736 if (rs->rs_more) { 737 /* 738 * Frame spans multiple descriptors; save 739 * it for the next completed descriptor, it 740 * will be used to construct a jumbogram. 741 */ 742 if (re->m_rxpending != NULL) { 743 /* NB: max frame size is currently 2 clusters */ 744 sc->sc_stats.ast_rx_toobig++; 745 m_freem(re->m_rxpending); 746 } 747 m->m_pkthdr.rcvif = ifp; 748 m->m_pkthdr.len = len; 749 re->m_rxpending = m; 750 m = NULL; 751 goto rx_next; 752 } else if (re->m_rxpending != NULL) { 753 /* 754 * This is the second part of a jumbogram, 755 * chain it to the first mbuf, adjust the 756 * frame length, and clear the rxpending state. 757 */ 758 re->m_rxpending->m_next = m; 759 re->m_rxpending->m_pkthdr.len += len; 760 m = re->m_rxpending; 761 re->m_rxpending = NULL; 762 } else { 763 /* 764 * Normal single-descriptor receive; setup 765 * the rcvif and packet length. 766 */ 767 m->m_pkthdr.rcvif = ifp; 768 m->m_pkthdr.len = len; 769 } 770 771 /* 772 * Validate rs->rs_antenna. 773 * 774 * Some users w/ AR9285 NICs have reported crashes 775 * here because rs_antenna field is bogusly large. 776 * Let's enforce the maximum antenna limit of 8 777 * (and it shouldn't be hard coded, but that's a 778 * separate problem) and if there's an issue, print 779 * out an error and adjust rs_antenna to something 780 * sensible. 781 * 782 * This code should be removed once the actual 783 * root cause of the issue has been identified. 784 * For example, it may be that the rs_antenna 785 * field is only valid for the lsat frame of 786 * an aggregate and it just happens that it is 787 * "mostly" right. (This is a general statement - 788 * the majority of the statistics are only valid 789 * for the last frame in an aggregate. 790 */ 791 if (rs->rs_antenna > 7) { 792 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 793 __func__, rs->rs_antenna); 794 #ifdef ATH_DEBUG 795 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 796 #endif /* ATH_DEBUG */ 797 rs->rs_antenna = 0; /* XXX better than nothing */ 798 } 799 800 /* 801 * If this is an AR9285/AR9485, then the receive and LNA 802 * configuration is stored in RSSI[2] / EXTRSSI[2]. 803 * We can extract this out to build a much better 804 * receive antenna profile. 805 * 806 * Yes, this just blurts over the above RX antenna field 807 * for now. It's fine, the AR9285 doesn't really use 808 * that. 809 * 810 * Later on we should store away the fine grained LNA 811 * information and keep separate counters just for 812 * that. It'll help when debugging the AR9285/AR9485 813 * combined diversity code. 814 */ 815 if (sc->sc_rx_lnamixer) { 816 rs->rs_antenna = 0; 817 818 /* Bits 0:1 - the LNA configuration used */ 819 rs->rs_antenna |= 820 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 821 >> HAL_RX_LNA_CFG_USED_S); 822 823 /* Bit 2 - the external RX antenna switch */ 824 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 825 rs->rs_antenna |= 0x4; 826 } 827 828 ifp->if_ipackets++; 829 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 830 831 /* 832 * Populate the rx status block. When there are bpf 833 * listeners we do the additional work to provide 834 * complete status. Otherwise we fill in only the 835 * material required by ieee80211_input. Note that 836 * noise setting is filled in above. 837 */ 838 if (ieee80211_radiotap_active(ic)) { 839 ath_rx_tap(ifp, m, rs, rstamp, nf); 840 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 841 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 842 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 843 } 844 845 /* 846 * From this point on we assume the frame is at least 847 * as large as ieee80211_frame_min; verify that. 848 */ 849 if (len < IEEE80211_MIN_LEN) { 850 if (!ieee80211_radiotap_active(ic)) { 851 DPRINTF(sc, ATH_DEBUG_RECV, 852 "%s: short packet %d\n", __func__, len); 853 sc->sc_stats.ast_rx_tooshort++; 854 } else { 855 /* NB: in particular this captures ack's */ 856 ieee80211_radiotap_rx_all(ic, m); 857 } 858 m_freem(m); m = NULL; 859 goto rx_next; 860 } 861 862 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 863 const HAL_RATE_TABLE *rt = sc->sc_currates; 864 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 865 866 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 867 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 868 } 869 870 m_adj(m, -IEEE80211_CRC_LEN); 871 872 /* 873 * Locate the node for sender, track state, and then 874 * pass the (referenced) node up to the 802.11 layer 875 * for its use. 876 */ 877 ni = ieee80211_find_rxnode_withkey(ic, 878 mtod(m, const struct ieee80211_frame_min *), 879 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 880 IEEE80211_KEYIX_NONE : rs->rs_keyix); 881 sc->sc_lastrs = rs; 882 883 #ifdef AH_SUPPORT_AR5416 884 if (rs->rs_isaggr) 885 sc->sc_stats.ast_rx_agg++; 886 #endif /* AH_SUPPORT_AR5416 */ 887 888 if (ni != NULL) { 889 /* 890 * Only punt packets for ampdu reorder processing for 891 * 11n nodes; net80211 enforces that M_AMPDU is only 892 * set for 11n nodes. 893 */ 894 if (ni->ni_flags & IEEE80211_NODE_HT) 895 m->m_flags |= M_AMPDU; 896 897 /* 898 * Sending station is known, dispatch directly. 899 */ 900 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 901 ieee80211_free_node(ni); 902 m = NULL; 903 /* 904 * Arrange to update the last rx timestamp only for 905 * frames from our ap when operating in station mode. 906 * This assumes the rx key is always setup when 907 * associated. 908 */ 909 if (ic->ic_opmode == IEEE80211_M_STA && 910 rs->rs_keyix != HAL_RXKEYIX_INVALID) 911 is_good = 1; 912 } else { 913 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 914 m = NULL; 915 } 916 917 /* 918 * At this point we have passed the frame up the stack; thus 919 * the mbuf is no longer ours. 920 */ 921 922 /* 923 * Track rx rssi and do any rx antenna management. 924 */ 925 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 926 if (sc->sc_diversity) { 927 /* 928 * When using fast diversity, change the default rx 929 * antenna if diversity chooses the other antenna 3 930 * times in a row. 931 */ 932 if (sc->sc_defant != rs->rs_antenna) { 933 if (++sc->sc_rxotherant >= 3) 934 ath_setdefantenna(sc, rs->rs_antenna); 935 } else 936 sc->sc_rxotherant = 0; 937 } 938 939 /* Handle slow diversity if enabled */ 940 if (sc->sc_dolnadiv) { 941 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 942 } 943 944 if (sc->sc_softled) { 945 /* 946 * Blink for any data frame. Otherwise do a 947 * heartbeat-style blink when idle. The latter 948 * is mainly for station mode where we depend on 949 * periodic beacon frames to trigger the poll event. 950 */ 951 if (type == IEEE80211_FC0_TYPE_DATA) { 952 const HAL_RATE_TABLE *rt = sc->sc_currates; 953 ath_led_event(sc, 954 rt->rateCodeToIndex[rs->rs_rate]); 955 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 956 ath_led_event(sc, 0); 957 } 958 rx_next: 959 /* 960 * Debugging - complain if we didn't NULL the mbuf pointer 961 * here. 962 */ 963 if (m != NULL) { 964 device_printf(sc->sc_dev, 965 "%s: mbuf %p should've been freed!\n", 966 __func__, 967 m); 968 } 969 return (is_good); 970 } 971 972 #define ATH_RX_MAX 128 973 974 static void 975 ath_rx_proc(struct ath_softc *sc, int resched) 976 { 977 #define PA2DESC(_sc, _pa) \ 978 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 979 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 980 struct ath_buf *bf; 981 struct ifnet *ifp = sc->sc_ifp; 982 struct ath_hal *ah = sc->sc_ah; 983 #ifdef IEEE80211_SUPPORT_SUPERG 984 struct ieee80211com *ic = ifp->if_l2com; 985 #endif 986 struct ath_desc *ds; 987 struct ath_rx_status *rs; 988 struct mbuf *m; 989 int ngood; 990 HAL_STATUS status; 991 int16_t nf; 992 u_int64_t tsf; 993 int npkts = 0; 994 int kickpcu = 0; 995 996 /* XXX we must not hold the ATH_LOCK here */ 997 ATH_UNLOCK_ASSERT(sc); 998 ATH_PCU_UNLOCK_ASSERT(sc); 999 1000 ATH_PCU_LOCK(sc); 1001 sc->sc_rxproc_cnt++; 1002 kickpcu = sc->sc_kickpcu; 1003 ATH_PCU_UNLOCK(sc); 1004 1005 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1006 1007 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1008 ngood = 0; 1009 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1010 sc->sc_stats.ast_rx_noise = nf; 1011 tsf = ath_hal_gettsf64(ah); 1012 do { 1013 /* 1014 * Don't process too many packets at a time; give the 1015 * TX thread time to also run - otherwise the TX 1016 * latency can jump by quite a bit, causing throughput 1017 * degredation. 1018 */ 1019 if (!kickpcu && npkts >= ATH_RX_MAX) 1020 break; 1021 1022 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1023 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1024 if_printf(ifp, "%s: no buffer!\n", __func__); 1025 break; 1026 } else if (bf == NULL) { 1027 /* 1028 * End of List: 1029 * this can happen for non-self-linked RX chains 1030 */ 1031 sc->sc_stats.ast_rx_hitqueueend++; 1032 break; 1033 } 1034 m = bf->bf_m; 1035 if (m == NULL) { /* NB: shouldn't happen */ 1036 /* 1037 * If mbuf allocation failed previously there 1038 * will be no mbuf; try again to re-populate it. 1039 */ 1040 /* XXX make debug msg */ 1041 if_printf(ifp, "%s: no mbuf!\n", __func__); 1042 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1043 goto rx_proc_next; 1044 } 1045 ds = bf->bf_desc; 1046 if (ds->ds_link == bf->bf_daddr) { 1047 /* NB: never process the self-linked entry at the end */ 1048 sc->sc_stats.ast_rx_hitqueueend++; 1049 break; 1050 } 1051 /* XXX sync descriptor memory */ 1052 /* 1053 * Must provide the virtual address of the current 1054 * descriptor, the physical address, and the virtual 1055 * address of the next descriptor in the h/w chain. 1056 * This allows the HAL to look ahead to see if the 1057 * hardware is done with a descriptor by checking the 1058 * done bit in the following descriptor and the address 1059 * of the current descriptor the DMA engine is working 1060 * on. All this is necessary because of our use of 1061 * a self-linked list to avoid rx overruns. 1062 */ 1063 rs = &bf->bf_status.ds_rxstat; 1064 status = ath_hal_rxprocdesc(ah, ds, 1065 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1066 #ifdef ATH_DEBUG 1067 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1068 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1069 #endif 1070 1071 #ifdef ATH_DEBUG_ALQ 1072 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1073 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1074 sc->sc_rx_statuslen, (char *) ds); 1075 #endif /* ATH_DEBUG_ALQ */ 1076 1077 if (status == HAL_EINPROGRESS) 1078 break; 1079 1080 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1081 npkts++; 1082 1083 /* 1084 * Process a single frame. 1085 */ 1086 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1087 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1088 bf->bf_m = NULL; 1089 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1090 ngood++; 1091 rx_proc_next: 1092 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1093 } while (ath_rxbuf_init(sc, bf) == 0); 1094 1095 /* rx signal state monitoring */ 1096 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1097 if (ngood) 1098 sc->sc_lastrx = tsf; 1099 1100 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1101 /* Queue DFS tasklet if needed */ 1102 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1103 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1104 1105 /* 1106 * Now that all the RX frames were handled that 1107 * need to be handled, kick the PCU if there's 1108 * been an RXEOL condition. 1109 */ 1110 if (resched && kickpcu) { 1111 ATH_PCU_LOCK(sc); 1112 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1113 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1114 __func__, npkts); 1115 1116 /* 1117 * Go through the process of fully tearing down 1118 * the RX buffers and reinitialising them. 1119 * 1120 * There's a hardware bug that causes the RX FIFO 1121 * to get confused under certain conditions and 1122 * constantly write over the same frame, leading 1123 * the RX driver code here to get heavily confused. 1124 */ 1125 #if 1 1126 ath_startrecv(sc); 1127 #else 1128 /* 1129 * Disabled for now - it'd be nice to be able to do 1130 * this in order to limit the amount of CPU time spent 1131 * reinitialising the RX side (and thus minimise RX 1132 * drops) however there's a hardware issue that 1133 * causes things to get too far out of whack. 1134 */ 1135 /* 1136 * XXX can we hold the PCU lock here? 1137 * Are there any net80211 buffer calls involved? 1138 */ 1139 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1140 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1141 ath_hal_rxena(ah); /* enable recv descriptors */ 1142 ath_mode_init(sc); /* set filters, etc. */ 1143 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1144 #endif 1145 1146 ath_hal_intrset(ah, sc->sc_imask); 1147 sc->sc_kickpcu = 0; 1148 ATH_PCU_UNLOCK(sc); 1149 } 1150 1151 /* XXX check this inside of IF_LOCK? */ 1152 if (resched && !ifq_is_oactive(&ifp->if_snd)) { 1153 #ifdef IEEE80211_SUPPORT_SUPERG 1154 ieee80211_ff_age_all(ic, 100); 1155 #endif 1156 if (!ifq_is_empty(&ifp->if_snd)) 1157 ath_tx_kick(sc); 1158 } 1159 #undef PA2DESC 1160 1161 /* 1162 * Put the hardware to sleep again if we're done with it. 1163 */ 1164 ath_power_restore_power_state(sc); 1165 1166 /* 1167 * If we hit the maximum number of frames in this round, 1168 * reschedule for another immediate pass. This gives 1169 * the TX and TX completion routines time to run, which 1170 * will reduce latency. 1171 */ 1172 if (npkts >= ATH_RX_MAX) 1173 sc->sc_rx.recv_sched(sc, resched); 1174 1175 ATH_PCU_LOCK(sc); 1176 sc->sc_rxproc_cnt--; 1177 ATH_PCU_UNLOCK(sc); 1178 } 1179 1180 #undef ATH_RX_MAX 1181 1182 /* 1183 * Only run the RX proc if it's not already running. 1184 * Since this may get run as part of the reset/flush path, 1185 * the task can't clash with an existing, running tasklet. 1186 */ 1187 static void 1188 ath_legacy_rx_tasklet(void *arg, int npending) 1189 { 1190 struct ath_softc *sc = arg; 1191 1192 wlan_serialize_enter(); 1193 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1194 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1195 ATH_PCU_LOCK(sc); 1196 if (sc->sc_inreset_cnt > 0) { 1197 device_printf(sc->sc_dev, 1198 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1199 ATH_PCU_UNLOCK(sc); 1200 wlan_serialize_exit(); 1201 return; 1202 } 1203 ATH_PCU_UNLOCK(sc); 1204 1205 ath_rx_proc(sc, 1); 1206 wlan_serialize_exit(); 1207 } 1208 1209 static void 1210 ath_legacy_flushrecv(struct ath_softc *sc) 1211 { 1212 1213 ath_rx_proc(sc, 0); 1214 } 1215 1216 /* 1217 * Disable the receive h/w in preparation for a reset. 1218 */ 1219 static void 1220 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1221 { 1222 #define PA2DESC(_sc, _pa) \ 1223 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1224 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1225 struct ath_hal *ah = sc->sc_ah; 1226 1227 ath_hal_stoppcurecv(ah); /* disable PCU */ 1228 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1229 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1230 /* 1231 * TODO: see if this particular DELAY() is required; it may be 1232 * masking some missing FIFO flush or DMA sync. 1233 */ 1234 #if 0 1235 if (dodelay) 1236 #endif 1237 DELAY(3000); /* 3ms is long enough for 1 frame */ 1238 #ifdef ATH_DEBUG 1239 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1240 struct ath_buf *bf; 1241 u_int ix; 1242 1243 device_printf(sc->sc_dev, 1244 "%s: rx queue %p, link %p\n", 1245 __func__, 1246 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1247 sc->sc_rxlink); 1248 ix = 0; 1249 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1250 struct ath_desc *ds = bf->bf_desc; 1251 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1252 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1253 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1254 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1255 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1256 ix++; 1257 } 1258 } 1259 #endif 1260 /* 1261 * Free both high/low RX pending, just in case. 1262 */ 1263 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1264 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1265 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1266 } 1267 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1268 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1269 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1270 } 1271 sc->sc_rxlink = NULL; /* just in case */ 1272 #undef PA2DESC 1273 } 1274 1275 /* 1276 * Enable the receive h/w following a reset. 1277 */ 1278 static int 1279 ath_legacy_startrecv(struct ath_softc *sc) 1280 { 1281 struct ath_hal *ah = sc->sc_ah; 1282 struct ath_buf *bf; 1283 1284 sc->sc_rxlink = NULL; 1285 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1286 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1287 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1288 int error = ath_rxbuf_init(sc, bf); 1289 if (error != 0) { 1290 DPRINTF(sc, ATH_DEBUG_RECV, 1291 "%s: ath_rxbuf_init failed %d\n", 1292 __func__, error); 1293 return error; 1294 } 1295 } 1296 1297 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1298 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1299 ath_hal_rxena(ah); /* enable recv descriptors */ 1300 ath_mode_init(sc); /* set filters, etc. */ 1301 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1302 return 0; 1303 } 1304 1305 static int 1306 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1307 { 1308 int error; 1309 1310 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1311 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1312 if (error != 0) 1313 return (error); 1314 1315 return (0); 1316 } 1317 1318 static int 1319 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1320 { 1321 1322 if (sc->sc_rxdma.dd_desc_len != 0) 1323 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1324 return (0); 1325 } 1326 1327 static void 1328 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1329 { 1330 1331 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1332 } 1333 1334 static void 1335 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1336 int dosched) 1337 { 1338 1339 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1340 } 1341 1342 void 1343 ath_recv_setup_legacy(struct ath_softc *sc) 1344 { 1345 1346 /* Sensible legacy defaults */ 1347 /* 1348 * XXX this should be changed to properly support the 1349 * exact RX descriptor size for each HAL. 1350 */ 1351 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1352 1353 sc->sc_rx.recv_start = ath_legacy_startrecv; 1354 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1355 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1356 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1357 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1358 1359 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1360 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1361 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1362 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1363 } 1364