1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 72 #if defined(__DragonFly__) 73 /* empty */ 74 #else 75 #include <sys/smp.h> /* for mp_ncpus */ 76 #include <machine/bus.h> 77 #endif 78 79 #include <net/if.h> 80 #include <net/if_var.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 #include <net/if_types.h> 84 #include <net/if_arp.h> 85 #include <net/ethernet.h> 86 #include <net/if_llc.h> 87 #if defined(__DragonFly__) 88 #include <net/ifq_var.h> 89 #endif 90 91 #include <netproto/802_11/ieee80211_var.h> 92 #include <netproto/802_11/ieee80211_regdomain.h> 93 #ifdef IEEE80211_SUPPORT_SUPERG 94 #include <netproto/802_11/ieee80211_superg.h> 95 #endif 96 #ifdef IEEE80211_SUPPORT_TDMA 97 #include <netproto/802_11/ieee80211_tdma.h> 98 #endif 99 100 #include <net/bpf.h> 101 102 #ifdef INET 103 #include <netinet/in.h> 104 #include <netinet/if_ether.h> 105 #endif 106 107 #include <dev/netif/ath/ath/if_athvar.h> 108 #include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */ 109 #include <dev/netif/ath/ath_hal/ah_diagcodes.h> 110 111 #include <dev/netif/ath/ath/if_ath_debug.h> 112 #include <dev/netif/ath/ath/if_ath_misc.h> 113 #include <dev/netif/ath/ath/if_ath_tsf.h> 114 #include <dev/netif/ath/ath/if_ath_tx.h> 115 #include <dev/netif/ath/ath/if_ath_sysctl.h> 116 #include <dev/netif/ath/ath/if_ath_led.h> 117 #include <dev/netif/ath/ath/if_ath_keycache.h> 118 #include <dev/netif/ath/ath/if_ath_rx.h> 119 #include <dev/netif/ath/ath/if_ath_beacon.h> 120 #include <dev/netif/ath/ath/if_athdfs.h> 121 #include <dev/netif/ath/ath/if_ath_descdma.h> 122 123 #ifdef ATH_TX99_DIAG 124 #include <dev/netif/ath/ath/ath_tx99/ath_tx99.h> 125 #endif 126 127 #ifdef ATH_DEBUG_ALQ 128 #include <dev/netif/ath/ath/if_ath_alq.h> 129 #endif 130 131 #include <dev/netif/ath/ath/if_ath_lna_div.h> 132 133 /* 134 * Calculate the receive filter according to the 135 * operating mode and state: 136 * 137 * o always accept unicast, broadcast, and multicast traffic 138 * o accept PHY error frames when hardware doesn't have MIB support 139 * to count and we need them for ANI (sta mode only until recently) 140 * and we are not scanning (ANI is disabled) 141 * NB: older hal's add rx filter bits out of sight and we need to 142 * blindly preserve them 143 * o probe request frames are accepted only when operating in 144 * hostap, adhoc, mesh, or monitor modes 145 * o enable promiscuous mode 146 * - when in monitor mode 147 * - if interface marked PROMISC (assumes bridge setting is filtered) 148 * o accept beacons: 149 * - when operating in station mode for collecting rssi data when 150 * the station is otherwise quiet, or 151 * - when operating in adhoc mode so the 802.11 layer creates 152 * node table entries for peers, 153 * - when scanning 154 * - when doing s/w beacon miss (e.g. for ap+sta) 155 * - when operating in ap mode in 11g to detect overlapping bss that 156 * require protection 157 * - when operating in mesh mode to detect neighbors 158 * o accept control frames: 159 * - when in monitor mode 160 * XXX HT protection for 11n 161 */ 162 u_int32_t 163 ath_calcrxfilter(struct ath_softc *sc) 164 { 165 struct ieee80211com *ic = &sc->sc_ic; 166 u_int32_t rfilt; 167 168 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 169 if (!sc->sc_needmib && !sc->sc_scanning) 170 rfilt |= HAL_RX_FILTER_PHYERR; 171 if (ic->ic_opmode != IEEE80211_M_STA) 172 rfilt |= HAL_RX_FILTER_PROBEREQ; 173 /* XXX ic->ic_monvaps != 0? */ 174 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0) 175 rfilt |= HAL_RX_FILTER_PROM; 176 177 /* 178 * Only listen to all beacons if we're scanning. 179 * 180 * Otherwise we only really need to hear beacons from 181 * our own BSSID. 182 * 183 * IBSS? software beacon miss? Just receive all beacons. 184 * We need to hear beacons/probe requests from everyone so 185 * we can merge ibss. 186 */ 187 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) { 188 rfilt |= HAL_RX_FILTER_BEACON; 189 } else if (ic->ic_opmode == IEEE80211_M_STA) { 190 if (sc->sc_do_mybeacon && ! sc->sc_scanning) { 191 rfilt |= HAL_RX_FILTER_MYBEACON; 192 } else { /* scanning, non-mybeacon chips */ 193 rfilt |= HAL_RX_FILTER_BEACON; 194 } 195 } 196 197 /* 198 * NB: We don't recalculate the rx filter when 199 * ic_protmode changes; otherwise we could do 200 * this only when ic_protmode != NONE. 201 */ 202 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 203 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 204 rfilt |= HAL_RX_FILTER_BEACON; 205 206 /* 207 * Enable hardware PS-POLL RX only for hostap mode; 208 * STA mode sends PS-POLL frames but never 209 * receives them. 210 */ 211 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 212 0, NULL) == HAL_OK && 213 ic->ic_opmode == IEEE80211_M_HOSTAP) 214 rfilt |= HAL_RX_FILTER_PSPOLL; 215 216 if (sc->sc_nmeshvaps) { 217 rfilt |= HAL_RX_FILTER_BEACON; 218 if (sc->sc_hasbmatch) 219 rfilt |= HAL_RX_FILTER_BSSID; 220 else 221 rfilt |= HAL_RX_FILTER_PROM; 222 } 223 if (ic->ic_opmode == IEEE80211_M_MONITOR) 224 rfilt |= HAL_RX_FILTER_CONTROL; 225 226 /* 227 * Enable RX of compressed BAR frames only when doing 228 * 802.11n. Required for A-MPDU. 229 */ 230 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 231 rfilt |= HAL_RX_FILTER_COMPBAR; 232 233 /* 234 * Enable radar PHY errors if requested by the 235 * DFS module. 236 */ 237 if (sc->sc_dodfs) 238 rfilt |= HAL_RX_FILTER_PHYRADAR; 239 240 /* 241 * Enable spectral PHY errors if requested by the 242 * spectral module. 243 */ 244 if (sc->sc_dospectral) 245 rfilt |= HAL_RX_FILTER_PHYRADAR; 246 247 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n", 248 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]); 249 return rfilt; 250 } 251 252 static int 253 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 254 { 255 struct ath_hal *ah = sc->sc_ah; 256 int error; 257 struct mbuf *m; 258 struct ath_desc *ds; 259 260 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */ 261 262 m = bf->bf_m; 263 if (m == NULL) { 264 /* 265 * NB: by assigning a page to the rx dma buffer we 266 * implicitly satisfy the Atheros requirement that 267 * this buffer be cache-line-aligned and sized to be 268 * multiple of the cache line size. Not doing this 269 * causes weird stuff to happen (for the 5210 at least). 270 */ 271 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 272 if (m == NULL) { 273 DPRINTF(sc, ATH_DEBUG_ANY, 274 "%s: no mbuf/cluster\n", __func__); 275 sc->sc_stats.ast_rx_nombuf++; 276 return ENOMEM; 277 } 278 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 279 280 #if defined(__DragonFly__) 281 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, 282 bf->bf_dmamap, m, 283 bf->bf_segs, 1, &bf->bf_nseg, 284 BUS_DMA_NOWAIT); 285 #else 286 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 287 bf->bf_dmamap, m, 288 bf->bf_segs, &bf->bf_nseg, 289 BUS_DMA_NOWAIT); 290 #endif 291 if (error != 0) { 292 DPRINTF(sc, ATH_DEBUG_ANY, 293 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 294 __func__, error); 295 sc->sc_stats.ast_rx_busdma++; 296 m_freem(m); 297 return error; 298 } 299 KASSERT(bf->bf_nseg == 1, 300 ("multi-segment packet; nseg %u", bf->bf_nseg)); 301 bf->bf_m = m; 302 } 303 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 304 305 /* 306 * Setup descriptors. For receive we always terminate 307 * the descriptor list with a self-linked entry so we'll 308 * not get overrun under high load (as can happen with a 309 * 5212 when ANI processing enables PHY error frames). 310 * 311 * To insure the last descriptor is self-linked we create 312 * each descriptor as self-linked and add it to the end. As 313 * each additional descriptor is added the previous self-linked 314 * entry is ``fixed'' naturally. This should be safe even 315 * if DMA is happening. When processing RX interrupts we 316 * never remove/process the last, self-linked, entry on the 317 * descriptor list. This insures the hardware always has 318 * someplace to write a new frame. 319 */ 320 /* 321 * 11N: we can no longer afford to self link the last descriptor. 322 * MAC acknowledges BA status as long as it copies frames to host 323 * buffer (or rx fifo). This can incorrectly acknowledge packets 324 * to a sender if last desc is self-linked. 325 */ 326 ds = bf->bf_desc; 327 if (sc->sc_rxslink) 328 ds->ds_link = bf->bf_daddr; /* link to self */ 329 else 330 ds->ds_link = 0; /* terminate the list */ 331 ds->ds_data = bf->bf_segs[0].ds_addr; 332 ath_hal_setuprxdesc(ah, ds 333 , m->m_len /* buffer size */ 334 , 0 335 ); 336 337 if (sc->sc_rxlink != NULL) 338 *sc->sc_rxlink = bf->bf_daddr; 339 sc->sc_rxlink = &ds->ds_link; 340 return 0; 341 } 342 343 /* 344 * Intercept management frames to collect beacon rssi data 345 * and to do ibss merges. 346 */ 347 void 348 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 349 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf) 350 { 351 struct ieee80211vap *vap = ni->ni_vap; 352 struct ath_softc *sc = vap->iv_ic->ic_softc; 353 uint64_t tsf_beacon_old, tsf_beacon; 354 uint64_t nexttbtt; 355 int64_t tsf_delta; 356 int32_t tsf_delta_bmiss; 357 int32_t tsf_remainder; 358 uint64_t tsf_beacon_target; 359 int tsf_intval; 360 361 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 362 tsf_beacon_old |= le32dec(ni->ni_tstamp.data); 363 364 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 365 tsf_intval = 1; 366 if (ni->ni_intval > 0) { 367 tsf_intval = TU_TO_TSF(ni->ni_intval); 368 } 369 #undef TU_TO_TSF 370 371 /* 372 * Call up first so subsequent work can use information 373 * potentially stored in the node (e.g. for ibss merge). 374 */ 375 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf); 376 switch (subtype) { 377 case IEEE80211_FC0_SUBTYPE_BEACON: 378 379 /* 380 * Only do the following processing if it's for 381 * the current BSS. 382 * 383 * In scan and IBSS mode we receive all beacons, 384 * which means we need to filter out stuff 385 * that isn't for us or we'll end up constantly 386 * trying to sync / merge to BSSes that aren't 387 * actually us. 388 */ 389 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) { 390 /* update rssi statistics for use by the hal */ 391 /* XXX unlocked check against vap->iv_bss? */ 392 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 393 394 395 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32; 396 tsf_beacon |= le32dec(ni->ni_tstamp.data); 397 398 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah); 399 400 /* 401 * Let's calculate the delta and remainder, so we can see 402 * if the beacon timer from the AP is varying by more than 403 * a few TU. (Which would be a huge, huge problem.) 404 */ 405 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old; 406 407 tsf_delta_bmiss = tsf_delta / tsf_intval; 408 409 /* 410 * If our delta is greater than half the beacon interval, 411 * let's round the bmiss value up to the next beacon 412 * interval. Ie, we're running really, really early 413 * on the next beacon. 414 */ 415 if (tsf_delta % tsf_intval > (tsf_intval / 2)) 416 tsf_delta_bmiss ++; 417 418 tsf_beacon_target = tsf_beacon_old + 419 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval); 420 421 /* 422 * The remainder using '%' is between 0 .. intval-1. 423 * If we're actually running too fast, then the remainder 424 * will be some large number just under intval-1. 425 * So we need to look at whether we're running 426 * before or after the target beacon interval 427 * and if we are, modify how we do the remainder 428 * calculation. 429 */ 430 if (tsf_beacon < tsf_beacon_target) { 431 tsf_remainder = 432 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval)); 433 } else { 434 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval; 435 } 436 437 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n", 438 __func__, 439 (unsigned long long) tsf_beacon_old, 440 (unsigned long long) tsf_beacon, 441 (unsigned long long) tsf_beacon_target, 442 (long long) tsf_delta, 443 tsf_delta_bmiss, 444 tsf_remainder); 445 446 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n", 447 __func__, 448 (unsigned long long) tsf_beacon, 449 (unsigned long long) nexttbtt, 450 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval); 451 452 /* We only do syncbeacon on STA VAPs; not on IBSS */ 453 if (vap->iv_opmode == IEEE80211_M_STA && 454 sc->sc_syncbeacon && 455 ni == vap->iv_bss && 456 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) { 457 DPRINTF(sc, ATH_DEBUG_BEACON, 458 "%s: syncbeacon=1; syncing\n", 459 __func__); 460 /* 461 * Resync beacon timers using the tsf of the beacon 462 * frame we just received. 463 */ 464 ath_beacon_config(sc, vap); 465 sc->sc_syncbeacon = 0; 466 } 467 } 468 469 /* fall thru... */ 470 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 471 if (vap->iv_opmode == IEEE80211_M_IBSS && 472 vap->iv_state == IEEE80211_S_RUN && 473 ieee80211_ibss_merge_check(ni)) { 474 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 475 uint64_t tsf = ath_extend_tsf(sc, rstamp, 476 ath_hal_gettsf64(sc->sc_ah)); 477 /* 478 * Handle ibss merge as needed; check the tsf on the 479 * frame before attempting the merge. The 802.11 spec 480 * says the station should change it's bssid to match 481 * the oldest station with the same ssid, where oldest 482 * is determined by the tsf. Note that hardware 483 * reconfiguration happens through callback to 484 * ath_newstate as the state machine will go from 485 * RUN -> RUN when this happens. 486 */ 487 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 488 DPRINTF(sc, ATH_DEBUG_STATE, 489 "ibss merge, rstamp %u tsf %ju " 490 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 491 (uintmax_t)ni->ni_tstamp.tsf); 492 (void) ieee80211_ibss_merge(ni); 493 } 494 } 495 break; 496 } 497 } 498 499 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 500 static void 501 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m, 502 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 503 { 504 505 /* Fill in the extension bitmap */ 506 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 507 508 /* Fill in the vendor header */ 509 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 510 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 511 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 512 513 /* XXX what should this be? */ 514 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 515 sc->sc_rx_th.wr_vh.vh_skip_len = 516 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 517 518 /* General version info */ 519 sc->sc_rx_th.wr_v.vh_version = 1; 520 521 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 522 523 /* rssi */ 524 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 525 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 526 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 527 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 528 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 529 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 530 531 /* evm */ 532 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 533 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 534 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 535 /* These are only populated from the AR9300 or later */ 536 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 537 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 538 539 /* direction */ 540 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 541 542 /* RX rate */ 543 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 544 545 /* RX flags */ 546 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 547 548 if (rs->rs_isaggr) 549 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 550 if (rs->rs_moreaggr) 551 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 552 553 /* phyerr info */ 554 if (rs->rs_status & HAL_RXERR_PHY) { 555 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 556 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 557 } else { 558 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 559 } 560 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 561 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 562 } 563 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 564 565 static void 566 ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 567 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 568 { 569 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 570 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 571 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 572 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 573 const HAL_RATE_TABLE *rt; 574 uint8_t rix; 575 576 rt = sc->sc_currates; 577 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 578 rix = rt->rateCodeToIndex[rs->rs_rate]; 579 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 580 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 581 #ifdef AH_SUPPORT_AR5416 582 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 583 if (rs->rs_status & HAL_RXERR_PHY) { 584 /* 585 * PHY error - make sure the channel flags 586 * reflect the actual channel configuration, 587 * not the received frame. 588 */ 589 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 590 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 591 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 592 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 593 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 594 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 595 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 596 struct ieee80211com *ic = &sc->sc_ic; 597 598 if ((rs->rs_flags & HAL_RX_2040) == 0) 599 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 600 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 601 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 602 else 603 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 604 if ((rs->rs_flags & HAL_RX_GI) == 0) 605 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 606 } 607 608 #endif 609 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 610 if (rs->rs_status & HAL_RXERR_CRC) 611 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 612 /* XXX propagate other error flags from descriptor */ 613 sc->sc_rx_th.wr_antnoise = nf; 614 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 615 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 616 #undef CHAN_HT 617 #undef CHAN_HT20 618 #undef CHAN_HT40U 619 #undef CHAN_HT40D 620 } 621 622 static void 623 ath_handle_micerror(struct ieee80211com *ic, 624 struct ieee80211_frame *wh, int keyix) 625 { 626 struct ieee80211_node *ni; 627 628 /* XXX recheck MIC to deal w/ chips that lie */ 629 /* XXX discard MIC errors on !data frames */ 630 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 631 if (ni != NULL) { 632 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 633 ieee80211_free_node(ni); 634 } 635 } 636 637 /* 638 * Process a single packet. 639 * 640 * The mbuf must already be synced, unmapped and removed from bf->bf_m 641 * by this stage. 642 * 643 * The mbuf must be consumed by this routine - either passed up the 644 * net80211 stack, put on the holding queue, or freed. 645 */ 646 int 647 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 648 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 649 struct mbuf *m) 650 { 651 uint64_t rstamp; 652 int len, type; 653 struct ieee80211com *ic = &sc->sc_ic; 654 struct ieee80211_node *ni; 655 int is_good = 0; 656 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 657 658 /* 659 * Calculate the correct 64 bit TSF given 660 * the TSF64 register value and rs_tstamp. 661 */ 662 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 663 664 /* These aren't specifically errors */ 665 #ifdef AH_SUPPORT_AR5416 666 if (rs->rs_flags & HAL_RX_GI) 667 sc->sc_stats.ast_rx_halfgi++; 668 if (rs->rs_flags & HAL_RX_2040) 669 sc->sc_stats.ast_rx_2040++; 670 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 671 sc->sc_stats.ast_rx_pre_crc_err++; 672 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 673 sc->sc_stats.ast_rx_post_crc_err++; 674 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 675 sc->sc_stats.ast_rx_decrypt_busy_err++; 676 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 677 sc->sc_stats.ast_rx_hi_rx_chain++; 678 if (rs->rs_flags & HAL_RX_STBC) 679 sc->sc_stats.ast_rx_stbc++; 680 #endif /* AH_SUPPORT_AR5416 */ 681 682 if (rs->rs_status != 0) { 683 if (rs->rs_status & HAL_RXERR_CRC) 684 sc->sc_stats.ast_rx_crcerr++; 685 if (rs->rs_status & HAL_RXERR_FIFO) 686 sc->sc_stats.ast_rx_fifoerr++; 687 if (rs->rs_status & HAL_RXERR_PHY) { 688 sc->sc_stats.ast_rx_phyerr++; 689 /* Process DFS radar events */ 690 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 691 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 692 /* Now pass it to the radar processing code */ 693 ath_dfs_process_phy_err(sc, m, rstamp, rs); 694 } 695 696 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 697 if (rs->rs_phyerr < 64) 698 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 699 goto rx_error; /* NB: don't count in ierrors */ 700 } 701 if (rs->rs_status & HAL_RXERR_DECRYPT) { 702 /* 703 * Decrypt error. If the error occurred 704 * because there was no hardware key, then 705 * let the frame through so the upper layers 706 * can process it. This is necessary for 5210 707 * parts which have no way to setup a ``clear'' 708 * key cache entry. 709 * 710 * XXX do key cache faulting 711 */ 712 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 713 goto rx_accept; 714 sc->sc_stats.ast_rx_badcrypt++; 715 } 716 /* 717 * Similar as above - if the failure was a keymiss 718 * just punt it up to the upper layers for now. 719 */ 720 if (rs->rs_status & HAL_RXERR_KEYMISS) { 721 sc->sc_stats.ast_rx_keymiss++; 722 goto rx_accept; 723 } 724 if (rs->rs_status & HAL_RXERR_MIC) { 725 sc->sc_stats.ast_rx_badmic++; 726 /* 727 * Do minimal work required to hand off 728 * the 802.11 header for notification. 729 */ 730 /* XXX frag's and qos frames */ 731 len = rs->rs_datalen; 732 if (len >= sizeof (struct ieee80211_frame)) { 733 ath_handle_micerror(ic, 734 mtod(m, struct ieee80211_frame *), 735 sc->sc_splitmic ? 736 rs->rs_keyix-32 : rs->rs_keyix); 737 } 738 } 739 #if defined(__DragonFly__) 740 ++ic->ic_ierrors; /* don't care about SMP races */ 741 #else 742 counter_u64_add(ic->ic_ierrors, 1); 743 #endif 744 rx_error: 745 /* 746 * Cleanup any pending partial frame. 747 */ 748 if (re->m_rxpending != NULL) { 749 m_freem(re->m_rxpending); 750 re->m_rxpending = NULL; 751 } 752 /* 753 * When a tap is present pass error frames 754 * that have been requested. By default we 755 * pass decrypt+mic errors but others may be 756 * interesting (e.g. crc). 757 */ 758 if (ieee80211_radiotap_active(ic) && 759 (rs->rs_status & sc->sc_monpass)) { 760 /* NB: bpf needs the mbuf length setup */ 761 len = rs->rs_datalen; 762 m->m_pkthdr.len = m->m_len = len; 763 ath_rx_tap(sc, m, rs, rstamp, nf); 764 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 765 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 766 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 767 ieee80211_radiotap_rx_all(ic, m); 768 } 769 /* XXX pass MIC errors up for s/w reclaculation */ 770 m_freem(m); m = NULL; 771 goto rx_next; 772 } 773 rx_accept: 774 len = rs->rs_datalen; 775 m->m_len = len; 776 777 if (rs->rs_more) { 778 /* 779 * Frame spans multiple descriptors; save 780 * it for the next completed descriptor, it 781 * will be used to construct a jumbogram. 782 */ 783 if (re->m_rxpending != NULL) { 784 /* NB: max frame size is currently 2 clusters */ 785 sc->sc_stats.ast_rx_toobig++; 786 m_freem(re->m_rxpending); 787 } 788 m->m_pkthdr.len = len; 789 re->m_rxpending = m; 790 m = NULL; 791 goto rx_next; 792 } else if (re->m_rxpending != NULL) { 793 /* 794 * This is the second part of a jumbogram, 795 * chain it to the first mbuf, adjust the 796 * frame length, and clear the rxpending state. 797 */ 798 re->m_rxpending->m_next = m; 799 re->m_rxpending->m_pkthdr.len += len; 800 m = re->m_rxpending; 801 re->m_rxpending = NULL; 802 } else { 803 /* 804 * Normal single-descriptor receive; setup packet length. 805 */ 806 m->m_pkthdr.len = len; 807 } 808 809 /* 810 * Validate rs->rs_antenna. 811 * 812 * Some users w/ AR9285 NICs have reported crashes 813 * here because rs_antenna field is bogusly large. 814 * Let's enforce the maximum antenna limit of 8 815 * (and it shouldn't be hard coded, but that's a 816 * separate problem) and if there's an issue, print 817 * out an error and adjust rs_antenna to something 818 * sensible. 819 * 820 * This code should be removed once the actual 821 * root cause of the issue has been identified. 822 * For example, it may be that the rs_antenna 823 * field is only valid for the last frame of 824 * an aggregate and it just happens that it is 825 * "mostly" right. (This is a general statement - 826 * the majority of the statistics are only valid 827 * for the last frame in an aggregate. 828 */ 829 if (rs->rs_antenna > 7) { 830 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 831 __func__, rs->rs_antenna); 832 #ifdef ATH_DEBUG 833 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 834 #endif /* ATH_DEBUG */ 835 rs->rs_antenna = 0; /* XXX better than nothing */ 836 } 837 838 /* 839 * If this is an AR9285/AR9485, then the receive and LNA 840 * configuration is stored in RSSI[2] / EXTRSSI[2]. 841 * We can extract this out to build a much better 842 * receive antenna profile. 843 * 844 * Yes, this just blurts over the above RX antenna field 845 * for now. It's fine, the AR9285 doesn't really use 846 * that. 847 * 848 * Later on we should store away the fine grained LNA 849 * information and keep separate counters just for 850 * that. It'll help when debugging the AR9285/AR9485 851 * combined diversity code. 852 */ 853 if (sc->sc_rx_lnamixer) { 854 rs->rs_antenna = 0; 855 856 /* Bits 0:1 - the LNA configuration used */ 857 rs->rs_antenna |= 858 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 859 >> HAL_RX_LNA_CFG_USED_S); 860 861 /* Bit 2 - the external RX antenna switch */ 862 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 863 rs->rs_antenna |= 0x4; 864 } 865 866 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 867 868 /* 869 * Populate the rx status block. When there are bpf 870 * listeners we do the additional work to provide 871 * complete status. Otherwise we fill in only the 872 * material required by ieee80211_input. Note that 873 * noise setting is filled in above. 874 */ 875 if (ieee80211_radiotap_active(ic)) { 876 ath_rx_tap(sc, m, rs, rstamp, nf); 877 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 878 ath_rx_tap_vendor(sc, m, rs, rstamp, nf); 879 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 880 } 881 882 /* 883 * From this point on we assume the frame is at least 884 * as large as ieee80211_frame_min; verify that. 885 */ 886 if (len < IEEE80211_MIN_LEN) { 887 if (!ieee80211_radiotap_active(ic)) { 888 DPRINTF(sc, ATH_DEBUG_RECV, 889 "%s: short packet %d\n", __func__, len); 890 sc->sc_stats.ast_rx_tooshort++; 891 } else { 892 /* NB: in particular this captures ack's */ 893 ieee80211_radiotap_rx_all(ic, m); 894 } 895 m_freem(m); m = NULL; 896 goto rx_next; 897 } 898 899 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 900 const HAL_RATE_TABLE *rt = sc->sc_currates; 901 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 902 903 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 904 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 905 } 906 907 m_adj(m, -IEEE80211_CRC_LEN); 908 909 /* 910 * Locate the node for sender, track state, and then 911 * pass the (referenced) node up to the 802.11 layer 912 * for its use. 913 */ 914 ni = ieee80211_find_rxnode_withkey(ic, 915 mtod(m, const struct ieee80211_frame_min *), 916 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 917 IEEE80211_KEYIX_NONE : rs->rs_keyix); 918 sc->sc_lastrs = rs; 919 920 #ifdef AH_SUPPORT_AR5416 921 if (rs->rs_isaggr) 922 sc->sc_stats.ast_rx_agg++; 923 #endif /* AH_SUPPORT_AR5416 */ 924 925 if (ni != NULL) { 926 /* 927 * Only punt packets for ampdu reorder processing for 928 * 11n nodes; net80211 enforces that M_AMPDU is only 929 * set for 11n nodes. 930 */ 931 if (ni->ni_flags & IEEE80211_NODE_HT) 932 m->m_flags |= M_AMPDU; 933 934 /* 935 * Sending station is known, dispatch directly. 936 */ 937 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 938 ieee80211_free_node(ni); 939 m = NULL; 940 /* 941 * Arrange to update the last rx timestamp only for 942 * frames from our ap when operating in station mode. 943 * This assumes the rx key is always setup when 944 * associated. 945 */ 946 if (ic->ic_opmode == IEEE80211_M_STA && 947 rs->rs_keyix != HAL_RXKEYIX_INVALID) 948 is_good = 1; 949 } else { 950 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 951 m = NULL; 952 } 953 954 /* 955 * At this point we have passed the frame up the stack; thus 956 * the mbuf is no longer ours. 957 */ 958 959 /* 960 * Track rx rssi and do any rx antenna management. 961 */ 962 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 963 if (sc->sc_diversity) { 964 /* 965 * When using fast diversity, change the default rx 966 * antenna if diversity chooses the other antenna 3 967 * times in a row. 968 */ 969 if (sc->sc_defant != rs->rs_antenna) { 970 if (++sc->sc_rxotherant >= 3) 971 ath_setdefantenna(sc, rs->rs_antenna); 972 } else 973 sc->sc_rxotherant = 0; 974 } 975 976 /* Handle slow diversity if enabled */ 977 if (sc->sc_dolnadiv) { 978 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 979 } 980 981 if (sc->sc_softled) { 982 /* 983 * Blink for any data frame. Otherwise do a 984 * heartbeat-style blink when idle. The latter 985 * is mainly for station mode where we depend on 986 * periodic beacon frames to trigger the poll event. 987 */ 988 if (type == IEEE80211_FC0_TYPE_DATA) { 989 const HAL_RATE_TABLE *rt = sc->sc_currates; 990 ath_led_event(sc, 991 rt->rateCodeToIndex[rs->rs_rate]); 992 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 993 ath_led_event(sc, 0); 994 } 995 rx_next: 996 /* 997 * Debugging - complain if we didn't NULL the mbuf pointer 998 * here. 999 */ 1000 if (m != NULL) { 1001 device_printf(sc->sc_dev, 1002 "%s: mbuf %p should've been freed!\n", 1003 __func__, 1004 m); 1005 } 1006 return (is_good); 1007 } 1008 1009 #define ATH_RX_MAX 128 1010 1011 /* 1012 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like 1013 * the EDMA code does. 1014 * 1015 * XXX TODO: then, do all of the RX list management stuff inside 1016 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA 1017 * code is doing it right. 1018 */ 1019 static void 1020 ath_rx_proc(struct ath_softc *sc, int resched) 1021 { 1022 #define PA2DESC(_sc, _pa) \ 1023 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1024 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1025 struct ath_buf *bf; 1026 struct ath_hal *ah = sc->sc_ah; 1027 #ifdef IEEE80211_SUPPORT_SUPERG 1028 struct ieee80211com *ic = &sc->sc_ic; 1029 #endif 1030 struct ath_desc *ds; 1031 struct ath_rx_status *rs; 1032 struct mbuf *m; 1033 int ngood; 1034 HAL_STATUS status; 1035 int16_t nf; 1036 u_int64_t tsf; 1037 int npkts = 0; 1038 int kickpcu = 0; 1039 int ret; 1040 1041 /* XXX we must not hold the ATH_LOCK here */ 1042 ATH_UNLOCK_ASSERT(sc); 1043 ATH_PCU_UNLOCK_ASSERT(sc); 1044 1045 ATH_PCU_LOCK(sc); 1046 sc->sc_rxproc_cnt++; 1047 kickpcu = sc->sc_kickpcu; 1048 ATH_PCU_UNLOCK(sc); 1049 1050 ATH_LOCK(sc); 1051 ath_power_set_power_state(sc, HAL_PM_AWAKE); 1052 ATH_UNLOCK(sc); 1053 1054 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 1055 ngood = 0; 1056 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 1057 sc->sc_stats.ast_rx_noise = nf; 1058 tsf = ath_hal_gettsf64(ah); 1059 do { 1060 /* 1061 * Don't process too many packets at a time; give the 1062 * TX thread time to also run - otherwise the TX 1063 * latency can jump by quite a bit, causing throughput 1064 * degredation. 1065 */ 1066 if (!kickpcu && npkts >= ATH_RX_MAX) 1067 break; 1068 1069 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1070 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 1071 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__); 1072 break; 1073 } else if (bf == NULL) { 1074 /* 1075 * End of List: 1076 * this can happen for non-self-linked RX chains 1077 */ 1078 sc->sc_stats.ast_rx_hitqueueend++; 1079 break; 1080 } 1081 m = bf->bf_m; 1082 if (m == NULL) { /* NB: shouldn't happen */ 1083 /* 1084 * If mbuf allocation failed previously there 1085 * will be no mbuf; try again to re-populate it. 1086 */ 1087 /* XXX make debug msg */ 1088 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__); 1089 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1090 goto rx_proc_next; 1091 } 1092 ds = bf->bf_desc; 1093 if (ds->ds_link == bf->bf_daddr) { 1094 /* NB: never process the self-linked entry at the end */ 1095 sc->sc_stats.ast_rx_hitqueueend++; 1096 break; 1097 } 1098 /* XXX sync descriptor memory */ 1099 /* 1100 * Must provide the virtual address of the current 1101 * descriptor, the physical address, and the virtual 1102 * address of the next descriptor in the h/w chain. 1103 * This allows the HAL to look ahead to see if the 1104 * hardware is done with a descriptor by checking the 1105 * done bit in the following descriptor and the address 1106 * of the current descriptor the DMA engine is working 1107 * on. All this is necessary because of our use of 1108 * a self-linked list to avoid rx overruns. 1109 */ 1110 rs = &bf->bf_status.ds_rxstat; 1111 status = ath_hal_rxprocdesc(ah, ds, 1112 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1113 #ifdef ATH_DEBUG 1114 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 1115 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 1116 #endif 1117 1118 #ifdef ATH_DEBUG_ALQ 1119 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 1120 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 1121 sc->sc_rx_statuslen, (char *) ds); 1122 #endif /* ATH_DEBUG_ALQ */ 1123 1124 if (status == HAL_EINPROGRESS) 1125 break; 1126 1127 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 1128 npkts++; 1129 1130 /* 1131 * Process a single frame. 1132 */ 1133 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 1134 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1135 bf->bf_m = NULL; 1136 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 1137 ngood++; 1138 rx_proc_next: 1139 /* 1140 * If there's a holding buffer, insert that onto 1141 * the RX list; the hardware is now definitely not pointing 1142 * to it now. 1143 */ 1144 ret = 0; 1145 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) { 1146 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, 1147 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf, 1148 bf_list); 1149 ret = ath_rxbuf_init(sc, 1150 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf); 1151 } 1152 /* 1153 * Next, throw our buffer into the holding entry. The hardware 1154 * may use the descriptor to read the link pointer before 1155 * DMAing the next descriptor in to write out a packet. 1156 */ 1157 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf; 1158 } while (ret == 0); 1159 1160 /* rx signal state monitoring */ 1161 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1162 if (ngood) 1163 sc->sc_lastrx = tsf; 1164 1165 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1166 /* Queue DFS tasklet if needed */ 1167 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1168 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1169 1170 /* 1171 * Now that all the RX frames were handled that 1172 * need to be handled, kick the PCU if there's 1173 * been an RXEOL condition. 1174 */ 1175 if (resched && kickpcu) { 1176 ATH_PCU_LOCK(sc); 1177 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1178 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1179 __func__, npkts); 1180 1181 /* 1182 * Go through the process of fully tearing down 1183 * the RX buffers and reinitialising them. 1184 * 1185 * There's a hardware bug that causes the RX FIFO 1186 * to get confused under certain conditions and 1187 * constantly write over the same frame, leading 1188 * the RX driver code here to get heavily confused. 1189 */ 1190 /* 1191 * XXX Has RX DMA stopped enough here to just call 1192 * ath_startrecv()? 1193 * XXX Do we need to use the holding buffer to restart 1194 * RX DMA by appending entries to the final 1195 * descriptor? Quite likely. 1196 */ 1197 #if 1 1198 ath_startrecv(sc); 1199 #else 1200 /* 1201 * Disabled for now - it'd be nice to be able to do 1202 * this in order to limit the amount of CPU time spent 1203 * reinitialising the RX side (and thus minimise RX 1204 * drops) however there's a hardware issue that 1205 * causes things to get too far out of whack. 1206 */ 1207 /* 1208 * XXX can we hold the PCU lock here? 1209 * Are there any net80211 buffer calls involved? 1210 */ 1211 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1212 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1213 ath_hal_rxena(ah); /* enable recv descriptors */ 1214 ath_mode_init(sc); /* set filters, etc. */ 1215 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1216 #endif 1217 1218 ath_hal_intrset(ah, sc->sc_imask); 1219 sc->sc_kickpcu = 0; 1220 ATH_PCU_UNLOCK(sc); 1221 } 1222 1223 #ifdef IEEE80211_SUPPORT_SUPERG 1224 if (resched) 1225 ieee80211_ff_age_all(ic, 100); 1226 #endif 1227 1228 /* 1229 * Put the hardware to sleep again if we're done with it. 1230 */ 1231 ATH_LOCK(sc); 1232 ath_power_restore_power_state(sc); 1233 ATH_UNLOCK(sc); 1234 1235 /* 1236 * If we hit the maximum number of frames in this round, 1237 * reschedule for another immediate pass. This gives 1238 * the TX and TX completion routines time to run, which 1239 * will reduce latency. 1240 */ 1241 if (npkts >= ATH_RX_MAX) 1242 sc->sc_rx.recv_sched(sc, resched); 1243 1244 ATH_PCU_LOCK(sc); 1245 sc->sc_rxproc_cnt--; 1246 ATH_PCU_UNLOCK(sc); 1247 } 1248 #undef PA2DESC 1249 #undef ATH_RX_MAX 1250 1251 /* 1252 * Only run the RX proc if it's not already running. 1253 * Since this may get run as part of the reset/flush path, 1254 * the task can't clash with an existing, running tasklet. 1255 */ 1256 static void 1257 ath_legacy_rx_tasklet(void *arg, int npending) 1258 { 1259 struct ath_softc *sc = arg; 1260 1261 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1262 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1263 ATH_PCU_LOCK(sc); 1264 if (sc->sc_inreset_cnt > 0) { 1265 device_printf(sc->sc_dev, 1266 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1267 ATH_PCU_UNLOCK(sc); 1268 return; 1269 } 1270 ATH_PCU_UNLOCK(sc); 1271 1272 ath_rx_proc(sc, 1); 1273 } 1274 1275 static void 1276 ath_legacy_flushrecv(struct ath_softc *sc) 1277 { 1278 1279 ath_rx_proc(sc, 0); 1280 } 1281 1282 static void 1283 ath_legacy_flush_rxpending(struct ath_softc *sc) 1284 { 1285 1286 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1287 1288 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1289 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1290 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1291 } 1292 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1293 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1294 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1295 } 1296 } 1297 1298 static int 1299 ath_legacy_flush_rxholdbf(struct ath_softc *sc) 1300 { 1301 struct ath_buf *bf; 1302 1303 /* XXX ATH_RX_LOCK_ASSERT(sc); */ 1304 /* 1305 * If there are RX holding buffers, free them here and return 1306 * them to the list. 1307 * 1308 * XXX should just verify that bf->bf_m is NULL, as it must 1309 * be at this point! 1310 */ 1311 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf; 1312 if (bf != NULL) { 1313 if (bf->bf_m != NULL) 1314 m_freem(bf->bf_m); 1315 bf->bf_m = NULL; 1316 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1317 (void) ath_rxbuf_init(sc, bf); 1318 } 1319 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL; 1320 1321 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf; 1322 if (bf != NULL) { 1323 if (bf->bf_m != NULL) 1324 m_freem(bf->bf_m); 1325 bf->bf_m = NULL; 1326 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 1327 (void) ath_rxbuf_init(sc, bf); 1328 } 1329 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL; 1330 1331 return (0); 1332 } 1333 1334 /* 1335 * Disable the receive h/w in preparation for a reset. 1336 */ 1337 static void 1338 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1339 { 1340 #define PA2DESC(_sc, _pa) \ 1341 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1342 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1343 struct ath_hal *ah = sc->sc_ah; 1344 1345 ATH_RX_LOCK(sc); 1346 1347 ath_hal_stoppcurecv(ah); /* disable PCU */ 1348 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1349 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1350 /* 1351 * TODO: see if this particular DELAY() is required; it may be 1352 * masking some missing FIFO flush or DMA sync. 1353 */ 1354 #if 0 1355 if (dodelay) 1356 #endif 1357 DELAY(3000); /* 3ms is long enough for 1 frame */ 1358 #ifdef ATH_DEBUG 1359 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1360 struct ath_buf *bf; 1361 u_int ix; 1362 1363 device_printf(sc->sc_dev, 1364 "%s: rx queue %p, link %p\n", 1365 __func__, 1366 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1367 sc->sc_rxlink); 1368 ix = 0; 1369 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1370 struct ath_desc *ds = bf->bf_desc; 1371 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1372 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1373 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1374 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1375 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1376 ix++; 1377 } 1378 } 1379 #endif 1380 1381 (void) ath_legacy_flush_rxpending(sc); 1382 (void) ath_legacy_flush_rxholdbf(sc); 1383 1384 sc->sc_rxlink = NULL; /* just in case */ 1385 1386 ATH_RX_UNLOCK(sc); 1387 #undef PA2DESC 1388 } 1389 1390 /* 1391 * XXX TODO: something was calling startrecv without calling 1392 * stoprecv. Let's figure out what/why. It was showing up 1393 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.) 1394 */ 1395 1396 /* 1397 * Enable the receive h/w following a reset. 1398 */ 1399 static int 1400 ath_legacy_startrecv(struct ath_softc *sc) 1401 { 1402 struct ath_hal *ah = sc->sc_ah; 1403 struct ath_buf *bf; 1404 1405 ATH_RX_LOCK(sc); 1406 1407 /* 1408 * XXX should verify these are already all NULL! 1409 */ 1410 sc->sc_rxlink = NULL; 1411 (void) ath_legacy_flush_rxpending(sc); 1412 (void) ath_legacy_flush_rxholdbf(sc); 1413 1414 /* 1415 * Re-chain all of the buffers in the RX buffer list. 1416 */ 1417 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1418 int error = ath_rxbuf_init(sc, bf); 1419 if (error != 0) { 1420 DPRINTF(sc, ATH_DEBUG_RECV, 1421 "%s: ath_rxbuf_init failed %d\n", 1422 __func__, error); 1423 return error; 1424 } 1425 } 1426 1427 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1428 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1429 ath_hal_rxena(ah); /* enable recv descriptors */ 1430 ath_mode_init(sc); /* set filters, etc. */ 1431 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1432 1433 ATH_RX_UNLOCK(sc); 1434 return 0; 1435 } 1436 1437 static int 1438 ath_legacy_dma_rxsetup(struct ath_softc *sc) 1439 { 1440 int error; 1441 1442 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1443 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1444 if (error != 0) 1445 return (error); 1446 1447 return (0); 1448 } 1449 1450 static int 1451 ath_legacy_dma_rxteardown(struct ath_softc *sc) 1452 { 1453 1454 if (sc->sc_rxdma.dd_desc_len != 0) 1455 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1456 return (0); 1457 } 1458 1459 static void 1460 ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1461 { 1462 1463 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1464 } 1465 1466 static void 1467 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1468 int dosched) 1469 { 1470 1471 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1472 } 1473 1474 void 1475 ath_recv_setup_legacy(struct ath_softc *sc) 1476 { 1477 1478 /* Sensible legacy defaults */ 1479 /* 1480 * XXX this should be changed to properly support the 1481 * exact RX descriptor size for each HAL. 1482 */ 1483 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1484 1485 sc->sc_rx.recv_start = ath_legacy_startrecv; 1486 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1487 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1488 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1489 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1490 1491 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1492 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1493 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1494 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1495 } 1496