xref: /dragonfly/sys/dev/netif/ath/ath/if_ath_sysctl.c (revision 2b3f93ea)
1572ff6f6SMatthew Dillon /*-
2572ff6f6SMatthew Dillon  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon  * All rights reserved.
4572ff6f6SMatthew Dillon  *
5572ff6f6SMatthew Dillon  * Redistribution and use in source and binary forms, with or without
6572ff6f6SMatthew Dillon  * modification, are permitted provided that the following conditions
7572ff6f6SMatthew Dillon  * are met:
8572ff6f6SMatthew Dillon  * 1. Redistributions of source code must retain the above copyright
9572ff6f6SMatthew Dillon  *    notice, this list of conditions and the following disclaimer,
10572ff6f6SMatthew Dillon  *    without modification.
11572ff6f6SMatthew Dillon  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12572ff6f6SMatthew Dillon  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13572ff6f6SMatthew Dillon  *    redistribution must be conditioned upon including a substantially
14572ff6f6SMatthew Dillon  *    similar Disclaimer requirement for further binary redistribution.
15572ff6f6SMatthew Dillon  *
16572ff6f6SMatthew Dillon  * NO WARRANTY
17572ff6f6SMatthew Dillon  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18572ff6f6SMatthew Dillon  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19df052c2aSSascha Wildner  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY
20572ff6f6SMatthew Dillon  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21572ff6f6SMatthew Dillon  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22572ff6f6SMatthew Dillon  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23572ff6f6SMatthew Dillon  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24572ff6f6SMatthew Dillon  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25572ff6f6SMatthew Dillon  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26572ff6f6SMatthew Dillon  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27572ff6f6SMatthew Dillon  * THE POSSIBILITY OF SUCH DAMAGES.
28572ff6f6SMatthew Dillon  */
29572ff6f6SMatthew Dillon 
30572ff6f6SMatthew Dillon #include <sys/cdefs.h>
31848b370cSMatthew Dillon __FBSDID("$FreeBSD$");
32572ff6f6SMatthew Dillon 
33572ff6f6SMatthew Dillon /*
34572ff6f6SMatthew Dillon  * Driver for the Atheros Wireless LAN controller.
35572ff6f6SMatthew Dillon  *
36572ff6f6SMatthew Dillon  * This software is derived from work of Atsushi Onoe; his contribution
37572ff6f6SMatthew Dillon  * is greatly appreciated.
38572ff6f6SMatthew Dillon  */
39572ff6f6SMatthew Dillon 
40572ff6f6SMatthew Dillon #include "opt_inet.h"
41572ff6f6SMatthew Dillon #include "opt_ath.h"
42572ff6f6SMatthew Dillon #include "opt_wlan.h"
43572ff6f6SMatthew Dillon 
44572ff6f6SMatthew Dillon #include <sys/param.h>
45572ff6f6SMatthew Dillon #include <sys/systm.h>
46572ff6f6SMatthew Dillon #include <sys/sysctl.h>
47572ff6f6SMatthew Dillon #include <sys/mbuf.h>
48572ff6f6SMatthew Dillon #include <sys/malloc.h>
49572ff6f6SMatthew Dillon #include <sys/lock.h>
50572ff6f6SMatthew Dillon #include <sys/kernel.h>
51572ff6f6SMatthew Dillon #include <sys/socket.h>
52572ff6f6SMatthew Dillon #include <sys/sockio.h>
53572ff6f6SMatthew Dillon #include <sys/errno.h>
54572ff6f6SMatthew Dillon #include <sys/callout.h>
55572ff6f6SMatthew Dillon #include <sys/bus.h>
56572ff6f6SMatthew Dillon #include <sys/endian.h>
57572ff6f6SMatthew Dillon #include <sys/kthread.h>
58572ff6f6SMatthew Dillon #include <sys/taskqueue.h>
59*2b3f93eaSMatthew Dillon #include <sys/caps.h>
60572ff6f6SMatthew Dillon 
61dc249793SMatthew Dillon #if defined(__DragonFly__)
62dc249793SMatthew Dillon /* empty */
63dc249793SMatthew Dillon #else
64b14ca477SMatthew Dillon #include <machine/bus.h>
65dc249793SMatthew Dillon #endif
66b14ca477SMatthew Dillon 
67572ff6f6SMatthew Dillon #include <net/if.h>
68572ff6f6SMatthew Dillon #include <net/if_var.h>
69572ff6f6SMatthew Dillon #include <net/if_dl.h>
70572ff6f6SMatthew Dillon #include <net/if_media.h>
71572ff6f6SMatthew Dillon #include <net/if_types.h>
72572ff6f6SMatthew Dillon #include <net/if_arp.h>
73572ff6f6SMatthew Dillon #include <net/ethernet.h>
74572ff6f6SMatthew Dillon #include <net/if_llc.h>
75572ff6f6SMatthew Dillon 
76dc249793SMatthew Dillon #include <netproto/802_11/ieee80211_var.h>
77dc249793SMatthew Dillon #include <netproto/802_11/ieee80211_regdomain.h>
78572ff6f6SMatthew Dillon #ifdef IEEE80211_SUPPORT_SUPERG
79dc249793SMatthew Dillon #include <netproto/802_11/ieee80211_superg.h>
80572ff6f6SMatthew Dillon #endif
81572ff6f6SMatthew Dillon #ifdef IEEE80211_SUPPORT_TDMA
82dc249793SMatthew Dillon #include <netproto/802_11/ieee80211_tdma.h>
83572ff6f6SMatthew Dillon #endif
84572ff6f6SMatthew Dillon 
85572ff6f6SMatthew Dillon #include <net/bpf.h>
86572ff6f6SMatthew Dillon 
87572ff6f6SMatthew Dillon #ifdef INET
88572ff6f6SMatthew Dillon #include <netinet/in.h>
89572ff6f6SMatthew Dillon #include <netinet/if_ether.h>
90572ff6f6SMatthew Dillon #endif
91572ff6f6SMatthew Dillon 
92dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_athvar.h>
93dc249793SMatthew Dillon #include <dev/netif/ath/ath_hal/ah_devid.h>		/* XXX for softled */
94dc249793SMatthew Dillon #include <dev/netif/ath/ath_hal/ah_diagcodes.h>
95572ff6f6SMatthew Dillon 
96dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_ath_debug.h>
97dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_ath_led.h>
98dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_ath_misc.h>
99dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_ath_tx.h>
100dc249793SMatthew Dillon #include <dev/netif/ath/ath/if_ath_sysctl.h>
101572ff6f6SMatthew Dillon 
102572ff6f6SMatthew Dillon #ifdef ATH_TX99_DIAG
103b14ca477SMatthew Dillon #include <dev/ath/ath_tx99/ath_tx99.h>
104572ff6f6SMatthew Dillon #endif
105572ff6f6SMatthew Dillon 
106572ff6f6SMatthew Dillon #ifdef	ATH_DEBUG_ALQ
107dc249793SMatthew Dillon #include <dev/netif/ath/if_ath_alq.h>
108572ff6f6SMatthew Dillon #endif
109572ff6f6SMatthew Dillon 
110572ff6f6SMatthew Dillon static int
ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)111572ff6f6SMatthew Dillon ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
112572ff6f6SMatthew Dillon {
113572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
1143133c5e3SMatthew Dillon 	u_int slottime;
115572ff6f6SMatthew Dillon 	int error;
116572ff6f6SMatthew Dillon 
117848b370cSMatthew Dillon 	ATH_LOCK(sc);
118d98a0bcfSMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
1193133c5e3SMatthew Dillon 	slottime = ath_hal_getslottime(sc->sc_ah);
120848b370cSMatthew Dillon 	ATH_UNLOCK(sc);
121848b370cSMatthew Dillon 
122572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &slottime, 0, req);
123848b370cSMatthew Dillon 	if (error || !req->newptr)
124848b370cSMatthew Dillon 		goto finish;
125848b370cSMatthew Dillon 
1263133c5e3SMatthew Dillon 	error = !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
127848b370cSMatthew Dillon 
128848b370cSMatthew Dillon finish:
129848b370cSMatthew Dillon 	ATH_LOCK(sc);
130d98a0bcfSMatthew Dillon 	ath_power_restore_power_state(sc);
131848b370cSMatthew Dillon 	ATH_UNLOCK(sc);
132848b370cSMatthew Dillon 
133572ff6f6SMatthew Dillon 	return error;
134572ff6f6SMatthew Dillon }
135572ff6f6SMatthew Dillon 
136572ff6f6SMatthew Dillon static int
ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)137572ff6f6SMatthew Dillon ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
138572ff6f6SMatthew Dillon {
139572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
140b14ca477SMatthew Dillon 	u_int acktimeout;
141572ff6f6SMatthew Dillon 	int error;
142572ff6f6SMatthew Dillon 
143b14ca477SMatthew Dillon 	ATH_LOCK(sc);
144b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
145b14ca477SMatthew Dillon 	acktimeout = ath_hal_getacktimeout(sc->sc_ah);
146b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
147b14ca477SMatthew Dillon 
148572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &acktimeout, 0, req);
149848b370cSMatthew Dillon 	if (error || !req->newptr)
150b14ca477SMatthew Dillon 		goto finish;
151b14ca477SMatthew Dillon 
152b14ca477SMatthew Dillon 	error = !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
153b14ca477SMatthew Dillon 
154b14ca477SMatthew Dillon finish:
155b14ca477SMatthew Dillon 	ATH_LOCK(sc);
156b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
157b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
158b14ca477SMatthew Dillon 
159b14ca477SMatthew Dillon 	return (error);
160572ff6f6SMatthew Dillon }
161572ff6f6SMatthew Dillon 
162572ff6f6SMatthew Dillon static int
ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)163572ff6f6SMatthew Dillon ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
164572ff6f6SMatthew Dillon {
165572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
166b14ca477SMatthew Dillon 	u_int ctstimeout;
167572ff6f6SMatthew Dillon 	int error;
168572ff6f6SMatthew Dillon 
169b14ca477SMatthew Dillon 	ATH_LOCK(sc);
170b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
171b14ca477SMatthew Dillon 	ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
172b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
173b14ca477SMatthew Dillon 
174572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
175848b370cSMatthew Dillon 	if (error || !req->newptr)
176b14ca477SMatthew Dillon 		goto finish;
177b14ca477SMatthew Dillon 
178b14ca477SMatthew Dillon 	error = !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
179b14ca477SMatthew Dillon 
180b14ca477SMatthew Dillon finish:
181b14ca477SMatthew Dillon 	ATH_LOCK(sc);
182b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
183b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
184b14ca477SMatthew Dillon 
185b14ca477SMatthew Dillon 	return (error);
186572ff6f6SMatthew Dillon }
187572ff6f6SMatthew Dillon 
188572ff6f6SMatthew Dillon static int
ath_sysctl_softled(SYSCTL_HANDLER_ARGS)189572ff6f6SMatthew Dillon ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
190572ff6f6SMatthew Dillon {
191572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
192848b370cSMatthew Dillon 	int softled = sc->sc_softled;
193572ff6f6SMatthew Dillon 	int error;
194572ff6f6SMatthew Dillon 
195572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &softled, 0, req);
196572ff6f6SMatthew Dillon 	if (error || !req->newptr)
197848b370cSMatthew Dillon 		return error;
198572ff6f6SMatthew Dillon 	softled = (softled != 0);
199572ff6f6SMatthew Dillon 	if (softled != sc->sc_softled) {
200572ff6f6SMatthew Dillon 		if (softled) {
201572ff6f6SMatthew Dillon 			/* NB: handle any sc_ledpin change */
202572ff6f6SMatthew Dillon 			ath_led_config(sc);
203572ff6f6SMatthew Dillon 		}
204572ff6f6SMatthew Dillon 		sc->sc_softled = softled;
205572ff6f6SMatthew Dillon 	}
206848b370cSMatthew Dillon 	return 0;
207572ff6f6SMatthew Dillon }
208572ff6f6SMatthew Dillon 
209572ff6f6SMatthew Dillon static int
ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)210572ff6f6SMatthew Dillon ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
211572ff6f6SMatthew Dillon {
212572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
213848b370cSMatthew Dillon 	int ledpin = sc->sc_ledpin;
214572ff6f6SMatthew Dillon 	int error;
215572ff6f6SMatthew Dillon 
216572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &ledpin, 0, req);
217572ff6f6SMatthew Dillon 	if (error || !req->newptr)
218848b370cSMatthew Dillon 		return error;
219572ff6f6SMatthew Dillon 	if (ledpin != sc->sc_ledpin) {
220572ff6f6SMatthew Dillon 		sc->sc_ledpin = ledpin;
221572ff6f6SMatthew Dillon 		if (sc->sc_softled) {
222572ff6f6SMatthew Dillon 			ath_led_config(sc);
223572ff6f6SMatthew Dillon 		}
224572ff6f6SMatthew Dillon 	}
225848b370cSMatthew Dillon 	return 0;
226572ff6f6SMatthew Dillon }
227572ff6f6SMatthew Dillon 
228572ff6f6SMatthew Dillon static int
ath_sysctl_hardled(SYSCTL_HANDLER_ARGS)229572ff6f6SMatthew Dillon ath_sysctl_hardled(SYSCTL_HANDLER_ARGS)
230572ff6f6SMatthew Dillon {
231572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
232848b370cSMatthew Dillon 	int hardled = sc->sc_hardled;
233572ff6f6SMatthew Dillon 	int error;
234572ff6f6SMatthew Dillon 
235572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &hardled, 0, req);
236572ff6f6SMatthew Dillon 	if (error || !req->newptr)
237848b370cSMatthew Dillon 		return error;
238572ff6f6SMatthew Dillon 	hardled = (hardled != 0);
239572ff6f6SMatthew Dillon 	if (hardled != sc->sc_hardled) {
240572ff6f6SMatthew Dillon 		if (hardled) {
241572ff6f6SMatthew Dillon 			/* NB: handle any sc_ledpin change */
242572ff6f6SMatthew Dillon 			ath_led_config(sc);
243572ff6f6SMatthew Dillon 		}
244572ff6f6SMatthew Dillon 		sc->sc_hardled = hardled;
245572ff6f6SMatthew Dillon 	}
246848b370cSMatthew Dillon 	return 0;
247572ff6f6SMatthew Dillon }
248572ff6f6SMatthew Dillon 
249572ff6f6SMatthew Dillon static int
ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)250572ff6f6SMatthew Dillon ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
251572ff6f6SMatthew Dillon {
252572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
253b14ca477SMatthew Dillon 	u_int txantenna;
254572ff6f6SMatthew Dillon 	int error;
255572ff6f6SMatthew Dillon 
256b14ca477SMatthew Dillon 	ATH_LOCK(sc);
257b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
258b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
259b14ca477SMatthew Dillon 
260b14ca477SMatthew Dillon 	txantenna = ath_hal_getantennaswitch(sc->sc_ah);
261b14ca477SMatthew Dillon 
262572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &txantenna, 0, req);
263572ff6f6SMatthew Dillon 	if (!error && req->newptr) {
264572ff6f6SMatthew Dillon 		/* XXX assumes 2 antenna ports */
265b14ca477SMatthew Dillon 		if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B) {
266b14ca477SMatthew Dillon 			error = EINVAL;
267b14ca477SMatthew Dillon 			goto finish;
268b14ca477SMatthew Dillon 		}
269572ff6f6SMatthew Dillon 		ath_hal_setantennaswitch(sc->sc_ah, txantenna);
270572ff6f6SMatthew Dillon 		/*
271572ff6f6SMatthew Dillon 		 * NB: with the switch locked this isn't meaningful,
272572ff6f6SMatthew Dillon 		 *     but set it anyway so things like radiotap get
273572ff6f6SMatthew Dillon 		 *     consistent info in their data.
274572ff6f6SMatthew Dillon 		 */
275572ff6f6SMatthew Dillon 		sc->sc_txantenna = txantenna;
276572ff6f6SMatthew Dillon 	}
277b14ca477SMatthew Dillon 
278b14ca477SMatthew Dillon finish:
279b14ca477SMatthew Dillon 	ATH_LOCK(sc);
280b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
281b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
282b14ca477SMatthew Dillon 
283b14ca477SMatthew Dillon 	return (error);
284572ff6f6SMatthew Dillon }
285572ff6f6SMatthew Dillon 
286572ff6f6SMatthew Dillon static int
ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)287572ff6f6SMatthew Dillon ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
288572ff6f6SMatthew Dillon {
289572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
290b14ca477SMatthew Dillon 	u_int defantenna;
291572ff6f6SMatthew Dillon 	int error;
292572ff6f6SMatthew Dillon 
293b14ca477SMatthew Dillon 	ATH_LOCK(sc);
294b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
295b14ca477SMatthew Dillon 	defantenna = ath_hal_getdefantenna(sc->sc_ah);
296b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
297b14ca477SMatthew Dillon 
298572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &defantenna, 0, req);
299572ff6f6SMatthew Dillon 	if (!error && req->newptr)
300572ff6f6SMatthew Dillon 		ath_hal_setdefantenna(sc->sc_ah, defantenna);
301b14ca477SMatthew Dillon 
302b14ca477SMatthew Dillon 	ATH_LOCK(sc);
303b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
304b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
305b14ca477SMatthew Dillon 
306b14ca477SMatthew Dillon 	return (error);
307572ff6f6SMatthew Dillon }
308572ff6f6SMatthew Dillon 
309572ff6f6SMatthew Dillon static int
ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)310572ff6f6SMatthew Dillon ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
311572ff6f6SMatthew Dillon {
312572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
313b14ca477SMatthew Dillon 	u_int diversity;
314572ff6f6SMatthew Dillon 	int error;
315572ff6f6SMatthew Dillon 
316b14ca477SMatthew Dillon 	ATH_LOCK(sc);
317b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
318b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
319b14ca477SMatthew Dillon 
320b14ca477SMatthew Dillon 	diversity = ath_hal_getdiversity(sc->sc_ah);
321b14ca477SMatthew Dillon 
322572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &diversity, 0, req);
323572ff6f6SMatthew Dillon 	if (error || !req->newptr)
324b14ca477SMatthew Dillon 		goto finish;
325b14ca477SMatthew Dillon 	if (!ath_hal_setdiversity(sc->sc_ah, diversity)) {
326b14ca477SMatthew Dillon 		error = EINVAL;
327b14ca477SMatthew Dillon 		goto finish;
328b14ca477SMatthew Dillon 	}
329848b370cSMatthew Dillon 	sc->sc_diversity = diversity;
330b14ca477SMatthew Dillon 	error = 0;
331b14ca477SMatthew Dillon 
332b14ca477SMatthew Dillon finish:
333b14ca477SMatthew Dillon 	ATH_LOCK(sc);
334b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
335b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
336b14ca477SMatthew Dillon 
337b14ca477SMatthew Dillon 	return (error);
338572ff6f6SMatthew Dillon }
339572ff6f6SMatthew Dillon 
340572ff6f6SMatthew Dillon static int
ath_sysctl_diag(SYSCTL_HANDLER_ARGS)341572ff6f6SMatthew Dillon ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
342572ff6f6SMatthew Dillon {
343572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
344572ff6f6SMatthew Dillon 	u_int32_t diag;
345572ff6f6SMatthew Dillon 	int error;
346572ff6f6SMatthew Dillon 
347b14ca477SMatthew Dillon 	ATH_LOCK(sc);
348b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
349b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
350b14ca477SMatthew Dillon 
351b14ca477SMatthew Dillon 	if (!ath_hal_getdiag(sc->sc_ah, &diag)) {
352b14ca477SMatthew Dillon 		error = EINVAL;
353b14ca477SMatthew Dillon 		goto finish;
354b14ca477SMatthew Dillon 	}
355b14ca477SMatthew Dillon 
356572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &diag, 0, req);
357572ff6f6SMatthew Dillon 	if (error || !req->newptr)
358b14ca477SMatthew Dillon 		goto finish;
359b14ca477SMatthew Dillon 	error = !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
360b14ca477SMatthew Dillon 
361b14ca477SMatthew Dillon finish:
362b14ca477SMatthew Dillon 	ATH_LOCK(sc);
363b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
364b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
365b14ca477SMatthew Dillon 
366b14ca477SMatthew Dillon 	return (error);
367572ff6f6SMatthew Dillon }
368572ff6f6SMatthew Dillon 
369572ff6f6SMatthew Dillon static int
ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)370572ff6f6SMatthew Dillon ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
371572ff6f6SMatthew Dillon {
372572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
373572ff6f6SMatthew Dillon 	u_int32_t scale;
374572ff6f6SMatthew Dillon 	int error;
375572ff6f6SMatthew Dillon 
376b14ca477SMatthew Dillon 	ATH_LOCK(sc);
377b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
378b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
379b14ca477SMatthew Dillon 
380572ff6f6SMatthew Dillon 	(void) ath_hal_gettpscale(sc->sc_ah, &scale);
381572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &scale, 0, req);
382572ff6f6SMatthew Dillon 	if (error || !req->newptr)
383b14ca477SMatthew Dillon 		goto finish;
384b14ca477SMatthew Dillon 
385b14ca477SMatthew Dillon 	error = !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL :
386b14ca477SMatthew Dillon 	    (sc->sc_running) ? ath_reset(sc, ATH_RESET_NOLOSS) : 0;
387b14ca477SMatthew Dillon 
388b14ca477SMatthew Dillon finish:
389b14ca477SMatthew Dillon 	ATH_LOCK(sc);
390b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
391b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
392b14ca477SMatthew Dillon 
393b14ca477SMatthew Dillon 	return (error);
394572ff6f6SMatthew Dillon }
395572ff6f6SMatthew Dillon 
396572ff6f6SMatthew Dillon static int
ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)397572ff6f6SMatthew Dillon ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
398572ff6f6SMatthew Dillon {
399572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
400b14ca477SMatthew Dillon 	u_int tpc;
401572ff6f6SMatthew Dillon 	int error;
402572ff6f6SMatthew Dillon 
403b14ca477SMatthew Dillon 	ATH_LOCK(sc);
404b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
405b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
406b14ca477SMatthew Dillon 
407b14ca477SMatthew Dillon 	tpc = ath_hal_gettpc(sc->sc_ah);
408b14ca477SMatthew Dillon 
409572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &tpc, 0, req);
410572ff6f6SMatthew Dillon 	if (error || !req->newptr)
411b14ca477SMatthew Dillon 		goto finish;
412b14ca477SMatthew Dillon 	error = !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
413b14ca477SMatthew Dillon 
414b14ca477SMatthew Dillon finish:
415b14ca477SMatthew Dillon 	ATH_LOCK(sc);
416b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
417b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
418b14ca477SMatthew Dillon 
419b14ca477SMatthew Dillon 	return (error);
420572ff6f6SMatthew Dillon }
421572ff6f6SMatthew Dillon 
422572ff6f6SMatthew Dillon static int
ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)423572ff6f6SMatthew Dillon ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
424572ff6f6SMatthew Dillon {
425572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
426572ff6f6SMatthew Dillon 	struct ath_hal *ah = sc->sc_ah;
427b14ca477SMatthew Dillon 	u_int rfkill;
428572ff6f6SMatthew Dillon 	int error;
429572ff6f6SMatthew Dillon 
430b14ca477SMatthew Dillon 	ATH_LOCK(sc);
431b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
432b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
433b14ca477SMatthew Dillon 
434b14ca477SMatthew Dillon 	rfkill = ath_hal_getrfkill(ah);
435b14ca477SMatthew Dillon 
436572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &rfkill, 0, req);
437572ff6f6SMatthew Dillon 	if (error || !req->newptr)
438b14ca477SMatthew Dillon 		goto finish;
439b14ca477SMatthew Dillon 	if (rfkill == ath_hal_getrfkill(ah)) {	/* unchanged */
440b14ca477SMatthew Dillon 		error = 0;
441b14ca477SMatthew Dillon 		goto finish;
442b14ca477SMatthew Dillon 	}
443b14ca477SMatthew Dillon 	if (!ath_hal_setrfkill(ah, rfkill)) {
444b14ca477SMatthew Dillon 		error = EINVAL;
445b14ca477SMatthew Dillon 		goto finish;
446b14ca477SMatthew Dillon 	}
447b14ca477SMatthew Dillon 	error = sc->sc_running ? ath_reset(sc, ATH_RESET_FULL) : 0;
448b14ca477SMatthew Dillon 
449b14ca477SMatthew Dillon finish:
450b14ca477SMatthew Dillon 	ATH_LOCK(sc);
451b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
452b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
453b14ca477SMatthew Dillon 
454b14ca477SMatthew Dillon 	return (error);
455572ff6f6SMatthew Dillon }
456572ff6f6SMatthew Dillon 
457572ff6f6SMatthew Dillon static int
ath_sysctl_txagg(SYSCTL_HANDLER_ARGS)458572ff6f6SMatthew Dillon ath_sysctl_txagg(SYSCTL_HANDLER_ARGS)
459572ff6f6SMatthew Dillon {
460572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
461572ff6f6SMatthew Dillon 	int i, t, param = 0;
462572ff6f6SMatthew Dillon 	int error;
463572ff6f6SMatthew Dillon 	struct ath_buf *bf;
464572ff6f6SMatthew Dillon 
465572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &param, 0, req);
466572ff6f6SMatthew Dillon 	if (error || !req->newptr)
467572ff6f6SMatthew Dillon 		return error;
468572ff6f6SMatthew Dillon 
469572ff6f6SMatthew Dillon 	if (param != 1)
470572ff6f6SMatthew Dillon 		return 0;
471572ff6f6SMatthew Dillon 
472dc249793SMatthew Dillon 	kprintf("no tx bufs (empty list): %d\n", sc->sc_stats.ast_tx_getnobuf);
473dc249793SMatthew Dillon 	kprintf("no tx bufs (was busy): %d\n", sc->sc_stats.ast_tx_getbusybuf);
474572ff6f6SMatthew Dillon 
475dc249793SMatthew Dillon 	kprintf("aggr single packet: %d\n",
476572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_single_pkt);
477dc249793SMatthew Dillon 	kprintf("aggr single packet w/ BAW closed: %d\n",
478572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_baw_closed_single_pkt);
479dc249793SMatthew Dillon 	kprintf("aggr non-baw packet: %d\n",
480572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_nonbaw_pkt);
481dc249793SMatthew Dillon 	kprintf("aggr aggregate packet: %d\n",
482572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_aggr_pkt);
483dc249793SMatthew Dillon 	kprintf("aggr single packet low hwq: %d\n",
484572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_low_hwq_single_pkt);
485dc249793SMatthew Dillon 	kprintf("aggr single packet RTS aggr limited: %d\n",
486572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_rts_aggr_limited);
487dc249793SMatthew Dillon 	kprintf("aggr sched, no work: %d\n",
488572ff6f6SMatthew Dillon 	    sc->sc_aggr_stats.aggr_sched_nopkt);
489572ff6f6SMatthew Dillon 	for (i = 0; i < 64; i++) {
490dc249793SMatthew Dillon 		kprintf("%2d: %10d ", i, sc->sc_aggr_stats.aggr_pkts[i]);
491572ff6f6SMatthew Dillon 		if (i % 4 == 3)
492dc249793SMatthew Dillon 			kprintf("\n");
493572ff6f6SMatthew Dillon 	}
494dc249793SMatthew Dillon 	kprintf("\n");
495572ff6f6SMatthew Dillon 
496572ff6f6SMatthew Dillon 	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
497572ff6f6SMatthew Dillon 		if (ATH_TXQ_SETUP(sc, i)) {
498dc249793SMatthew Dillon 			kprintf("HW TXQ %d: axq_depth=%d, axq_aggr_depth=%d, "
499572ff6f6SMatthew Dillon 			    "axq_fifo_depth=%d, holdingbf=%p\n",
500572ff6f6SMatthew Dillon 			    i,
501572ff6f6SMatthew Dillon 			    sc->sc_txq[i].axq_depth,
502572ff6f6SMatthew Dillon 			    sc->sc_txq[i].axq_aggr_depth,
503572ff6f6SMatthew Dillon 			    sc->sc_txq[i].axq_fifo_depth,
504572ff6f6SMatthew Dillon 			    sc->sc_txq[i].axq_holdingbf);
505572ff6f6SMatthew Dillon 		}
506572ff6f6SMatthew Dillon 	}
507572ff6f6SMatthew Dillon 
508572ff6f6SMatthew Dillon 	i = t = 0;
509572ff6f6SMatthew Dillon 	ATH_TXBUF_LOCK(sc);
510572ff6f6SMatthew Dillon 	TAILQ_FOREACH(bf, &sc->sc_txbuf, bf_list) {
511572ff6f6SMatthew Dillon 		if (bf->bf_flags & ATH_BUF_BUSY) {
512dc249793SMatthew Dillon 			kprintf("Busy: %d\n", t);
513572ff6f6SMatthew Dillon 			i++;
514572ff6f6SMatthew Dillon 		}
515572ff6f6SMatthew Dillon 		t++;
516572ff6f6SMatthew Dillon 	}
517572ff6f6SMatthew Dillon 	ATH_TXBUF_UNLOCK(sc);
518dc249793SMatthew Dillon 	kprintf("Total TX buffers: %d; Total TX buffers busy: %d (%d)\n",
519572ff6f6SMatthew Dillon 	    t, i, sc->sc_txbuf_cnt);
520572ff6f6SMatthew Dillon 
521572ff6f6SMatthew Dillon 	i = t = 0;
522572ff6f6SMatthew Dillon 	ATH_TXBUF_LOCK(sc);
523572ff6f6SMatthew Dillon 	TAILQ_FOREACH(bf, &sc->sc_txbuf_mgmt, bf_list) {
524572ff6f6SMatthew Dillon 		if (bf->bf_flags & ATH_BUF_BUSY) {
525dc249793SMatthew Dillon 			kprintf("Busy: %d\n", t);
526572ff6f6SMatthew Dillon 			i++;
527572ff6f6SMatthew Dillon 		}
528572ff6f6SMatthew Dillon 		t++;
529572ff6f6SMatthew Dillon 	}
530572ff6f6SMatthew Dillon 	ATH_TXBUF_UNLOCK(sc);
531dc249793SMatthew Dillon 	kprintf("Total mgmt TX buffers: %d; Total mgmt TX buffers busy: %d\n",
532572ff6f6SMatthew Dillon 	    t, i);
533572ff6f6SMatthew Dillon 
534572ff6f6SMatthew Dillon 	ATH_RX_LOCK(sc);
535572ff6f6SMatthew Dillon 	for (i = 0; i < 2; i++) {
536dc249793SMatthew Dillon 		kprintf("%d: fifolen: %d/%d; head=%d; tail=%d; m_pending=%p, m_holdbf=%p\n",
537572ff6f6SMatthew Dillon 		    i,
538572ff6f6SMatthew Dillon 		    sc->sc_rxedma[i].m_fifo_depth,
539572ff6f6SMatthew Dillon 		    sc->sc_rxedma[i].m_fifolen,
540572ff6f6SMatthew Dillon 		    sc->sc_rxedma[i].m_fifo_head,
5413ca56885SMatthew Dillon 		    sc->sc_rxedma[i].m_fifo_tail,
5423ca56885SMatthew Dillon 		    sc->sc_rxedma[i].m_rxpending,
5433ca56885SMatthew Dillon 		    sc->sc_rxedma[i].m_holdbf);
544572ff6f6SMatthew Dillon 	}
545572ff6f6SMatthew Dillon 	i = 0;
546572ff6f6SMatthew Dillon 	TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
547572ff6f6SMatthew Dillon 		i++;
548572ff6f6SMatthew Dillon 	}
549dc249793SMatthew Dillon 	kprintf("Total RX buffers in free list: %d buffers\n",
550572ff6f6SMatthew Dillon 	    i);
551572ff6f6SMatthew Dillon 	ATH_RX_UNLOCK(sc);
552572ff6f6SMatthew Dillon 
553572ff6f6SMatthew Dillon 	return 0;
554572ff6f6SMatthew Dillon }
555572ff6f6SMatthew Dillon 
556572ff6f6SMatthew Dillon static int
ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)557572ff6f6SMatthew Dillon ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
558572ff6f6SMatthew Dillon {
559572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
560572ff6f6SMatthew Dillon 	u_int rfsilent;
561572ff6f6SMatthew Dillon 	int error;
562572ff6f6SMatthew Dillon 
563b14ca477SMatthew Dillon 	ATH_LOCK(sc);
564b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
565b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
566b14ca477SMatthew Dillon 
567572ff6f6SMatthew Dillon 	(void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
568572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &rfsilent, 0, req);
569572ff6f6SMatthew Dillon 	if (error || !req->newptr)
570b14ca477SMatthew Dillon 		goto finish;
571b14ca477SMatthew Dillon 	if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent)) {
572b14ca477SMatthew Dillon 		error = EINVAL;
573b14ca477SMatthew Dillon 		goto finish;
574b14ca477SMatthew Dillon 	}
575848b370cSMatthew Dillon 	/*
576848b370cSMatthew Dillon 	 * Earlier chips (< AR5212) have up to 8 GPIO
577848b370cSMatthew Dillon 	 * pins exposed.
578848b370cSMatthew Dillon 	 *
579848b370cSMatthew Dillon 	 * AR5416 and later chips have many more GPIO
580848b370cSMatthew Dillon 	 * pins (up to 16) so the mask is expanded to
581848b370cSMatthew Dillon 	 * four bits.
582848b370cSMatthew Dillon 	 */
583848b370cSMatthew Dillon 	sc->sc_rfsilentpin = rfsilent & 0x3c;
584848b370cSMatthew Dillon 	sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
585b14ca477SMatthew Dillon 	error = 0;
586b14ca477SMatthew Dillon 
587b14ca477SMatthew Dillon finish:
588b14ca477SMatthew Dillon 	ATH_LOCK(sc);
589b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
590b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
591b14ca477SMatthew Dillon 
592b14ca477SMatthew Dillon 	return (error);
593572ff6f6SMatthew Dillon }
594572ff6f6SMatthew Dillon 
595572ff6f6SMatthew Dillon static int
ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)596572ff6f6SMatthew Dillon ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
597572ff6f6SMatthew Dillon {
598572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
599572ff6f6SMatthew Dillon 	u_int32_t tpack;
600572ff6f6SMatthew Dillon 	int error;
601572ff6f6SMatthew Dillon 
602b14ca477SMatthew Dillon 	ATH_LOCK(sc);
603b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
604b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
605b14ca477SMatthew Dillon 
606572ff6f6SMatthew Dillon 	(void) ath_hal_gettpack(sc->sc_ah, &tpack);
607572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &tpack, 0, req);
608572ff6f6SMatthew Dillon 	if (error || !req->newptr)
609b14ca477SMatthew Dillon 		goto finish;
610b14ca477SMatthew Dillon 	error = !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
611b14ca477SMatthew Dillon 
612b14ca477SMatthew Dillon finish:
613b14ca477SMatthew Dillon 	ATH_LOCK(sc);
614b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
615b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
616b14ca477SMatthew Dillon 
617b14ca477SMatthew Dillon 	return (error);
618572ff6f6SMatthew Dillon }
619572ff6f6SMatthew Dillon 
620572ff6f6SMatthew Dillon static int
ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)621572ff6f6SMatthew Dillon ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
622572ff6f6SMatthew Dillon {
623572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
624572ff6f6SMatthew Dillon 	u_int32_t tpcts;
625572ff6f6SMatthew Dillon 	int error;
626572ff6f6SMatthew Dillon 
627b14ca477SMatthew Dillon 	ATH_LOCK(sc);
628b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
629b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
630b14ca477SMatthew Dillon 
631572ff6f6SMatthew Dillon 	(void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
632572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &tpcts, 0, req);
633572ff6f6SMatthew Dillon 	if (error || !req->newptr)
634b14ca477SMatthew Dillon 		goto finish;
635b14ca477SMatthew Dillon 
636b14ca477SMatthew Dillon 	error = !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
637b14ca477SMatthew Dillon 
638b14ca477SMatthew Dillon finish:
639b14ca477SMatthew Dillon 	ATH_LOCK(sc);
640b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
641b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
642b14ca477SMatthew Dillon 
643b14ca477SMatthew Dillon 	return (error);
644572ff6f6SMatthew Dillon }
645572ff6f6SMatthew Dillon 
646572ff6f6SMatthew Dillon static int
ath_sysctl_intmit(SYSCTL_HANDLER_ARGS)647572ff6f6SMatthew Dillon ath_sysctl_intmit(SYSCTL_HANDLER_ARGS)
648572ff6f6SMatthew Dillon {
649572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
650572ff6f6SMatthew Dillon 	int intmit, error;
651572ff6f6SMatthew Dillon 
652b14ca477SMatthew Dillon 	ATH_LOCK(sc);
653b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
654b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
655b14ca477SMatthew Dillon 
656572ff6f6SMatthew Dillon 	intmit = ath_hal_getintmit(sc->sc_ah);
657572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &intmit, 0, req);
658572ff6f6SMatthew Dillon 	if (error || !req->newptr)
659b14ca477SMatthew Dillon 		goto finish;
660572ff6f6SMatthew Dillon 
661572ff6f6SMatthew Dillon 	/* reusing error; 1 here means "good"; 0 means "fail" */
662572ff6f6SMatthew Dillon 	error = ath_hal_setintmit(sc->sc_ah, intmit);
663b14ca477SMatthew Dillon 	if (! error) {
664b14ca477SMatthew Dillon 		error = EINVAL;
665b14ca477SMatthew Dillon 		goto finish;
666b14ca477SMatthew Dillon 	}
667572ff6f6SMatthew Dillon 
668572ff6f6SMatthew Dillon 	/*
669572ff6f6SMatthew Dillon 	 * Reset the hardware here - disabling ANI in the HAL
670572ff6f6SMatthew Dillon 	 * doesn't reset ANI related registers, so it'll leave
671572ff6f6SMatthew Dillon 	 * things in an inconsistent state.
672572ff6f6SMatthew Dillon 	 */
673b14ca477SMatthew Dillon 	if (sc->sc_running)
674b14ca477SMatthew Dillon 		ath_reset(sc, ATH_RESET_NOLOSS);
675848b370cSMatthew Dillon 
676b14ca477SMatthew Dillon 	error = 0;
677b14ca477SMatthew Dillon 
678b14ca477SMatthew Dillon finish:
679b14ca477SMatthew Dillon 	ATH_LOCK(sc);
680b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
681b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
682b14ca477SMatthew Dillon 
683b14ca477SMatthew Dillon 	return (error);
684572ff6f6SMatthew Dillon }
685572ff6f6SMatthew Dillon 
686572ff6f6SMatthew Dillon #ifdef IEEE80211_SUPPORT_TDMA
687572ff6f6SMatthew Dillon static int
ath_sysctl_setcca(SYSCTL_HANDLER_ARGS)688572ff6f6SMatthew Dillon ath_sysctl_setcca(SYSCTL_HANDLER_ARGS)
689572ff6f6SMatthew Dillon {
690572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
691572ff6f6SMatthew Dillon 	int setcca, error;
692572ff6f6SMatthew Dillon 
693572ff6f6SMatthew Dillon 	setcca = sc->sc_setcca;
694572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &setcca, 0, req);
695572ff6f6SMatthew Dillon 	if (error || !req->newptr)
6963133c5e3SMatthew Dillon 		return error;
697848b370cSMatthew Dillon 	sc->sc_setcca = (setcca != 0);
698848b370cSMatthew Dillon 	return 0;
699572ff6f6SMatthew Dillon }
700572ff6f6SMatthew Dillon #endif /* IEEE80211_SUPPORT_TDMA */
701572ff6f6SMatthew Dillon 
702572ff6f6SMatthew Dillon static int
ath_sysctl_forcebstuck(SYSCTL_HANDLER_ARGS)703572ff6f6SMatthew Dillon ath_sysctl_forcebstuck(SYSCTL_HANDLER_ARGS)
704572ff6f6SMatthew Dillon {
705572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
706572ff6f6SMatthew Dillon 	int val = 0;
707572ff6f6SMatthew Dillon 	int error;
708572ff6f6SMatthew Dillon 
709572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &val, 0, req);
710572ff6f6SMatthew Dillon 	if (error || !req->newptr)
7113133c5e3SMatthew Dillon 		return error;
712848b370cSMatthew Dillon 	if (val == 0)
713848b370cSMatthew Dillon 		return 0;
714848b370cSMatthew Dillon 
715848b370cSMatthew Dillon 	taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
716848b370cSMatthew Dillon 	val = 0;
717848b370cSMatthew Dillon 	return 0;
718572ff6f6SMatthew Dillon }
719572ff6f6SMatthew Dillon 
720572ff6f6SMatthew Dillon static int
ath_sysctl_hangcheck(SYSCTL_HANDLER_ARGS)721572ff6f6SMatthew Dillon ath_sysctl_hangcheck(SYSCTL_HANDLER_ARGS)
722572ff6f6SMatthew Dillon {
723572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
724572ff6f6SMatthew Dillon 	int val = 0;
725572ff6f6SMatthew Dillon 	int error;
726572ff6f6SMatthew Dillon 	uint32_t mask = 0xffffffff;
727572ff6f6SMatthew Dillon 	uint32_t *sp;
728572ff6f6SMatthew Dillon 	uint32_t rsize;
729572ff6f6SMatthew Dillon 	struct ath_hal *ah = sc->sc_ah;
730572ff6f6SMatthew Dillon 
731572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &val, 0, req);
732572ff6f6SMatthew Dillon 	if (error || !req->newptr)
733572ff6f6SMatthew Dillon 		return error;
734572ff6f6SMatthew Dillon 	if (val == 0)
735572ff6f6SMatthew Dillon 		return 0;
736572ff6f6SMatthew Dillon 
737b14ca477SMatthew Dillon 	ATH_LOCK(sc);
738b14ca477SMatthew Dillon 	ath_power_set_power_state(sc, HAL_PM_AWAKE);
739b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
740b14ca477SMatthew Dillon 
741572ff6f6SMatthew Dillon 	/* Do a hang check */
742572ff6f6SMatthew Dillon 	if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS,
743572ff6f6SMatthew Dillon 	    &mask, sizeof(mask),
744b14ca477SMatthew Dillon 	    (void *) &sp, &rsize)) {
745b14ca477SMatthew Dillon 		error = 0;
746b14ca477SMatthew Dillon 		goto finish;
747b14ca477SMatthew Dillon 	}
748b14ca477SMatthew Dillon 
749572ff6f6SMatthew Dillon 	device_printf(sc->sc_dev, "%s: sp=0x%08x\n", __func__, *sp);
750572ff6f6SMatthew Dillon 
751572ff6f6SMatthew Dillon 	val = 0;
752b14ca477SMatthew Dillon 	error = 0;
753b14ca477SMatthew Dillon finish:
754b14ca477SMatthew Dillon 	ATH_LOCK(sc);
755b14ca477SMatthew Dillon 	ath_power_restore_power_state(sc);
756b14ca477SMatthew Dillon 	ATH_UNLOCK(sc);
757b14ca477SMatthew Dillon 
758b14ca477SMatthew Dillon 	return (error);
759572ff6f6SMatthew Dillon }
760572ff6f6SMatthew Dillon 
761572ff6f6SMatthew Dillon #ifdef ATH_DEBUG_ALQ
762572ff6f6SMatthew Dillon static int
ath_sysctl_alq_log(SYSCTL_HANDLER_ARGS)763572ff6f6SMatthew Dillon ath_sysctl_alq_log(SYSCTL_HANDLER_ARGS)
764572ff6f6SMatthew Dillon {
765572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
766572ff6f6SMatthew Dillon 	int error, enable;
767572ff6f6SMatthew Dillon 
768572ff6f6SMatthew Dillon 	enable = (sc->sc_alq.sc_alq_isactive);
769848b370cSMatthew Dillon 
770572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &enable, 0, req);
771572ff6f6SMatthew Dillon 	if (error || !req->newptr)
772848b370cSMatthew Dillon 		return (error);
773848b370cSMatthew Dillon 	else if (enable)
774572ff6f6SMatthew Dillon 		error = if_ath_alq_start(&sc->sc_alq);
775572ff6f6SMatthew Dillon 	else
776572ff6f6SMatthew Dillon 		error = if_ath_alq_stop(&sc->sc_alq);
777572ff6f6SMatthew Dillon 	return (error);
778572ff6f6SMatthew Dillon }
779572ff6f6SMatthew Dillon 
780572ff6f6SMatthew Dillon /*
781572ff6f6SMatthew Dillon  * Attach the ALQ debugging if required.
782572ff6f6SMatthew Dillon  */
783572ff6f6SMatthew Dillon static void
ath_sysctl_alq_attach(struct ath_softc * sc)784572ff6f6SMatthew Dillon ath_sysctl_alq_attach(struct ath_softc *sc)
785572ff6f6SMatthew Dillon {
78626595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
78726595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
788572ff6f6SMatthew Dillon 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
789572ff6f6SMatthew Dillon 
790572ff6f6SMatthew Dillon 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "alq", CTLFLAG_RD,
791572ff6f6SMatthew Dillon 	    NULL, "Atheros ALQ logging parameters");
792572ff6f6SMatthew Dillon 	child = SYSCTL_CHILDREN(tree);
793572ff6f6SMatthew Dillon 
794572ff6f6SMatthew Dillon 	SYSCTL_ADD_STRING(ctx, child, OID_AUTO, "filename",
795572ff6f6SMatthew Dillon 	    CTLFLAG_RW, sc->sc_alq.sc_alq_filename, 0, "ALQ filename");
796572ff6f6SMatthew Dillon 
797572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
798572ff6f6SMatthew Dillon 		"enable", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
799572ff6f6SMatthew Dillon 		ath_sysctl_alq_log, "I", "");
800572ff6f6SMatthew Dillon 
801572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
802572ff6f6SMatthew Dillon 		"debugmask", CTLFLAG_RW, &sc->sc_alq.sc_alq_debug, 0,
803572ff6f6SMatthew Dillon 		"ALQ debug mask");
804572ff6f6SMatthew Dillon 
805572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
806572ff6f6SMatthew Dillon 		"numlost", CTLFLAG_RW, &sc->sc_alq.sc_alq_numlost, 0,
807572ff6f6SMatthew Dillon 		"number lost");
808572ff6f6SMatthew Dillon }
809572ff6f6SMatthew Dillon #endif /* ATH_DEBUG_ALQ */
810572ff6f6SMatthew Dillon 
811572ff6f6SMatthew Dillon void
ath_sysctlattach(struct ath_softc * sc)812572ff6f6SMatthew Dillon ath_sysctlattach(struct ath_softc *sc)
813572ff6f6SMatthew Dillon {
81426595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
81526595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
816572ff6f6SMatthew Dillon 	struct ath_hal *ah = sc->sc_ah;
817572ff6f6SMatthew Dillon 
818572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
819572ff6f6SMatthew Dillon 		"countrycode", CTLFLAG_RD, &sc->sc_eecc, 0,
820572ff6f6SMatthew Dillon 		"EEPROM country code");
821572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
822572ff6f6SMatthew Dillon 		"regdomain", CTLFLAG_RD, &sc->sc_eerd, 0,
823572ff6f6SMatthew Dillon 		"EEPROM regdomain code");
824572ff6f6SMatthew Dillon #ifdef	ATH_DEBUG
825848b370cSMatthew Dillon 	SYSCTL_ADD_QUAD(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
826848b370cSMatthew Dillon 		"debug", CTLFLAG_RW, &sc->sc_debug,
827dc249793SMatthew Dillon #if defined(__DragonFly__)
828dc249793SMatthew Dillon 		0,
829dc249793SMatthew Dillon #endif
830848b370cSMatthew Dillon 		"control debugging printfs");
831848b370cSMatthew Dillon #endif
832572ff6f6SMatthew Dillon #ifdef	ATH_DEBUG_ALQ
833848b370cSMatthew Dillon 	SYSCTL_ADD_QUAD(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
834848b370cSMatthew Dillon 		"ktrdebug", CTLFLAG_RW, &sc->sc_ktrdebug,
835dc249793SMatthew Dillon #if defined(__DragonFly__)
836dc249793SMatthew Dillon 		0,
837dc249793SMatthew Dillon #endif
838848b370cSMatthew Dillon 		"control debugging KTR");
839572ff6f6SMatthew Dillon #endif /* ATH_DEBUG_ALQ */
840572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
841572ff6f6SMatthew Dillon 		"slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
842572ff6f6SMatthew Dillon 		ath_sysctl_slottime, "I", "802.11 slot time (us)");
843572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
844572ff6f6SMatthew Dillon 		"acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
845572ff6f6SMatthew Dillon 		ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
846572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
847572ff6f6SMatthew Dillon 		"ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
848572ff6f6SMatthew Dillon 		ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
849572ff6f6SMatthew Dillon 
850572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
851572ff6f6SMatthew Dillon 		"softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
852572ff6f6SMatthew Dillon 		ath_sysctl_softled, "I", "enable/disable software LED support");
853572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
854572ff6f6SMatthew Dillon 		"ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
855572ff6f6SMatthew Dillon 		ath_sysctl_ledpin, "I", "GPIO pin connected to LED");
856572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
857572ff6f6SMatthew Dillon 		"ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
858572ff6f6SMatthew Dillon 		"setting to turn LED on");
859572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
860572ff6f6SMatthew Dillon 		"ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
861572ff6f6SMatthew Dillon 		"idle time for inactivity LED (ticks)");
862572ff6f6SMatthew Dillon 
863572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
864572ff6f6SMatthew Dillon 		"hardled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
865572ff6f6SMatthew Dillon 		ath_sysctl_hardled, "I", "enable/disable hardware LED support");
866572ff6f6SMatthew Dillon 	/* XXX Laziness - configure pins, then flip hardled off/on */
867572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
868572ff6f6SMatthew Dillon 		"led_net_pin", CTLFLAG_RW, &sc->sc_led_net_pin, 0,
869572ff6f6SMatthew Dillon 		"MAC Network LED pin, or -1 to disable");
870572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
871572ff6f6SMatthew Dillon 		"led_pwr_pin", CTLFLAG_RW, &sc->sc_led_pwr_pin, 0,
872572ff6f6SMatthew Dillon 		"MAC Power LED pin, or -1 to disable");
873572ff6f6SMatthew Dillon 
874572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
875572ff6f6SMatthew Dillon 		"txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
876572ff6f6SMatthew Dillon 		ath_sysctl_txantenna, "I", "antenna switch");
877572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
878572ff6f6SMatthew Dillon 		"rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
879572ff6f6SMatthew Dillon 		ath_sysctl_rxantenna, "I", "default/rx antenna");
880572ff6f6SMatthew Dillon 	if (ath_hal_hasdiversity(ah))
881572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
882572ff6f6SMatthew Dillon 			"diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
883572ff6f6SMatthew Dillon 			ath_sysctl_diversity, "I", "antenna diversity");
884572ff6f6SMatthew Dillon 	sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
885572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
886572ff6f6SMatthew Dillon 		"txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
887572ff6f6SMatthew Dillon 		"tx descriptor batching");
888572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
889572ff6f6SMatthew Dillon 		"diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
890572ff6f6SMatthew Dillon 		ath_sysctl_diag, "I", "h/w diagnostic control");
891572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
892572ff6f6SMatthew Dillon 		"tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
893572ff6f6SMatthew Dillon 		ath_sysctl_tpscale, "I", "tx power scaling");
894572ff6f6SMatthew Dillon 	if (ath_hal_hastpc(ah)) {
895572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
896572ff6f6SMatthew Dillon 			"tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
897572ff6f6SMatthew Dillon 			ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
898572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
899572ff6f6SMatthew Dillon 			"tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
900572ff6f6SMatthew Dillon 			ath_sysctl_tpack, "I", "tx power for ack frames");
901572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
902572ff6f6SMatthew Dillon 			"tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
903572ff6f6SMatthew Dillon 			ath_sysctl_tpcts, "I", "tx power for cts frames");
904572ff6f6SMatthew Dillon 	}
905572ff6f6SMatthew Dillon 	if (ath_hal_hasrfsilent(ah)) {
906572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
907572ff6f6SMatthew Dillon 			"rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
908572ff6f6SMatthew Dillon 			ath_sysctl_rfsilent, "I", "h/w RF silent config");
909572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
910572ff6f6SMatthew Dillon 			"rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
911572ff6f6SMatthew Dillon 			ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
912572ff6f6SMatthew Dillon 	}
913572ff6f6SMatthew Dillon 
914572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
915572ff6f6SMatthew Dillon 		"txagg", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
916572ff6f6SMatthew Dillon 		ath_sysctl_txagg, "I", "");
917572ff6f6SMatthew Dillon 
918572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
919572ff6f6SMatthew Dillon 		"forcebstuck", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
920572ff6f6SMatthew Dillon 		ath_sysctl_forcebstuck, "I", "");
921572ff6f6SMatthew Dillon 
922572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
923572ff6f6SMatthew Dillon 		"hangcheck", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
924572ff6f6SMatthew Dillon 		ath_sysctl_hangcheck, "I", "");
925572ff6f6SMatthew Dillon 
926572ff6f6SMatthew Dillon 	if (ath_hal_hasintmit(ah)) {
927572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
928572ff6f6SMatthew Dillon 			"intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
929572ff6f6SMatthew Dillon 			ath_sysctl_intmit, "I", "interference mitigation");
930572ff6f6SMatthew Dillon 	}
931572ff6f6SMatthew Dillon 	sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
932572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
933572ff6f6SMatthew Dillon 		"monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
934572ff6f6SMatthew Dillon 		"mask of error frames to pass when monitoring");
935572ff6f6SMatthew Dillon 
936572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
937572ff6f6SMatthew Dillon 		"hwq_limit_nonaggr", CTLFLAG_RW, &sc->sc_hwq_limit_nonaggr, 0,
938572ff6f6SMatthew Dillon 		"Hardware non-AMPDU queue depth before software-queuing TX frames");
939572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
940572ff6f6SMatthew Dillon 		"hwq_limit_aggr", CTLFLAG_RW, &sc->sc_hwq_limit_aggr, 0,
941572ff6f6SMatthew Dillon 		"Hardware AMPDU queue depth before software-queuing TX frames");
942572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
943572ff6f6SMatthew Dillon 		"tid_hwq_lo", CTLFLAG_RW, &sc->sc_tid_hwq_lo, 0,
944572ff6f6SMatthew Dillon 		"");
945572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
946572ff6f6SMatthew Dillon 		"tid_hwq_hi", CTLFLAG_RW, &sc->sc_tid_hwq_hi, 0,
947572ff6f6SMatthew Dillon 		"");
948572ff6f6SMatthew Dillon 
949572ff6f6SMatthew Dillon 	/* Aggregate length twiddles */
950572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
951572ff6f6SMatthew Dillon 		"aggr_limit", CTLFLAG_RW, &sc->sc_aggr_limit, 0,
952572ff6f6SMatthew Dillon 		"Maximum A-MPDU size, or 0 for 'default'");
953572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
954572ff6f6SMatthew Dillon 		"rts_aggr_limit", CTLFLAG_RW, &sc->sc_rts_aggr_limit, 0,
955572ff6f6SMatthew Dillon 		"Maximum A-MPDU size for RTS-protected frames, or '0' "
956572ff6f6SMatthew Dillon 		"for default");
957572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
958572ff6f6SMatthew Dillon 		"delim_min_pad", CTLFLAG_RW, &sc->sc_delim_min_pad, 0,
959572ff6f6SMatthew Dillon 		"Enforce a minimum number of delimiters per A-MPDU "
960572ff6f6SMatthew Dillon 		" sub-frame");
961572ff6f6SMatthew Dillon 
962572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
963572ff6f6SMatthew Dillon 		"txq_data_minfree", CTLFLAG_RW, &sc->sc_txq_data_minfree,
964572ff6f6SMatthew Dillon 		0, "Minimum free buffers before adding a data frame"
965572ff6f6SMatthew Dillon 		" to the TX queue");
966572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
967572ff6f6SMatthew Dillon 		"txq_mcastq_maxdepth", CTLFLAG_RW,
968572ff6f6SMatthew Dillon 		&sc->sc_txq_mcastq_maxdepth, 0,
969572ff6f6SMatthew Dillon 		"Maximum buffer depth for multicast/broadcast frames");
970572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
971572ff6f6SMatthew Dillon 		"txq_node_maxdepth", CTLFLAG_RW,
972572ff6f6SMatthew Dillon 		&sc->sc_txq_node_maxdepth, 0,
973572ff6f6SMatthew Dillon 		"Maximum buffer depth for a single node");
974572ff6f6SMatthew Dillon 
975572ff6f6SMatthew Dillon #if 0
976572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
977572ff6f6SMatthew Dillon 		"cabq_enable", CTLFLAG_RW,
978572ff6f6SMatthew Dillon 		&sc->sc_cabq_enable, 0,
979572ff6f6SMatthew Dillon 		"Whether to transmit on the CABQ or not");
980572ff6f6SMatthew Dillon #endif
981572ff6f6SMatthew Dillon 
982572ff6f6SMatthew Dillon #ifdef IEEE80211_SUPPORT_TDMA
983572ff6f6SMatthew Dillon 	if (ath_hal_macversion(ah) > 0x78) {
984572ff6f6SMatthew Dillon 		sc->sc_tdmadbaprep = 2;
985572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
986572ff6f6SMatthew Dillon 			"dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0,
987572ff6f6SMatthew Dillon 			"TDMA DBA preparation time");
988572ff6f6SMatthew Dillon 		sc->sc_tdmaswbaprep = 10;
989572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
990572ff6f6SMatthew Dillon 			"swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0,
991572ff6f6SMatthew Dillon 			"TDMA SWBA preparation time");
992572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
993572ff6f6SMatthew Dillon 			"guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0,
994572ff6f6SMatthew Dillon 			"TDMA slot guard time");
995572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
996572ff6f6SMatthew Dillon 			"superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0,
997572ff6f6SMatthew Dillon 			"TDMA calculated super frame");
998572ff6f6SMatthew Dillon 		SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
999572ff6f6SMatthew Dillon 			"setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
1000572ff6f6SMatthew Dillon 			ath_sysctl_setcca, "I", "enable CCA control");
1001572ff6f6SMatthew Dillon 	}
1002572ff6f6SMatthew Dillon #endif
1003572ff6f6SMatthew Dillon 
1004572ff6f6SMatthew Dillon #ifdef	ATH_DEBUG_ALQ
1005572ff6f6SMatthew Dillon 	ath_sysctl_alq_attach(sc);
1006572ff6f6SMatthew Dillon #endif
1007572ff6f6SMatthew Dillon }
1008572ff6f6SMatthew Dillon 
1009572ff6f6SMatthew Dillon static int
ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS)1010572ff6f6SMatthew Dillon ath_sysctl_clearstats(SYSCTL_HANDLER_ARGS)
1011572ff6f6SMatthew Dillon {
1012572ff6f6SMatthew Dillon 	struct ath_softc *sc = arg1;
1013572ff6f6SMatthew Dillon 	int val = 0;
1014572ff6f6SMatthew Dillon 	int error;
1015572ff6f6SMatthew Dillon 
1016572ff6f6SMatthew Dillon 	error = sysctl_handle_int(oidp, &val, 0, req);
1017572ff6f6SMatthew Dillon 	if (error || !req->newptr)
1018572ff6f6SMatthew Dillon 		return error;
1019572ff6f6SMatthew Dillon 	if (val == 0)
1020572ff6f6SMatthew Dillon 		return 0;       /* Not clearing the stats is still valid */
1021572ff6f6SMatthew Dillon 	memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
1022572ff6f6SMatthew Dillon 	memset(&sc->sc_aggr_stats, 0, sizeof(sc->sc_aggr_stats));
1023572ff6f6SMatthew Dillon 	memset(&sc->sc_intr_stats, 0, sizeof(sc->sc_intr_stats));
1024572ff6f6SMatthew Dillon 
1025572ff6f6SMatthew Dillon 	val = 0;
1026572ff6f6SMatthew Dillon 	return 0;
1027572ff6f6SMatthew Dillon }
1028572ff6f6SMatthew Dillon 
1029572ff6f6SMatthew Dillon static void
ath_sysctl_stats_attach_rxphyerr(struct ath_softc * sc,struct sysctl_oid_list * parent)1030572ff6f6SMatthew Dillon ath_sysctl_stats_attach_rxphyerr(struct ath_softc *sc, struct sysctl_oid_list *parent)
1031572ff6f6SMatthew Dillon {
103226595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
103326595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
1034572ff6f6SMatthew Dillon 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
1035572ff6f6SMatthew Dillon 	int i;
1036572ff6f6SMatthew Dillon 	char sn[8];
1037572ff6f6SMatthew Dillon 
1038572ff6f6SMatthew Dillon 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx_phy_err", CTLFLAG_RD, NULL, "Per-code RX PHY Errors");
1039572ff6f6SMatthew Dillon 	child = SYSCTL_CHILDREN(tree);
1040572ff6f6SMatthew Dillon 	for (i = 0; i < 64; i++) {
1041dc249793SMatthew Dillon 		ksnprintf(sn, sizeof(sn), "%d", i);
1042572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD, &sc->sc_stats.ast_rx_phy[i], 0, "");
1043572ff6f6SMatthew Dillon 	}
1044572ff6f6SMatthew Dillon }
1045572ff6f6SMatthew Dillon 
1046572ff6f6SMatthew Dillon static void
ath_sysctl_stats_attach_intr(struct ath_softc * sc,struct sysctl_oid_list * parent)1047572ff6f6SMatthew Dillon ath_sysctl_stats_attach_intr(struct ath_softc *sc,
1048572ff6f6SMatthew Dillon     struct sysctl_oid_list *parent)
1049572ff6f6SMatthew Dillon {
105026595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
105126595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
1052572ff6f6SMatthew Dillon 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
1053572ff6f6SMatthew Dillon 	int i;
1054572ff6f6SMatthew Dillon 	char sn[8];
1055572ff6f6SMatthew Dillon 
1056572ff6f6SMatthew Dillon 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "sync_intr",
1057572ff6f6SMatthew Dillon 	    CTLFLAG_RD, NULL, "Sync interrupt statistics");
1058572ff6f6SMatthew Dillon 	child = SYSCTL_CHILDREN(tree);
1059572ff6f6SMatthew Dillon 	for (i = 0; i < 32; i++) {
1060dc249793SMatthew Dillon 		ksnprintf(sn, sizeof(sn), "%d", i);
1061572ff6f6SMatthew Dillon 		SYSCTL_ADD_UINT(ctx, child, OID_AUTO, sn, CTLFLAG_RD,
1062572ff6f6SMatthew Dillon 		    &sc->sc_intr_stats.sync_intr[i], 0, "");
1063572ff6f6SMatthew Dillon 	}
1064572ff6f6SMatthew Dillon }
1065572ff6f6SMatthew Dillon 
1066572ff6f6SMatthew Dillon void
ath_sysctl_stats_attach(struct ath_softc * sc)1067572ff6f6SMatthew Dillon ath_sysctl_stats_attach(struct ath_softc *sc)
1068572ff6f6SMatthew Dillon {
106926595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
107026595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
1071572ff6f6SMatthew Dillon 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
1072572ff6f6SMatthew Dillon 
1073572ff6f6SMatthew Dillon 	/* Create "clear" node */
1074572ff6f6SMatthew Dillon 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
1075572ff6f6SMatthew Dillon 	    "clear_stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
1076572ff6f6SMatthew Dillon 	    ath_sysctl_clearstats, "I", "clear stats");
1077572ff6f6SMatthew Dillon 
1078572ff6f6SMatthew Dillon 	/* Create stats node */
1079572ff6f6SMatthew Dillon 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1080572ff6f6SMatthew Dillon 	    NULL, "Statistics");
1081572ff6f6SMatthew Dillon 	child = SYSCTL_CHILDREN(tree);
1082572ff6f6SMatthew Dillon 
1083572ff6f6SMatthew Dillon 	/* This was generated from if_athioctl.h */
1084572ff6f6SMatthew Dillon 
1085572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_watchdog", CTLFLAG_RD,
1086572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_watchdog, 0, "device reset by watchdog");
1087572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_hardware", CTLFLAG_RD,
1088572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_hardware, 0, "fatal hardware error interrupts");
1089572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss", CTLFLAG_RD,
1090572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_bmiss, 0, "beacon miss interrupts");
1091572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bmiss_phantom", CTLFLAG_RD,
1092572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_bmiss_phantom, 0, "beacon miss interrupts");
1093572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_bstuck", CTLFLAG_RD,
1094572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_bstuck, 0, "beacon stuck interrupts");
1095572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxorn", CTLFLAG_RD,
1096572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rxorn, 0, "rx overrun interrupts");
1097572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rxeol", CTLFLAG_RD,
1098572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rxeol, 0, "rx eol interrupts");
1099572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_txurn", CTLFLAG_RD,
1100572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_txurn, 0, "tx underrun interrupts");
1101572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_mib", CTLFLAG_RD,
1102572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_mib, 0, "mib interrupts");
1103572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_intrcoal", CTLFLAG_RD,
1104572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_intrcoal, 0, "interrupts coalesced");
1105572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_packets", CTLFLAG_RD,
1106572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_packets, 0, "packet sent on the interface");
1107572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mgmt", CTLFLAG_RD,
1108572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_mgmt, 0, "management frames transmitted");
1109572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_discard", CTLFLAG_RD,
1110572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_discard, 0, "frames discarded prior to assoc");
1111572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qstop", CTLFLAG_RD,
1112572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_qstop, 0, "output stopped 'cuz no buffer");
1113572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_encap", CTLFLAG_RD,
1114572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_encap, 0, "tx encapsulation failed");
1115572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nonode", CTLFLAG_RD,
1116572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nonode, 0, "tx failed 'cuz no node");
1117572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nombuf", CTLFLAG_RD,
1118572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nombuf, 0, "tx failed 'cuz no mbuf");
1119572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nomcl", CTLFLAG_RD,
1120572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nomcl, 0, "tx failed 'cuz no cluster");
1121572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_linear", CTLFLAG_RD,
1122572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_linear, 0, "tx linearized to cluster");
1123572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nodata", CTLFLAG_RD,
1124572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nodata, 0, "tx discarded empty frame");
1125572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_busdma", CTLFLAG_RD,
1126572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_busdma, 0, "tx failed for dma resrcs");
1127572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xretries", CTLFLAG_RD,
1128572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_xretries, 0, "tx failed 'cuz too many retries");
1129572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_fifoerr", CTLFLAG_RD,
1130572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_fifoerr, 0, "tx failed 'cuz FIFO underrun");
1131572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_filtered", CTLFLAG_RD,
1132572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_filtered, 0, "tx failed 'cuz xmit filtered");
1133572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortretry", CTLFLAG_RD,
1134572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_shortretry, 0, "tx on-chip retries (short)");
1135572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_longretry", CTLFLAG_RD,
1136572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_longretry, 0, "tx on-chip retries (long)");
1137572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_badrate", CTLFLAG_RD,
1138572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_badrate, 0, "tx failed 'cuz bogus xmit rate");
1139572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_noack", CTLFLAG_RD,
1140572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_noack, 0, "tx frames with no ack marked");
1141572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_rts", CTLFLAG_RD,
1142572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_rts, 0, "tx frames with rts enabled");
1143572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cts", CTLFLAG_RD,
1144572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_cts, 0, "tx frames with cts enabled");
1145572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_shortpre", CTLFLAG_RD,
1146572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_shortpre, 0, "tx frames with short preamble");
1147572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_altrate", CTLFLAG_RD,
1148572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_altrate, 0, "tx frames with alternate rate");
1149572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_protect", CTLFLAG_RD,
1150572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_protect, 0, "tx frames with protection");
1151572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsburst", CTLFLAG_RD,
1152572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_ctsburst, 0, "tx frames with cts and bursting");
1153572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ctsext", CTLFLAG_RD,
1154572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_ctsext, 0, "tx frames with cts extension");
1155572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_nombuf", CTLFLAG_RD,
1156572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_nombuf, 0, "rx setup failed 'cuz no mbuf");
1157572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_busdma", CTLFLAG_RD,
1158572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_busdma, 0, "rx setup failed for dma resrcs");
1159572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_orn", CTLFLAG_RD,
1160572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_orn, 0, "rx failed 'cuz of desc overrun");
1161572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_crcerr", CTLFLAG_RD,
1162572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_crcerr, 0, "rx failed 'cuz of bad CRC");
1163572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_fifoerr", CTLFLAG_RD,
1164572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_fifoerr, 0, "rx failed 'cuz of FIFO overrun");
1165572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badcrypt", CTLFLAG_RD,
1166572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_badcrypt, 0, "rx failed 'cuz decryption");
1167572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_badmic", CTLFLAG_RD,
1168572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_badmic, 0, "rx failed 'cuz MIC failure");
1169572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_phyerr", CTLFLAG_RD,
1170572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_phyerr, 0, "rx failed 'cuz of PHY err");
1171572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_tooshort", CTLFLAG_RD,
1172572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_tooshort, 0, "rx discarded 'cuz frame too short");
1173572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_toobig", CTLFLAG_RD,
1174572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_toobig, 0, "rx discarded 'cuz frame too large");
1175572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_packets", CTLFLAG_RD,
1176572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_packets, 0, "packet recv on the interface");
1177572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_mgt", CTLFLAG_RD,
1178572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_mgt, 0, "management frames received");
1179572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_ctl", CTLFLAG_RD,
1180572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_ctl, 0, "rx discarded 'cuz ctl frame");
1181572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_xmit", CTLFLAG_RD,
1182572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_be_xmit, 0, "beacons transmitted");
1183572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_nombuf", CTLFLAG_RD,
1184572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_be_nombuf, 0, "beacon setup failed 'cuz no mbuf");
1185572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_cal", CTLFLAG_RD,
1186572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_per_cal, 0, "periodic calibration calls");
1187572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_calfail", CTLFLAG_RD,
1188572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_per_calfail, 0, "periodic calibration failed");
1189572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_per_rfgain", CTLFLAG_RD,
1190572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_per_rfgain, 0, "periodic calibration rfgain reset");
1191572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_calls", CTLFLAG_RD,
1192572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rate_calls, 0, "rate control checks");
1193572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_raise", CTLFLAG_RD,
1194572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rate_raise, 0, "rate control raised xmit rate");
1195572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rate_drop", CTLFLAG_RD,
1196572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rate_drop, 0, "rate control dropped xmit rate");
1197572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_defswitch", CTLFLAG_RD,
1198572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ant_defswitch, 0, "rx/default antenna switches");
1199572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ant_txswitch", CTLFLAG_RD,
1200572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ant_txswitch, 0, "tx antenna switches");
1201572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_xmit", CTLFLAG_RD,
1202572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_cabq_xmit, 0, "cabq frames transmitted");
1203572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_cabq_busy", CTLFLAG_RD,
1204572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_cabq_busy, 0, "cabq found busy");
1205572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw", CTLFLAG_RD,
1206572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_raw, 0, "tx frames through raw api");
1207572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txok", CTLFLAG_RD,
1208572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ff_txok, 0, "fast frames tx'd successfully");
1209572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_txerr", CTLFLAG_RD,
1210572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ff_txerr, 0, "fast frames tx'd w/ error");
1211572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_rx", CTLFLAG_RD,
1212572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ff_rx, 0, "fast frames rx'd");
1213572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ff_flush", CTLFLAG_RD,
1214572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ff_flush, 0, "fast frames flushed from staging q");
1215572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_qfull", CTLFLAG_RD,
1216572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_qfull, 0, "tx dropped 'cuz of queue limit");
1217572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nobuf", CTLFLAG_RD,
1218572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nobuf, 0, "tx dropped 'cuz no ath buffer");
1219572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_update", CTLFLAG_RD,
1220572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tdma_update, 0, "TDMA slot timing updates");
1221572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_timers", CTLFLAG_RD,
1222572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tdma_timers, 0, "TDMA slot update set beacon timers");
1223572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_tsf", CTLFLAG_RD,
1224572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tdma_tsf, 0, "TDMA slot update set TSF");
1225572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tdma_ack", CTLFLAG_RD,
1226572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tdma_ack, 0, "TDMA tx failed 'cuz ACK required");
1227572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_raw_fail", CTLFLAG_RD,
1228572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_raw_fail, 0, "raw tx failed 'cuz h/w down");
1229572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_nofrag", CTLFLAG_RD,
1230572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_nofrag, 0, "tx dropped 'cuz no ath frag buffer");
1231572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_be_missed", CTLFLAG_RD,
1232572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_be_missed, 0, "number of -missed- beacons");
1233572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_ani_cal", CTLFLAG_RD,
1234572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_ani_cal, 0, "number of ANI polls");
1235572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_agg", CTLFLAG_RD,
1236572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_agg, 0, "number of aggregate frames received");
1237572ff6f6SMatthew Dillon 
1238572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_halfgi", CTLFLAG_RD,
1239572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_halfgi, 0, "number of frames received with half-GI");
1240572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_2040", CTLFLAG_RD,
1241572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_2040, 0, "number of HT/40 frames received");
1242572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_pre_crc_err", CTLFLAG_RD,
1243572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_pre_crc_err, 0, "number of delimeter-CRC errors detected");
1244572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_post_crc_err", CTLFLAG_RD,
1245572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_post_crc_err, 0, "number of post-delimiter CRC errors detected");
1246572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_decrypt_busy_err", CTLFLAG_RD,
1247572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_decrypt_busy_err, 0, "number of frames received w/ busy decrypt engine");
1248572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_hi_rx_chain", CTLFLAG_RD,
1249572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_hi_rx_chain, 0, "");
1250572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_htprotect", CTLFLAG_RD,
1251572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_htprotect, 0, "HT tx frames with protection");
1252572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_hitqueueend", CTLFLAG_RD,
1253572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_hitqueueend, 0, "RX hit queue end");
1254572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_timeout", CTLFLAG_RD,
1255572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_timeout, 0, "TX Global Timeout");
1256572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_cst", CTLFLAG_RD,
1257572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_cst, 0, "TX Carrier Sense Timeout");
1258572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_xtxop", CTLFLAG_RD,
1259572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_xtxop, 0, "TX exceeded TXOP");
1260572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_timerexpired", CTLFLAG_RD,
1261572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_timerexpired, 0, "TX exceeded TX_TIMER register");
1262572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_desccfgerr", CTLFLAG_RD,
1263572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_desccfgerr, 0, "TX Descriptor Cfg Error");
1264572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swretries", CTLFLAG_RD,
1265572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_swretries, 0, "TX software retry count");
1266572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swretrymax", CTLFLAG_RD,
1267572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_swretrymax, 0, "TX software retry max reached");
1268572ff6f6SMatthew Dillon 
1269572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_data_underrun", CTLFLAG_RD,
1270572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_data_underrun, 0, "");
1271572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_delim_underrun", CTLFLAG_RD,
1272572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_delim_underrun, 0, "");
1273572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_failall", CTLFLAG_RD,
1274572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_aggr_failall, 0,
1275572ff6f6SMatthew Dillon 	    "Number of aggregate TX failures (whole frame)");
1276572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_ok", CTLFLAG_RD,
1277572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_aggr_ok, 0,
1278572ff6f6SMatthew Dillon 	    "Number of aggregate TX OK completions (subframe)");
1279572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_aggr_fail", CTLFLAG_RD,
1280572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_aggr_fail, 0,
1281572ff6f6SMatthew Dillon 	    "Number of aggregate TX failures (subframe)");
1282572ff6f6SMatthew Dillon 
1283572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_intr", CTLFLAG_RD,
1284572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_intr, 0, "RX interrupts");
1285572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_intr", CTLFLAG_RD,
1286572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_intr, 0, "TX interrupts");
1287572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_mcastq_overflow",
1288572ff6f6SMatthew Dillon 	    CTLFLAG_RD, &sc->sc_stats.ast_tx_mcastq_overflow, 0,
1289572ff6f6SMatthew Dillon 	    "Number of multicast frames exceeding maximum mcast queue depth");
1290572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_keymiss", CTLFLAG_RD,
1291572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_rx_keymiss, 0, "");
1292572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_swfiltered", CTLFLAG_RD,
1293572ff6f6SMatthew Dillon 	    &sc->sc_stats.ast_tx_swfiltered, 0, "");
1294572ff6f6SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_rx_stbc",
1295572ff6f6SMatthew Dillon 	    CTLFLAG_RD, &sc->sc_stats.ast_rx_stbc, 0,
1296572ff6f6SMatthew Dillon 	    "Number of STBC frames received");
1297b14ca477SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_stbc",
1298b14ca477SMatthew Dillon 	    CTLFLAG_RD, &sc->sc_stats.ast_tx_stbc, 0,
1299b14ca477SMatthew Dillon 	    "Number of STBC frames transmitted");
1300b14ca477SMatthew Dillon 	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "ast_tx_ldpc",
1301b14ca477SMatthew Dillon 	    CTLFLAG_RD, &sc->sc_stats.ast_tx_ldpc, 0,
1302b14ca477SMatthew Dillon 	    "Number of LDPC frames transmitted");
1303572ff6f6SMatthew Dillon 
1304572ff6f6SMatthew Dillon 	/* Attach the RX phy error array */
1305572ff6f6SMatthew Dillon 	ath_sysctl_stats_attach_rxphyerr(sc, child);
1306572ff6f6SMatthew Dillon 
1307572ff6f6SMatthew Dillon 	/* Attach the interrupt statistics array */
1308572ff6f6SMatthew Dillon 	ath_sysctl_stats_attach_intr(sc, child);
1309572ff6f6SMatthew Dillon }
1310572ff6f6SMatthew Dillon 
1311572ff6f6SMatthew Dillon /*
1312572ff6f6SMatthew Dillon  * This doesn't necessarily belong here (because it's HAL related, not
1313572ff6f6SMatthew Dillon  * driver related).
1314572ff6f6SMatthew Dillon  */
1315572ff6f6SMatthew Dillon void
ath_sysctl_hal_attach(struct ath_softc * sc)1316572ff6f6SMatthew Dillon ath_sysctl_hal_attach(struct ath_softc *sc)
1317572ff6f6SMatthew Dillon {
131826595b18SSascha Wildner 	struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
131926595b18SSascha Wildner 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
1320572ff6f6SMatthew Dillon 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
1321572ff6f6SMatthew Dillon 
1322572ff6f6SMatthew Dillon 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "hal", CTLFLAG_RD,
1323572ff6f6SMatthew Dillon 	    NULL, "Atheros HAL parameters");
1324572ff6f6SMatthew Dillon 	child = SYSCTL_CHILDREN(tree);
1325572ff6f6SMatthew Dillon 
1326572ff6f6SMatthew Dillon 	sc->sc_ah->ah_config.ah_debug = 0;
1327572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "debug", CTLFLAG_RW,
1328572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_debug, 0, "Atheros HAL debugging printfs");
1329572ff6f6SMatthew Dillon 
1330572ff6f6SMatthew Dillon 	sc->sc_ah->ah_config.ah_ar5416_biasadj = 0;
1331572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "ar5416_biasadj", CTLFLAG_RW,
1332572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_ar5416_biasadj, 0,
1333572ff6f6SMatthew Dillon 	    "Enable 2GHz AR5416 direction sensitivity bias adjust");
1334572ff6f6SMatthew Dillon 
1335572ff6f6SMatthew Dillon 	sc->sc_ah->ah_config.ah_dma_beacon_response_time = 2;
1336572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "dma_brt", CTLFLAG_RW,
1337572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_dma_beacon_response_time, 0,
1338572ff6f6SMatthew Dillon 	    "Atheros HAL DMA beacon response time");
1339572ff6f6SMatthew Dillon 
1340572ff6f6SMatthew Dillon 	sc->sc_ah->ah_config.ah_sw_beacon_response_time = 10;
1341572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "sw_brt", CTLFLAG_RW,
1342572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_sw_beacon_response_time, 0,
1343572ff6f6SMatthew Dillon 	    "Atheros HAL software beacon response time");
1344572ff6f6SMatthew Dillon 
1345572ff6f6SMatthew Dillon 	sc->sc_ah->ah_config.ah_additional_swba_backoff = 0;
1346572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "swba_backoff", CTLFLAG_RW,
1347572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_additional_swba_backoff, 0,
1348572ff6f6SMatthew Dillon 	    "Atheros HAL additional SWBA backoff time");
1349572ff6f6SMatthew Dillon 
1350848b370cSMatthew Dillon 	sc->sc_ah->ah_config.ah_force_full_reset = 0;
1351572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "force_full_reset", CTLFLAG_RW,
1352572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_force_full_reset, 0,
1353572ff6f6SMatthew Dillon 	    "Force full chip reset rather than a warm reset");
1354572ff6f6SMatthew Dillon 
1355572ff6f6SMatthew Dillon 	/*
1356572ff6f6SMatthew Dillon 	 * This is initialised by the driver.
1357572ff6f6SMatthew Dillon 	 */
1358572ff6f6SMatthew Dillon 	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "serialise_reg_war", CTLFLAG_RW,
1359572ff6f6SMatthew Dillon 	    &sc->sc_ah->ah_config.ah_serialise_reg_war, 0,
1360572ff6f6SMatthew Dillon 	    "Force register access serialisation");
1361572ff6f6SMatthew Dillon }
1362