1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <machine/atomic.h> 39 40 #include <dev/netif/ath/ath_hal/ah.h> 41 #include <dev/netif/ath/ath_hal/ah_desc.h> 42 #include <netproto/802_11/ieee80211_radiotap.h> 43 #include <dev/netif/ath/ath/if_athioctl.h> 44 #include <dev/netif/ath/ath/if_athrate.h> 45 #ifdef ATH_DEBUG_ALQ 46 #include <dev/netif/ath/ath/if_ath_alq.h> 47 #endif 48 49 #define ATH_TIMEOUT 1000 50 51 /* 52 * There is a separate TX ath_buf pool for management frames. 53 * This ensures that management frames such as probe responses 54 * and BAR frames can be transmitted during periods of high 55 * TX activity. 56 */ 57 #define ATH_MGMT_TXBUF 32 58 59 #ifndef ATH_RXBUF 60 #ifdef ATH_ENABLE_11N 61 #define ATH_RXBUF 512 /* 802.11n requires more buffers to do AMPDU. */ 62 #elif defined(__DragonFly__) 63 #define ATH_RXBUF 256 /* a default of 40 RXBUFs is not enough */ 64 #else 65 #define ATH_RXBUF 40 /* number of RX buffers */ 66 #endif 67 #endif 68 #ifndef ATH_TXBUF 69 #ifdef ATH_ENABLE_11N 70 #define ATH_TXBUF 512 /* 802.11n requires more buffers to do AMPDU. */ 71 #elif defined(__DragonFly__) 72 #define ATH_TXBUF 256 /* a default of 40 RXBUFs is not enough */ 73 #else 74 #define ATH_TXBUF 200 /* number of TX buffers */ 75 #endif 76 #endif 77 #define ATH_BCBUF 4 /* number of beacon buffers */ 78 79 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 80 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 81 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 82 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 83 84 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 85 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 86 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 87 88 /* 89 * The key cache is used for h/w cipher state and also for 90 * tracking station state such as the current tx antenna. 91 * We also setup a mapping table between key cache slot indices 92 * and station state to short-circuit node lookups on rx. 93 * Different parts have different size key caches. We handle 94 * up to ATH_KEYMAX entries (could dynamically allocate state). 95 */ 96 #define ATH_KEYMAX 128 /* max key cache size we handle */ 97 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 98 99 struct taskqueue; 100 struct kthread; 101 struct ath_buf; 102 103 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 104 105 /* 106 * Per-TID state 107 * 108 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 109 */ 110 struct ath_tid { 111 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 112 struct ath_node *an; /* pointer to parent */ 113 int tid; /* tid */ 114 int ac; /* which AC gets this trafic */ 115 int hwq_depth; /* how many buffers are on HW */ 116 u_int axq_depth; /* SW queue depth */ 117 118 struct { 119 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 120 u_int axq_depth; /* SW queue depth */ 121 } filtq; 122 123 /* 124 * Entry on the ath_txq; when there's traffic 125 * to send 126 */ 127 TAILQ_ENTRY(ath_tid) axq_qelem; 128 int sched; 129 int paused; /* >0 if the TID has been paused */ 130 131 /* 132 * These are flags - perhaps later collapse 133 * down to a single uint32_t ? 134 */ 135 int addba_tx_pending; /* TX ADDBA pending */ 136 int bar_wait; /* waiting for BAR */ 137 int bar_tx; /* BAR TXed */ 138 int isfiltered; /* is this node currently filtered */ 139 140 /* 141 * Is the TID being cleaned up after a transition 142 * from aggregation to non-aggregation? 143 * When this is set to 1, this TID will be paused 144 * and no further traffic will be queued until all 145 * the hardware packets pending for this TID have been 146 * TXed/completed; at which point (non-aggregation) 147 * traffic will resume being TXed. 148 */ 149 int cleanup_inprogress; 150 /* 151 * How many hardware-queued packets are 152 * waiting to be cleaned up. 153 * This is only valid if cleanup_inprogress is 1. 154 */ 155 int incomp; 156 157 /* 158 * The following implements a ring representing 159 * the frames in the current BAW. 160 * To avoid copying the array content each time 161 * the BAW is moved, the baw_head/baw_tail point 162 * to the current BAW begin/end; when the BAW is 163 * shifted the head/tail of the array are also 164 * appropriately shifted. 165 */ 166 /* active tx buffers, beginning at current BAW */ 167 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 168 /* where the baw head is in the array */ 169 int baw_head; 170 /* where the BAW tail is in the array */ 171 int baw_tail; 172 }; 173 174 /* driver-specific node state */ 175 struct ath_node { 176 struct ieee80211_node an_node; /* base class */ 177 u_int8_t an_mgmtrix; /* min h/w rate index */ 178 u_int8_t an_mcastrix; /* mcast h/w rate index */ 179 uint32_t an_is_powersave; /* node is sleeping */ 180 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 181 uint32_t an_tim_set; /* TIM has been set */ 182 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 183 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 184 char an_name[32]; /* eg "wlan0_a1" */ 185 #if 0 186 struct mtx an_mtx; /* protecting the rate control state */ 187 #endif 188 uint32_t an_swq_depth; /* how many SWQ packets for this 189 node */ 190 int clrdmask; /* has clrdmask been set */ 191 uint32_t an_leak_count; /* How many frames to leak during pause */ 192 /* variable-length rate control state follows */ 193 }; 194 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 195 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 196 197 #define ATH_RSSI_LPF_LEN 10 198 #define ATH_RSSI_DUMMY_MARKER 0x127 199 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 200 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 201 #define ATH_LPF_RSSI(x, y, len) \ 202 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 203 #define ATH_RSSI_LPF(x, y) do { \ 204 if ((y) >= -20) \ 205 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 206 } while (0) 207 #define ATH_EP_RND(x,mul) \ 208 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 209 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 210 211 typedef enum { 212 ATH_BUFTYPE_NORMAL = 0, 213 ATH_BUFTYPE_MGMT = 1, 214 } ath_buf_type_t; 215 216 struct ath_buf { 217 TAILQ_ENTRY(ath_buf) bf_list; 218 struct ath_buf * bf_next; /* next buffer in the aggregate */ 219 int bf_nseg; 220 HAL_STATUS bf_rxstatus; 221 uint16_t bf_flags; /* status flags (below) */ 222 uint16_t bf_descid; /* 16 bit descriptor ID */ 223 struct ath_desc *bf_desc; /* virtual addr of desc */ 224 struct ath_desc_status bf_status; /* tx/rx status */ 225 bus_addr_t bf_daddr; /* physical addr of desc */ 226 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 227 struct mbuf *bf_m; /* mbuf for buf */ 228 struct ieee80211_node *bf_node; /* pointer to the node */ 229 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 230 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 231 bus_size_t bf_mapsize; 232 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 233 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 234 uint32_t bf_nextfraglen; /* length of next fragment */ 235 236 /* Completion function to call on TX complete (fail or not) */ 237 /* 238 * "fail" here is set to 1 if the queue entries were removed 239 * through a call to ath_tx_draintxq(). 240 */ 241 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 242 243 /* This state is kept to support software retries and aggregation */ 244 struct { 245 uint16_t bfs_seqno; /* sequence number of this packet */ 246 uint16_t bfs_ndelim; /* number of delims for padding */ 247 248 uint8_t bfs_retries; /* retry count */ 249 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 250 uint8_t bfs_nframes; /* number of frames in aggregate */ 251 uint8_t bfs_pri; /* packet AC priority */ 252 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 253 254 u_int32_t bfs_aggr:1, /* part of aggregate? */ 255 bfs_aggrburst:1, /* part of aggregate burst? */ 256 bfs_isretried:1, /* retried frame? */ 257 bfs_dobaw:1, /* actually check against BAW? */ 258 bfs_addedbaw:1, /* has been added to the BAW */ 259 bfs_shpream:1, /* use short preamble */ 260 bfs_istxfrag:1, /* is fragmented */ 261 bfs_ismrr:1, /* do multi-rate TX retry */ 262 bfs_doprot:1, /* do RTS/CTS based protection */ 263 bfs_doratelookup:1; /* do rate lookup before each TX */ 264 265 /* 266 * These fields are passed into the 267 * descriptor setup functions. 268 */ 269 270 /* Make this an 8 bit value? */ 271 HAL_PKT_TYPE bfs_atype; /* packet type */ 272 273 uint32_t bfs_pktlen; /* length of this packet */ 274 275 uint16_t bfs_hdrlen; /* length of this packet header */ 276 uint16_t bfs_al; /* length of aggregate */ 277 278 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 279 uint8_t bfs_txrate0; /* first TX rate */ 280 uint8_t bfs_try0; /* first try count */ 281 282 uint16_t bfs_txpower; /* tx power */ 283 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 284 uint8_t bfs_ctsrate; /* CTS rate */ 285 286 /* 16 bit? */ 287 int32_t bfs_keyix; /* crypto key index */ 288 int32_t bfs_txantenna; /* TX antenna config */ 289 290 /* Make this an 8 bit value? */ 291 enum ieee80211_protmode bfs_protmode; 292 293 /* 16 bit? */ 294 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 295 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 296 } bf_state; 297 }; 298 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 299 300 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 301 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 302 #define ATH_BUF_FIFOEND 0x00000004 303 #define ATH_BUF_FIFOPTR 0x00000008 304 305 #define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 306 307 /* 308 * DMA state for tx/rx descriptors. 309 */ 310 struct ath_descdma { 311 const char* dd_name; 312 struct ath_desc *dd_desc; /* descriptors */ 313 int dd_descsize; /* size of single descriptor */ 314 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 315 bus_size_t dd_desc_len; /* size of dd_desc */ 316 bus_dma_segment_t dd_dseg; 317 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 318 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 319 struct ath_buf *dd_bufptr; /* associated buffers */ 320 }; 321 322 /* 323 * Data transmit queue state. One of these exists for each 324 * hardware transmit queue. Packets sent to us from above 325 * are assigned to queues based on their priority. Not all 326 * devices support a complete set of hardware transmit queues. 327 * For those devices the array sc_ac2q will map multiple 328 * priorities to fewer hardware queues (typically all to one 329 * hardware queue). 330 */ 331 struct ath_txq { 332 struct ath_softc *axq_softc; /* Needed for scheduling */ 333 u_int axq_qnum; /* hardware q number */ 334 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 335 u_int axq_ac; /* WME AC */ 336 u_int axq_flags; 337 //#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 338 #define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 339 u_int axq_depth; /* queue depth (stat only) */ 340 u_int axq_aggr_depth; /* how many aggregates are queued */ 341 u_int axq_intrcnt; /* interrupt count */ 342 u_int32_t *axq_link; /* link ptr in last TX desc */ 343 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 344 struct lock axq_lock; /* lock on q and link */ 345 346 /* 347 * This is the FIFO staging buffer when doing EDMA. 348 * 349 * For legacy chips, we just push the head pointer to 350 * the hardware and we ignore this list. 351 * 352 * For EDMA, the staging buffer is treated as normal; 353 * when it's time to push a list of frames to the hardware 354 * we move that list here and we stamp buffers with 355 * flags to identify the beginning/end of that particular 356 * FIFO entry. 357 */ 358 struct { 359 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 360 u_int axq_depth; 361 } fifo; 362 u_int axq_fifo_depth; /* depth of FIFO frames */ 363 364 /* 365 * XXX the holdingbf field is protected by the TXBUF lock 366 * for now, NOT the TXQ lock. 367 * 368 * Architecturally, it would likely be better to move 369 * the holdingbf field to a separate array in ath_softc 370 * just to highlight that it's not protected by the normal 371 * TX path lock. 372 */ 373 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 374 char axq_name[12]; /* e.g. "ath0_txq4" */ 375 376 /* Per-TID traffic queue for software -> hardware TX */ 377 /* 378 * This is protected by the general TX path lock, not (for now) 379 * by the TXQ lock. 380 */ 381 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 382 }; 383 384 #ifdef __DragonFly__ 385 /* already serialized by wlan_serializer */ 386 #define IF_LOCK(ifp) 387 #define IF_UNLOCK(ifp) 388 #define IEEE80211_LOCK_ASSERT(ic) 389 #define IEEE80211_LOCK(ic) 390 #define IEEE80211_UNLOCK(ic) 391 #endif 392 393 #define ATH_TXQ_LOCK_INIT(_sc, _tq) 394 #define ATH_TXQ_LOCK_DESTROY(_tq) 395 #define ATH_TXQ_LOCK(_tq) 396 #define ATH_TXQ_UNLOCK(_tq) 397 #define ATH_TXQ_LOCK_ASSERT(_tq) 398 #define ATH_TXQ_UNLOCK_ASSERT(_tq) 399 400 #define ATH_NODE_LOCK(_an) 401 #define ATH_NODE_UNLOCK(_an) 402 #define ATH_NODE_LOCK_ASSERT(_an) 403 #define ATH_NODE_UNLOCK_ASSERT(_an) 404 405 /* 406 * These are for the hardware queue. 407 */ 408 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 409 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 410 (_tq)->axq_depth++; \ 411 } while (0) 412 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 413 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 414 (_tq)->axq_depth++; \ 415 } while (0) 416 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 417 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 418 (_tq)->axq_depth--; \ 419 } while (0) 420 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 421 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 422 423 /* 424 * These are for the TID software queue. 425 */ 426 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 427 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 428 (_tq)->axq_depth++; \ 429 (_tq)->an->an_swq_depth++; \ 430 } while (0) 431 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 432 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 433 (_tq)->axq_depth++; \ 434 (_tq)->an->an_swq_depth++; \ 435 } while (0) 436 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 437 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 438 (_tq)->axq_depth--; \ 439 (_tq)->an->an_swq_depth--; \ 440 } while (0) 441 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 442 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 443 444 /* 445 * These are for the TID filtered frame queue 446 */ 447 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 448 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 449 (_tq)->axq_depth++; \ 450 (_tq)->an->an_swq_depth++; \ 451 } while (0) 452 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 453 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 454 (_tq)->axq_depth++; \ 455 (_tq)->an->an_swq_depth++; \ 456 } while (0) 457 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 458 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 459 (_tq)->axq_depth--; \ 460 (_tq)->an->an_swq_depth--; \ 461 } while (0) 462 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 463 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 464 465 struct ath_vap { 466 struct ieee80211vap av_vap; /* base class */ 467 int av_bslot; /* beacon slot index */ 468 struct ath_buf *av_bcbuf; /* beacon buffer */ 469 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 470 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 471 472 void (*av_recv_mgmt)(struct ieee80211_node *, 473 struct mbuf *, int, int, int); 474 int (*av_newstate)(struct ieee80211vap *, 475 enum ieee80211_state, int); 476 void (*av_bmiss)(struct ieee80211vap *); 477 void (*av_node_ps)(struct ieee80211_node *, int); 478 int (*av_set_tim)(struct ieee80211_node *, int); 479 void (*av_recv_pspoll)(struct ieee80211_node *, 480 struct mbuf *); 481 }; 482 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 483 484 struct taskqueue; 485 struct ath_tx99; 486 487 /* 488 * Whether to reset the TX/RX queue with or without 489 * a queue flush. 490 */ 491 typedef enum { 492 ATH_RESET_DEFAULT = 0, 493 ATH_RESET_NOLOSS = 1, 494 ATH_RESET_FULL = 2, 495 } ATH_RESET_TYPE; 496 497 struct ath_rx_methods { 498 void (*recv_sched_queue)(struct ath_softc *sc, 499 HAL_RX_QUEUE q, int dosched); 500 void (*recv_sched)(struct ath_softc *sc, int dosched); 501 void (*recv_stop)(struct ath_softc *sc, int dodelay); 502 int (*recv_start)(struct ath_softc *sc); 503 void (*recv_flush)(struct ath_softc *sc); 504 void (*recv_tasklet)(void *arg, int npending); 505 int (*recv_rxbuf_init)(struct ath_softc *sc, 506 struct ath_buf *bf); 507 int (*recv_setup)(struct ath_softc *sc); 508 int (*recv_teardown)(struct ath_softc *sc); 509 }; 510 511 /* 512 * Represent the current state of the RX FIFO. 513 */ 514 struct ath_rx_edma { 515 struct ath_buf **m_fifo; 516 int m_fifolen; 517 int m_fifo_head; 518 int m_fifo_tail; 519 int m_fifo_depth; 520 struct mbuf *m_rxpending; 521 }; 522 523 struct ath_tx_edma_fifo { 524 struct ath_buf **m_fifo; 525 int m_fifolen; 526 int m_fifo_head; 527 int m_fifo_tail; 528 int m_fifo_depth; 529 }; 530 531 struct ath_tx_methods { 532 int (*xmit_setup)(struct ath_softc *sc); 533 int (*xmit_teardown)(struct ath_softc *sc); 534 void (*xmit_attach_comp_func)(struct ath_softc *sc); 535 536 void (*xmit_dma_restart)(struct ath_softc *sc, 537 struct ath_txq *txq); 538 void (*xmit_handoff)(struct ath_softc *sc, 539 struct ath_txq *txq, struct ath_buf *bf); 540 void (*xmit_drain)(struct ath_softc *sc, 541 ATH_RESET_TYPE reset_type); 542 }; 543 544 struct ath_softc { 545 struct ifnet *sc_ifp; /* interface common */ 546 struct ath_stats sc_stats; /* interface statistics */ 547 struct ath_tx_aggr_stats sc_aggr_stats; 548 struct ath_intr_stats sc_intr_stats; 549 struct sysctl_ctx_list sc_sysctl_ctx; 550 struct sysctl_oid *sc_sysctl_tree; 551 uint64_t sc_debug; 552 uint64_t sc_ktrdebug; 553 int sc_nvaps; /* # vaps */ 554 int sc_nstavaps; /* # station vaps */ 555 int sc_nmeshvaps; /* # mbss vaps */ 556 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 557 u_int8_t sc_nbssid0; /* # vap's using base mac */ 558 uint32_t sc_bssidmask; /* bssid mask */ 559 560 struct ath_rx_methods sc_rx; 561 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 562 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 563 struct ath_tx_methods sc_tx; 564 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 565 566 /* 567 * This is (currently) protected by the TX queue lock; 568 * it should migrate to a separate lock later 569 * so as to minimise contention. 570 */ 571 ath_bufhead sc_txbuf_list; 572 573 int sc_rx_statuslen; 574 int sc_tx_desclen; 575 int sc_tx_statuslen; 576 int sc_tx_nmaps; /* Number of TX maps */ 577 int sc_edma_bufsize; 578 579 void (*sc_node_cleanup)(struct ieee80211_node *); 580 void (*sc_node_free)(struct ieee80211_node *); 581 device_t sc_dev; 582 HAL_BUS_TAG sc_st; /* bus space tag */ 583 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 584 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 585 #if 0 586 struct mtx sc_mtx; /* master lock (recursive) */ 587 struct mtx sc_pcu_mtx; /* PCU access mutex */ 588 char sc_pcu_mtx_name[32]; 589 struct mtx sc_rx_mtx; /* RX access mutex */ 590 char sc_rx_mtx_name[32]; 591 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 592 char sc_tx_mtx_name[32]; 593 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 594 char sc_tx_ic_mtx_name[32]; 595 #endif 596 struct taskqueue *sc_tq; /* private task queue */ 597 struct ath_hal *sc_ah; /* Atheros HAL */ 598 struct ath_ratectrl *sc_rc; /* tx rate control support */ 599 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 600 void (*sc_setdefantenna)(struct ath_softc *, u_int); 601 602 /* 603 * First set of flags. 604 */ 605 uint32_t sc_invalid : 1,/* disable hardware accesses */ 606 sc_mrretry : 1,/* multi-rate retry support */ 607 sc_mrrprot : 1,/* MRR + protection support */ 608 sc_softled : 1,/* enable LED gpio status */ 609 sc_hardled : 1,/* enable MAC LED status */ 610 sc_splitmic : 1,/* split TKIP MIC keys */ 611 sc_needmib : 1,/* enable MIB stats intr */ 612 sc_diversity: 1,/* enable rx diversity */ 613 sc_hasveol : 1,/* tx VEOL support */ 614 sc_ledstate : 1,/* LED on/off state */ 615 sc_blinking : 1,/* LED blink operation active */ 616 sc_mcastkey : 1,/* mcast key cache search */ 617 sc_scanning : 1,/* scanning active */ 618 sc_syncbeacon:1,/* sync/resync beacon timers */ 619 sc_hasclrkey: 1,/* CLR key supported */ 620 sc_xchanmode: 1,/* extended channel mode */ 621 sc_outdoor : 1,/* outdoor operation */ 622 sc_dturbo : 1,/* dynamic turbo in use */ 623 sc_hasbmask : 1,/* bssid mask support */ 624 sc_hasbmatch: 1,/* bssid match disable support*/ 625 sc_hastsfadd: 1,/* tsf adjust support */ 626 sc_beacons : 1,/* beacons running */ 627 sc_swbmiss : 1,/* sta mode using sw bmiss */ 628 sc_stagbeacons:1,/* use staggered beacons */ 629 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 630 sc_resume_up: 1,/* on resume, start all vaps */ 631 sc_tdma : 1,/* TDMA in use */ 632 sc_setcca : 1,/* set/clr CCA with TDMA */ 633 sc_resetcal : 1,/* reset cal state next trip */ 634 sc_rxslink : 1,/* do self-linked final descriptor */ 635 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 636 sc_isedma : 1;/* supports EDMA */ 637 638 /* 639 * Second set of flags. 640 */ 641 u_int32_t sc_use_ent : 1, 642 sc_rx_stbc : 1, 643 sc_tx_stbc : 1, 644 sc_hasenforcetxop : 1, /* support enforce TxOP */ 645 sc_hasdivcomb : 1, /* RX diversity combining */ 646 sc_rx_lnamixer : 1; /* RX using LNA mixing */ 647 648 int sc_cabq_enable; /* Enable cabq transmission */ 649 650 /* 651 * Enterprise mode configuration for AR9380 and later chipsets. 652 */ 653 uint32_t sc_ent_cfg; 654 655 uint32_t sc_eerd; /* regdomain from EEPROM */ 656 uint32_t sc_eecc; /* country code from EEPROM */ 657 /* rate tables */ 658 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 659 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 660 enum ieee80211_phymode sc_curmode; /* current phy mode */ 661 HAL_OPMODE sc_opmode; /* current operating mode */ 662 u_int16_t sc_curtxpow; /* current tx power limit */ 663 u_int16_t sc_curaid; /* current association id */ 664 struct ieee80211_channel *sc_curchan; /* current installed channel */ 665 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 666 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 667 struct { 668 u_int8_t ieeerate; /* IEEE rate */ 669 u_int8_t rxflags; /* radiotap rx flags */ 670 u_int8_t txflags; /* radiotap tx flags */ 671 u_int16_t ledon; /* softled on time */ 672 u_int16_t ledoff; /* softled off time */ 673 } sc_hwmap[32]; /* h/w rate ix mappings */ 674 u_int8_t sc_protrix; /* protection rate index */ 675 u_int8_t sc_lastdatarix; /* last data frame rate index */ 676 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 677 u_int sc_fftxqmin; /* min frames before staging */ 678 u_int sc_fftxqmax; /* max frames before drop */ 679 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 680 681 HAL_INT sc_imask; /* interrupt mask copy */ 682 683 /* 684 * These are modified in the interrupt handler as well as 685 * the task queues and other contexts. Thus these must be 686 * protected by a mutex, or they could clash. 687 * 688 * For now, access to these is behind the ATH_LOCK, 689 * just to save time. 690 */ 691 uint32_t sc_txq_active; /* bitmap of active TXQs */ 692 uint32_t sc_kickpcu; /* whether to kick the PCU */ 693 uint32_t sc_rxproc_cnt; /* In RX processing */ 694 uint32_t sc_txproc_cnt; /* In TX processing */ 695 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 696 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 697 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 698 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 699 700 u_int sc_keymax; /* size of key cache */ 701 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 702 703 /* 704 * Software based LED blinking 705 */ 706 u_int sc_ledpin; /* GPIO pin for driving LED */ 707 u_int sc_ledon; /* pin setting for LED on */ 708 u_int sc_ledidle; /* idle polling interval */ 709 int sc_ledevent; /* time of last LED event */ 710 u_int8_t sc_txrix; /* current tx rate for LED */ 711 u_int16_t sc_ledoff; /* off time for current blink */ 712 struct callout sc_ledtimer; /* led off timer */ 713 714 /* 715 * Hardware based LED blinking 716 */ 717 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 718 int sc_led_net_pin; /* MAC network LED GPIO pin */ 719 720 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 721 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 722 723 struct ath_descdma sc_rxdma; /* RX descriptors */ 724 ath_bufhead sc_rxbuf; /* receive buffer */ 725 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 726 struct task sc_rxtask; /* rx int processing */ 727 u_int8_t sc_defant; /* current default antenna */ 728 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 729 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 730 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 731 struct ath_rx_radiotap_header sc_rx_th; 732 int sc_rx_th_len; 733 u_int sc_monpass; /* frames to pass in mon.mode */ 734 735 struct ath_descdma sc_txdma; /* TX descriptors */ 736 uint16_t sc_txbuf_descid; 737 ath_bufhead sc_txbuf; /* transmit buffer */ 738 int sc_txbuf_cnt; /* how many buffers avail */ 739 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 740 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 741 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 742 #if 0 743 struct mtx sc_txbuflock; /* txbuf lock */ 744 char sc_txname[12]; /* e.g. "ath0_buf" */ 745 #endif 746 u_int sc_txqsetup; /* h/w queues setup */ 747 u_int sc_txintrperiod;/* tx interrupt batching */ 748 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 749 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 750 struct task sc_txtask; /* tx int processing */ 751 struct task sc_txqtask; /* tx proc processing */ 752 753 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 754 #if 0 755 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 756 char sc_txcompname[12]; /* eg ath0_txcomp */ 757 #endif 758 759 int sc_wd_timer; /* count down for wd timer */ 760 struct callout sc_wd_ch; /* tx watchdog timer */ 761 struct ath_tx_radiotap_header sc_tx_th; 762 int sc_tx_th_len; 763 764 struct ath_descdma sc_bdma; /* beacon descriptors */ 765 ath_bufhead sc_bbuf; /* beacon buffers */ 766 u_int sc_bhalq; /* HAL q for outgoing beacons */ 767 u_int sc_bmisscount; /* missed beacon transmits */ 768 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 769 struct ath_txq *sc_cabq; /* tx q for cab frames */ 770 struct task sc_bmisstask; /* bmiss int processing */ 771 struct task sc_bstucktask; /* stuck beacon processing */ 772 struct task sc_resettask; /* interface reset task */ 773 struct task sc_fataltask; /* fatal task */ 774 enum { 775 OK, /* no change needed */ 776 UPDATE, /* update pending */ 777 COMMIT /* beacon sent, commit change */ 778 } sc_updateslot; /* slot time update fsm */ 779 int sc_slotupdate; /* slot to advance fsm */ 780 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 781 int sc_nbcnvaps; /* # vaps with beacons */ 782 783 struct callout sc_cal_ch; /* callout handle for cals */ 784 int sc_lastlongcal; /* last long cal completed */ 785 int sc_lastcalreset;/* last cal reset done */ 786 int sc_lastani; /* last ANI poll */ 787 int sc_lastshortcal; /* last short calibration */ 788 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 789 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 790 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 791 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 792 u_int sc_tdmaswba; /* TDMA SWBA counter */ 793 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 794 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 795 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 796 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 797 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 798 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 799 uint32_t sc_txchainmask; /* hardware TX chainmask */ 800 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 801 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 802 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 803 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 804 int sc_aggr_limit; /* TX limit on all aggregates */ 805 int sc_delim_min_pad; /* Minimum delimiter count */ 806 807 /* Queue limits */ 808 809 /* 810 * To avoid queue starvation in congested conditions, 811 * these parameters tune the maximum number of frames 812 * queued to the data/mcastq before they're dropped. 813 * 814 * This is to prevent: 815 * + a single destination overwhelming everything, including 816 * management/multicast frames; 817 * + multicast frames overwhelming everything (when the 818 * air is sufficiently busy that cabq can't drain.) 819 * + A node in powersave shouldn't be allowed to exhaust 820 * all available mbufs; 821 * 822 * These implement: 823 * + data_minfree is the maximum number of free buffers 824 * overall to successfully allow a data frame. 825 * 826 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 827 */ 828 int sc_txq_node_maxdepth; 829 int sc_txq_data_minfree; 830 int sc_txq_mcastq_maxdepth; 831 int sc_txq_node_psq_maxdepth; 832 833 /* 834 * Software queue twiddles 835 * 836 * hwq_limit_nonaggr: 837 * when to begin limiting non-aggregate frames to the 838 * hardware queue, regardless of the TID. 839 * hwq_limit_aggr: 840 * when to begin limiting A-MPDU frames to the 841 * hardware queue, regardless of the TID. 842 * tid_hwq_lo: how low the per-TID hwq count has to be before the 843 * TID will be scheduled again 844 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 845 * stops being scheduled. 846 */ 847 int sc_hwq_limit_nonaggr; 848 int sc_hwq_limit_aggr; 849 int sc_tid_hwq_lo; 850 int sc_tid_hwq_hi; 851 852 /* DFS related state */ 853 void *sc_dfs; /* Used by an optional DFS module */ 854 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 855 struct task sc_dfstask; /* DFS processing task */ 856 857 /* Spectral related state */ 858 void *sc_spectral; 859 int sc_dospectral; 860 861 /* LNA diversity related state */ 862 void *sc_lna_div; 863 int sc_dolnadiv; 864 865 /* ALQ */ 866 #ifdef ATH_DEBUG_ALQ 867 struct if_ath_alq sc_alq; 868 #endif 869 870 /* TX AMPDU handling */ 871 int (*sc_addba_request)(struct ieee80211_node *, 872 struct ieee80211_tx_ampdu *, int, int, int); 873 int (*sc_addba_response)(struct ieee80211_node *, 874 struct ieee80211_tx_ampdu *, int, int, int); 875 void (*sc_addba_stop)(struct ieee80211_node *, 876 struct ieee80211_tx_ampdu *); 877 void (*sc_addba_response_timeout) 878 (struct ieee80211_node *, 879 struct ieee80211_tx_ampdu *); 880 void (*sc_bar_response)(struct ieee80211_node *ni, 881 struct ieee80211_tx_ampdu *tap, 882 int status); 883 }; 884 885 #define ATH_LOCK_INIT(_sc) 886 #define ATH_LOCK_DESTROY(_sc) 887 #define ATH_LOCK(_sc) 888 #define ATH_UNLOCK(_sc) 889 #define ATH_LOCK_ASSERT(_sc) 890 #define ATH_UNLOCK_ASSERT(_sc) 891 892 /* 893 * The TX lock is non-reentrant and serialises the TX frame send 894 * and completion operations. 895 */ 896 #define ATH_TX_LOCK_INIT(_sc) 897 #define ATH_TX_LOCK_DESTROY(_sc) 898 #define ATH_TX_LOCK(_sc) 899 #define ATH_TX_UNLOCK(_sc) 900 #define ATH_TX_LOCK_ASSERT(_sc) 901 #define ATH_TX_UNLOCK_ASSERT(_sc) 902 /* #define ATH_TX_TRYLOCK(_sc) removed */ 903 904 /* 905 * The IC TX lock is non-reentrant and serialises packet queuing from 906 * the upper layers. 907 */ 908 #define ATH_TX_IC_LOCK_INIT(_sc) 909 #define ATH_TX_IC_LOCK_DESTROY(_sc) 910 #define ATH_TX_IC_LOCK(_sc) 911 #define ATH_TX_IC_UNLOCK(_sc) 912 #define ATH_TX_IC_LOCK_ASSERT(_sc) 913 #define ATH_TX_IC_UNLOCK_ASSERT(_sc) 914 915 /* 916 * The PCU lock is non-recursive and should be treated as a spinlock. 917 * Although currently the interrupt code is run in netisr context and 918 * doesn't require this, this may change in the future. 919 * Please keep this in mind when protecting certain code paths 920 * with the PCU lock. 921 * 922 * The PCU lock is used to serialise access to the PCU so things such 923 * as TX, RX, state change (eg channel change), channel reset and updates 924 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 925 * 926 * Although the current single-thread taskqueue mechanism protects the 927 * majority of these situations by simply serialising them, there are 928 * a few others which occur at the same time. These include the TX path 929 * (which only acquires ATH_LOCK when recycling buffers to the free list), 930 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 931 */ 932 #define ATH_PCU_LOCK_INIT(_sc) 933 #define ATH_PCU_LOCK_DESTROY(_sc) 934 #define ATH_PCU_LOCK(_sc) 935 #define ATH_PCU_UNLOCK(_sc) 936 #define ATH_PCU_LOCK_ASSERT(_sc) 937 #define ATH_PCU_UNLOCK_ASSERT(_sc) 938 939 /* 940 * The RX lock is primarily a(nother) workaround to ensure that the 941 * RX FIFO/list isn't modified by various execution paths. 942 * Even though RX occurs in a single context (the ath taskqueue), the 943 * RX path can be executed via various reset/channel change paths. 944 */ 945 #define ATH_RX_LOCK_INIT(_sc) 946 #define ATH_RX_LOCK_DESTROY(_sc) 947 #define ATH_RX_LOCK(_sc) 948 #define ATH_RX_UNLOCK(_sc) 949 #define ATH_RX_LOCK_ASSERT(_sc) 950 #define ATH_RX_UNLOCK_ASSERT(_sc) 951 952 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 953 954 #define ATH_TXBUF_LOCK_INIT(_sc) 955 #define ATH_TXBUF_LOCK_DESTROY(_sc) 956 #define ATH_TXBUF_LOCK(_sc) 957 #define ATH_TXBUF_UNLOCK(_sc) 958 #define ATH_TXBUF_LOCK_ASSERT(_sc) 959 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) 960 961 #define ATH_TXSTATUS_LOCK_INIT(_sc) 962 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) 963 #define ATH_TXSTATUS_LOCK(_sc) 964 #define ATH_TXSTATUS_UNLOCK(_sc) 965 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) 966 967 int ath_attach(u_int16_t, struct ath_softc *); 968 int ath_detach(struct ath_softc *); 969 void ath_resume(struct ath_softc *); 970 void ath_suspend(struct ath_softc *); 971 void ath_shutdown(struct ath_softc *); 972 void ath_intr(void *); 973 974 /* 975 * HAL definitions to comply with local coding convention. 976 */ 977 #define ath_hal_detach(_ah) \ 978 ((*(_ah)->ah_detach)((_ah))) 979 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 980 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 981 #define ath_hal_macversion(_ah) \ 982 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 983 #define ath_hal_getratetable(_ah, _mode) \ 984 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 985 #define ath_hal_getmac(_ah, _mac) \ 986 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 987 #define ath_hal_setmac(_ah, _mac) \ 988 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 989 #define ath_hal_getbssidmask(_ah, _mask) \ 990 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 991 #define ath_hal_setbssidmask(_ah, _mask) \ 992 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 993 #define ath_hal_intrset(_ah, _mask) \ 994 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 995 #define ath_hal_intrget(_ah) \ 996 ((*(_ah)->ah_getInterrupts)((_ah))) 997 #define ath_hal_intrpend(_ah) \ 998 ((*(_ah)->ah_isInterruptPending)((_ah))) 999 #define ath_hal_getisr(_ah, _pmask) \ 1000 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1001 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 1002 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1003 #define ath_hal_setpower(_ah, _mode) \ 1004 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1005 #define ath_hal_keycachesize(_ah) \ 1006 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1007 #define ath_hal_keyreset(_ah, _ix) \ 1008 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1009 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1010 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1011 #define ath_hal_keyisvalid(_ah, _ix) \ 1012 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1013 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 1014 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1015 #define ath_hal_getrxfilter(_ah) \ 1016 ((*(_ah)->ah_getRxFilter)((_ah))) 1017 #define ath_hal_setrxfilter(_ah, _filter) \ 1018 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1019 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1020 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1021 #define ath_hal_waitforbeacon(_ah, _bf) \ 1022 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1023 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1024 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1025 /* NB: common across all chips */ 1026 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1027 #define ath_hal_gettsf32(_ah) \ 1028 OS_REG_READ(_ah, AR_TSF_L32) 1029 #define ath_hal_gettsf64(_ah) \ 1030 ((*(_ah)->ah_getTsf64)((_ah))) 1031 #define ath_hal_settsf64(_ah, _val) \ 1032 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1033 #define ath_hal_resettsf(_ah) \ 1034 ((*(_ah)->ah_resetTsf)((_ah))) 1035 #define ath_hal_rxena(_ah) \ 1036 ((*(_ah)->ah_enableReceive)((_ah))) 1037 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1038 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1039 #define ath_hal_gettxbuf(_ah, _q) \ 1040 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1041 #define ath_hal_numtxpending(_ah, _q) \ 1042 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1043 #define ath_hal_getrxbuf(_ah, _rxq) \ 1044 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1045 #define ath_hal_txstart(_ah, _q) \ 1046 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1047 #define ath_hal_setchannel(_ah, _chan) \ 1048 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1049 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1050 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1051 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1052 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1053 #define ath_hal_calreset(_ah, _chan) \ 1054 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1055 #define ath_hal_setledstate(_ah, _state) \ 1056 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1057 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1058 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1059 #define ath_hal_beaconreset(_ah) \ 1060 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1061 #define ath_hal_beaconsettimers(_ah, _bt) \ 1062 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1063 #define ath_hal_beacontimers(_ah, _bs) \ 1064 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1065 #define ath_hal_getnexttbtt(_ah) \ 1066 ((*(_ah)->ah_getNextTBTT)((_ah))) 1067 #define ath_hal_setassocid(_ah, _bss, _associd) \ 1068 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1069 #define ath_hal_phydisable(_ah) \ 1070 ((*(_ah)->ah_phyDisable)((_ah))) 1071 #define ath_hal_setopmode(_ah) \ 1072 ((*(_ah)->ah_setPCUConfig)((_ah))) 1073 #define ath_hal_stoptxdma(_ah, _qnum) \ 1074 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1075 #define ath_hal_stoppcurecv(_ah) \ 1076 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1077 #define ath_hal_startpcurecv(_ah) \ 1078 ((*(_ah)->ah_startPcuReceive)((_ah))) 1079 #define ath_hal_stopdmarecv(_ah) \ 1080 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1081 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1082 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1083 (_indata), (_insize), (_outdata), (_outsize))) 1084 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1085 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1086 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1087 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1088 #define ath_hal_resettxqueue(_ah, _q) \ 1089 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1090 #define ath_hal_releasetxqueue(_ah, _q) \ 1091 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1092 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1093 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1094 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1095 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1096 /* NB: common across all chips */ 1097 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1098 #define ath_hal_txqenabled(_ah, _qnum) \ 1099 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1100 #define ath_hal_getrfgain(_ah) \ 1101 ((*(_ah)->ah_getRfGain)((_ah))) 1102 #define ath_hal_getdefantenna(_ah) \ 1103 ((*(_ah)->ah_getDefAntenna)((_ah))) 1104 #define ath_hal_setdefantenna(_ah, _ant) \ 1105 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1106 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1107 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1108 #define ath_hal_ani_poll(_ah, _chan) \ 1109 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1110 #define ath_hal_mibevent(_ah, _stats) \ 1111 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1112 #define ath_hal_setslottime(_ah, _us) \ 1113 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1114 #define ath_hal_getslottime(_ah) \ 1115 ((*(_ah)->ah_getSlotTime)((_ah))) 1116 #define ath_hal_setacktimeout(_ah, _us) \ 1117 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1118 #define ath_hal_getacktimeout(_ah) \ 1119 ((*(_ah)->ah_getAckTimeout)((_ah))) 1120 #define ath_hal_setctstimeout(_ah, _us) \ 1121 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1122 #define ath_hal_getctstimeout(_ah) \ 1123 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1124 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1125 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1126 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1127 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1128 #define ath_hal_ciphersupported(_ah, _cipher) \ 1129 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1130 #define ath_hal_getregdomain(_ah, _prd) \ 1131 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1132 #define ath_hal_setregdomain(_ah, _rd) \ 1133 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1134 #define ath_hal_getcountrycode(_ah, _pcc) \ 1135 (*(_pcc) = (_ah)->ah_countryCode) 1136 #define ath_hal_gettkipmic(_ah) \ 1137 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1138 #define ath_hal_settkipmic(_ah, _v) \ 1139 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1140 #define ath_hal_hastkipsplit(_ah) \ 1141 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1142 #define ath_hal_gettkipsplit(_ah) \ 1143 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1144 #define ath_hal_settkipsplit(_ah, _v) \ 1145 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1146 #define ath_hal_haswmetkipmic(_ah) \ 1147 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1148 #define ath_hal_hwphycounters(_ah) \ 1149 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1150 #define ath_hal_hasdiversity(_ah) \ 1151 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1152 #define ath_hal_getdiversity(_ah) \ 1153 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1154 #define ath_hal_setdiversity(_ah, _v) \ 1155 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1156 #define ath_hal_getantennaswitch(_ah) \ 1157 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1158 #define ath_hal_setantennaswitch(_ah, _v) \ 1159 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1160 #define ath_hal_getdiag(_ah, _pv) \ 1161 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1162 #define ath_hal_setdiag(_ah, _v) \ 1163 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1164 #define ath_hal_getnumtxqueues(_ah, _pv) \ 1165 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1166 #define ath_hal_hasveol(_ah) \ 1167 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1168 #define ath_hal_hastxpowlimit(_ah) \ 1169 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1170 #define ath_hal_settxpowlimit(_ah, _pow) \ 1171 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1172 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 1173 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1174 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 1175 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1176 #define ath_hal_gettpscale(_ah, _scale) \ 1177 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1178 #define ath_hal_settpscale(_ah, _v) \ 1179 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1180 #define ath_hal_hastpc(_ah) \ 1181 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1182 #define ath_hal_gettpc(_ah) \ 1183 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1184 #define ath_hal_settpc(_ah, _v) \ 1185 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1186 #define ath_hal_hasbursting(_ah) \ 1187 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1188 #define ath_hal_setmcastkeysearch(_ah, _v) \ 1189 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1190 #define ath_hal_hasmcastkeysearch(_ah) \ 1191 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1192 #define ath_hal_getmcastkeysearch(_ah) \ 1193 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1194 #define ath_hal_hasfastframes(_ah) \ 1195 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1196 #define ath_hal_hasbssidmask(_ah) \ 1197 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1198 #define ath_hal_hasbssidmatch(_ah) \ 1199 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1200 #define ath_hal_hastsfadjust(_ah) \ 1201 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1202 #define ath_hal_gettsfadjust(_ah) \ 1203 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1204 #define ath_hal_settsfadjust(_ah, _onoff) \ 1205 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1206 #define ath_hal_hasrfsilent(_ah) \ 1207 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1208 #define ath_hal_getrfkill(_ah) \ 1209 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1210 #define ath_hal_setrfkill(_ah, _onoff) \ 1211 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1212 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1213 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1214 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1215 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1216 #define ath_hal_gettpack(_ah, _ptpack) \ 1217 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1218 #define ath_hal_settpack(_ah, _tpack) \ 1219 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1220 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1221 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1222 #define ath_hal_settpcts(_ah, _tpcts) \ 1223 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1224 #define ath_hal_hasintmit(_ah) \ 1225 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1226 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1227 #define ath_hal_getintmit(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1229 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1230 #define ath_hal_setintmit(_ah, _v) \ 1231 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1232 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1233 1234 #define ath_hal_hasenforcetxop(_ah) \ 1235 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK) 1236 #define ath_hal_getenforcetxop(_ah) \ 1237 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK) 1238 #define ath_hal_setenforcetxop(_ah, _v) \ 1239 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL) 1240 1241 #define ath_hal_hasrxlnamixer(_ah) \ 1242 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK) 1243 1244 #define ath_hal_hasdivantcomb(_ah) \ 1245 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK) 1246 1247 /* EDMA definitions */ 1248 #define ath_hal_hasedma(_ah) \ 1249 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1250 0, NULL) == HAL_OK) 1251 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1252 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1253 == HAL_OK) 1254 #define ath_hal_getntxmaps(_ah, _req) \ 1255 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1256 == HAL_OK) 1257 #define ath_hal_gettxdesclen(_ah, _req) \ 1258 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1259 == HAL_OK) 1260 #define ath_hal_gettxstatuslen(_ah, _req) \ 1261 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1262 == HAL_OK) 1263 #define ath_hal_getrxstatuslen(_ah, _req) \ 1264 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1265 == HAL_OK) 1266 #define ath_hal_setrxbufsize(_ah, _req) \ 1267 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1268 == AH_TRUE) 1269 1270 #define ath_hal_getchannoise(_ah, _c) \ 1271 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1272 1273 /* 802.11n HAL methods */ 1274 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1275 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1276 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1277 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1278 #define ath_hal_setrxchainmask(_ah, _rx) \ 1279 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1280 #define ath_hal_settxchainmask(_ah, _tx) \ 1281 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1282 #define ath_hal_split4ktrans(_ah) \ 1283 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1284 0, NULL) == HAL_OK) 1285 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1286 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1287 0, NULL) == HAL_OK) 1288 #define ath_hal_gtxto_supported(_ah) \ 1289 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1290 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1291 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1292 0, NULL) == HAL_OK) 1293 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1294 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1295 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1296 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1297 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1298 _txr0, _txtr0, _keyix, _ant, _flags, \ 1299 _rtsrate, _rtsdura) \ 1300 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1301 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1302 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1303 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1304 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1305 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1306 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1307 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1308 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1309 (_first), (_last), (_ds0))) 1310 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1311 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1312 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1313 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1314 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1315 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1316 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1317 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1318 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1319 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1320 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1321 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1322 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1323 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1324 (_size))) 1325 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1326 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1327 1328 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1329 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1330 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1331 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1332 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1333 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1334 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1335 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1336 (_first), (_last), (_lastaggr))) 1337 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1338 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1339 1340 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1341 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1342 (_series), (_ns), (_flags))) 1343 1344 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1345 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1346 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1347 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1348 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1349 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1350 1351 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1352 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1353 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1354 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1355 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1356 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1357 1358 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1359 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1360 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1361 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1362 #define ath_hal_gpioget(_ah, _gpio) \ 1363 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1364 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1365 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1366 1367 /* 1368 * PCIe suspend/resume/poweron/poweroff related macros 1369 */ 1370 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1371 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1372 #define ath_hal_disablepcie(_ah) \ 1373 ((*(_ah)->ah_disablePCIE)((_ah))) 1374 1375 /* 1376 * This is badly-named; you need to set the correct parameters 1377 * to begin to receive useful radar events; and even then 1378 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1379 * more information. 1380 */ 1381 #define ath_hal_enabledfs(_ah, _param) \ 1382 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1383 #define ath_hal_getdfsthresh(_ah, _param) \ 1384 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1385 #define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1386 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1387 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1388 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1389 (_buf), (_event))) 1390 #define ath_hal_is_fast_clock_enabled(_ah) \ 1391 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1392 #define ath_hal_radar_wait(_ah, _chan) \ 1393 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1394 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1395 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1396 #define ath_hal_get_chan_ext_busy(_ah) \ 1397 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1398 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1399 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1400 1401 #define ath_hal_spectral_supported(_ah) \ 1402 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1403 #define ath_hal_spectral_get_config(_ah, _p) \ 1404 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1405 #define ath_hal_spectral_configure(_ah, _p) \ 1406 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1407 #define ath_hal_spectral_start(_ah) \ 1408 ((*(_ah)->ah_spectralStart)((_ah))) 1409 #define ath_hal_spectral_stop(_ah) \ 1410 ((*(_ah)->ah_spectralStop)((_ah))) 1411 1412 #define ath_hal_btcoex_supported(_ah) \ 1413 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK) 1414 #define ath_hal_btcoex_set_info(_ah, _info) \ 1415 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info))) 1416 #define ath_hal_btcoex_set_config(_ah, _cfg) \ 1417 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg))) 1418 #define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \ 1419 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid))) 1420 #define ath_hal_btcoex_set_weights(_ah, _weight) \ 1421 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1422 #define ath_hal_btcoex_set_weights(_ah, _weight) \ 1423 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight))) 1424 #define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \ 1425 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr))) 1426 #define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \ 1427 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val))) 1428 #define ath_hal_btcoex_enable(_ah) \ 1429 ((*(_ah)->ah_btCoexEnable)((_ah))) 1430 #define ath_hal_btcoex_disable(_ah) \ 1431 ((*(_ah)->ah_btCoexDisable)((_ah))) 1432 1433 #define ath_hal_div_comb_conf_get(_ah, _conf) \ 1434 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf))) 1435 #define ath_hal_div_comb_conf_set(_ah, _conf) \ 1436 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf))) 1437 1438 #endif /* _DEV_ATH_ATHVAR_H */ 1439