1*572ff6f6SMatthew Dillon /* 2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc. 4*572ff6f6SMatthew Dillon * 5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8*572ff6f6SMatthew Dillon * 9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*572ff6f6SMatthew Dillon * 17*572ff6f6SMatthew Dillon * $FreeBSD$ 18*572ff6f6SMatthew Dillon */ 19*572ff6f6SMatthew Dillon #ifndef _ATH_AH_EEPROM_H_ 20*572ff6f6SMatthew Dillon #define _ATH_AH_EEPROM_H_ 21*572ff6f6SMatthew Dillon 22*572ff6f6SMatthew Dillon #define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */ 23*572ff6f6SMatthew Dillon /* 24*572ff6f6SMatthew Dillon * Version 3 EEPROMs are all 16K. 25*572ff6f6SMatthew Dillon * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info, 26*572ff6f6SMatthew Dillon * and 2.4Ghz ob/db for B & G 27*572ff6f6SMatthew Dillon * 3.2 has more accurate pcdac intercepts and analog chip 28*572ff6f6SMatthew Dillon * calibration. 29*572ff6f6SMatthew Dillon * 3.3 adds ctl in-band limit, 32 ctl's, and frequency 30*572ff6f6SMatthew Dillon * expansion 31*572ff6f6SMatthew Dillon * 3.4 adds xr power, gainI, and 2.4 turbo params 32*572ff6f6SMatthew Dillon */ 33*572ff6f6SMatthew Dillon #define AR_EEPROM_VER3 0x3000 /* Version 3.0; start of 16k EEPROM */ 34*572ff6f6SMatthew Dillon #define AR_EEPROM_VER3_1 0x3001 /* Version 3.1 */ 35*572ff6f6SMatthew Dillon #define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */ 36*572ff6f6SMatthew Dillon #define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */ 37*572ff6f6SMatthew Dillon #define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */ 38*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4 0x4000 /* Version 4.x */ 39*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */ 40*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */ 41*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */ 42*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */ 43*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */ 44*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */ 45*572ff6f6SMatthew Dillon #define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ 46*572ff6f6SMatthew Dillon #define AR_EEPROM_VER5 0x5000 /* Version 5.x */ 47*572ff6f6SMatthew Dillon #define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ 48*572ff6f6SMatthew Dillon #define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ 49*572ff6f6SMatthew Dillon #define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */ 50*572ff6f6SMatthew Dillon #define AR_EEPROM_VER5_4 0x5004 51*572ff6f6SMatthew Dillon /* 52*572ff6f6SMatthew Dillon * Version 14 EEPROMs came in with AR5416. 53*572ff6f6SMatthew Dillon * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc 54*572ff6f6SMatthew Dillon * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40 55*572ff6f6SMatthew Dillon */ 56*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14 0xE000 /* Version 14.x */ 57*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */ 58*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_2 0xE002 59*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_3 0xE003 60*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_7 0xE007 61*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_9 0xE009 62*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_16 0xE010 63*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_17 0xE011 64*572ff6f6SMatthew Dillon #define AR_EEPROM_VER14_19 0xE013 65*572ff6f6SMatthew Dillon 66*572ff6f6SMatthew Dillon enum { 67*572ff6f6SMatthew Dillon AR_EEP_RFKILL, /* use ath_hal_eepromGetFlag */ 68*572ff6f6SMatthew Dillon AR_EEP_AMODE, /* use ath_hal_eepromGetFlag */ 69*572ff6f6SMatthew Dillon AR_EEP_BMODE, /* use ath_hal_eepromGetFlag */ 70*572ff6f6SMatthew Dillon AR_EEP_GMODE, /* use ath_hal_eepromGetFlag */ 71*572ff6f6SMatthew Dillon AR_EEP_TURBO5DISABLE, /* use ath_hal_eepromGetFlag */ 72*572ff6f6SMatthew Dillon AR_EEP_TURBO2DISABLE, /* use ath_hal_eepromGetFlag */ 73*572ff6f6SMatthew Dillon AR_EEP_ISTALON, /* use ath_hal_eepromGetFlag */ 74*572ff6f6SMatthew Dillon AR_EEP_32KHZCRYSTAL, /* use ath_hal_eepromGetFlag */ 75*572ff6f6SMatthew Dillon AR_EEP_MACADDR, /* uint8_t* */ 76*572ff6f6SMatthew Dillon AR_EEP_COMPRESS, /* use ath_hal_eepromGetFlag */ 77*572ff6f6SMatthew Dillon AR_EEP_FASTFRAME, /* use ath_hal_eepromGetFlag */ 78*572ff6f6SMatthew Dillon AR_EEP_AES, /* use ath_hal_eepromGetFlag */ 79*572ff6f6SMatthew Dillon AR_EEP_BURST, /* use ath_hal_eepromGetFlag */ 80*572ff6f6SMatthew Dillon AR_EEP_MAXQCU, /* uint16_t* */ 81*572ff6f6SMatthew Dillon AR_EEP_KCENTRIES, /* uint16_t* */ 82*572ff6f6SMatthew Dillon AR_EEP_NFTHRESH_5, /* int16_t* */ 83*572ff6f6SMatthew Dillon AR_EEP_NFTHRESH_2, /* int16_t* */ 84*572ff6f6SMatthew Dillon AR_EEP_REGDMN_0, /* uint16_t* */ 85*572ff6f6SMatthew Dillon AR_EEP_REGDMN_1, /* uint16_t* */ 86*572ff6f6SMatthew Dillon AR_EEP_OPCAP, /* uint16_t* */ 87*572ff6f6SMatthew Dillon AR_EEP_OPMODE, /* uint16_t* */ 88*572ff6f6SMatthew Dillon AR_EEP_RFSILENT, /* uint16_t* */ 89*572ff6f6SMatthew Dillon AR_EEP_OB_5, /* uint8_t* */ 90*572ff6f6SMatthew Dillon AR_EEP_DB_5, /* uint8_t* */ 91*572ff6f6SMatthew Dillon AR_EEP_OB_2, /* uint8_t* */ 92*572ff6f6SMatthew Dillon AR_EEP_DB_2, /* uint8_t* */ 93*572ff6f6SMatthew Dillon AR_EEP_TXMASK, /* uint8_t* */ 94*572ff6f6SMatthew Dillon AR_EEP_RXMASK, /* uint8_t* */ 95*572ff6f6SMatthew Dillon AR_EEP_RXGAIN_TYPE, /* uint8_t* */ 96*572ff6f6SMatthew Dillon AR_EEP_TXGAIN_TYPE, /* uint8_t* */ 97*572ff6f6SMatthew Dillon AR_EEP_DAC_HPWR_5G, /* uint8_t* */ 98*572ff6f6SMatthew Dillon AR_EEP_OL_PWRCTRL, /* use ath_hal_eepromGetFlag */ 99*572ff6f6SMatthew Dillon AR_EEP_FSTCLK_5G, /* use ath_hal_eepromGetFlag */ 100*572ff6f6SMatthew Dillon AR_EEP_ANTGAINMAX_5, /* int8_t* */ 101*572ff6f6SMatthew Dillon AR_EEP_ANTGAINMAX_2, /* int8_t* */ 102*572ff6f6SMatthew Dillon AR_EEP_WRITEPROTECT, /* use ath_hal_eepromGetFlag */ 103*572ff6f6SMatthew Dillon AR_EEP_PWR_TABLE_OFFSET,/* int8_t* */ 104*572ff6f6SMatthew Dillon AR_EEP_PWDCLKIND, /* uint8_t* */ 105*572ff6f6SMatthew Dillon AR_EEP_TEMPSENSE_SLOPE, /* int8_t* */ 106*572ff6f6SMatthew Dillon AR_EEP_TEMPSENSE_SLOPE_PAL_ON, /* int8_t* */ 107*572ff6f6SMatthew Dillon AR_EEP_FRAC_N_5G, /* uint8_t* */ 108*572ff6f6SMatthew Dillon 109*572ff6f6SMatthew Dillon /* New fields for AR9300 and later */ 110*572ff6f6SMatthew Dillon AR_EEP_DRIVE_STRENGTH, 111*572ff6f6SMatthew Dillon AR_EEP_PAPRD_ENABLED, 112*572ff6f6SMatthew Dillon }; 113*572ff6f6SMatthew Dillon 114*572ff6f6SMatthew Dillon typedef struct { 115*572ff6f6SMatthew Dillon uint16_t rdEdge; 116*572ff6f6SMatthew Dillon uint16_t twice_rdEdgePower; 117*572ff6f6SMatthew Dillon HAL_BOOL flag; 118*572ff6f6SMatthew Dillon } RD_EDGES_POWER; 119*572ff6f6SMatthew Dillon 120*572ff6f6SMatthew Dillon /* XXX should probably be version-dependent */ 121*572ff6f6SMatthew Dillon #define SD_NO_CTL 0xf0 122*572ff6f6SMatthew Dillon #define NO_CTL 0xff 123*572ff6f6SMatthew Dillon #define CTL_MODE_M 0x0f 124*572ff6f6SMatthew Dillon #define CTL_11A 0 125*572ff6f6SMatthew Dillon #define CTL_11B 1 126*572ff6f6SMatthew Dillon #define CTL_11G 2 127*572ff6f6SMatthew Dillon #define CTL_TURBO 3 128*572ff6f6SMatthew Dillon #define CTL_108G 4 129*572ff6f6SMatthew Dillon #define CTL_2GHT20 5 130*572ff6f6SMatthew Dillon #define CTL_5GHT20 6 131*572ff6f6SMatthew Dillon #define CTL_2GHT40 7 132*572ff6f6SMatthew Dillon #define CTL_5GHT40 8 133*572ff6f6SMatthew Dillon 134*572ff6f6SMatthew Dillon /* XXX must match what FCC/MKK/ETSI are defined as in ah_regdomain.h */ 135*572ff6f6SMatthew Dillon #define HAL_REG_DMN_MASK 0xf0 136*572ff6f6SMatthew Dillon #define HAL_REGDMN_FCC 0x10 137*572ff6f6SMatthew Dillon #define HAL_REGDMN_MKK 0x40 138*572ff6f6SMatthew Dillon #define HAL_REGDMN_ETSI 0x30 139*572ff6f6SMatthew Dillon 140*572ff6f6SMatthew Dillon #define is_reg_dmn_fcc(reg_dmn) \ 141*572ff6f6SMatthew Dillon (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_FCC) ? 1 : 0) 142*572ff6f6SMatthew Dillon #define is_reg_dmn_etsi(reg_dmn) \ 143*572ff6f6SMatthew Dillon (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_ETSI) ? 1 : 0) 144*572ff6f6SMatthew Dillon #define is_reg_dmn_mkk(reg_dmn) \ 145*572ff6f6SMatthew Dillon (((reg_dmn & HAL_REG_DMN_MASK) == HAL_REGDMN_MKK) ? 1 : 0) 146*572ff6f6SMatthew Dillon 147*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 148*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 149*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 150*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 151*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 152*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 153*572ff6f6SMatthew Dillon 154*572ff6f6SMatthew Dillon /* regulatory capabilities prior to eeprom version 4.0 */ 155*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 156*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 157*572ff6f6SMatthew Dillon 158*572ff6f6SMatthew Dillon #define AR_NO_SPUR 0x8000 159*572ff6f6SMatthew Dillon 160*572ff6f6SMatthew Dillon /* XXX exposed to chip code */ 161*572ff6f6SMatthew Dillon #define MAX_RATE_POWER 63 162*572ff6f6SMatthew Dillon 163*572ff6f6SMatthew Dillon HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah); 164*572ff6f6SMatthew Dillon HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah); 165*572ff6f6SMatthew Dillon HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah); 166*572ff6f6SMatthew Dillon HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah); 167*572ff6f6SMatthew Dillon HAL_STATUS ath_hal_9287EepromAttach(struct ath_hal *ah); 168*572ff6f6SMatthew Dillon #endif /* _ATH_AH_EEPROM_H_ */ 169