1*572ff6f6SMatthew Dillon /* 2*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3*572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc. 4*572ff6f6SMatthew Dillon * 5*572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any 6*572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above 7*572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies. 8*572ff6f6SMatthew Dillon * 9*572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*572ff6f6SMatthew Dillon * 17*572ff6f6SMatthew Dillon * $FreeBSD$ 18*572ff6f6SMatthew Dillon */ 19*572ff6f6SMatthew Dillon #ifndef _ATH_AH_EEPROM_V3_H_ 20*572ff6f6SMatthew Dillon #define _ATH_AH_EEPROM_V3_H_ 21*572ff6f6SMatthew Dillon 22*572ff6f6SMatthew Dillon #include "ah_eeprom.h" 23*572ff6f6SMatthew Dillon 24*572ff6f6SMatthew Dillon /* EEPROM defines for Version 2 & 3 AR5211 chips */ 25*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT 0x0f /* RF Silent/Clock Run Enable */ 26*572ff6f6SMatthew Dillon #define AR_EEPROM_MAC(i) (0x1d+(i)) /* MAC address word */ 27*572ff6f6SMatthew Dillon #define AR_EEPROM_MAGIC 0x3d /* magic number */ 28*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT 0x3f /* EEPROM protect bits */ 29*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_PCIE 0x01 /* EEPROM protect bits for Condor/Swan*/ 30*572ff6f6SMatthew Dillon #define AR_EEPROM_REG_DOMAIN 0xbf /* current regulatory domain */ 31*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */ 32*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i)) 33*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE) 34*572ff6f6SMatthew Dillon #define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1) 35*572ff6f6SMatthew Dillon 36*572ff6f6SMatthew Dillon /* FLASH(EEPROM) Defines for AR531X chips */ 37*572ff6f6SMatthew Dillon #define AR_EEPROM_SIZE_LOWER 0x1b /* size info -- lower */ 38*572ff6f6SMatthew Dillon #define AR_EEPROM_SIZE_UPPER 0x1c /* size info -- upper */ 39*572ff6f6SMatthew Dillon #define AR_EEPROM_SIZE_UPPER_MASK 0xfff0 40*572ff6f6SMatthew Dillon #define AR_EEPROM_SIZE_UPPER_SHIFT 4 41*572ff6f6SMatthew Dillon #define AR_EEPROM_SIZE_ENDLOC_SHIFT 12 42*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_MAX_LOC 0x400 43*572ff6f6SMatthew Dillon #define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE) 44*572ff6f6SMatthew Dillon 45*572ff6f6SMatthew Dillon /* regulatory capabilities offsets */ 46*572ff6f6SMatthew Dillon #define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA 47*572ff6f6SMatthew Dillon #define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF /* prior to 4.0 */ 48*572ff6f6SMatthew Dillon 49*572ff6f6SMatthew Dillon /* regulatory capabilities */ 50*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 51*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 52*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 53*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 54*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 55*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 56*572ff6f6SMatthew Dillon 57*572ff6f6SMatthew Dillon /* regulatory capabilities prior to eeprom version 4.0 */ 58*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 59*572ff6f6SMatthew Dillon #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 60*572ff6f6SMatthew Dillon 61*572ff6f6SMatthew Dillon /* 62*572ff6f6SMatthew Dillon * AR2413 (includes AR5413) 63*572ff6f6SMatthew Dillon */ 64*572ff6f6SMatthew Dillon #define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0 /* EEPROM serial number */ 65*572ff6f6SMatthew Dillon #define AR_EEPROM_SERIAL_NUM_SIZE 12 /* EEPROM serial number size */ 66*572ff6f6SMatthew Dillon #define AR_EEPROM_CAPABILITIES_OFFSET 0xC9 /* EEPROM Location of capabilities */ 67*572ff6f6SMatthew Dillon 68*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 69*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 70*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 71*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 72*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 73*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_MAXQCU_S 4 74*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 75*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 76*572ff6f6SMatthew Dillon #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 77*572ff6f6SMatthew Dillon 78*572ff6f6SMatthew Dillon /* XXX used to index various EEPROM-derived data structures */ 79*572ff6f6SMatthew Dillon enum { 80*572ff6f6SMatthew Dillon headerInfo11A = 0, 81*572ff6f6SMatthew Dillon headerInfo11B = 1, 82*572ff6f6SMatthew Dillon headerInfo11G = 2, 83*572ff6f6SMatthew Dillon }; 84*572ff6f6SMatthew Dillon 85*572ff6f6SMatthew Dillon #define GROUPS_OFFSET3_2 0x100 /* groups offset for ver3.2 and earlier */ 86*572ff6f6SMatthew Dillon #define GROUPS_OFFSET3_3 0x150 /* groups offset for ver3.3 */ 87*572ff6f6SMatthew Dillon /* relative offset of GROUPi to GROUPS_OFFSET */ 88*572ff6f6SMatthew Dillon #define GROUP1_OFFSET 0x0 89*572ff6f6SMatthew Dillon #define GROUP2_OFFSET 0x5 90*572ff6f6SMatthew Dillon #define GROUP3_OFFSET 0x37 91*572ff6f6SMatthew Dillon #define GROUP4_OFFSET 0x46 92*572ff6f6SMatthew Dillon #define GROUP5_OFFSET 0x55 93*572ff6f6SMatthew Dillon #define GROUP6_OFFSET 0x65 94*572ff6f6SMatthew Dillon #define GROUP7_OFFSET 0x69 95*572ff6f6SMatthew Dillon #define GROUP8_OFFSET 0x6f 96*572ff6f6SMatthew Dillon 97*572ff6f6SMatthew Dillon /* RF silent fields in EEPROM */ 98*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 99*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 100*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_POLARITY 0x0002 101*572ff6f6SMatthew Dillon #define AR_EEPROM_RFSILENT_POLARITY_S 1 102*572ff6f6SMatthew Dillon 103*572ff6f6SMatthew Dillon /* Protect Bits RP is read protect, WP is write protect */ 104*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_0_31 0x0001 105*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_0_31 0x0002 106*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_32_63 0x0004 107*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_32_63 0x0008 108*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_64_127 0x0010 109*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_64_127 0x0020 110*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_128_191 0x0040 111*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_128_191 0x0080 112*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_192_207 0x0100 113*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_192_207 0x0200 114*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_208_223 0x0400 115*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_208_223 0x0800 116*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_224_239 0x1000 117*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_224_239 0x2000 118*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_RP_240_255 0x4000 119*572ff6f6SMatthew Dillon #define AR_EEPROM_PROTECT_WP_240_255 0x8000 120*572ff6f6SMatthew Dillon 121*572ff6f6SMatthew Dillon #define AR_EEPROM_MODAL_SPURS 5 122*572ff6f6SMatthew Dillon #define AR_SPUR_5413_1 1640 /* Freq 2464 */ 123*572ff6f6SMatthew Dillon #define AR_SPUR_5413_2 1200 /* Freq 2420 */ 124*572ff6f6SMatthew Dillon 125*572ff6f6SMatthew Dillon /* 126*572ff6f6SMatthew Dillon * EEPROM fixed point conversion scale factors. 127*572ff6f6SMatthew Dillon * NB: if you change one be sure to keep the other in sync. 128*572ff6f6SMatthew Dillon */ 129*572ff6f6SMatthew Dillon #define EEP_SCALE 100 /* conversion scale to avoid fp arith */ 130*572ff6f6SMatthew Dillon #define EEP_DELTA 10 /* SCALE/10, to avoid arith divide */ 131*572ff6f6SMatthew Dillon 132*572ff6f6SMatthew Dillon #define PWR_MIN 0 133*572ff6f6SMatthew Dillon #define PWR_MAX 3150 /* 31.5 * SCALE */ 134*572ff6f6SMatthew Dillon #define PWR_STEP 50 /* 0.5 * SCALE */ 135*572ff6f6SMatthew Dillon /* Keep 2 above defines together */ 136*572ff6f6SMatthew Dillon 137*572ff6f6SMatthew Dillon #define NUM_11A_EEPROM_CHANNELS 10 138*572ff6f6SMatthew Dillon #define NUM_2_4_EEPROM_CHANNELS 3 139*572ff6f6SMatthew Dillon #define NUM_PCDAC_VALUES 11 140*572ff6f6SMatthew Dillon #define NUM_TEST_FREQUENCIES 8 141*572ff6f6SMatthew Dillon #define NUM_EDGES 8 142*572ff6f6SMatthew Dillon #define NUM_INTERCEPTS 11 143*572ff6f6SMatthew Dillon #define FREQ_MASK 0x7f 144*572ff6f6SMatthew Dillon #define FREQ_MASK_3_3 0xff /* expanded in version 3.3 */ 145*572ff6f6SMatthew Dillon #define PCDAC_MASK 0x3f 146*572ff6f6SMatthew Dillon #define POWER_MASK 0x3f 147*572ff6f6SMatthew Dillon #define NON_EDGE_FLAG_MASK 0x40 148*572ff6f6SMatthew Dillon #define CHANNEL_POWER_INFO 8 149*572ff6f6SMatthew Dillon #define OBDB_UNSET 0xffff 150*572ff6f6SMatthew Dillon #define CHANNEL_UNUSED 0xff 151*572ff6f6SMatthew Dillon #define SCALE_OC_DELTA(_x) (((_x) * 2) / 10) 152*572ff6f6SMatthew Dillon 153*572ff6f6SMatthew Dillon /* Used during pcdac table construction */ 154*572ff6f6SMatthew Dillon #define PCDAC_START 1 155*572ff6f6SMatthew Dillon #define PCDAC_STOP 63 156*572ff6f6SMatthew Dillon #define PCDAC_STEP 1 157*572ff6f6SMatthew Dillon #define PWR_TABLE_SIZE 64 158*572ff6f6SMatthew Dillon #define MAX_RATE_POWER 63 159*572ff6f6SMatthew Dillon 160*572ff6f6SMatthew Dillon /* Used during power/rate table construction */ 161*572ff6f6SMatthew Dillon #define NUM_CTLS 16 162*572ff6f6SMatthew Dillon #define NUM_CTLS_3_3 32 /* expanded in version 3.3 */ 163*572ff6f6SMatthew Dillon #define NUM_CTLS_MAX NUM_CTLS_3_3 164*572ff6f6SMatthew Dillon 165*572ff6f6SMatthew Dillon typedef struct fullPcdacStruct { 166*572ff6f6SMatthew Dillon uint16_t channelValue; 167*572ff6f6SMatthew Dillon uint16_t pcdacMin; 168*572ff6f6SMatthew Dillon uint16_t pcdacMax; 169*572ff6f6SMatthew Dillon uint16_t numPcdacValues; 170*572ff6f6SMatthew Dillon uint16_t PcdacValues[64]; 171*572ff6f6SMatthew Dillon /* power is 32bit since in dest it is scaled */ 172*572ff6f6SMatthew Dillon int16_t PwrValues[64]; 173*572ff6f6SMatthew Dillon } FULL_PCDAC_STRUCT; 174*572ff6f6SMatthew Dillon 175*572ff6f6SMatthew Dillon typedef struct dataPerChannel { 176*572ff6f6SMatthew Dillon uint16_t channelValue; 177*572ff6f6SMatthew Dillon uint16_t pcdacMin; 178*572ff6f6SMatthew Dillon uint16_t pcdacMax; 179*572ff6f6SMatthew Dillon uint16_t numPcdacValues; 180*572ff6f6SMatthew Dillon uint16_t PcdacValues[NUM_PCDAC_VALUES]; 181*572ff6f6SMatthew Dillon /* NB: power is 32bit since in dest it is scaled */ 182*572ff6f6SMatthew Dillon int16_t PwrValues[NUM_PCDAC_VALUES]; 183*572ff6f6SMatthew Dillon } DATA_PER_CHANNEL; 184*572ff6f6SMatthew Dillon 185*572ff6f6SMatthew Dillon /* points to the appropriate pcdac structs in the above struct based on mode */ 186*572ff6f6SMatthew Dillon typedef struct pcdacsEeprom { 187*572ff6f6SMatthew Dillon const uint16_t *pChannelList; 188*572ff6f6SMatthew Dillon uint16_t numChannels; 189*572ff6f6SMatthew Dillon const DATA_PER_CHANNEL *pDataPerChannel; 190*572ff6f6SMatthew Dillon } PCDACS_EEPROM; 191*572ff6f6SMatthew Dillon 192*572ff6f6SMatthew Dillon typedef struct trgtPowerInfo { 193*572ff6f6SMatthew Dillon uint16_t twicePwr54; 194*572ff6f6SMatthew Dillon uint16_t twicePwr48; 195*572ff6f6SMatthew Dillon uint16_t twicePwr36; 196*572ff6f6SMatthew Dillon uint16_t twicePwr6_24; 197*572ff6f6SMatthew Dillon uint16_t testChannel; 198*572ff6f6SMatthew Dillon } TRGT_POWER_INFO; 199*572ff6f6SMatthew Dillon 200*572ff6f6SMatthew Dillon typedef struct trgtPowerAllModes { 201*572ff6f6SMatthew Dillon uint16_t numTargetPwr_11a; 202*572ff6f6SMatthew Dillon TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES]; 203*572ff6f6SMatthew Dillon uint16_t numTargetPwr_11g; 204*572ff6f6SMatthew Dillon TRGT_POWER_INFO trgtPwr_11g[3]; 205*572ff6f6SMatthew Dillon uint16_t numTargetPwr_11b; 206*572ff6f6SMatthew Dillon TRGT_POWER_INFO trgtPwr_11b[2]; 207*572ff6f6SMatthew Dillon } TRGT_POWER_ALL_MODES; 208*572ff6f6SMatthew Dillon 209*572ff6f6SMatthew Dillon typedef struct cornerCalInfo { 210*572ff6f6SMatthew Dillon uint16_t gSel; 211*572ff6f6SMatthew Dillon uint16_t pd84; 212*572ff6f6SMatthew Dillon uint16_t pd90; 213*572ff6f6SMatthew Dillon uint16_t clip; 214*572ff6f6SMatthew Dillon } CORNER_CAL_INFO; 215*572ff6f6SMatthew Dillon 216*572ff6f6SMatthew Dillon /* 217*572ff6f6SMatthew Dillon * EEPROM version 4 definitions 218*572ff6f6SMatthew Dillon */ 219*572ff6f6SMatthew Dillon #define NUM_XPD_PER_CHANNEL 4 220*572ff6f6SMatthew Dillon #define NUM_POINTS_XPD0 4 221*572ff6f6SMatthew Dillon #define NUM_POINTS_XPD3 3 222*572ff6f6SMatthew Dillon #define IDEAL_10dB_INTERCEPT_2G 35 223*572ff6f6SMatthew Dillon #define IDEAL_10dB_INTERCEPT_5G 55 224*572ff6f6SMatthew Dillon 225*572ff6f6SMatthew Dillon #define TENX_OFDM_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 226*572ff6f6SMatthew Dillon #define TENX_CH14_FILTER_CCK_DELTA_INIT 15 /* power 1.5 dbm */ 227*572ff6f6SMatthew Dillon #define CCK_OFDM_GAIN_DELTA 15 228*572ff6f6SMatthew Dillon 229*572ff6f6SMatthew Dillon #define NUM_TARGET_POWER_LOCATIONS_11B 4 230*572ff6f6SMatthew Dillon #define NUM_TARGET_POWER_LOCATIONS_11G 6 231*572ff6f6SMatthew Dillon 232*572ff6f6SMatthew Dillon 233*572ff6f6SMatthew Dillon typedef struct { 234*572ff6f6SMatthew Dillon uint16_t xpd_gain; 235*572ff6f6SMatthew Dillon uint16_t numPcdacs; 236*572ff6f6SMatthew Dillon uint16_t pcdac[NUM_POINTS_XPD0]; 237*572ff6f6SMatthew Dillon int16_t pwr_t4[NUM_POINTS_XPD0]; /* or gainF */ 238*572ff6f6SMatthew Dillon } EXPN_DATA_PER_XPD_5112; 239*572ff6f6SMatthew Dillon 240*572ff6f6SMatthew Dillon typedef struct { 241*572ff6f6SMatthew Dillon uint16_t channelValue; 242*572ff6f6SMatthew Dillon int16_t maxPower_t4; 243*572ff6f6SMatthew Dillon EXPN_DATA_PER_XPD_5112 pDataPerXPD[NUM_XPD_PER_CHANNEL]; 244*572ff6f6SMatthew Dillon } EXPN_DATA_PER_CHANNEL_5112; 245*572ff6f6SMatthew Dillon 246*572ff6f6SMatthew Dillon typedef struct { 247*572ff6f6SMatthew Dillon uint16_t *pChannels; 248*572ff6f6SMatthew Dillon uint16_t numChannels; 249*572ff6f6SMatthew Dillon uint16_t xpdMask; /* mask of permitted xpd_gains */ 250*572ff6f6SMatthew Dillon EXPN_DATA_PER_CHANNEL_5112 *pDataPerChannel; 251*572ff6f6SMatthew Dillon } EEPROM_POWER_EXPN_5112; 252*572ff6f6SMatthew Dillon 253*572ff6f6SMatthew Dillon typedef struct { 254*572ff6f6SMatthew Dillon uint16_t channelValue; 255*572ff6f6SMatthew Dillon uint16_t pcd1_xg0; 256*572ff6f6SMatthew Dillon int16_t pwr1_xg0; 257*572ff6f6SMatthew Dillon uint16_t pcd2_delta_xg0; 258*572ff6f6SMatthew Dillon int16_t pwr2_xg0; 259*572ff6f6SMatthew Dillon uint16_t pcd3_delta_xg0; 260*572ff6f6SMatthew Dillon int16_t pwr3_xg0; 261*572ff6f6SMatthew Dillon uint16_t pcd4_delta_xg0; 262*572ff6f6SMatthew Dillon int16_t pwr4_xg0; 263*572ff6f6SMatthew Dillon int16_t maxPower_t4; 264*572ff6f6SMatthew Dillon int16_t pwr1_xg3; /* pcdac = 20 */ 265*572ff6f6SMatthew Dillon int16_t pwr2_xg3; /* pcdac = 35 */ 266*572ff6f6SMatthew Dillon int16_t pwr3_xg3; /* pcdac = 63 */ 267*572ff6f6SMatthew Dillon /* XXX - Should be pwr1_xg2, etc to agree with documentation */ 268*572ff6f6SMatthew Dillon } EEPROM_DATA_PER_CHANNEL_5112; 269*572ff6f6SMatthew Dillon 270*572ff6f6SMatthew Dillon typedef struct { 271*572ff6f6SMatthew Dillon uint16_t pChannels[NUM_11A_EEPROM_CHANNELS]; 272*572ff6f6SMatthew Dillon uint16_t numChannels; 273*572ff6f6SMatthew Dillon uint16_t xpdMask; /* mask of permitted xpd_gains */ 274*572ff6f6SMatthew Dillon EEPROM_DATA_PER_CHANNEL_5112 pDataPerChannel[NUM_11A_EEPROM_CHANNELS]; 275*572ff6f6SMatthew Dillon } EEPROM_POWER_5112; 276*572ff6f6SMatthew Dillon 277*572ff6f6SMatthew Dillon /* 278*572ff6f6SMatthew Dillon * EEPROM version 5 definitions (Griffin, et. al.). 279*572ff6f6SMatthew Dillon */ 280*572ff6f6SMatthew Dillon #define NUM_2_4_EEPROM_CHANNELS_2413 4 281*572ff6f6SMatthew Dillon #define NUM_11A_EEPROM_CHANNELS_2413 10 282*572ff6f6SMatthew Dillon #define PWR_TABLE_SIZE_2413 128 283*572ff6f6SMatthew Dillon 284*572ff6f6SMatthew Dillon /* Used during pdadc construction */ 285*572ff6f6SMatthew Dillon #define MAX_NUM_PDGAINS_PER_CHANNEL 4 286*572ff6f6SMatthew Dillon #define NUM_PDGAINS_PER_CHANNEL 2 287*572ff6f6SMatthew Dillon #define NUM_POINTS_LAST_PDGAIN 5 288*572ff6f6SMatthew Dillon #define NUM_POINTS_OTHER_PDGAINS 4 289*572ff6f6SMatthew Dillon #define XPD_GAIN1_GEN5 3 290*572ff6f6SMatthew Dillon #define XPD_GAIN2_GEN5 1 291*572ff6f6SMatthew Dillon #define MAX_PWR_RANGE_IN_HALF_DB 64 292*572ff6f6SMatthew Dillon #define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4 293*572ff6f6SMatthew Dillon 294*572ff6f6SMatthew Dillon typedef struct { 295*572ff6f6SMatthew Dillon uint16_t pd_gain; 296*572ff6f6SMatthew Dillon uint16_t numVpd; 297*572ff6f6SMatthew Dillon uint16_t Vpd[NUM_POINTS_LAST_PDGAIN]; 298*572ff6f6SMatthew Dillon int16_t pwr_t4[NUM_POINTS_LAST_PDGAIN]; /* or gainF */ 299*572ff6f6SMatthew Dillon } RAW_DATA_PER_PDGAIN_2413; 300*572ff6f6SMatthew Dillon 301*572ff6f6SMatthew Dillon typedef struct { 302*572ff6f6SMatthew Dillon uint16_t channelValue; 303*572ff6f6SMatthew Dillon int16_t maxPower_t4; 304*572ff6f6SMatthew Dillon uint16_t numPdGains; /* # Pd Gains per channel */ 305*572ff6f6SMatthew Dillon RAW_DATA_PER_PDGAIN_2413 pDataPerPDGain[MAX_NUM_PDGAINS_PER_CHANNEL]; 306*572ff6f6SMatthew Dillon } RAW_DATA_PER_CHANNEL_2413; 307*572ff6f6SMatthew Dillon 308*572ff6f6SMatthew Dillon /* XXX: assumes NUM_11A_EEPROM_CHANNELS_2413 >= NUM_2_4_EEPROM_CHANNELS_2413 ??? */ 309*572ff6f6SMatthew Dillon typedef struct { 310*572ff6f6SMatthew Dillon uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 311*572ff6f6SMatthew Dillon uint16_t numChannels; 312*572ff6f6SMatthew Dillon uint16_t xpd_mask; /* mask of permitted xpd_gains */ 313*572ff6f6SMatthew Dillon RAW_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 314*572ff6f6SMatthew Dillon } RAW_DATA_STRUCT_2413; 315*572ff6f6SMatthew Dillon 316*572ff6f6SMatthew Dillon typedef struct { 317*572ff6f6SMatthew Dillon uint16_t channelValue; 318*572ff6f6SMatthew Dillon uint16_t numPdGains; 319*572ff6f6SMatthew Dillon uint16_t Vpd_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 320*572ff6f6SMatthew Dillon int16_t pwr_I[MAX_NUM_PDGAINS_PER_CHANNEL]; 321*572ff6f6SMatthew Dillon uint16_t Vpd_delta[NUM_POINTS_LAST_PDGAIN] 322*572ff6f6SMatthew Dillon [MAX_NUM_PDGAINS_PER_CHANNEL]; 323*572ff6f6SMatthew Dillon int16_t pwr_delta_t2[NUM_POINTS_LAST_PDGAIN] 324*572ff6f6SMatthew Dillon [MAX_NUM_PDGAINS_PER_CHANNEL]; 325*572ff6f6SMatthew Dillon int16_t maxPower_t4; 326*572ff6f6SMatthew Dillon } EEPROM_DATA_PER_CHANNEL_2413; 327*572ff6f6SMatthew Dillon 328*572ff6f6SMatthew Dillon typedef struct { 329*572ff6f6SMatthew Dillon uint16_t pChannels[NUM_11A_EEPROM_CHANNELS_2413]; 330*572ff6f6SMatthew Dillon uint16_t numChannels; 331*572ff6f6SMatthew Dillon uint16_t xpd_mask; /* mask of permitted xpd_gains */ 332*572ff6f6SMatthew Dillon EEPROM_DATA_PER_CHANNEL_2413 pDataPerChannel[NUM_11A_EEPROM_CHANNELS_2413]; 333*572ff6f6SMatthew Dillon } EEPROM_DATA_STRUCT_2413; 334*572ff6f6SMatthew Dillon 335*572ff6f6SMatthew Dillon /* 336*572ff6f6SMatthew Dillon * Information retrieved from EEPROM. 337*572ff6f6SMatthew Dillon */ 338*572ff6f6SMatthew Dillon typedef struct { 339*572ff6f6SMatthew Dillon uint16_t ee_version; /* Version field */ 340*572ff6f6SMatthew Dillon uint16_t ee_protect; /* EEPROM protect field */ 341*572ff6f6SMatthew Dillon uint16_t ee_regdomain; /* Regulatory domain */ 342*572ff6f6SMatthew Dillon 343*572ff6f6SMatthew Dillon /* General Device Parameters */ 344*572ff6f6SMatthew Dillon uint16_t ee_turbo5Disable; 345*572ff6f6SMatthew Dillon uint16_t ee_turbo2Disable; 346*572ff6f6SMatthew Dillon uint16_t ee_rfKill; 347*572ff6f6SMatthew Dillon uint16_t ee_deviceType; 348*572ff6f6SMatthew Dillon uint16_t ee_turbo2WMaxPower5; 349*572ff6f6SMatthew Dillon uint16_t ee_turbo2WMaxPower2; 350*572ff6f6SMatthew Dillon uint16_t ee_xrTargetPower5; 351*572ff6f6SMatthew Dillon uint16_t ee_xrTargetPower2; 352*572ff6f6SMatthew Dillon uint16_t ee_Amode; 353*572ff6f6SMatthew Dillon uint16_t ee_regCap; 354*572ff6f6SMatthew Dillon uint16_t ee_Bmode; 355*572ff6f6SMatthew Dillon uint16_t ee_Gmode; 356*572ff6f6SMatthew Dillon int8_t ee_antennaGainMax[2]; 357*572ff6f6SMatthew Dillon uint16_t ee_xtnd5GSupport; 358*572ff6f6SMatthew Dillon uint8_t ee_cckOfdmPwrDelta; 359*572ff6f6SMatthew Dillon uint8_t ee_exist32kHzCrystal; 360*572ff6f6SMatthew Dillon uint16_t ee_targetPowersStart; 361*572ff6f6SMatthew Dillon uint16_t ee_fixedBias5; 362*572ff6f6SMatthew Dillon uint16_t ee_fixedBias2; 363*572ff6f6SMatthew Dillon uint16_t ee_cckOfdmGainDelta; 364*572ff6f6SMatthew Dillon uint16_t ee_scaledCh14FilterCckDelta; 365*572ff6f6SMatthew Dillon uint16_t ee_eepMap; 366*572ff6f6SMatthew Dillon uint16_t ee_earStart; 367*572ff6f6SMatthew Dillon 368*572ff6f6SMatthew Dillon /* 5 GHz / 2.4 GHz CKK / 2.4 GHz OFDM common parameters */ 369*572ff6f6SMatthew Dillon uint16_t ee_switchSettling[3]; 370*572ff6f6SMatthew Dillon uint16_t ee_txrxAtten[3]; 371*572ff6f6SMatthew Dillon uint16_t ee_txEndToXLNAOn[3]; 372*572ff6f6SMatthew Dillon uint16_t ee_thresh62[3]; 373*572ff6f6SMatthew Dillon uint16_t ee_txEndToXPAOff[3]; 374*572ff6f6SMatthew Dillon uint16_t ee_txFrameToXPAOn[3]; 375*572ff6f6SMatthew Dillon int8_t ee_adcDesiredSize[3]; /* 8-bit signed value */ 376*572ff6f6SMatthew Dillon int8_t ee_pgaDesiredSize[3]; /* 8-bit signed value */ 377*572ff6f6SMatthew Dillon int16_t ee_noiseFloorThresh[3]; 378*572ff6f6SMatthew Dillon uint16_t ee_xlnaGain[3]; 379*572ff6f6SMatthew Dillon uint16_t ee_xgain[3]; 380*572ff6f6SMatthew Dillon uint16_t ee_xpd[3]; 381*572ff6f6SMatthew Dillon uint16_t ee_antennaControl[11][3]; 382*572ff6f6SMatthew Dillon uint16_t ee_falseDetectBackoff[3]; 383*572ff6f6SMatthew Dillon uint16_t ee_gainI[3]; 384*572ff6f6SMatthew Dillon uint16_t ee_rxtxMargin[3]; 385*572ff6f6SMatthew Dillon 386*572ff6f6SMatthew Dillon /* new parameters added for the AR2413 */ 387*572ff6f6SMatthew Dillon HAL_BOOL ee_disableXr5; 388*572ff6f6SMatthew Dillon HAL_BOOL ee_disableXr2; 389*572ff6f6SMatthew Dillon uint16_t ee_eepMap2PowerCalStart; 390*572ff6f6SMatthew Dillon uint16_t ee_capField; 391*572ff6f6SMatthew Dillon 392*572ff6f6SMatthew Dillon uint16_t ee_switchSettlingTurbo[2]; 393*572ff6f6SMatthew Dillon uint16_t ee_txrxAttenTurbo[2]; 394*572ff6f6SMatthew Dillon int8_t ee_adcDesiredSizeTurbo[2]; 395*572ff6f6SMatthew Dillon int8_t ee_pgaDesiredSizeTurbo[2]; 396*572ff6f6SMatthew Dillon uint16_t ee_rxtxMarginTurbo[2]; 397*572ff6f6SMatthew Dillon 398*572ff6f6SMatthew Dillon /* 5 GHz parameters */ 399*572ff6f6SMatthew Dillon uint16_t ee_ob1; 400*572ff6f6SMatthew Dillon uint16_t ee_db1; 401*572ff6f6SMatthew Dillon uint16_t ee_ob2; 402*572ff6f6SMatthew Dillon uint16_t ee_db2; 403*572ff6f6SMatthew Dillon uint16_t ee_ob3; 404*572ff6f6SMatthew Dillon uint16_t ee_db3; 405*572ff6f6SMatthew Dillon uint16_t ee_ob4; 406*572ff6f6SMatthew Dillon uint16_t ee_db4; 407*572ff6f6SMatthew Dillon 408*572ff6f6SMatthew Dillon /* 2.4 GHz parameters */ 409*572ff6f6SMatthew Dillon uint16_t ee_obFor24; 410*572ff6f6SMatthew Dillon uint16_t ee_dbFor24; 411*572ff6f6SMatthew Dillon uint16_t ee_obFor24g; 412*572ff6f6SMatthew Dillon uint16_t ee_dbFor24g; 413*572ff6f6SMatthew Dillon uint16_t ee_ob2GHz[2]; 414*572ff6f6SMatthew Dillon uint16_t ee_db2GHz[2]; 415*572ff6f6SMatthew Dillon uint16_t ee_numCtls; 416*572ff6f6SMatthew Dillon uint16_t ee_ctl[NUM_CTLS_MAX]; 417*572ff6f6SMatthew Dillon uint16_t ee_iqCalI[2]; 418*572ff6f6SMatthew Dillon uint16_t ee_iqCalQ[2]; 419*572ff6f6SMatthew Dillon uint16_t ee_calPier11g[NUM_2_4_EEPROM_CHANNELS]; 420*572ff6f6SMatthew Dillon uint16_t ee_calPier11b[NUM_2_4_EEPROM_CHANNELS]; 421*572ff6f6SMatthew Dillon 422*572ff6f6SMatthew Dillon /* corner calibration information */ 423*572ff6f6SMatthew Dillon CORNER_CAL_INFO ee_cornerCal; 424*572ff6f6SMatthew Dillon 425*572ff6f6SMatthew Dillon uint16_t ee_opCap; 426*572ff6f6SMatthew Dillon 427*572ff6f6SMatthew Dillon /* 11a info */ 428*572ff6f6SMatthew Dillon uint16_t ee_channels11a[NUM_11A_EEPROM_CHANNELS]; 429*572ff6f6SMatthew Dillon uint16_t ee_numChannels11a; 430*572ff6f6SMatthew Dillon DATA_PER_CHANNEL ee_dataPerChannel11a[NUM_11A_EEPROM_CHANNELS]; 431*572ff6f6SMatthew Dillon 432*572ff6f6SMatthew Dillon uint16_t ee_numChannels2_4; 433*572ff6f6SMatthew Dillon uint16_t ee_channels11g[NUM_2_4_EEPROM_CHANNELS]; 434*572ff6f6SMatthew Dillon uint16_t ee_channels11b[NUM_2_4_EEPROM_CHANNELS]; 435*572ff6f6SMatthew Dillon uint16_t ee_spurChans[AR_EEPROM_MODAL_SPURS][2]; 436*572ff6f6SMatthew Dillon 437*572ff6f6SMatthew Dillon /* 11g info */ 438*572ff6f6SMatthew Dillon DATA_PER_CHANNEL ee_dataPerChannel11g[NUM_2_4_EEPROM_CHANNELS]; 439*572ff6f6SMatthew Dillon 440*572ff6f6SMatthew Dillon /* 11b info */ 441*572ff6f6SMatthew Dillon DATA_PER_CHANNEL ee_dataPerChannel11b[NUM_2_4_EEPROM_CHANNELS]; 442*572ff6f6SMatthew Dillon 443*572ff6f6SMatthew Dillon TRGT_POWER_ALL_MODES ee_tpow; 444*572ff6f6SMatthew Dillon 445*572ff6f6SMatthew Dillon RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*NUM_CTLS_MAX]; 446*572ff6f6SMatthew Dillon 447*572ff6f6SMatthew Dillon union { 448*572ff6f6SMatthew Dillon EEPROM_POWER_EXPN_5112 eu_modePowerArray5112[3]; 449*572ff6f6SMatthew Dillon RAW_DATA_STRUCT_2413 eu_rawDataset2413[3]; 450*572ff6f6SMatthew Dillon } ee_u; 451*572ff6f6SMatthew Dillon } HAL_EEPROM; 452*572ff6f6SMatthew Dillon 453*572ff6f6SMatthew Dillon /* write-around defines */ 454*572ff6f6SMatthew Dillon #define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a 455*572ff6f6SMatthew Dillon #define ee_trgtPwr_11a ee_tpow.trgtPwr_11a 456*572ff6f6SMatthew Dillon #define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g 457*572ff6f6SMatthew Dillon #define ee_trgtPwr_11g ee_tpow.trgtPwr_11g 458*572ff6f6SMatthew Dillon #define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b 459*572ff6f6SMatthew Dillon #define ee_trgtPwr_11b ee_tpow.trgtPwr_11b 460*572ff6f6SMatthew Dillon #define ee_modePowerArray5112 ee_u.eu_modePowerArray5112 461*572ff6f6SMatthew Dillon #define ee_rawDataset2413 ee_u.eu_rawDataset2413 462*572ff6f6SMatthew Dillon #endif /* _ATH_AH_EEPROM_V3_H_ */ 463