1572ff6f6SMatthew Dillon /*
2572ff6f6SMatthew Dillon * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3572ff6f6SMatthew Dillon * Copyright (c) 2002-2008 Atheros Communications, Inc.
4572ff6f6SMatthew Dillon *
5572ff6f6SMatthew Dillon * Permission to use, copy, modify, and/or distribute this software for any
6572ff6f6SMatthew Dillon * purpose with or without fee is hereby granted, provided that the above
7572ff6f6SMatthew Dillon * copyright notice and this permission notice appear in all copies.
8572ff6f6SMatthew Dillon *
9572ff6f6SMatthew Dillon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10572ff6f6SMatthew Dillon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11572ff6f6SMatthew Dillon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12572ff6f6SMatthew Dillon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13572ff6f6SMatthew Dillon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14572ff6f6SMatthew Dillon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15572ff6f6SMatthew Dillon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16572ff6f6SMatthew Dillon *
17572ff6f6SMatthew Dillon * $FreeBSD$
18572ff6f6SMatthew Dillon */
19572ff6f6SMatthew Dillon #ifndef _ATH_AH_INTERAL_H_
20572ff6f6SMatthew Dillon #define _ATH_AH_INTERAL_H_
21572ff6f6SMatthew Dillon /*
22572ff6f6SMatthew Dillon * Atheros Device Hardware Access Layer (HAL).
23572ff6f6SMatthew Dillon *
24572ff6f6SMatthew Dillon * Internal definitions.
25572ff6f6SMatthew Dillon */
26572ff6f6SMatthew Dillon #define AH_NULL 0
27572ff6f6SMatthew Dillon #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28572ff6f6SMatthew Dillon #define AH_MAX(a,b) ((a)>(b)?(a):(b))
29572ff6f6SMatthew Dillon
30dc249793SMatthew Dillon #include <netproto/802_11/_ieee80211.h>
31572ff6f6SMatthew Dillon #include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
32572ff6f6SMatthew Dillon
33572ff6f6SMatthew Dillon #ifndef AH_SUPPORT_AR5416
34572ff6f6SMatthew Dillon #define AH_SUPPORT_AR5416 1
35572ff6f6SMatthew Dillon #endif
36572ff6f6SMatthew Dillon
37572ff6f6SMatthew Dillon #ifndef NBBY
38572ff6f6SMatthew Dillon #define NBBY 8 /* number of bits/byte */
39572ff6f6SMatthew Dillon #endif
40572ff6f6SMatthew Dillon
41572ff6f6SMatthew Dillon #ifndef roundup
42572ff6f6SMatthew Dillon #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
43572ff6f6SMatthew Dillon #endif
44572ff6f6SMatthew Dillon #ifndef howmany
45572ff6f6SMatthew Dillon #define howmany(x, y) (((x)+((y)-1))/(y))
46572ff6f6SMatthew Dillon #endif
47572ff6f6SMatthew Dillon
48572ff6f6SMatthew Dillon #ifndef offsetof
49572ff6f6SMatthew Dillon #define offsetof(type, field) ((size_t)(&((type *)0)->field))
50572ff6f6SMatthew Dillon #endif
51572ff6f6SMatthew Dillon
52572ff6f6SMatthew Dillon typedef struct {
53848b370cSMatthew Dillon uint32_t start; /* first register */
54848b370cSMatthew Dillon uint32_t end; /* ending register or zero */
55572ff6f6SMatthew Dillon } HAL_REGRANGE;
56572ff6f6SMatthew Dillon
57572ff6f6SMatthew Dillon typedef struct {
58572ff6f6SMatthew Dillon uint32_t addr; /* regiser address/offset */
59572ff6f6SMatthew Dillon uint32_t value; /* value to write */
60572ff6f6SMatthew Dillon } HAL_REGWRITE;
61572ff6f6SMatthew Dillon
62572ff6f6SMatthew Dillon /*
63572ff6f6SMatthew Dillon * Transmit power scale factor.
64572ff6f6SMatthew Dillon *
65572ff6f6SMatthew Dillon * NB: This is not public because we want to discourage the use of
66572ff6f6SMatthew Dillon * scaling; folks should use the tx power limit interface.
67572ff6f6SMatthew Dillon */
68572ff6f6SMatthew Dillon typedef enum {
69572ff6f6SMatthew Dillon HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
70572ff6f6SMatthew Dillon HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
71572ff6f6SMatthew Dillon HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
72572ff6f6SMatthew Dillon HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
73572ff6f6SMatthew Dillon HAL_TP_SCALE_MIN = 4, /* min, but still on */
74572ff6f6SMatthew Dillon } HAL_TP_SCALE;
75572ff6f6SMatthew Dillon
76572ff6f6SMatthew Dillon typedef enum {
77572ff6f6SMatthew Dillon HAL_CAP_RADAR = 0, /* Radar capability */
78572ff6f6SMatthew Dillon HAL_CAP_AR = 1, /* AR capability */
79572ff6f6SMatthew Dillon } HAL_PHYDIAG_CAPS;
80572ff6f6SMatthew Dillon
81572ff6f6SMatthew Dillon /*
82572ff6f6SMatthew Dillon * Enable/disable strong signal fast diversity
83572ff6f6SMatthew Dillon */
84572ff6f6SMatthew Dillon #define HAL_CAP_STRONG_DIV 2
85572ff6f6SMatthew Dillon
86572ff6f6SMatthew Dillon /*
87572ff6f6SMatthew Dillon * Each chip or class of chips registers to offer support.
88572ff6f6SMatthew Dillon */
89572ff6f6SMatthew Dillon struct ath_hal_chip {
90572ff6f6SMatthew Dillon const char *name;
91572ff6f6SMatthew Dillon const char *(*probe)(uint16_t vendorid, uint16_t devid);
92572ff6f6SMatthew Dillon struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
93572ff6f6SMatthew Dillon HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
94848b370cSMatthew Dillon HAL_OPS_CONFIG *ah,
95572ff6f6SMatthew Dillon HAL_STATUS *error);
96572ff6f6SMatthew Dillon };
97572ff6f6SMatthew Dillon #ifndef AH_CHIP
98572ff6f6SMatthew Dillon #define AH_CHIP(_name, _probe, _attach) \
99572ff6f6SMatthew Dillon static struct ath_hal_chip _name##_chip = { \
100572ff6f6SMatthew Dillon .name = #_name, \
101572ff6f6SMatthew Dillon .probe = _probe, \
102572ff6f6SMatthew Dillon .attach = _attach \
103572ff6f6SMatthew Dillon }; \
104572ff6f6SMatthew Dillon OS_DATA_SET(ah_chips, _name##_chip)
105572ff6f6SMatthew Dillon #endif
106572ff6f6SMatthew Dillon
107572ff6f6SMatthew Dillon /*
108572ff6f6SMatthew Dillon * Each RF backend registers to offer support; this is mostly
109572ff6f6SMatthew Dillon * used by multi-chip 5212 solutions. Single-chip solutions
110572ff6f6SMatthew Dillon * have a fixed idea about which RF to use.
111572ff6f6SMatthew Dillon */
112572ff6f6SMatthew Dillon struct ath_hal_rf {
113572ff6f6SMatthew Dillon const char *name;
114572ff6f6SMatthew Dillon HAL_BOOL (*probe)(struct ath_hal *ah);
115572ff6f6SMatthew Dillon HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
116572ff6f6SMatthew Dillon };
117572ff6f6SMatthew Dillon #ifndef AH_RF
118572ff6f6SMatthew Dillon #define AH_RF(_name, _probe, _attach) \
119572ff6f6SMatthew Dillon static struct ath_hal_rf _name##_rf = { \
120572ff6f6SMatthew Dillon .name = __STRING(_name), \
121572ff6f6SMatthew Dillon .probe = _probe, \
122572ff6f6SMatthew Dillon .attach = _attach \
123572ff6f6SMatthew Dillon }; \
124572ff6f6SMatthew Dillon OS_DATA_SET(ah_rfs, _name##_rf)
125572ff6f6SMatthew Dillon #endif
126572ff6f6SMatthew Dillon
127572ff6f6SMatthew Dillon struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
128572ff6f6SMatthew Dillon
129572ff6f6SMatthew Dillon /*
130572ff6f6SMatthew Dillon * Maximum number of internal channels. Entries are per unique
131572ff6f6SMatthew Dillon * frequency so this might be need to be increased to handle all
132572ff6f6SMatthew Dillon * usage cases; typically no more than 32 are really needed but
133572ff6f6SMatthew Dillon * dynamically allocating the data structures is a bit painful
134572ff6f6SMatthew Dillon * right now.
135572ff6f6SMatthew Dillon */
136572ff6f6SMatthew Dillon #ifndef AH_MAXCHAN
13720825c8aSJohn Marino #define AH_MAXCHAN 128
138572ff6f6SMatthew Dillon #endif
139572ff6f6SMatthew Dillon
140572ff6f6SMatthew Dillon #define HAL_NF_CAL_HIST_LEN_FULL 5
141572ff6f6SMatthew Dillon #define HAL_NF_CAL_HIST_LEN_SMALL 1
142572ff6f6SMatthew Dillon #define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */
143572ff6f6SMatthew Dillon #define HAL_NF_LOAD_DELAY 1000
144572ff6f6SMatthew Dillon
145572ff6f6SMatthew Dillon /*
146572ff6f6SMatthew Dillon * PER_CHAN doesn't work for now, as it looks like the device layer
147572ff6f6SMatthew Dillon * has to pre-populate the per-channel list with nominal values.
148572ff6f6SMatthew Dillon */
149572ff6f6SMatthew Dillon //#define ATH_NF_PER_CHAN 1
150572ff6f6SMatthew Dillon
151572ff6f6SMatthew Dillon typedef struct {
152572ff6f6SMatthew Dillon u_int8_t curr_index;
153572ff6f6SMatthew Dillon int8_t invalidNFcount; /* TO DO: REMOVE THIS! */
154572ff6f6SMatthew Dillon int16_t priv_nf[HAL_NUM_NF_READINGS];
155572ff6f6SMatthew Dillon } HAL_NFCAL_BASE;
156572ff6f6SMatthew Dillon
157572ff6f6SMatthew Dillon typedef struct {
158572ff6f6SMatthew Dillon HAL_NFCAL_BASE base;
159572ff6f6SMatthew Dillon int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
160572ff6f6SMatthew Dillon } HAL_NFCAL_HIST_FULL;
161572ff6f6SMatthew Dillon
162572ff6f6SMatthew Dillon typedef struct {
163572ff6f6SMatthew Dillon HAL_NFCAL_BASE base;
164572ff6f6SMatthew Dillon int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
165572ff6f6SMatthew Dillon } HAL_NFCAL_HIST_SMALL;
166572ff6f6SMatthew Dillon
167572ff6f6SMatthew Dillon #ifdef ATH_NF_PER_CHAN
168572ff6f6SMatthew Dillon typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
169572ff6f6SMatthew Dillon #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
170572ff6f6SMatthew Dillon #else
171572ff6f6SMatthew Dillon typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
172572ff6f6SMatthew Dillon #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
173572ff6f6SMatthew Dillon #endif /* ATH_NF_PER_CHAN */
174572ff6f6SMatthew Dillon
175572ff6f6SMatthew Dillon /*
176572ff6f6SMatthew Dillon * Internal per-channel state. These are found
177572ff6f6SMatthew Dillon * using ic_devdata in the ieee80211_channel.
178572ff6f6SMatthew Dillon */
179572ff6f6SMatthew Dillon typedef struct {
180572ff6f6SMatthew Dillon uint16_t channel; /* h/w frequency, NB: may be mapped */
181572ff6f6SMatthew Dillon uint8_t privFlags;
182572ff6f6SMatthew Dillon #define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
183572ff6f6SMatthew Dillon #define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
184572ff6f6SMatthew Dillon #define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
185572ff6f6SMatthew Dillon #define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */
186572ff6f6SMatthew Dillon uint8_t calValid; /* bitmask of cal types */
187572ff6f6SMatthew Dillon int8_t iCoff;
188572ff6f6SMatthew Dillon int8_t qCoff;
189572ff6f6SMatthew Dillon int16_t rawNoiseFloor;
190572ff6f6SMatthew Dillon int16_t noiseFloorAdjust;
191572ff6f6SMatthew Dillon #ifdef AH_SUPPORT_AR5416
192572ff6f6SMatthew Dillon int16_t noiseFloorCtl[AH_MAX_CHAINS];
193572ff6f6SMatthew Dillon int16_t noiseFloorExt[AH_MAX_CHAINS];
194572ff6f6SMatthew Dillon #endif /* AH_SUPPORT_AR5416 */
195572ff6f6SMatthew Dillon uint16_t mainSpur; /* cached spur value for this channel */
196572ff6f6SMatthew Dillon
197572ff6f6SMatthew Dillon /*XXX TODO: make these part of privFlags */
198572ff6f6SMatthew Dillon uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */
199572ff6f6SMatthew Dillon paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
200572ff6f6SMatthew Dillon int one_time_cals_done;
201572ff6f6SMatthew Dillon HAL_CHAN_NFCAL_HIST nf_cal_hist;
202572ff6f6SMatthew Dillon } HAL_CHANNEL_INTERNAL;
203572ff6f6SMatthew Dillon
204572ff6f6SMatthew Dillon /* channel requires noise floor check */
205572ff6f6SMatthew Dillon #define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
206572ff6f6SMatthew Dillon
207572ff6f6SMatthew Dillon /* all full-width channels */
208572ff6f6SMatthew Dillon #define IEEE80211_CHAN_ALLFULL \
209572ff6f6SMatthew Dillon (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
210572ff6f6SMatthew Dillon #define IEEE80211_CHAN_ALLTURBOFULL \
211572ff6f6SMatthew Dillon (IEEE80211_CHAN_ALLTURBO - \
212572ff6f6SMatthew Dillon (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
213572ff6f6SMatthew Dillon
214572ff6f6SMatthew Dillon typedef struct {
215572ff6f6SMatthew Dillon uint32_t halChanSpreadSupport : 1,
216572ff6f6SMatthew Dillon halSleepAfterBeaconBroken : 1,
217572ff6f6SMatthew Dillon halCompressSupport : 1,
218572ff6f6SMatthew Dillon halBurstSupport : 1,
219572ff6f6SMatthew Dillon halFastFramesSupport : 1,
220572ff6f6SMatthew Dillon halChapTuningSupport : 1,
221572ff6f6SMatthew Dillon halTurboGSupport : 1,
222572ff6f6SMatthew Dillon halTurboPrimeSupport : 1,
223572ff6f6SMatthew Dillon halMicAesCcmSupport : 1,
224572ff6f6SMatthew Dillon halMicCkipSupport : 1,
225572ff6f6SMatthew Dillon halMicTkipSupport : 1,
226572ff6f6SMatthew Dillon halTkipMicTxRxKeySupport : 1,
227572ff6f6SMatthew Dillon halCipherAesCcmSupport : 1,
228572ff6f6SMatthew Dillon halCipherCkipSupport : 1,
229572ff6f6SMatthew Dillon halCipherTkipSupport : 1,
230572ff6f6SMatthew Dillon halPSPollBroken : 1,
231572ff6f6SMatthew Dillon halVEOLSupport : 1,
232572ff6f6SMatthew Dillon halBssIdMaskSupport : 1,
233572ff6f6SMatthew Dillon halMcastKeySrchSupport : 1,
234572ff6f6SMatthew Dillon halTsfAddSupport : 1,
235572ff6f6SMatthew Dillon halChanHalfRate : 1,
236572ff6f6SMatthew Dillon halChanQuarterRate : 1,
237572ff6f6SMatthew Dillon halHTSupport : 1,
238572ff6f6SMatthew Dillon halHTSGI20Support : 1,
239572ff6f6SMatthew Dillon halRfSilentSupport : 1,
240572ff6f6SMatthew Dillon halHwPhyCounterSupport : 1,
241572ff6f6SMatthew Dillon halWowSupport : 1,
242572ff6f6SMatthew Dillon halWowMatchPatternExact : 1,
243572ff6f6SMatthew Dillon halAutoSleepSupport : 1,
244572ff6f6SMatthew Dillon halFastCCSupport : 1,
245572ff6f6SMatthew Dillon halBtCoexSupport : 1;
246572ff6f6SMatthew Dillon uint32_t halRxStbcSupport : 1,
247572ff6f6SMatthew Dillon halTxStbcSupport : 1,
248572ff6f6SMatthew Dillon halGTTSupport : 1,
249572ff6f6SMatthew Dillon halCSTSupport : 1,
250572ff6f6SMatthew Dillon halRifsRxSupport : 1,
251572ff6f6SMatthew Dillon halRifsTxSupport : 1,
252572ff6f6SMatthew Dillon hal4AddrAggrSupport : 1,
253572ff6f6SMatthew Dillon halExtChanDfsSupport : 1,
254572ff6f6SMatthew Dillon halUseCombinedRadarRssi : 1,
255572ff6f6SMatthew Dillon halForcePpmSupport : 1,
256572ff6f6SMatthew Dillon halEnhancedPmSupport : 1,
257572ff6f6SMatthew Dillon halEnhancedDfsSupport : 1,
258572ff6f6SMatthew Dillon halMbssidAggrSupport : 1,
259572ff6f6SMatthew Dillon halBssidMatchSupport : 1,
260572ff6f6SMatthew Dillon hal4kbSplitTransSupport : 1,
261572ff6f6SMatthew Dillon halHasRxSelfLinkedTail : 1,
262572ff6f6SMatthew Dillon halSupportsFastClock5GHz : 1,
263572ff6f6SMatthew Dillon halHasLongRxDescTsf : 1,
264572ff6f6SMatthew Dillon halHasBBReadWar : 1,
265572ff6f6SMatthew Dillon halSerialiseRegWar : 1,
266572ff6f6SMatthew Dillon halMciSupport : 1,
267572ff6f6SMatthew Dillon halRxTxAbortSupport : 1,
268572ff6f6SMatthew Dillon halPaprdEnabled : 1,
269572ff6f6SMatthew Dillon halHasUapsdSupport : 1,
270572ff6f6SMatthew Dillon halWpsPushButtonSupport : 1,
271572ff6f6SMatthew Dillon halBtCoexApsmWar : 1,
272572ff6f6SMatthew Dillon halGenTimerSupport : 1,
273572ff6f6SMatthew Dillon halLDPCSupport : 1,
274572ff6f6SMatthew Dillon halHwBeaconProcSupport : 1,
275572ff6f6SMatthew Dillon halEnhancedDmaSupport : 1;
276572ff6f6SMatthew Dillon uint32_t halIsrRacSupport : 1,
277572ff6f6SMatthew Dillon halApmEnable : 1,
278572ff6f6SMatthew Dillon halIntrMitigation : 1,
279572ff6f6SMatthew Dillon hal49GhzSupport : 1,
280572ff6f6SMatthew Dillon halAntDivCombSupport : 1,
281572ff6f6SMatthew Dillon halAntDivCombSupportOrg : 1,
282572ff6f6SMatthew Dillon halRadioRetentionSupport : 1,
283572ff6f6SMatthew Dillon halSpectralScanSupport : 1,
284d98a0bcfSMatthew Dillon halRxUsingLnaMixing : 1,
285b14ca477SMatthew Dillon halRxDoMyBeacon : 1,
286b14ca477SMatthew Dillon halHwUapsdTrig : 1;
287572ff6f6SMatthew Dillon
288572ff6f6SMatthew Dillon uint32_t halWirelessModes;
289572ff6f6SMatthew Dillon uint16_t halTotalQueues;
290572ff6f6SMatthew Dillon uint16_t halKeyCacheSize;
291572ff6f6SMatthew Dillon uint16_t halLow5GhzChan, halHigh5GhzChan;
292572ff6f6SMatthew Dillon uint16_t halLow2GhzChan, halHigh2GhzChan;
293572ff6f6SMatthew Dillon int halTstampPrecision;
294572ff6f6SMatthew Dillon int halRtsAggrLimit;
295572ff6f6SMatthew Dillon uint8_t halTxChainMask;
296572ff6f6SMatthew Dillon uint8_t halRxChainMask;
297572ff6f6SMatthew Dillon uint8_t halNumGpioPins;
298572ff6f6SMatthew Dillon uint8_t halNumAntCfg2GHz;
299572ff6f6SMatthew Dillon uint8_t halNumAntCfg5GHz;
300572ff6f6SMatthew Dillon uint32_t halIntrMask;
301572ff6f6SMatthew Dillon uint8_t halTxStreams;
302572ff6f6SMatthew Dillon uint8_t halRxStreams;
303572ff6f6SMatthew Dillon HAL_MFP_OPT_T halMfpSupport;
304572ff6f6SMatthew Dillon
305572ff6f6SMatthew Dillon /* AR9300 HAL porting capabilities */
306572ff6f6SMatthew Dillon int hal_paprd_enabled;
307572ff6f6SMatthew Dillon int hal_pcie_lcr_offset;
308572ff6f6SMatthew Dillon int hal_pcie_lcr_extsync_en;
309572ff6f6SMatthew Dillon int halNumTxMaps;
310572ff6f6SMatthew Dillon int halTxDescLen;
311572ff6f6SMatthew Dillon int halTxStatusLen;
312572ff6f6SMatthew Dillon int halRxStatusLen;
313572ff6f6SMatthew Dillon int halRxHpFifoDepth;
314572ff6f6SMatthew Dillon int halRxLpFifoDepth;
315572ff6f6SMatthew Dillon uint32_t halRegCap; /* XXX needed? */
316572ff6f6SMatthew Dillon int halNumMRRetries;
317572ff6f6SMatthew Dillon int hal_ani_poll_interval;
318572ff6f6SMatthew Dillon int hal_channel_switch_time_usec;
319572ff6f6SMatthew Dillon } HAL_CAPABILITIES;
320572ff6f6SMatthew Dillon
321572ff6f6SMatthew Dillon struct regDomain;
322572ff6f6SMatthew Dillon
323572ff6f6SMatthew Dillon /*
324572ff6f6SMatthew Dillon * Definitions for ah_flags in ath_hal_private
325572ff6f6SMatthew Dillon */
326572ff6f6SMatthew Dillon #define AH_USE_EEPROM 0x1
327572ff6f6SMatthew Dillon #define AH_IS_HB63 0x2
328572ff6f6SMatthew Dillon
329572ff6f6SMatthew Dillon /*
330572ff6f6SMatthew Dillon * The ``private area'' follows immediately after the ``public area''
331572ff6f6SMatthew Dillon * in the data structure returned by ath_hal_attach. Private data are
332572ff6f6SMatthew Dillon * used by device-independent code such as the regulatory domain support.
333572ff6f6SMatthew Dillon * In general, code within the HAL should never depend on data in the
334572ff6f6SMatthew Dillon * public area. Instead any public data needed internally should be
335572ff6f6SMatthew Dillon * shadowed here.
336572ff6f6SMatthew Dillon *
337572ff6f6SMatthew Dillon * When declaring a device-specific ath_hal data structure this structure
338572ff6f6SMatthew Dillon * is assumed to at the front; e.g.
339572ff6f6SMatthew Dillon *
340572ff6f6SMatthew Dillon * struct ath_hal_5212 {
341572ff6f6SMatthew Dillon * struct ath_hal_private ah_priv;
342572ff6f6SMatthew Dillon * ...
343572ff6f6SMatthew Dillon * };
344572ff6f6SMatthew Dillon *
345572ff6f6SMatthew Dillon * It might be better to manage the method pointers in this structure
346572ff6f6SMatthew Dillon * using an indirect pointer to a read-only data structure but this would
347572ff6f6SMatthew Dillon * disallow class-style method overriding.
348572ff6f6SMatthew Dillon */
349572ff6f6SMatthew Dillon struct ath_hal_private {
350572ff6f6SMatthew Dillon struct ath_hal h; /* public area */
351572ff6f6SMatthew Dillon
352572ff6f6SMatthew Dillon /* NB: all methods go first to simplify initialization */
353572ff6f6SMatthew Dillon HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
354572ff6f6SMatthew Dillon uint16_t channelFlags,
355572ff6f6SMatthew Dillon uint16_t *lowChannel, uint16_t *highChannel);
356572ff6f6SMatthew Dillon u_int (*ah_getWirelessModes)(struct ath_hal*);
357572ff6f6SMatthew Dillon HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
358572ff6f6SMatthew Dillon uint16_t *data);
359572ff6f6SMatthew Dillon HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
360572ff6f6SMatthew Dillon uint16_t data);
361572ff6f6SMatthew Dillon HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
362572ff6f6SMatthew Dillon struct ieee80211_channel *);
363572ff6f6SMatthew Dillon int16_t (*ah_getNfAdjust)(struct ath_hal *,
364572ff6f6SMatthew Dillon const HAL_CHANNEL_INTERNAL*);
365572ff6f6SMatthew Dillon void (*ah_getNoiseFloor)(struct ath_hal *,
366572ff6f6SMatthew Dillon int16_t nfarray[]);
367572ff6f6SMatthew Dillon
368572ff6f6SMatthew Dillon void *ah_eeprom; /* opaque EEPROM state */
369572ff6f6SMatthew Dillon uint16_t ah_eeversion; /* EEPROM version */
370572ff6f6SMatthew Dillon void (*ah_eepromDetach)(struct ath_hal *);
371572ff6f6SMatthew Dillon HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
372572ff6f6SMatthew Dillon HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int);
373572ff6f6SMatthew Dillon uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
374572ff6f6SMatthew Dillon HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
375572ff6f6SMatthew Dillon const void *args, uint32_t argsize,
376572ff6f6SMatthew Dillon void **result, uint32_t *resultsize);
377572ff6f6SMatthew Dillon
378572ff6f6SMatthew Dillon /*
379572ff6f6SMatthew Dillon * Device revision information.
380572ff6f6SMatthew Dillon */
381572ff6f6SMatthew Dillon uint16_t ah_devid; /* PCI device ID */
382572ff6f6SMatthew Dillon uint16_t ah_subvendorid; /* PCI subvendor ID */
383572ff6f6SMatthew Dillon uint32_t ah_macVersion; /* MAC version id */
384572ff6f6SMatthew Dillon uint16_t ah_macRev; /* MAC revision */
385572ff6f6SMatthew Dillon uint16_t ah_phyRev; /* PHY revision */
386572ff6f6SMatthew Dillon uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
387572ff6f6SMatthew Dillon uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
388572ff6f6SMatthew Dillon uint32_t ah_flags; /* misc flags */
389572ff6f6SMatthew Dillon uint8_t ah_ispcie; /* PCIE, special treatment */
390572ff6f6SMatthew Dillon uint8_t ah_devType; /* card type - CB, PCI, PCIe */
391572ff6f6SMatthew Dillon
392572ff6f6SMatthew Dillon HAL_OPMODE ah_opmode; /* operating mode from reset */
393572ff6f6SMatthew Dillon const struct ieee80211_channel *ah_curchan;/* operating channel */
394572ff6f6SMatthew Dillon HAL_CAPABILITIES ah_caps; /* device capabilities */
395572ff6f6SMatthew Dillon uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
396572ff6f6SMatthew Dillon int16_t ah_powerLimit; /* tx power cap */
397572ff6f6SMatthew Dillon uint16_t ah_maxPowerLevel; /* calculated max tx power */
398572ff6f6SMatthew Dillon u_int ah_tpScale; /* tx power scale factor */
399572ff6f6SMatthew Dillon u_int16_t ah_extraTxPow; /* low rates extra-txpower */
400572ff6f6SMatthew Dillon uint32_t ah_11nCompat; /* 11n compat controls */
401572ff6f6SMatthew Dillon
402572ff6f6SMatthew Dillon /*
403572ff6f6SMatthew Dillon * State for regulatory domain handling.
404572ff6f6SMatthew Dillon */
405572ff6f6SMatthew Dillon HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
406572ff6f6SMatthew Dillon HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */
407572ff6f6SMatthew Dillon HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */
408572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
409572ff6f6SMatthew Dillon u_int ah_nchan; /* valid items in ah_channels */
410572ff6f6SMatthew Dillon const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
411572ff6f6SMatthew Dillon const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
412572ff6f6SMatthew Dillon
413572ff6f6SMatthew Dillon uint8_t ah_coverageClass; /* coverage class */
414572ff6f6SMatthew Dillon /*
415572ff6f6SMatthew Dillon * RF Silent handling; setup according to the EEPROM.
416572ff6f6SMatthew Dillon */
417572ff6f6SMatthew Dillon uint16_t ah_rfsilent; /* GPIO pin + polarity */
418572ff6f6SMatthew Dillon HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
419572ff6f6SMatthew Dillon /*
420572ff6f6SMatthew Dillon * Diagnostic support for discriminating HIUERR reports.
421572ff6f6SMatthew Dillon */
422572ff6f6SMatthew Dillon uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
423572ff6f6SMatthew Dillon int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
424572ff6f6SMatthew Dillon
425b14ca477SMatthew Dillon /* Only used if ATH_NF_PER_CHAN is defined */
426572ff6f6SMatthew Dillon HAL_NFCAL_HIST_FULL nf_cal_hist;
427b14ca477SMatthew Dillon
428b14ca477SMatthew Dillon /*
429b14ca477SMatthew Dillon * Channel survey history - current channel only.
430b14ca477SMatthew Dillon */
431b14ca477SMatthew Dillon HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */
432572ff6f6SMatthew Dillon };
433572ff6f6SMatthew Dillon
434572ff6f6SMatthew Dillon #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
435572ff6f6SMatthew Dillon
436572ff6f6SMatthew Dillon #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
437572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
438572ff6f6SMatthew Dillon #define ath_hal_getWirelessModes(_ah) \
439572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
440572ff6f6SMatthew Dillon #define ath_hal_eepromRead(_ah, _off, _data) \
441572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
442572ff6f6SMatthew Dillon #define ath_hal_eepromWrite(_ah, _off, _data) \
443572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
444572ff6f6SMatthew Dillon #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
445572ff6f6SMatthew Dillon (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
446572ff6f6SMatthew Dillon #define ath_hal_gpioCfgInput(_ah, _gpio) \
447572ff6f6SMatthew Dillon (_ah)->ah_gpioCfgInput(_ah, _gpio)
448572ff6f6SMatthew Dillon #define ath_hal_gpioGet(_ah, _gpio) \
449572ff6f6SMatthew Dillon (_ah)->ah_gpioGet(_ah, _gpio)
450572ff6f6SMatthew Dillon #define ath_hal_gpioSet(_ah, _gpio, _val) \
451572ff6f6SMatthew Dillon (_ah)->ah_gpioSet(_ah, _gpio, _val)
452572ff6f6SMatthew Dillon #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
453572ff6f6SMatthew Dillon (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
454572ff6f6SMatthew Dillon #define ath_hal_getpowerlimits(_ah, _chan) \
455572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
456572ff6f6SMatthew Dillon #define ath_hal_getNfAdjust(_ah, _c) \
457572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
458572ff6f6SMatthew Dillon #define ath_hal_getNoiseFloor(_ah, _nfArray) \
459572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
460572ff6f6SMatthew Dillon #define ath_hal_configPCIE(_ah, _reset, _poweroff) \
461572ff6f6SMatthew Dillon (_ah)->ah_configPCIE(_ah, _reset, _poweroff)
462572ff6f6SMatthew Dillon #define ath_hal_disablePCIE(_ah) \
463572ff6f6SMatthew Dillon (_ah)->ah_disablePCIE(_ah)
464572ff6f6SMatthew Dillon #define ath_hal_setInterrupts(_ah, _mask) \
465572ff6f6SMatthew Dillon (_ah)->ah_setInterrupts(_ah, _mask)
466572ff6f6SMatthew Dillon
467572ff6f6SMatthew Dillon #define ath_hal_isrfkillenabled(_ah) \
468572ff6f6SMatthew Dillon (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
469572ff6f6SMatthew Dillon #define ath_hal_enable_rfkill(_ah, _v) \
470572ff6f6SMatthew Dillon ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
471572ff6f6SMatthew Dillon #define ath_hal_hasrfkill_int(_ah) \
472572ff6f6SMatthew Dillon (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
473572ff6f6SMatthew Dillon
474572ff6f6SMatthew Dillon #define ath_hal_eepromDetach(_ah) do { \
475572ff6f6SMatthew Dillon if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
476572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
477572ff6f6SMatthew Dillon } while (0)
478572ff6f6SMatthew Dillon #define ath_hal_eepromGet(_ah, _param, _val) \
479572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
480572ff6f6SMatthew Dillon #define ath_hal_eepromSet(_ah, _param, _val) \
481572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
482572ff6f6SMatthew Dillon #define ath_hal_eepromGetFlag(_ah, _param) \
483572ff6f6SMatthew Dillon (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
484572ff6f6SMatthew Dillon #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
485572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
486572ff6f6SMatthew Dillon #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
487572ff6f6SMatthew Dillon AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
488572ff6f6SMatthew Dillon
489572ff6f6SMatthew Dillon #ifndef _NET_IF_IEEE80211_H_
490572ff6f6SMatthew Dillon /*
491572ff6f6SMatthew Dillon * Stuff that would naturally come from _ieee80211.h
492572ff6f6SMatthew Dillon */
493572ff6f6SMatthew Dillon #define IEEE80211_ADDR_LEN 6
494572ff6f6SMatthew Dillon
495572ff6f6SMatthew Dillon #define IEEE80211_WEP_IVLEN 3 /* 24bit */
496572ff6f6SMatthew Dillon #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
497572ff6f6SMatthew Dillon #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
498572ff6f6SMatthew Dillon
499572ff6f6SMatthew Dillon #define IEEE80211_CRC_LEN 4
500572ff6f6SMatthew Dillon
501572ff6f6SMatthew Dillon #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
502572ff6f6SMatthew Dillon (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
503572ff6f6SMatthew Dillon #endif /* _NET_IF_IEEE80211_H_ */
504572ff6f6SMatthew Dillon
505572ff6f6SMatthew Dillon #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
506572ff6f6SMatthew Dillon
507572ff6f6SMatthew Dillon #define INIT_AIFS 2
508572ff6f6SMatthew Dillon #define INIT_CWMIN 15
509572ff6f6SMatthew Dillon #define INIT_CWMIN_11B 31
510572ff6f6SMatthew Dillon #define INIT_CWMAX 1023
511572ff6f6SMatthew Dillon #define INIT_SH_RETRY 10
512572ff6f6SMatthew Dillon #define INIT_LG_RETRY 10
513572ff6f6SMatthew Dillon #define INIT_SSH_RETRY 32
514572ff6f6SMatthew Dillon #define INIT_SLG_RETRY 32
515572ff6f6SMatthew Dillon
516572ff6f6SMatthew Dillon typedef struct {
517572ff6f6SMatthew Dillon uint32_t tqi_ver; /* HAL TXQ verson */
518572ff6f6SMatthew Dillon HAL_TX_QUEUE tqi_type; /* hw queue type*/
519572ff6f6SMatthew Dillon HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
520572ff6f6SMatthew Dillon HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
521572ff6f6SMatthew Dillon uint32_t tqi_priority;
522572ff6f6SMatthew Dillon uint32_t tqi_aifs; /* aifs */
523572ff6f6SMatthew Dillon uint32_t tqi_cwmin; /* cwMin */
524572ff6f6SMatthew Dillon uint32_t tqi_cwmax; /* cwMax */
525572ff6f6SMatthew Dillon uint16_t tqi_shretry; /* frame short retry limit */
526572ff6f6SMatthew Dillon uint16_t tqi_lgretry; /* frame long retry limit */
527572ff6f6SMatthew Dillon uint32_t tqi_cbrPeriod;
528572ff6f6SMatthew Dillon uint32_t tqi_cbrOverflowLimit;
529572ff6f6SMatthew Dillon uint32_t tqi_burstTime;
530572ff6f6SMatthew Dillon uint32_t tqi_readyTime;
531572ff6f6SMatthew Dillon uint32_t tqi_physCompBuf;
532572ff6f6SMatthew Dillon uint32_t tqi_intFlags; /* flags for internal use */
533572ff6f6SMatthew Dillon } HAL_TX_QUEUE_INFO;
534572ff6f6SMatthew Dillon
535572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
536572ff6f6SMatthew Dillon HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
537572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
538572ff6f6SMatthew Dillon HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
539572ff6f6SMatthew Dillon
540572ff6f6SMatthew Dillon #define HAL_SPUR_VAL_MASK 0x3FFF
541572ff6f6SMatthew Dillon #define HAL_SPUR_CHAN_WIDTH 87
542572ff6f6SMatthew Dillon #define HAL_BIN_WIDTH_BASE_100HZ 3125
543572ff6f6SMatthew Dillon #define HAL_BIN_WIDTH_TURBO_100HZ 6250
544572ff6f6SMatthew Dillon #define HAL_MAX_BINS_ALLOWED 28
545572ff6f6SMatthew Dillon
546572ff6f6SMatthew Dillon #define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
547572ff6f6SMatthew Dillon #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
548572ff6f6SMatthew Dillon
549572ff6f6SMatthew Dillon #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
550572ff6f6SMatthew Dillon
551572ff6f6SMatthew Dillon /*
552572ff6f6SMatthew Dillon * Deduce if the host cpu has big- or litt-endian byte order.
553572ff6f6SMatthew Dillon */
554572ff6f6SMatthew Dillon static __inline__ int
isBigEndian(void)555572ff6f6SMatthew Dillon isBigEndian(void)
556572ff6f6SMatthew Dillon {
557572ff6f6SMatthew Dillon union {
558572ff6f6SMatthew Dillon int32_t i;
559572ff6f6SMatthew Dillon char c[4];
560572ff6f6SMatthew Dillon } u;
561572ff6f6SMatthew Dillon u.i = 1;
562572ff6f6SMatthew Dillon return (u.c[0] == 0);
563572ff6f6SMatthew Dillon }
564572ff6f6SMatthew Dillon
565572ff6f6SMatthew Dillon /* unalligned little endian access */
566572ff6f6SMatthew Dillon #define LE_READ_2(p) \
567572ff6f6SMatthew Dillon ((uint16_t) \
568572ff6f6SMatthew Dillon ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
569572ff6f6SMatthew Dillon #define LE_READ_4(p) \
570572ff6f6SMatthew Dillon ((uint32_t) \
571572ff6f6SMatthew Dillon ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
572572ff6f6SMatthew Dillon (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
573572ff6f6SMatthew Dillon
574572ff6f6SMatthew Dillon /*
575572ff6f6SMatthew Dillon * Register manipulation macros that expect bit field defines
576572ff6f6SMatthew Dillon * to follow the convention that an _S suffix is appended for
577572ff6f6SMatthew Dillon * a shift count, while the field mask has no suffix.
578572ff6f6SMatthew Dillon */
579572ff6f6SMatthew Dillon #define SM(_v, _f) (((_v) << _f##_S) & (_f))
580572ff6f6SMatthew Dillon #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
581572ff6f6SMatthew Dillon #define OS_REG_RMW(_a, _r, _set, _clr) \
582572ff6f6SMatthew Dillon OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
583572ff6f6SMatthew Dillon #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
584572ff6f6SMatthew Dillon OS_REG_WRITE(_a, _r, \
585572ff6f6SMatthew Dillon (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
586572ff6f6SMatthew Dillon #define OS_REG_SET_BIT(_a, _r, _f) \
587572ff6f6SMatthew Dillon OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
588572ff6f6SMatthew Dillon #define OS_REG_CLR_BIT(_a, _r, _f) \
589572ff6f6SMatthew Dillon OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
590572ff6f6SMatthew Dillon #define OS_REG_IS_BIT_SET(_a, _r, _f) \
591572ff6f6SMatthew Dillon ((OS_REG_READ(_a, _r) & (_f)) != 0)
592572ff6f6SMatthew Dillon #define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
593572ff6f6SMatthew Dillon OS_REG_WRITE(_a, _r, \
594572ff6f6SMatthew Dillon (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
595572ff6f6SMatthew Dillon (((_v) << _f##_S) & (_f<<_f##_S)))
596572ff6f6SMatthew Dillon #define OS_REG_READ_FIELD(_a, _r, _f) \
597572ff6f6SMatthew Dillon (((OS_REG_READ(_a, _r) & _f) >> _f##_S))
598572ff6f6SMatthew Dillon #define OS_REG_READ_FIELD_ALT(_a, _r, _f) \
599572ff6f6SMatthew Dillon ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
600572ff6f6SMatthew Dillon
601572ff6f6SMatthew Dillon /* Analog register writes may require a delay between each one (eg Merlin?) */
602572ff6f6SMatthew Dillon #define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
603572ff6f6SMatthew Dillon do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
604572ff6f6SMatthew Dillon (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
605572ff6f6SMatthew Dillon #define OS_A_REG_WRITE(_a, _r, _v) \
606572ff6f6SMatthew Dillon do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
607572ff6f6SMatthew Dillon
608572ff6f6SMatthew Dillon /* wait for the register contents to have the specified value */
609572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
610572ff6f6SMatthew Dillon uint32_t mask, uint32_t val);
611572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
612572ff6f6SMatthew Dillon uint32_t mask, uint32_t val, uint32_t timeout);
613572ff6f6SMatthew Dillon
614572ff6f6SMatthew Dillon /* return the first n bits in val reversed */
615572ff6f6SMatthew Dillon extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
616572ff6f6SMatthew Dillon
617572ff6f6SMatthew Dillon /* printf interfaces */
618572ff6f6SMatthew Dillon extern void ath_hal_printf(struct ath_hal *, const char*, ...)
619572ff6f6SMatthew Dillon __printflike(2,3);
620572ff6f6SMatthew Dillon extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
621572ff6f6SMatthew Dillon __printflike(2, 0);
622572ff6f6SMatthew Dillon extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
623572ff6f6SMatthew Dillon
624572ff6f6SMatthew Dillon /* allocate and free memory */
625572ff6f6SMatthew Dillon extern void *ath_hal_malloc(size_t);
626572ff6f6SMatthew Dillon extern void ath_hal_free(void *);
627572ff6f6SMatthew Dillon
628572ff6f6SMatthew Dillon /* common debugging interfaces */
629572ff6f6SMatthew Dillon #ifdef AH_DEBUG
630572ff6f6SMatthew Dillon #include "ah_debug.h"
631572ff6f6SMatthew Dillon extern int ath_hal_debug; /* Global debug flags */
632572ff6f6SMatthew Dillon
633572ff6f6SMatthew Dillon /*
634572ff6f6SMatthew Dillon * The typecast is purely because some callers will pass in
635572ff6f6SMatthew Dillon * AH_NULL directly rather than using a NULL ath_hal pointer.
636572ff6f6SMatthew Dillon */
637572ff6f6SMatthew Dillon #define HALDEBUG(_ah, __m, ...) \
638572ff6f6SMatthew Dillon do { \
639572ff6f6SMatthew Dillon if ((__m) == HAL_DEBUG_UNMASKABLE || \
640572ff6f6SMatthew Dillon ath_hal_debug & (__m) || \
641572ff6f6SMatthew Dillon ((_ah) != NULL && \
642572ff6f6SMatthew Dillon ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \
643572ff6f6SMatthew Dillon DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
644572ff6f6SMatthew Dillon } \
645*6e17739dSzrj } while(0)
646572ff6f6SMatthew Dillon
647572ff6f6SMatthew Dillon extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
648572ff6f6SMatthew Dillon __printflike(3,4);
649572ff6f6SMatthew Dillon #else
650*6e17739dSzrj #define HALDEBUG(_ah, __m, ...) do { } while (0)
651572ff6f6SMatthew Dillon #endif /* AH_DEBUG */
652572ff6f6SMatthew Dillon
653572ff6f6SMatthew Dillon /*
654572ff6f6SMatthew Dillon * Register logging definitions shared with ardecode.
655572ff6f6SMatthew Dillon */
656572ff6f6SMatthew Dillon #include "ah_decode.h"
657572ff6f6SMatthew Dillon
658572ff6f6SMatthew Dillon /*
659572ff6f6SMatthew Dillon * Common assertion interface. Note: it is a bad idea to generate
660572ff6f6SMatthew Dillon * an assertion failure for any recoverable event. Instead catch
661572ff6f6SMatthew Dillon * the violation and, if possible, fix it up or recover from it; either
662572ff6f6SMatthew Dillon * with an error return value or a diagnostic messages. System software
663572ff6f6SMatthew Dillon * does not panic unless the situation is hopeless.
664572ff6f6SMatthew Dillon */
665572ff6f6SMatthew Dillon #ifdef AH_ASSERT
666572ff6f6SMatthew Dillon extern void ath_hal_assert_failed(const char* filename,
667572ff6f6SMatthew Dillon int lineno, const char* msg);
668572ff6f6SMatthew Dillon
669572ff6f6SMatthew Dillon #define HALASSERT(_x) do { \
670572ff6f6SMatthew Dillon if (!(_x)) { \
671572ff6f6SMatthew Dillon ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
672572ff6f6SMatthew Dillon } \
673572ff6f6SMatthew Dillon } while (0)
674572ff6f6SMatthew Dillon #else
675572ff6f6SMatthew Dillon #define HALASSERT(_x)
676572ff6f6SMatthew Dillon #endif /* AH_ASSERT */
677572ff6f6SMatthew Dillon
678572ff6f6SMatthew Dillon /*
679572ff6f6SMatthew Dillon * Regulatory domain support.
680572ff6f6SMatthew Dillon */
681572ff6f6SMatthew Dillon
682572ff6f6SMatthew Dillon /*
683572ff6f6SMatthew Dillon * Return the max allowed antenna gain and apply any regulatory
684572ff6f6SMatthew Dillon * domain specific changes.
685572ff6f6SMatthew Dillon */
686572ff6f6SMatthew Dillon u_int ath_hal_getantennareduction(struct ath_hal *ah,
687572ff6f6SMatthew Dillon const struct ieee80211_channel *chan, u_int twiceGain);
688572ff6f6SMatthew Dillon
689572ff6f6SMatthew Dillon /*
690572ff6f6SMatthew Dillon * Return the test group for the specific channel based on
691572ff6f6SMatthew Dillon * the current regulatory setup.
692572ff6f6SMatthew Dillon */
693572ff6f6SMatthew Dillon u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
694572ff6f6SMatthew Dillon
695572ff6f6SMatthew Dillon /*
696572ff6f6SMatthew Dillon * Map a public channel definition to the corresponding
697572ff6f6SMatthew Dillon * internal data structure. This implicitly specifies
698572ff6f6SMatthew Dillon * whether or not the specified channel is ok to use
699572ff6f6SMatthew Dillon * based on the current regulatory domain constraints.
700572ff6f6SMatthew Dillon */
701572ff6f6SMatthew Dillon #ifndef AH_DEBUG
702572ff6f6SMatthew Dillon static OS_INLINE HAL_CHANNEL_INTERNAL *
ath_hal_checkchannel(struct ath_hal * ah,const struct ieee80211_channel * c)703572ff6f6SMatthew Dillon ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
704572ff6f6SMatthew Dillon {
705572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *cc;
706572ff6f6SMatthew Dillon
707572ff6f6SMatthew Dillon HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
708572ff6f6SMatthew Dillon cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
709572ff6f6SMatthew Dillon HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
710572ff6f6SMatthew Dillon return cc;
711572ff6f6SMatthew Dillon }
712572ff6f6SMatthew Dillon #else
713572ff6f6SMatthew Dillon /* NB: non-inline version that checks state */
714572ff6f6SMatthew Dillon HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
715572ff6f6SMatthew Dillon const struct ieee80211_channel *);
716572ff6f6SMatthew Dillon #endif /* AH_DEBUG */
717572ff6f6SMatthew Dillon
718572ff6f6SMatthew Dillon /*
719572ff6f6SMatthew Dillon * Return the h/w frequency for a channel. This may be
720572ff6f6SMatthew Dillon * different from ic_freq if this is a GSM device that
721572ff6f6SMatthew Dillon * takes 2.4GHz frequencies and down-converts them.
722572ff6f6SMatthew Dillon */
723572ff6f6SMatthew Dillon static OS_INLINE uint16_t
ath_hal_gethwchannel(struct ath_hal * ah,const struct ieee80211_channel * c)724572ff6f6SMatthew Dillon ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
725572ff6f6SMatthew Dillon {
726572ff6f6SMatthew Dillon return ath_hal_checkchannel(ah, c)->channel;
727572ff6f6SMatthew Dillon }
728572ff6f6SMatthew Dillon
729572ff6f6SMatthew Dillon /*
730572ff6f6SMatthew Dillon * Convert between microseconds and core system clocks.
731572ff6f6SMatthew Dillon */
732572ff6f6SMatthew Dillon extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
733572ff6f6SMatthew Dillon extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
734572ff6f6SMatthew Dillon
735572ff6f6SMatthew Dillon /*
736572ff6f6SMatthew Dillon * Generic get/set capability support. Each chip overrides
737572ff6f6SMatthew Dillon * this routine to support chip-specific capabilities.
738572ff6f6SMatthew Dillon */
739572ff6f6SMatthew Dillon extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
740572ff6f6SMatthew Dillon HAL_CAPABILITY_TYPE type, uint32_t capability,
741572ff6f6SMatthew Dillon uint32_t *result);
742572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
743572ff6f6SMatthew Dillon HAL_CAPABILITY_TYPE type, uint32_t capability,
744572ff6f6SMatthew Dillon uint32_t setting, HAL_STATUS *status);
745572ff6f6SMatthew Dillon
746572ff6f6SMatthew Dillon /* The diagnostic codes used to be internally defined here -adrian */
747572ff6f6SMatthew Dillon #include "ah_diagcodes.h"
748572ff6f6SMatthew Dillon
749572ff6f6SMatthew Dillon /*
750572ff6f6SMatthew Dillon * The AR5416 and later HALs have MAC and baseband hang checking.
751572ff6f6SMatthew Dillon */
752572ff6f6SMatthew Dillon typedef struct {
753572ff6f6SMatthew Dillon uint32_t hang_reg_offset;
754572ff6f6SMatthew Dillon uint32_t hang_val;
755572ff6f6SMatthew Dillon uint32_t hang_mask;
756572ff6f6SMatthew Dillon uint32_t hang_offset;
757572ff6f6SMatthew Dillon } hal_hw_hang_check_t;
758572ff6f6SMatthew Dillon
759572ff6f6SMatthew Dillon typedef struct {
760572ff6f6SMatthew Dillon uint32_t dma_dbg_3;
761572ff6f6SMatthew Dillon uint32_t dma_dbg_4;
762572ff6f6SMatthew Dillon uint32_t dma_dbg_5;
763572ff6f6SMatthew Dillon uint32_t dma_dbg_6;
764572ff6f6SMatthew Dillon } mac_dbg_regs_t;
765572ff6f6SMatthew Dillon
766572ff6f6SMatthew Dillon typedef enum {
767572ff6f6SMatthew Dillon dcu_chain_state = 0x1,
768572ff6f6SMatthew Dillon dcu_complete_state = 0x2,
769572ff6f6SMatthew Dillon qcu_state = 0x4,
770572ff6f6SMatthew Dillon qcu_fsp_ok = 0x8,
771572ff6f6SMatthew Dillon qcu_fsp_state = 0x10,
772572ff6f6SMatthew Dillon qcu_stitch_state = 0x20,
773572ff6f6SMatthew Dillon qcu_fetch_state = 0x40,
774572ff6f6SMatthew Dillon qcu_complete_state = 0x80
775572ff6f6SMatthew Dillon } hal_mac_hangs_t;
776572ff6f6SMatthew Dillon
777572ff6f6SMatthew Dillon typedef struct {
778572ff6f6SMatthew Dillon int states;
779572ff6f6SMatthew Dillon uint8_t dcu_chain_state;
780572ff6f6SMatthew Dillon uint8_t dcu_complete_state;
781572ff6f6SMatthew Dillon uint8_t qcu_state;
782572ff6f6SMatthew Dillon uint8_t qcu_fsp_ok;
783572ff6f6SMatthew Dillon uint8_t qcu_fsp_state;
784572ff6f6SMatthew Dillon uint8_t qcu_stitch_state;
785572ff6f6SMatthew Dillon uint8_t qcu_fetch_state;
786572ff6f6SMatthew Dillon uint8_t qcu_complete_state;
787572ff6f6SMatthew Dillon } hal_mac_hang_check_t;
788572ff6f6SMatthew Dillon
789572ff6f6SMatthew Dillon enum {
790572ff6f6SMatthew Dillon HAL_BB_HANG_DFS = 0x0001,
791572ff6f6SMatthew Dillon HAL_BB_HANG_RIFS = 0x0002,
792572ff6f6SMatthew Dillon HAL_BB_HANG_RX_CLEAR = 0x0004,
793572ff6f6SMatthew Dillon HAL_BB_HANG_UNKNOWN = 0x0080,
794572ff6f6SMatthew Dillon
795572ff6f6SMatthew Dillon HAL_MAC_HANG_SIG1 = 0x0100,
796572ff6f6SMatthew Dillon HAL_MAC_HANG_SIG2 = 0x0200,
797572ff6f6SMatthew Dillon HAL_MAC_HANG_UNKNOWN = 0x8000,
798572ff6f6SMatthew Dillon
799572ff6f6SMatthew Dillon HAL_BB_HANGS = HAL_BB_HANG_DFS
800572ff6f6SMatthew Dillon | HAL_BB_HANG_RIFS
801572ff6f6SMatthew Dillon | HAL_BB_HANG_RX_CLEAR
802572ff6f6SMatthew Dillon | HAL_BB_HANG_UNKNOWN,
803572ff6f6SMatthew Dillon HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
804572ff6f6SMatthew Dillon | HAL_MAC_HANG_SIG2
805572ff6f6SMatthew Dillon | HAL_MAC_HANG_UNKNOWN,
806572ff6f6SMatthew Dillon };
807572ff6f6SMatthew Dillon
808572ff6f6SMatthew Dillon /* Merge these with above */
809572ff6f6SMatthew Dillon typedef enum hal_hw_hangs {
810572ff6f6SMatthew Dillon HAL_DFS_BB_HANG_WAR = 0x1,
811572ff6f6SMatthew Dillon HAL_RIFS_BB_HANG_WAR = 0x2,
812572ff6f6SMatthew Dillon HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
813572ff6f6SMatthew Dillon HAL_MAC_HANG_WAR = 0x8,
814572ff6f6SMatthew Dillon HAL_PHYRESTART_CLR_WAR = 0x10,
815572ff6f6SMatthew Dillon HAL_MAC_HANG_DETECTED = 0x40000000,
816572ff6f6SMatthew Dillon HAL_BB_HANG_DETECTED = 0x80000000
817572ff6f6SMatthew Dillon } hal_hw_hangs_t;
818572ff6f6SMatthew Dillon
819572ff6f6SMatthew Dillon /*
820572ff6f6SMatthew Dillon * Device revision information.
821572ff6f6SMatthew Dillon */
822572ff6f6SMatthew Dillon typedef struct {
823572ff6f6SMatthew Dillon uint16_t ah_devid; /* PCI device ID */
824572ff6f6SMatthew Dillon uint16_t ah_subvendorid; /* PCI subvendor ID */
825572ff6f6SMatthew Dillon uint32_t ah_macVersion; /* MAC version id */
826572ff6f6SMatthew Dillon uint16_t ah_macRev; /* MAC revision */
827572ff6f6SMatthew Dillon uint16_t ah_phyRev; /* PHY revision */
828572ff6f6SMatthew Dillon uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
829572ff6f6SMatthew Dillon uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
830572ff6f6SMatthew Dillon } HAL_REVS;
831572ff6f6SMatthew Dillon
832572ff6f6SMatthew Dillon /*
833572ff6f6SMatthew Dillon * Argument payload for HAL_DIAG_SETKEY.
834572ff6f6SMatthew Dillon */
835572ff6f6SMatthew Dillon typedef struct {
836572ff6f6SMatthew Dillon HAL_KEYVAL dk_keyval;
837572ff6f6SMatthew Dillon uint16_t dk_keyix; /* key index */
838572ff6f6SMatthew Dillon uint8_t dk_mac[IEEE80211_ADDR_LEN];
839572ff6f6SMatthew Dillon int dk_xor; /* XOR key data */
840572ff6f6SMatthew Dillon } HAL_DIAG_KEYVAL;
841572ff6f6SMatthew Dillon
842572ff6f6SMatthew Dillon /*
843572ff6f6SMatthew Dillon * Argument payload for HAL_DIAG_EEWRITE.
844572ff6f6SMatthew Dillon */
845572ff6f6SMatthew Dillon typedef struct {
846572ff6f6SMatthew Dillon uint16_t ee_off; /* eeprom offset */
847572ff6f6SMatthew Dillon uint16_t ee_data; /* write data */
848572ff6f6SMatthew Dillon } HAL_DIAG_EEVAL;
849572ff6f6SMatthew Dillon
850572ff6f6SMatthew Dillon
851572ff6f6SMatthew Dillon typedef struct {
852572ff6f6SMatthew Dillon u_int offset; /* reg offset */
853572ff6f6SMatthew Dillon uint32_t val; /* reg value */
854572ff6f6SMatthew Dillon } HAL_DIAG_REGVAL;
855572ff6f6SMatthew Dillon
856572ff6f6SMatthew Dillon /*
857572ff6f6SMatthew Dillon * 11n compatibility tweaks.
858572ff6f6SMatthew Dillon */
859572ff6f6SMatthew Dillon #define HAL_DIAG_11N_SERVICES 0x00000003
860572ff6f6SMatthew Dillon #define HAL_DIAG_11N_SERVICES_S 0
861572ff6f6SMatthew Dillon #define HAL_DIAG_11N_TXSTOMP 0x0000000c
862572ff6f6SMatthew Dillon #define HAL_DIAG_11N_TXSTOMP_S 2
863572ff6f6SMatthew Dillon
864572ff6f6SMatthew Dillon typedef struct {
865572ff6f6SMatthew Dillon int maxNoiseImmunityLevel; /* [0..4] */
866572ff6f6SMatthew Dillon int totalSizeDesired[5];
867572ff6f6SMatthew Dillon int coarseHigh[5];
868572ff6f6SMatthew Dillon int coarseLow[5];
869572ff6f6SMatthew Dillon int firpwr[5];
870572ff6f6SMatthew Dillon
871572ff6f6SMatthew Dillon int maxSpurImmunityLevel; /* [0..7] */
872572ff6f6SMatthew Dillon int cycPwrThr1[8];
873572ff6f6SMatthew Dillon
874572ff6f6SMatthew Dillon int maxFirstepLevel; /* [0..2] */
875572ff6f6SMatthew Dillon int firstep[3];
876572ff6f6SMatthew Dillon
877572ff6f6SMatthew Dillon uint32_t ofdmTrigHigh;
878572ff6f6SMatthew Dillon uint32_t ofdmTrigLow;
879572ff6f6SMatthew Dillon int32_t cckTrigHigh;
880572ff6f6SMatthew Dillon int32_t cckTrigLow;
881572ff6f6SMatthew Dillon int32_t rssiThrLow;
882572ff6f6SMatthew Dillon int32_t rssiThrHigh;
883572ff6f6SMatthew Dillon
884572ff6f6SMatthew Dillon int period; /* update listen period */
885572ff6f6SMatthew Dillon } HAL_ANI_PARAMS;
886572ff6f6SMatthew Dillon
887572ff6f6SMatthew Dillon extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
888572ff6f6SMatthew Dillon const void *args, uint32_t argsize,
889572ff6f6SMatthew Dillon void **result, uint32_t *resultsize);
890572ff6f6SMatthew Dillon
891572ff6f6SMatthew Dillon /*
892572ff6f6SMatthew Dillon * Setup a h/w rate table for use.
893572ff6f6SMatthew Dillon */
894572ff6f6SMatthew Dillon extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
895572ff6f6SMatthew Dillon
896572ff6f6SMatthew Dillon /*
897572ff6f6SMatthew Dillon * Common routine for implementing getChanNoise api.
898572ff6f6SMatthew Dillon */
899572ff6f6SMatthew Dillon int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
900572ff6f6SMatthew Dillon
901572ff6f6SMatthew Dillon /*
902572ff6f6SMatthew Dillon * Initialization support.
903572ff6f6SMatthew Dillon */
904572ff6f6SMatthew Dillon typedef struct {
905572ff6f6SMatthew Dillon const uint32_t *data;
906572ff6f6SMatthew Dillon int rows, cols;
907572ff6f6SMatthew Dillon } HAL_INI_ARRAY;
908572ff6f6SMatthew Dillon
909572ff6f6SMatthew Dillon #define HAL_INI_INIT(_ia, _data, _cols) do { \
910572ff6f6SMatthew Dillon (_ia)->data = (const uint32_t *)(_data); \
911572ff6f6SMatthew Dillon (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
912572ff6f6SMatthew Dillon (_ia)->cols = (_cols); \
913572ff6f6SMatthew Dillon } while (0)
914572ff6f6SMatthew Dillon #define HAL_INI_VAL(_ia, _r, _c) \
915572ff6f6SMatthew Dillon ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
916572ff6f6SMatthew Dillon
917572ff6f6SMatthew Dillon /*
918572ff6f6SMatthew Dillon * OS_DELAY() does a PIO READ on the PCI bus which allows
919572ff6f6SMatthew Dillon * other cards' DMA reads to complete in the middle of our reset.
920572ff6f6SMatthew Dillon */
921572ff6f6SMatthew Dillon #define DMA_YIELD(x) do { \
922572ff6f6SMatthew Dillon if ((++(x) % 64) == 0) \
923572ff6f6SMatthew Dillon OS_DELAY(1); \
924572ff6f6SMatthew Dillon } while (0)
925572ff6f6SMatthew Dillon
926572ff6f6SMatthew Dillon #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
927572ff6f6SMatthew Dillon int r; \
928572ff6f6SMatthew Dillon for (r = 0; r < N(regArray); r++) { \
929572ff6f6SMatthew Dillon OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
930572ff6f6SMatthew Dillon DMA_YIELD(regWr); \
931572ff6f6SMatthew Dillon } \
932572ff6f6SMatthew Dillon } while (0)
933572ff6f6SMatthew Dillon
934572ff6f6SMatthew Dillon #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
935572ff6f6SMatthew Dillon int r; \
936572ff6f6SMatthew Dillon for (r = 0; r < N(regArray); r++) { \
937572ff6f6SMatthew Dillon OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
938572ff6f6SMatthew Dillon DMA_YIELD(regWr); \
939572ff6f6SMatthew Dillon } \
940572ff6f6SMatthew Dillon } while (0)
941572ff6f6SMatthew Dillon
942572ff6f6SMatthew Dillon extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
943572ff6f6SMatthew Dillon int col, int regWr);
944572ff6f6SMatthew Dillon extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
945572ff6f6SMatthew Dillon int col);
946572ff6f6SMatthew Dillon extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
947572ff6f6SMatthew Dillon const uint32_t data[], int regWr);
948572ff6f6SMatthew Dillon
949572ff6f6SMatthew Dillon #define CCK_SIFS_TIME 10
950572ff6f6SMatthew Dillon #define CCK_PREAMBLE_BITS 144
951572ff6f6SMatthew Dillon #define CCK_PLCP_BITS 48
952572ff6f6SMatthew Dillon
953572ff6f6SMatthew Dillon #define OFDM_SIFS_TIME 16
954572ff6f6SMatthew Dillon #define OFDM_PREAMBLE_TIME 20
955572ff6f6SMatthew Dillon #define OFDM_PLCP_BITS 22
956572ff6f6SMatthew Dillon #define OFDM_SYMBOL_TIME 4
957572ff6f6SMatthew Dillon
958572ff6f6SMatthew Dillon #define OFDM_HALF_SIFS_TIME 32
959572ff6f6SMatthew Dillon #define OFDM_HALF_PREAMBLE_TIME 40
960572ff6f6SMatthew Dillon #define OFDM_HALF_PLCP_BITS 22
961572ff6f6SMatthew Dillon #define OFDM_HALF_SYMBOL_TIME 8
962572ff6f6SMatthew Dillon
963572ff6f6SMatthew Dillon #define OFDM_QUARTER_SIFS_TIME 64
964572ff6f6SMatthew Dillon #define OFDM_QUARTER_PREAMBLE_TIME 80
965572ff6f6SMatthew Dillon #define OFDM_QUARTER_PLCP_BITS 22
966572ff6f6SMatthew Dillon #define OFDM_QUARTER_SYMBOL_TIME 16
967572ff6f6SMatthew Dillon
968572ff6f6SMatthew Dillon #define TURBO_SIFS_TIME 8
969572ff6f6SMatthew Dillon #define TURBO_PREAMBLE_TIME 14
970572ff6f6SMatthew Dillon #define TURBO_PLCP_BITS 22
971572ff6f6SMatthew Dillon #define TURBO_SYMBOL_TIME 4
972572ff6f6SMatthew Dillon
973572ff6f6SMatthew Dillon #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
974572ff6f6SMatthew Dillon
975572ff6f6SMatthew Dillon /* Generic EEPROM board value functions */
976572ff6f6SMatthew Dillon extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
977572ff6f6SMatthew Dillon uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
978572ff6f6SMatthew Dillon extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
979572ff6f6SMatthew Dillon uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
980572ff6f6SMatthew Dillon uint8_t *pRetVpdList);
981572ff6f6SMatthew Dillon extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
982572ff6f6SMatthew Dillon uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
983572ff6f6SMatthew Dillon
984572ff6f6SMatthew Dillon /* Whether 5ghz fast clock is needed */
985572ff6f6SMatthew Dillon /*
986572ff6f6SMatthew Dillon * The chipset (Merlin, AR9300/later) should set the capability flag below;
987572ff6f6SMatthew Dillon * this flag simply says that the hardware can do it, not that the EEPROM
988572ff6f6SMatthew Dillon * says it can.
989572ff6f6SMatthew Dillon *
990572ff6f6SMatthew Dillon * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock
991572ff6f6SMatthew Dillon * if the relevant eeprom flag is set.
992572ff6f6SMatthew Dillon * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock
993572ff6f6SMatthew Dillon * by default.
994572ff6f6SMatthew Dillon */
995572ff6f6SMatthew Dillon #define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
996572ff6f6SMatthew Dillon (IEEE80211_IS_CHAN_5GHZ(_c) && \
997572ff6f6SMatthew Dillon AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
998572ff6f6SMatthew Dillon ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
999572ff6f6SMatthew Dillon
1000572ff6f6SMatthew Dillon /*
1001572ff6f6SMatthew Dillon * Fetch the maximum regulatory domain power for the given channel
1002572ff6f6SMatthew Dillon * in 1/2dBm steps.
1003572ff6f6SMatthew Dillon */
1004572ff6f6SMatthew Dillon static inline int
ath_hal_get_twice_max_regpower(struct ath_hal_private * ahp,const HAL_CHANNEL_INTERNAL * ichan,const struct ieee80211_channel * chan)1005572ff6f6SMatthew Dillon ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
1006572ff6f6SMatthew Dillon const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
1007572ff6f6SMatthew Dillon {
1008572ff6f6SMatthew Dillon struct ath_hal *ah = &ahp->h;
1009572ff6f6SMatthew Dillon
1010572ff6f6SMatthew Dillon if (! chan) {
1011572ff6f6SMatthew Dillon ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
1012572ff6f6SMatthew Dillon return (0);
1013572ff6f6SMatthew Dillon }
1014572ff6f6SMatthew Dillon return (chan->ic_maxpower);
1015572ff6f6SMatthew Dillon }
1016572ff6f6SMatthew Dillon
1017572ff6f6SMatthew Dillon /*
1018572ff6f6SMatthew Dillon * Get the maximum antenna gain allowed, in 1/2dBm steps.
1019572ff6f6SMatthew Dillon */
1020572ff6f6SMatthew Dillon static inline int
ath_hal_getantennaallowed(struct ath_hal * ah,const struct ieee80211_channel * chan)1021572ff6f6SMatthew Dillon ath_hal_getantennaallowed(struct ath_hal *ah,
1022572ff6f6SMatthew Dillon const struct ieee80211_channel *chan)
1023572ff6f6SMatthew Dillon {
1024572ff6f6SMatthew Dillon
1025572ff6f6SMatthew Dillon if (! chan)
1026572ff6f6SMatthew Dillon return (0);
1027572ff6f6SMatthew Dillon
1028572ff6f6SMatthew Dillon return (chan->ic_maxantgain);
1029572ff6f6SMatthew Dillon }
1030572ff6f6SMatthew Dillon
1031572ff6f6SMatthew Dillon /*
1032572ff6f6SMatthew Dillon * Map the given 2GHz channel to an IEEE number.
1033572ff6f6SMatthew Dillon */
1034b14ca477SMatthew Dillon extern int ath_hal_mhz2ieee_2ghz(struct ath_hal *, int freq);
1035b14ca477SMatthew Dillon
1036b14ca477SMatthew Dillon /*
1037b14ca477SMatthew Dillon * Clear the channel survey data.
1038b14ca477SMatthew Dillon */
1039b14ca477SMatthew Dillon extern void ath_hal_survey_clear(struct ath_hal *ah);
1040b14ca477SMatthew Dillon
1041b14ca477SMatthew Dillon /*
1042b14ca477SMatthew Dillon * Add a sample to the channel survey data.
1043b14ca477SMatthew Dillon */
1044b14ca477SMatthew Dillon extern void ath_hal_survey_add_sample(struct ath_hal *ah,
1045b14ca477SMatthew Dillon HAL_SURVEY_SAMPLE *hs);
1046572ff6f6SMatthew Dillon
1047572ff6f6SMatthew Dillon #endif /* _ATH_AH_INTERAL_H_ */
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