1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _ATH_AH_OSDEP_H_ 32 #define _ATH_AH_OSDEP_H_ 33 /* 34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35 */ 36 #include <sys/cdefs.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/linker_set.h> 41 #include <sys/bus.h> 42 43 /* 44 * Bus i/o type definitions. 45 */ 46 typedef void *HAL_SOFTC; 47 typedef bus_space_tag_t HAL_BUS_TAG; 48 typedef bus_space_handle_t HAL_BUS_HANDLE; 49 50 /* 51 * Although the underlying hardware may support 64 bit DMA, the 52 * current Atheros hardware only supports 32 bit addressing. 53 */ 54 typedef uint32_t HAL_DMA_ADDR; 55 56 /* 57 * Linker set writearounds for chip and RF backend registration. 58 */ 59 #define OS_DATA_SET(set, item) DATA_SET(set, item) 60 #define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 61 #define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 62 63 /* 64 * Delay n microseconds. 65 */ 66 #define OS_DELAY(_n) DELAY(_n) 67 68 #define OS_INLINE __inline 69 #define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 70 #define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 71 #define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l)) 72 73 #define abs(_a) __builtin_abs(_a) 74 75 struct ath_hal; 76 77 /* 78 * The hardware registers are native little-endian byte order. 79 * Big-endian hosts are handled by enabling hardware byte-swap 80 * of register reads and writes at reset. But the PCI clock 81 * domain registers are not byte swapped! Thus, on big-endian 82 * platforms we have to explicitly byte-swap those registers. 83 * OS_REG_UNSWAPPED identifies the registers that need special handling. 84 * 85 * This is not currently used by the FreeBSD HAL osdep code; the HAL 86 * currently does not configure hardware byteswapping for register space 87 * accesses and instead does it through the FreeBSD bus space code. 88 */ 89 #if _BYTE_ORDER == _BIG_ENDIAN 90 #define OS_REG_UNSWAPPED(_reg) \ 91 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 92 ((_reg) >= 0x7000 && (_reg) < 0x8000)) 93 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 94 #define OS_REG_UNSWAPPED(_reg) (0) 95 #endif /* _BYTE_ORDER */ 96 97 /* 98 * For USB/SDIO support (where access latencies are quite high); 99 * some write accesses may be buffered and then flushed when 100 * either a read is done, or an explicit flush is done. 101 * 102 * These are simply placeholders for now. 103 */ 104 #define OS_REG_WRITE_BUFFER_ENABLE(_ah) \ 105 do { } while (0) 106 #define OS_REG_WRITE_BUFFER_DISABLE(_ah) \ 107 do { } while (0) 108 #define OS_REG_WRITE_BUFFER_FLUSH(_ah) \ 109 do { } while (0) 110 111 /* 112 * Register read/write operations are either handled through 113 * platform-dependent routines (or when debugging is enabled 114 * with AH_DEBUG); or they are inline expanded using the macros 115 * defined below. 116 */ 117 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) 118 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 119 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 120 121 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 122 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 123 #else 124 #define OS_REG_WRITE(_ah, _reg, _val) \ 125 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ 126 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) 127 #define OS_REG_READ(_ah, _reg) \ 128 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ 129 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) 130 #endif 131 132 #ifdef AH_DEBUG_ALQ 133 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 134 #else 135 #define OS_MARK(_ah, _id, _v) 136 #endif 137 138 #endif /* _ATH_AH_OSDEP_H_ */ 139