1 /*- 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 #ifndef _ATH_AH_OSDEP_H_ 32 #define _ATH_AH_OSDEP_H_ 33 /* 34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. 35 */ 36 #include <sys/cdefs.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/endian.h> 40 #include <sys/linker_set.h> 41 42 #if defined(__DragonFly__) 43 44 #include <sys/bus.h> 45 46 #ifndef true 47 #define true 1 48 #endif 49 50 #ifndef false 51 #define false 0 52 #endif 53 54 #endif 55 56 /* 57 * Bus i/o type definitions. 58 */ 59 typedef void *HAL_SOFTC; 60 typedef bus_space_tag_t HAL_BUS_TAG; 61 typedef bus_space_handle_t HAL_BUS_HANDLE; 62 63 /* 64 * Although the underlying hardware may support 64 bit DMA, the 65 * current Atheros hardware only supports 32 bit addressing. 66 */ 67 typedef uint32_t HAL_DMA_ADDR; 68 69 /* 70 * Linker set writearounds for chip and RF backend registration. 71 */ 72 #define OS_DATA_SET(set, item) DATA_SET(set, item) 73 #define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype) 74 #define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set) 75 76 /* 77 * Delay n microseconds. 78 */ 79 #define OS_DELAY(_n) DELAY(_n) 80 81 #define OS_INLINE __inline 82 #define OS_MEMZERO(_a, _n) bzero((_a), (_n)) 83 #define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n) 84 #define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l)) 85 86 #define abs(_a) __builtin_abs(_a) 87 88 struct ath_hal; 89 90 /* 91 * The hardware registers are native little-endian byte order. 92 * Big-endian hosts are handled by enabling hardware byte-swap 93 * of register reads and writes at reset. But the PCI clock 94 * domain registers are not byte swapped! Thus, on big-endian 95 * platforms we have to explicitly byte-swap those registers. 96 * OS_REG_UNSWAPPED identifies the registers that need special handling. 97 * 98 * This is not currently used by the FreeBSD HAL osdep code; the HAL 99 * currently does not configure hardware byteswapping for register space 100 * accesses and instead does it through the FreeBSD bus space code. 101 */ 102 #if _BYTE_ORDER == _BIG_ENDIAN 103 #define OS_REG_UNSWAPPED(_reg) \ 104 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \ 105 ((_reg) >= 0x7000 && (_reg) < 0x8000)) 106 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ 107 #define OS_REG_UNSWAPPED(_reg) (0) 108 #endif /* _BYTE_ORDER */ 109 110 /* 111 * For USB/SDIO support (where access latencies are quite high); 112 * some write accesses may be buffered and then flushed when 113 * either a read is done, or an explicit flush is done. 114 * 115 * These are simply placeholders for now. 116 */ 117 #define OS_REG_WRITE_BUFFER_ENABLE(_ah) \ 118 do { } while (0) 119 #define OS_REG_WRITE_BUFFER_DISABLE(_ah) \ 120 do { } while (0) 121 #define OS_REG_WRITE_BUFFER_FLUSH(_ah) \ 122 do { } while (0) 123 124 /* 125 * Read and write barriers. Some platforms require more strongly ordered 126 * operations and unfortunately most of the HAL is written assuming everything 127 * is either an x86 or the bus layer will do the barriers for you. 128 * 129 * Read barriers should occur before each read, and write barriers 130 * occur after each write. 131 * 132 * Later on for SDIO/USB parts we will methodize this and make them no-ops; 133 * register accesses will go via USB commands. 134 */ 135 #define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ 136 #define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE 137 #define OS_BUS_BARRIER_RW \ 138 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 139 #define OS_BUS_BARRIER(_ah, _start, _len, _t) \ 140 bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \ 141 (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t)) 142 #define OS_BUS_BARRIER_REG(_ah, _reg, _t) \ 143 OS_BUS_BARRIER((_ah), (_reg), 4, (_t)) 144 145 /* 146 * Register read/write operations are handled through 147 * platform-dependent routines. 148 */ 149 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) 150 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) 151 152 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); 153 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); 154 155 #ifdef AH_DEBUG_ALQ 156 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); 157 #else 158 #define OS_MARK(_ah, _id, _v) 159 #endif 160 161 #endif /* _ATH_AH_OSDEP_H_ */ 162