1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2005-2006 Atheros Communications, Inc. 4 * All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD$ 19 */ 20 21 #ifndef __AH_REGDOMAIN_DOMAINS_H__ 22 #define __AH_REGDOMAIN_DOMAINS_H__ 23 24 /* 25 * BMLEN defines the size of the bitmask used to hold frequency 26 * band specifications. Note this must agree with the BM macro 27 * definition that's used to setup initializers. See also further 28 * comments below. 29 */ 30 /* BMLEN is now defined in ah_regdomain.h */ 31 #define W0(_a) \ 32 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) 33 #define W1(_a) \ 34 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) 35 #define BM1(_fa) { W0(_fa), W1(_fa) } 36 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } 37 #define BM3(_fa, _fb, _fc) \ 38 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } 39 #define BM4(_fa, _fb, _fc, _fd) \ 40 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ 41 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } 42 #define BM5(_fa, _fb, _fc, _fd, _fe) \ 43 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ 44 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } 45 #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ 46 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ 47 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } 48 #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ 49 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 50 W0(_fg),\ 51 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 52 W1(_fg) } 53 #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ 54 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 55 W0(_fg) | W0(_fh) , \ 56 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 57 W1(_fg) | W1(_fh) } 58 #define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \ 59 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ 60 W0(_fg) | W0(_fh) | W0(_fi) , \ 61 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ 62 W1(_fg) | W1(_fh) | W1(_fi) } 63 64 static REG_DOMAIN regDomains[] = { 65 66 {.regDmnEnum = DEBUG_REG_DMN, 67 .conformanceTestLimit = FCC, 68 .dfsMask = DFS_FCC3, 69 .chan11a = BM4(F1_4950_4980, 70 F1_5120_5240, 71 F1_5260_5700, 72 F1_5745_5825), 73 .chan11a_half = BM4(F1_4945_4985, 74 F2_5120_5240, 75 F2_5260_5700, 76 F7_5745_5825), 77 .chan11a_quarter = BM4(F1_4942_4987, 78 F3_5120_5240, 79 F3_5260_5700, 80 F8_5745_5825), 81 .chan11a_turbo = BM8(T1_5130_5210, 82 T1_5250_5330, 83 T1_5370_5490, 84 T1_5530_5650, 85 T1_5150_5190, 86 T1_5230_5310, 87 T1_5350_5470, 88 T1_5510_5670), 89 .chan11a_dyn_turbo = BM4(T1_5200_5240, 90 T1_5280_5280, 91 T1_5540_5660, 92 T1_5765_5805), 93 .chan11b = BM4(F1_2312_2372, 94 F1_2412_2472, 95 F1_2484_2484, 96 F1_2512_2732), 97 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732), 98 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732), 99 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732), 100 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732), 101 }, 102 103 {.regDmnEnum = APL1, 104 .conformanceTestLimit = FCC, 105 .chan11a = BM1(F4_5745_5825), 106 }, 107 108 {.regDmnEnum = APL2, 109 .conformanceTestLimit = FCC, 110 .chan11a = BM1(F1_5745_5805), 111 }, 112 113 {.regDmnEnum = APL3, 114 .conformanceTestLimit = FCC, 115 .chan11a = BM2(F1_5280_5320, F2_5745_5805), 116 }, 117 118 {.regDmnEnum = APL4, 119 .conformanceTestLimit = FCC, 120 .chan11a = BM2(F4_5180_5240, F3_5745_5825), 121 }, 122 123 {.regDmnEnum = APL5, 124 .conformanceTestLimit = FCC, 125 .chan11a = BM1(F2_5745_5825), 126 }, 127 128 {.regDmnEnum = APL6, 129 .conformanceTestLimit = ETSI, 130 .dfsMask = DFS_ETSI, 131 .pscan = PSCAN_FCC_T | PSCAN_FCC, 132 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825), 133 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800), 134 }, 135 136 {.regDmnEnum = APL8, 137 .conformanceTestLimit = ETSI, 138 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 139 .chan11a = BM2(F6_5260_5320, F4_5745_5825), 140 }, 141 142 {.regDmnEnum = APL9, 143 .conformanceTestLimit = ETSI, 144 .dfsMask = DFS_ETSI, 145 .pscan = PSCAN_ETSI, 146 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB, 147 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805), 148 }, 149 150 {.regDmnEnum = ETSI1, 151 .conformanceTestLimit = ETSI, 152 .dfsMask = DFS_ETSI, 153 .pscan = PSCAN_ETSI, 154 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 155 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700), 156 }, 157 158 {.regDmnEnum = ETSI2, 159 .conformanceTestLimit = ETSI, 160 .dfsMask = DFS_ETSI, 161 .pscan = PSCAN_ETSI, 162 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 163 .chan11a = BM1(F3_5180_5240), 164 }, 165 166 {.regDmnEnum = ETSI3, 167 .conformanceTestLimit = ETSI, 168 .dfsMask = DFS_ETSI, 169 .pscan = PSCAN_ETSI, 170 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 171 .chan11a = BM2(W2_5180_5240, F2_5260_5320), 172 }, 173 174 {.regDmnEnum = ETSI4, 175 .conformanceTestLimit = ETSI, 176 .dfsMask = DFS_ETSI, 177 .pscan = PSCAN_ETSI, 178 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 179 .chan11a = BM2(F3_5180_5240, F1_5260_5320), 180 }, 181 182 {.regDmnEnum = ETSI5, 183 .conformanceTestLimit = ETSI, 184 .dfsMask = DFS_ETSI, 185 .pscan = PSCAN_ETSI, 186 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 187 .chan11a = BM1(F1_5180_5240), 188 }, 189 190 {.regDmnEnum = ETSI6, 191 .conformanceTestLimit = ETSI, 192 .dfsMask = DFS_ETSI, 193 .pscan = PSCAN_ETSI, 194 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 195 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700), 196 }, 197 198 {.regDmnEnum = FCC1, 199 .conformanceTestLimit = FCC, 200 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 201 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 202 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 203 }, 204 205 {.regDmnEnum = FCC2, 206 .conformanceTestLimit = FCC, 207 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825), 208 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805), 209 }, 210 211 {.regDmnEnum = FCC3, 212 .conformanceTestLimit = FCC, 213 .dfsMask = DFS_FCC3, 214 .pscan = PSCAN_FCC | PSCAN_FCC_T, 215 .chan11a = BM4(F2_5180_5240, 216 F3_5260_5320, 217 F1_5500_5700, 218 F5_5745_5825), 219 .chan11a_turbo = BM4(T1_5210_5210, 220 T1_5250_5250, 221 T1_5290_5290, 222 T2_5760_5800), 223 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660), 224 }, 225 226 {.regDmnEnum = FCC4, 227 .conformanceTestLimit = FCC, 228 .dfsMask = DFS_FCC3, 229 .pscan = PSCAN_FCC | PSCAN_FCC_T, 230 .chan11a = BM1(F1_4950_4980), 231 .chan11a_half = BM1(F1_4945_4985), 232 .chan11a_quarter = BM1(F1_4942_4987), 233 }, 234 235 /* FCC1 w/ 1/2 and 1/4 width channels */ 236 {.regDmnEnum = FCC5, 237 .conformanceTestLimit = FCC, 238 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825), 239 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800), 240 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805), 241 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 242 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 243 }, 244 245 {.regDmnEnum = FCC6, 246 .conformanceTestLimit = FCC, 247 .chan11a = BM5(F8_5180_5240, F5_5260_5320, F1_5500_5580, F2_5660_5720, F6_5745_5825), 248 .chan11a_turbo = BM3(T7_5210_5210, T3_5250_5290, T2_5760_5800), 249 .chan11a_dyn_turbo = BM4(T7_5200_5200, T1_5240_5240, T2_5280_5280, T1_5765_5805), 250 #if 0 251 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825), 252 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825), 253 #endif 254 }, 255 256 {.regDmnEnum = MKK1, 257 .conformanceTestLimit = MKK, 258 .pscan = PSCAN_MKK1, 259 .flags = DISALLOW_ADHOC_11A_TURB, 260 .chan11a = BM1(F1_5170_5230), 261 }, 262 263 {.regDmnEnum = MKK2, 264 .conformanceTestLimit = MKK, 265 .pscan = PSCAN_MKK2, 266 .flags = DISALLOW_ADHOC_11A_TURB, 267 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230), 268 .chan11a_half = BM4(F1_4915_4925, 269 F1_4935_4945, 270 F1_5035_5040, 271 F1_5055_5055), 272 }, 273 274 /* UNI-1 even */ 275 {.regDmnEnum = MKK3, 276 .conformanceTestLimit = MKK, 277 .pscan = PSCAN_MKK3, 278 .flags = DISALLOW_ADHOC_11A_TURB, 279 .chan11a = BM1(F4_5180_5240), 280 }, 281 282 /* UNI-1 even + UNI-2 */ 283 {.regDmnEnum = MKK4, 284 .conformanceTestLimit = MKK, 285 .dfsMask = DFS_MKK4, 286 .pscan = PSCAN_MKK3, 287 .flags = DISALLOW_ADHOC_11A_TURB, 288 .chan11a = BM2(F4_5180_5240, F2_5260_5320), 289 }, 290 291 /* UNI-1 even + UNI-2 + mid-band */ 292 {.regDmnEnum = MKK5, 293 .conformanceTestLimit = MKK, 294 .dfsMask = DFS_MKK4, 295 .pscan = PSCAN_MKK3, 296 .flags = DISALLOW_ADHOC_11A_TURB, 297 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700), 298 }, 299 300 /* UNI-1 odd + even */ 301 {.regDmnEnum = MKK6, 302 .conformanceTestLimit = MKK, 303 .pscan = PSCAN_MKK1, 304 .flags = DISALLOW_ADHOC_11A_TURB, 305 .chan11a = BM2(F2_5170_5230, F4_5180_5240), 306 }, 307 308 /* UNI-1 odd + UNI-1 even + UNI-2 */ 309 {.regDmnEnum = MKK7, 310 .conformanceTestLimit = MKK, 311 .dfsMask = DFS_MKK4, 312 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 313 .flags = DISALLOW_ADHOC_11A_TURB, 314 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320), 315 }, 316 317 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */ 318 {.regDmnEnum = MKK8, 319 .conformanceTestLimit = MKK, 320 .dfsMask = DFS_MKK4, 321 .pscan = PSCAN_MKK1 | PSCAN_MKK3, 322 .flags = DISALLOW_ADHOC_11A_TURB, 323 .chan11a = BM4(F1_5170_5230, 324 F4_5180_5240, 325 F2_5260_5320, 326 F4_5500_5700), 327 }, 328 329 /* UNI-1 even + 4.9 GHZ */ 330 {.regDmnEnum = MKK9, 331 .conformanceTestLimit = MKK, 332 .pscan = PSCAN_MKK3, 333 .flags = DISALLOW_ADHOC_11A_TURB, 334 .chan11a = BM7(F1_4915_4925, 335 F1_4935_4945, 336 F1_4920_4980, 337 F1_5035_5040, 338 F1_5055_5055, 339 F1_5040_5080, 340 F4_5180_5240), 341 }, 342 343 /* UNI-1 even + UNI-2 + 4.9 GHZ */ 344 {.regDmnEnum = MKK10, 345 .conformanceTestLimit = MKK, 346 .dfsMask = DFS_MKK4, 347 .pscan = PSCAN_MKK3, 348 .flags = DISALLOW_ADHOC_11A_TURB, 349 .chan11a = BM8(F1_4915_4925, 350 F1_4935_4945, 351 F1_4920_4980, 352 F1_5035_5040, 353 F1_5055_5055, 354 F1_5040_5080, 355 F4_5180_5240, 356 F2_5260_5320), 357 }, 358 359 /* Defined here to use when 2G channels are authorised for country K2 */ 360 {.regDmnEnum = APLD, 361 .conformanceTestLimit = NO_CTL, 362 .chan11b = BM2(F2_2312_2372,F2_2412_2472), 363 .chan11g = BM2(G2_2312_2372,G2_2412_2472), 364 }, 365 366 {.regDmnEnum = ETSIA, 367 .conformanceTestLimit = NO_CTL, 368 .pscan = PSCAN_ETSIA, 369 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 370 .chan11b = BM1(F1_2457_2472), 371 .chan11g = BM1(G1_2457_2472), 372 .chan11g_turbo = BM1(T2_2437_2437) 373 }, 374 375 {.regDmnEnum = ETSIB, 376 .conformanceTestLimit = ETSI, 377 .pscan = PSCAN_ETSIB, 378 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 379 .chan11b = BM1(F1_2432_2442), 380 .chan11g = BM1(G1_2432_2442), 381 .chan11g_turbo = BM1(T2_2437_2437) 382 }, 383 384 {.regDmnEnum = ETSIC, 385 .conformanceTestLimit = ETSI, 386 .pscan = PSCAN_ETSIC, 387 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, 388 .chan11b = BM1(F3_2412_2472), 389 .chan11g = BM1(G3_2412_2472), 390 .chan11g_turbo = BM1(T2_2437_2437) 391 }, 392 393 {.regDmnEnum = FCCA, 394 .conformanceTestLimit = FCC, 395 .chan11b = BM1(F1_2412_2462), 396 .chan11g = BM1(G1_2412_2462), 397 .chan11g_turbo = BM1(T2_2437_2437), 398 }, 399 400 /* FCCA w/ 1/2 and 1/4 width channels */ 401 {.regDmnEnum = FCCB, 402 .conformanceTestLimit = FCC, 403 .chan11b = BM1(F1_2412_2462), 404 .chan11g = BM1(G1_2412_2462), 405 .chan11g_turbo = BM1(T2_2437_2437), 406 .chan11g_half = BM1(G3_2412_2462), 407 .chan11g_quarter = BM1(G4_2412_2462), 408 }, 409 410 {.regDmnEnum = MKKA, 411 .conformanceTestLimit = MKK, 412 .pscan = PSCAN_MKKA | PSCAN_MKKA_G 413 | PSCAN_MKKA1 | PSCAN_MKKA1_G 414 | PSCAN_MKKA2 | PSCAN_MKKA2_G, 415 .flags = DISALLOW_ADHOC_11A_TURB, 416 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484), 417 .chan11g = BM2(G2_2412_2462, G1_2467_2472), 418 .chan11g_turbo = BM1(T2_2437_2437) 419 }, 420 421 {.regDmnEnum = MKKC, 422 .conformanceTestLimit = MKK, 423 .chan11b = BM1(F2_2412_2472), 424 .chan11g = BM1(G2_2412_2472), 425 .chan11g_turbo = BM1(T2_2437_2437) 426 }, 427 428 {.regDmnEnum = WORLD, 429 .conformanceTestLimit = ETSI, 430 .chan11b = BM1(F2_2412_2472), 431 .chan11g = BM1(G2_2412_2472), 432 .chan11g_turbo = BM1(T2_2437_2437) 433 }, 434 435 {.regDmnEnum = WOR0_WORLD, 436 .conformanceTestLimit = NO_CTL, 437 .dfsMask = DFS_FCC3 | DFS_ETSI, 438 .pscan = PSCAN_WWR, 439 .flags = ADHOC_PER_11D, 440 .chan11a = BM5(W1_5260_5320, 441 W1_5180_5240, 442 W1_5170_5230, 443 W1_5745_5825, 444 W1_5500_5700), 445 .chan11a_turbo = BM3(WT1_5210_5250, 446 WT1_5290_5290, 447 WT1_5760_5800), 448 .chan11b = BM8(W1_2412_2412, 449 W1_2437_2442, 450 W1_2462_2462, 451 W1_2472_2472, 452 W1_2417_2432, 453 W1_2447_2457, 454 W1_2467_2467, 455 W1_2484_2484), 456 .chan11g = BM7(WG1_2412_2412, 457 WG1_2437_2442, 458 WG1_2462_2462, 459 WG1_2472_2472, 460 WG1_2417_2432, 461 WG1_2447_2457, 462 WG1_2467_2467), 463 .chan11g_turbo = BM1(T3_2437_2437) 464 }, 465 466 {.regDmnEnum = WOR01_WORLD, 467 .conformanceTestLimit = NO_CTL, 468 .dfsMask = DFS_FCC3 | DFS_ETSI, 469 .pscan = PSCAN_WWR, 470 .flags = ADHOC_PER_11D, 471 .chan11a = BM5(W1_5260_5320, 472 W1_5180_5240, 473 W1_5170_5230, 474 W1_5745_5825, 475 W1_5500_5700), 476 .chan11a_turbo = BM3(WT1_5210_5250, 477 WT1_5290_5290, 478 WT1_5760_5800), 479 .chan11b = BM5(W1_2412_2412, 480 W1_2437_2442, 481 W1_2462_2462, 482 W1_2417_2432, 483 W1_2447_2457), 484 .chan11g = BM5(WG1_2412_2412, 485 WG1_2437_2442, 486 WG1_2462_2462, 487 WG1_2417_2432, 488 WG1_2447_2457), 489 .chan11g_turbo = BM1(T3_2437_2437)}, 490 491 {.regDmnEnum = WOR02_WORLD, 492 .conformanceTestLimit = NO_CTL, 493 .dfsMask = DFS_FCC3 | DFS_ETSI, 494 .pscan = PSCAN_WWR, 495 .flags = ADHOC_PER_11D, 496 .chan11a = BM5(W1_5260_5320, 497 W1_5180_5240, 498 W1_5170_5230, 499 W1_5745_5825, 500 W1_5500_5700), 501 .chan11a_turbo = BM3(WT1_5210_5250, 502 WT1_5290_5290, 503 WT1_5760_5800), 504 .chan11b = BM7(W1_2412_2412, 505 W1_2437_2442, 506 W1_2462_2462, 507 W1_2472_2472, 508 W1_2417_2432, 509 W1_2447_2457, 510 W1_2467_2467), 511 .chan11g = BM7(WG1_2412_2412, 512 WG1_2437_2442, 513 WG1_2462_2462, 514 WG1_2472_2472, 515 WG1_2417_2432, 516 WG1_2447_2457, 517 WG1_2467_2467), 518 .chan11g_turbo = BM1(T3_2437_2437)}, 519 520 {.regDmnEnum = EU1_WORLD, 521 .conformanceTestLimit = NO_CTL, 522 .dfsMask = DFS_FCC3 | DFS_ETSI, 523 .pscan = PSCAN_WWR, 524 .flags = ADHOC_PER_11D, 525 .chan11a = BM5(W1_5260_5320, 526 W1_5180_5240, 527 W1_5170_5230, 528 W1_5745_5825, 529 W1_5500_5700), 530 .chan11a_turbo = BM3(WT1_5210_5250, 531 WT1_5290_5290, 532 WT1_5760_5800), 533 .chan11b = BM7(W1_2412_2412, 534 W1_2437_2442, 535 W1_2462_2462, 536 W2_2472_2472, 537 W1_2417_2432, 538 W1_2447_2457, 539 W2_2467_2467), 540 .chan11g = BM7(WG1_2412_2412, 541 WG1_2437_2442, 542 WG1_2462_2462, 543 WG2_2472_2472, 544 WG1_2417_2432, 545 WG1_2447_2457, 546 WG2_2467_2467), 547 .chan11g_turbo = BM1(T3_2437_2437)}, 548 549 {.regDmnEnum = WOR1_WORLD, 550 .conformanceTestLimit = NO_CTL, 551 .dfsMask = DFS_FCC3 | DFS_ETSI, 552 .pscan = PSCAN_WWR, 553 .flags = DISALLOW_ADHOC_11A, 554 .chan11a = BM5(W1_5260_5320, 555 W1_5180_5240, 556 W1_5170_5230, 557 W1_5745_5825, 558 W1_5500_5700), 559 .chan11b = BM8(W1_2412_2412, 560 W1_2437_2442, 561 W1_2462_2462, 562 W1_2472_2472, 563 W1_2417_2432, 564 W1_2447_2457, 565 W1_2467_2467, 566 W1_2484_2484), 567 .chan11g = BM7(WG1_2412_2412, 568 WG1_2437_2442, 569 WG1_2462_2462, 570 WG1_2472_2472, 571 WG1_2417_2432, 572 WG1_2447_2457, 573 WG1_2467_2467), 574 .chan11g_turbo = BM1(T3_2437_2437) 575 }, 576 577 {.regDmnEnum = WOR2_WORLD, 578 .conformanceTestLimit = NO_CTL, 579 .dfsMask = DFS_FCC3 | DFS_ETSI, 580 .pscan = PSCAN_WWR, 581 .flags = DISALLOW_ADHOC_11A, 582 .chan11a = BM5(W1_5260_5320, 583 W1_5180_5240, 584 W1_5170_5230, 585 W1_5745_5825, 586 W1_5500_5700), 587 .chan11a_turbo = BM3(WT1_5210_5250, 588 WT1_5290_5290, 589 WT1_5760_5800), 590 .chan11b = BM8(W1_2412_2412, 591 W1_2437_2442, 592 W1_2462_2462, 593 W1_2472_2472, 594 W1_2417_2432, 595 W1_2447_2457, 596 W1_2467_2467, 597 W1_2484_2484), 598 .chan11g = BM7(WG1_2412_2412, 599 WG1_2437_2442, 600 WG1_2462_2462, 601 WG1_2472_2472, 602 WG1_2417_2432, 603 WG1_2447_2457, 604 WG1_2467_2467), 605 .chan11g_turbo = BM1(T3_2437_2437)}, 606 607 {.regDmnEnum = WOR3_WORLD, 608 .conformanceTestLimit = NO_CTL, 609 .dfsMask = DFS_FCC3 | DFS_ETSI, 610 .pscan = PSCAN_WWR, 611 .flags = ADHOC_PER_11D, 612 .chan11a = BM4(W1_5260_5320, 613 W1_5180_5240, 614 W1_5170_5230, 615 W1_5745_5825), 616 .chan11a_turbo = BM3(WT1_5210_5250, 617 WT1_5290_5290, 618 WT1_5760_5800), 619 .chan11b = BM7(W1_2412_2412, 620 W1_2437_2442, 621 W1_2462_2462, 622 W1_2472_2472, 623 W1_2417_2432, 624 W1_2447_2457, 625 W1_2467_2467), 626 .chan11g = BM7(WG1_2412_2412, 627 WG1_2437_2442, 628 WG1_2462_2462, 629 WG1_2472_2472, 630 WG1_2417_2432, 631 WG1_2447_2457, 632 WG1_2467_2467), 633 .chan11g_turbo = BM1(T3_2437_2437)}, 634 635 {.regDmnEnum = WOR4_WORLD, 636 .conformanceTestLimit = NO_CTL, 637 .dfsMask = DFS_FCC3 | DFS_ETSI, 638 .pscan = PSCAN_WWR, 639 .flags = DISALLOW_ADHOC_11A, 640 .chan11a = BM4(W2_5260_5320, 641 W2_5180_5240, 642 F2_5745_5805, 643 W2_5825_5825), 644 .chan11a_turbo = BM3(WT1_5210_5250, 645 WT1_5290_5290, 646 WT1_5760_5800), 647 .chan11b = BM5(W1_2412_2412, 648 W1_2437_2442, 649 W1_2462_2462, 650 W1_2417_2432, 651 W1_2447_2457), 652 .chan11g = BM5(WG1_2412_2412, 653 WG1_2437_2442, 654 WG1_2462_2462, 655 WG1_2417_2432, 656 WG1_2447_2457), 657 .chan11g_turbo = BM1(T3_2437_2437)}, 658 659 {.regDmnEnum = WOR5_ETSIC, 660 .conformanceTestLimit = NO_CTL, 661 .dfsMask = DFS_FCC3 | DFS_ETSI, 662 .pscan = PSCAN_WWR, 663 .flags = DISALLOW_ADHOC_11A, 664 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825), 665 .chan11b = BM7(W1_2412_2412, 666 W1_2437_2442, 667 W1_2462_2462, 668 W2_2472_2472, 669 W1_2417_2432, 670 W1_2447_2457, 671 W2_2467_2467), 672 .chan11g = BM7(WG1_2412_2412, 673 WG1_2437_2442, 674 WG1_2462_2462, 675 WG2_2472_2472, 676 WG1_2417_2432, 677 WG1_2447_2457, 678 WG2_2467_2467), 679 .chan11g_turbo = BM1(T3_2437_2437)}, 680 681 {.regDmnEnum = WOR9_WORLD, 682 .conformanceTestLimit = NO_CTL, 683 .dfsMask = DFS_FCC3 | DFS_ETSI, 684 .pscan = PSCAN_WWR, 685 .flags = DISALLOW_ADHOC_11A, 686 .chan11a = BM4(W1_5260_5320, 687 W1_5180_5240, 688 W1_5745_5825, 689 W1_5500_5700), 690 .chan11a_turbo = BM3(WT1_5210_5250, 691 WT1_5290_5290, 692 WT1_5760_5800), 693 .chan11b = BM5(W1_2412_2412, 694 W1_2437_2442, 695 W1_2462_2462, 696 W1_2417_2432, 697 W1_2447_2457), 698 .chan11g = BM5(WG1_2412_2412, 699 WG1_2437_2442, 700 WG1_2462_2462, 701 WG1_2417_2432, 702 WG1_2447_2457), 703 .chan11g_turbo = BM1(T3_2437_2437)}, 704 705 {.regDmnEnum = WORA_WORLD, 706 .conformanceTestLimit = NO_CTL, 707 .dfsMask = DFS_FCC3 | DFS_ETSI, 708 .pscan = PSCAN_WWR, 709 .flags = DISALLOW_ADHOC_11A, 710 .chan11a = BM4(W1_5260_5320, 711 W1_5180_5240, 712 W1_5745_5825, 713 W1_5500_5700), 714 .chan11b = BM7(W1_2412_2412, 715 W1_2437_2442, 716 W1_2462_2462, 717 W1_2472_2472, 718 W1_2417_2432, 719 W1_2447_2457, 720 W1_2467_2467), 721 .chan11g = BM7(WG1_2412_2412, 722 WG1_2437_2442, 723 WG1_2462_2462, 724 WG1_2472_2472, 725 WG1_2417_2432, 726 WG1_2447_2457, 727 WG1_2467_2467), 728 .chan11g_turbo = BM1(T3_2437_2437)}, 729 730 {.regDmnEnum = WORB_WORLD, 731 .conformanceTestLimit = NO_CTL, 732 .dfsMask = DFS_FCC3 | DFS_ETSI, 733 .pscan = PSCAN_WWR, 734 .flags = DISALLOW_ADHOC_11A, 735 .chan11a = BM4(W1_5260_5320, 736 W1_5180_5240, 737 W1_5745_5825, 738 W1_5500_5700), 739 .chan11b = BM7(W1_2412_2412, 740 W1_2437_2442, 741 W1_2462_2462, 742 W1_2472_2472, 743 W1_2417_2432, 744 W1_2447_2457, 745 W1_2467_2467), 746 .chan11g = BM7(WG1_2412_2412, 747 WG1_2437_2442, 748 WG1_2462_2462, 749 WG1_2472_2472, 750 WG1_2417_2432, 751 WG1_2447_2457, 752 WG1_2467_2467), 753 .chan11g_turbo = BM1(T3_2437_2437)}, 754 755 {.regDmnEnum = WORC_WORLD, 756 .conformanceTestLimit = NO_CTL, 757 .dfsMask = DFS_FCC3 | DFS_ETSI, 758 .pscan = PSCAN_WWR, 759 .flags = ADHOC_PER_11D, 760 .chan11a = BM4(W1_5260_5320, 761 W1_5180_5240, 762 W1_5745_5825, 763 W1_5500_5700), 764 .chan11b = BM7(W1_2412_2412, 765 W1_2437_2442, 766 W1_2462_2462, 767 W1_2472_2472, 768 W1_2417_2432, 769 W1_2447_2457, 770 W1_2467_2467), 771 .chan11g = BM7(WG1_2412_2412, 772 WG1_2437_2442, 773 WG1_2462_2462, 774 WG1_2472_2472, 775 WG1_2417_2432, 776 WG1_2447_2457, 777 WG1_2467_2467), 778 .chan11g_turbo = BM1(T3_2437_2437)}, 779 780 {.regDmnEnum = NULL1, 781 .conformanceTestLimit = NO_CTL, 782 } 783 }; 784 785 #endif 786