1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2005-2006 Atheros Communications, Inc. 4 * All rights reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD$ 19 */ 20 21 #ifndef __AH_REGDOMAIN_FREQBANDS_H__ 22 #define __AH_REGDOMAIN_FREQBANDS_H__ 23 24 #define AFTER(x) ((x)+1) 25 26 /* 27 * Frequency band collections are defined using bitmasks. Each bit 28 * in a mask is the index of an entry in one of the following tables. 29 * Bitmasks are BMLEN*64 bits so if a table grows beyond that the bit 30 * vectors must be enlarged or the tables split somehow (e.g. split 31 * 1/2 and 1/4 rate channels into a separate table). 32 * 33 * Beware of ordering; the indices are defined relative to the preceding 34 * entry so if things get off there will be confusion. A good way to 35 * check the indices is to collect them in a switch statement in a stub 36 * function so the compiler checks for duplicates. 37 */ 38 39 /* 40 * 5GHz 11A channel tags 41 */ 42 static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { 43 { 4915, 4925, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 44 #define F1_4915_4925 0 45 { 4935, 4945, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 46 #define F1_4935_4945 AFTER(F1_4915_4925) 47 { 4920, 4980, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 48 #define F1_4920_4980 AFTER(F1_4935_4945) 49 { 4942, 4987, 27, 6, 5, 5, NO_DFS, PSCAN_FCC }, 50 #define F1_4942_4987 AFTER(F1_4920_4980) 51 { 4945, 4985, 30, 6, 10, 5, NO_DFS, PSCAN_FCC }, 52 #define F1_4945_4985 AFTER(F1_4942_4987) 53 { 4950, 4980, 33, 6, 20, 5, NO_DFS, PSCAN_FCC }, 54 #define F1_4950_4980 AFTER(F1_4945_4985) 55 { 5035, 5040, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 56 #define F1_5035_5040 AFTER(F1_4950_4980) 57 { 5040, 5080, 23, 0, 20, 20, NO_DFS, PSCAN_MKK2 }, 58 #define F1_5040_5080 AFTER(F1_5035_5040) 59 { 5055, 5055, 23, 0, 10, 5, NO_DFS, PSCAN_MKK2 }, 60 #define F1_5055_5055 AFTER(F1_5040_5080) 61 62 { 5120, 5240, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 63 #define F1_5120_5240 AFTER(F1_5055_5055) 64 { 5120, 5240, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 65 #define F2_5120_5240 AFTER(F1_5120_5240) 66 { 5120, 5240, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 67 #define F3_5120_5240 AFTER(F2_5120_5240) 68 69 { 5170, 5230, 23, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 70 #define F1_5170_5230 AFTER(F3_5120_5240) 71 { 5170, 5230, 20, 0, 20, 20, NO_DFS, PSCAN_MKK1 | PSCAN_MKK2 }, 72 #define F2_5170_5230 AFTER(F1_5170_5230) 73 74 { 5180, 5240, 15, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 75 #define F1_5180_5240 AFTER(F2_5170_5230) 76 { 5180, 5240, 17, 6, 20, 20, NO_DFS, PSCAN_FCC }, 77 #define F2_5180_5240 AFTER(F1_5180_5240) 78 { 5180, 5240, 18, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 79 #define F3_5180_5240 AFTER(F2_5180_5240) 80 { 5180, 5240, 20, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 81 #define F4_5180_5240 AFTER(F3_5180_5240) 82 { 5180, 5240, 23, 0, 20, 20, NO_DFS, PSCAN_FCC | PSCAN_ETSI }, 83 #define F5_5180_5240 AFTER(F4_5180_5240) 84 { 5180, 5240, 23, 6, 20, 20, NO_DFS, PSCAN_FCC }, 85 #define F6_5180_5240 AFTER(F5_5180_5240) 86 { 5180, 5240, 17, 6, 20, 10, NO_DFS, PSCAN_FCC }, 87 #define F7_5180_5240 AFTER(F6_5180_5240) 88 { 5180, 5240, 17, 6, 20, 5, NO_DFS, PSCAN_FCC }, 89 #define F8_5180_5240 AFTER(F7_5180_5240) 90 { 5180, 5320, 20, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 91 92 #define F1_5180_5320 AFTER(F8_5180_5240) 93 { 5240, 5280, 23, 0, 20, 20, DFS_FCC3, PSCAN_FCC | PSCAN_ETSI }, 94 95 #define F1_5240_5280 AFTER(F1_5180_5320) 96 { 5260, 5280, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 97 98 #define F1_5260_5280 AFTER(F1_5240_5280) 99 { 5260, 5320, 18, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 100 101 #define F1_5260_5320 AFTER(F1_5260_5280) 102 { 5260, 5320, 20, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_FCC | PSCAN_ETSI | PSCAN_MKK3 }, 103 #define F2_5260_5320 AFTER(F1_5260_5320) 104 105 { 5260, 5320, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 106 #define F3_5260_5320 AFTER(F2_5260_5320) 107 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 108 #define F4_5260_5320 AFTER(F3_5260_5320) 109 { 5260, 5320, 23, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 110 #define F5_5260_5320 AFTER(F4_5260_5320) 111 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 112 #define F6_5260_5320 AFTER(F5_5260_5320) 113 { 5260, 5320, 23, 6, 20, 10, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 114 #define F7_5260_5320 AFTER(F6_5260_5320) 115 { 5260, 5320, 23, 6, 20, 5, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 116 #define F8_5260_5320 AFTER(F7_5260_5320) 117 118 { 5260, 5700, 5, 6, 20, 20, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 119 #define F1_5260_5700 AFTER(F8_5260_5320) 120 { 5260, 5700, 5, 6, 10, 10, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 121 #define F2_5260_5700 AFTER(F1_5260_5700) 122 { 5260, 5700, 5, 6, 5, 5, DFS_FCC3 | DFS_ETSI, NO_PSCAN }, 123 #define F3_5260_5700 AFTER(F2_5260_5700) 124 125 { 5280, 5320, 17, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 126 #define F1_5280_5320 AFTER(F3_5260_5700) 127 128 { 5500, 5620, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 129 #define F1_5500_5620 AFTER(F1_5280_5320) 130 131 { 5500, 5700, 20, 6, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC }, 132 #define F1_5500_5700 AFTER(F1_5500_5620) 133 { 5500, 5700, 27, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 134 #define F2_5500_5700 AFTER(F1_5500_5700) 135 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_FCC | PSCAN_ETSI }, 136 #define F3_5500_5700 AFTER(F2_5500_5700) 137 { 5500, 5700, 23, 0, 20, 20, DFS_FCC3 | DFS_ETSI | DFS_MKK4, PSCAN_MKK3 | PSCAN_FCC }, 138 #define F4_5500_5700 AFTER(F3_5500_5700) 139 140 { 5745, 5805, 23, 0, 20, 20, NO_DFS, NO_PSCAN }, 141 #define F1_5745_5805 AFTER(F4_5500_5700) 142 { 5745, 5805, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 143 #define F2_5745_5805 AFTER(F1_5745_5805) 144 { 5745, 5805, 30, 6, 20, 20, DFS_ETSI, PSCAN_ETSI }, 145 #define F3_5745_5805 AFTER(F2_5745_5805) 146 { 5745, 5825, 5, 6, 20, 20, NO_DFS, NO_PSCAN }, 147 #define F1_5745_5825 AFTER(F3_5745_5805) 148 { 5745, 5825, 17, 0, 20, 20, NO_DFS, NO_PSCAN }, 149 #define F2_5745_5825 AFTER(F1_5745_5825) 150 { 5745, 5825, 20, 0, 20, 20, NO_DFS, NO_PSCAN }, 151 #define F3_5745_5825 AFTER(F2_5745_5825) 152 { 5745, 5825, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 153 #define F4_5745_5825 AFTER(F3_5745_5825) 154 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 155 #define F5_5745_5825 AFTER(F4_5745_5825) 156 { 5745, 5825, 30, 6, 20, 20, NO_DFS, NO_PSCAN }, 157 #define F6_5745_5825 AFTER(F5_5745_5825) 158 { 5745, 5825, 5, 6, 10, 10, NO_DFS, NO_PSCAN }, 159 #define F7_5745_5825 AFTER(F6_5745_5825) 160 { 5745, 5825, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 161 #define F8_5745_5825 AFTER(F7_5745_5825) 162 { 5745, 5825, 30, 6, 20, 10, NO_DFS, NO_PSCAN }, 163 #define F9_5745_5825 AFTER(F8_5745_5825) 164 { 5745, 5825, 30, 6, 20, 5, NO_DFS, NO_PSCAN }, 165 #define F10_5745_5825 AFTER(F9_5745_5825) 166 167 /* 168 * Below are the world roaming channels 169 * All WWR domains have no power limit, instead use the card's CTL 170 * or max power settings. 171 */ 172 { 4920, 4980, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 173 #define W1_4920_4980 AFTER(F10_5745_5825) 174 { 5040, 5080, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 175 #define W1_5040_5080 AFTER(W1_4920_4980) 176 { 5170, 5230, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 177 #define W1_5170_5230 AFTER(W1_5040_5080) 178 { 5180, 5240, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 179 #define W1_5180_5240 AFTER(W1_5170_5230) 180 { 5260, 5320, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 181 #define W1_5260_5320 AFTER(W1_5180_5240) 182 { 5745, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 183 #define W1_5745_5825 AFTER(W1_5260_5320) 184 { 5500, 5700, 30, 0, 20, 20, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 185 #define W1_5500_5700 AFTER(W1_5745_5825) 186 { 5260, 5320, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 187 #define W2_5260_5320 AFTER(W1_5500_5700) 188 { 5180, 5240, 30, 0, 20, 20, NO_DFS, NO_PSCAN }, 189 #define W2_5180_5240 AFTER(W2_5260_5320) 190 { 5825, 5825, 30, 0, 20, 20, NO_DFS, PSCAN_WWR }, 191 #define W2_5825_5825 AFTER(W2_5180_5240) 192 }; 193 194 /* 195 * 5GHz Turbo (dynamic & static) tags 196 */ 197 static REG_DMN_FREQ_BAND regDmn5GhzTurboFreq[] = { 198 { 5130, 5210, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 199 #define T1_5130_5210 0 200 { 5250, 5330, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 201 #define T1_5250_5330 AFTER(T1_5130_5210) 202 { 5370, 5490, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 203 #define T1_5370_5490 AFTER(T1_5250_5330) 204 { 5530, 5650, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 205 #define T1_5530_5650 AFTER(T1_5370_5490) 206 207 { 5150, 5190, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 208 #define T1_5150_5190 AFTER(T1_5530_5650) 209 { 5230, 5310, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 210 #define T1_5230_5310 AFTER(T1_5150_5190) 211 { 5350, 5470, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 212 #define T1_5350_5470 AFTER(T1_5230_5310) 213 { 5510, 5670, 5, 6, 40, 40, DFS_FCC3, NO_PSCAN }, 214 #define T1_5510_5670 AFTER(T1_5350_5470) 215 216 { 5200, 5240, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 217 #define T1_5200_5240 AFTER(T1_5510_5670) 218 { 5200, 5240, 23, 6, 40, 40, NO_DFS, NO_PSCAN }, 219 #define T2_5200_5240 AFTER(T1_5200_5240) 220 { 5210, 5210, 17, 6, 40, 40, NO_DFS, NO_PSCAN }, 221 #define T1_5210_5210 AFTER(T2_5200_5240) 222 { 5210, 5210, 23, 0, 40, 40, NO_DFS, NO_PSCAN }, 223 #define T2_5210_5210 AFTER(T1_5210_5210) 224 225 { 5280, 5280, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 226 #define T1_5280_5280 AFTER(T2_5210_5210) 227 { 5280, 5280, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 228 #define T2_5280_5280 AFTER(T1_5280_5280) 229 { 5250, 5250, 17, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 230 #define T1_5250_5250 AFTER(T2_5280_5280) 231 { 5290, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 232 #define T1_5290_5290 AFTER(T1_5250_5250) 233 { 5250, 5290, 20, 0, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 234 #define T1_5250_5290 AFTER(T1_5290_5290) 235 { 5250, 5290, 23, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 236 #define T2_5250_5290 AFTER(T1_5250_5290) 237 238 { 5540, 5660, 20, 6, 40, 40, DFS_FCC3, PSCAN_FCC_T }, 239 #define T1_5540_5660 AFTER(T2_5250_5290) 240 { 5760, 5800, 20, 0, 40, 40, NO_DFS, NO_PSCAN }, 241 #define T1_5760_5800 AFTER(T1_5540_5660) 242 { 5760, 5800, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 243 #define T2_5760_5800 AFTER(T1_5760_5800) 244 245 { 5765, 5805, 30, 6, 40, 40, NO_DFS, NO_PSCAN }, 246 #define T1_5765_5805 AFTER(T2_5760_5800) 247 248 /* 249 * Below are the WWR frequencies 250 */ 251 { 5210, 5250, 15, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 252 #define WT1_5210_5250 AFTER(T1_5765_5805) 253 { 5290, 5290, 18, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 254 #define WT1_5290_5290 AFTER(WT1_5210_5250) 255 { 5540, 5660, 20, 0, 40, 40, DFS_FCC3 | DFS_ETSI, PSCAN_WWR }, 256 #define WT1_5540_5660 AFTER(WT1_5290_5290) 257 { 5760, 5800, 20, 0, 40, 40, NO_DFS, PSCAN_WWR }, 258 #define WT1_5760_5800 AFTER(WT1_5540_5660) 259 }; 260 261 /* 262 * 2GHz 11b channel tags 263 */ 264 static REG_DMN_FREQ_BAND regDmn2GhzFreq[] = { 265 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 266 #define F1_2312_2372 0 267 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 268 #define F2_2312_2372 AFTER(F1_2312_2372) 269 270 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 271 #define F1_2412_2472 AFTER(F2_2312_2372) 272 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 273 #define F2_2412_2472 AFTER(F1_2412_2472) 274 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 275 #define F3_2412_2472 AFTER(F2_2412_2472) 276 277 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 278 #define F1_2412_2462 AFTER(F3_2412_2472) 279 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA }, 280 #define F2_2412_2462 AFTER(F1_2412_2462) 281 282 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 283 #define F1_2432_2442 AFTER(F2_2412_2462) 284 285 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 286 #define F1_2457_2472 AFTER(F1_2432_2442) 287 288 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 289 #define F1_2467_2472 AFTER(F1_2457_2472) 290 291 { 2484, 2484, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 292 #define F1_2484_2484 AFTER(F1_2467_2472) 293 { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA | PSCAN_MKKA1 | PSCAN_MKKA2 }, 294 #define F2_2484_2484 AFTER(F1_2484_2484) 295 296 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 297 #define F1_2512_2732 AFTER(F2_2484_2484) 298 299 /* 300 * WWR have powers opened up to 20dBm. 301 * Limits should often come from CTL/Max powers 302 */ 303 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 304 #define W1_2312_2372 AFTER(F1_2512_2732) 305 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 306 #define W1_2412_2412 AFTER(W1_2312_2372) 307 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 308 #define W1_2417_2432 AFTER(W1_2412_2412) 309 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 310 #define W1_2437_2442 AFTER(W1_2417_2432) 311 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 312 #define W1_2447_2457 AFTER(W1_2437_2442) 313 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 314 #define W1_2462_2462 AFTER(W1_2447_2457) 315 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 316 #define W1_2467_2467 AFTER(W1_2462_2462) 317 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 318 #define W2_2467_2467 AFTER(W1_2467_2467) 319 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 320 #define W1_2472_2472 AFTER(W2_2467_2467) 321 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 322 #define W2_2472_2472 AFTER(W1_2472_2472) 323 { 2484, 2484, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 324 #define W1_2484_2484 AFTER(W2_2472_2472) 325 { 2484, 2484, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 326 #define W2_2484_2484 AFTER(W1_2484_2484) 327 }; 328 329 /* 330 * 2GHz 11g channel tags 331 */ 332 static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { 333 { 2312, 2372, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 334 #define G1_2312_2372 0 335 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 336 #define G2_2312_2372 AFTER(G1_2312_2372) 337 { 2312, 2372, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 338 #define G3_2312_2372 AFTER(G2_2312_2372) 339 { 2312, 2372, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 340 #define G4_2312_2372 AFTER(G3_2312_2372) 341 342 { 2412, 2472, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 343 #define G1_2412_2472 AFTER(G4_2312_2372) 344 { 2412, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 345 #define G2_2412_2472 AFTER(G1_2412_2472) 346 { 2412, 2472, 30, 0, 20, 5, NO_DFS, NO_PSCAN }, 347 #define G3_2412_2472 AFTER(G2_2412_2472) 348 { 2412, 2472, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 349 #define G4_2412_2472 AFTER(G3_2412_2472) 350 { 2412, 2472, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 351 #define G5_2412_2472 AFTER(G4_2412_2472) 352 353 { 2412, 2462, 27, 6, 20, 5, NO_DFS, NO_PSCAN }, 354 #define G1_2412_2462 AFTER(G5_2412_2472) 355 { 2412, 2462, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA_G }, 356 #define G2_2412_2462 AFTER(G1_2412_2462) 357 { 2412, 2462, 27, 6, 10, 5, NO_DFS, NO_PSCAN }, 358 #define G3_2412_2462 AFTER(G2_2412_2462) 359 { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN }, 360 #define G4_2412_2462 AFTER(G3_2412_2462) 361 362 { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 363 #define G1_2432_2442 AFTER(G4_2412_2462) 364 365 { 2457, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 366 #define G1_2457_2472 AFTER(G1_2432_2442) 367 368 { 2512, 2732, 5, 6, 20, 5, NO_DFS, NO_PSCAN }, 369 #define G1_2512_2732 AFTER(G1_2457_2472) 370 { 2512, 2732, 5, 6, 10, 5, NO_DFS, NO_PSCAN }, 371 #define G2_2512_2732 AFTER(G1_2512_2732) 372 { 2512, 2732, 5, 6, 5, 5, NO_DFS, NO_PSCAN }, 373 #define G3_2512_2732 AFTER(G2_2512_2732) 374 375 { 2467, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_MKKA2 | PSCAN_MKKA }, 376 #define G1_2467_2472 AFTER(G3_2512_2732) 377 378 /* 379 * WWR open up the power to 20dBm 380 */ 381 { 2312, 2372, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 382 #define WG1_2312_2372 AFTER(G1_2467_2472) 383 { 2412, 2412, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 384 #define WG1_2412_2412 AFTER(WG1_2312_2372) 385 { 2417, 2432, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 386 #define WG1_2417_2432 AFTER(WG1_2412_2412) 387 { 2437, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 388 #define WG1_2437_2442 AFTER(WG1_2417_2432) 389 { 2447, 2457, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 390 #define WG1_2447_2457 AFTER(WG1_2437_2442) 391 { 2462, 2462, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, 392 #define WG1_2462_2462 AFTER(WG1_2447_2457) 393 { 2467, 2467, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 394 #define WG1_2467_2467 AFTER(WG1_2462_2462) 395 { 2467, 2467, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 396 #define WG2_2467_2467 AFTER(WG1_2467_2467) 397 { 2472, 2472, 20, 0, 20, 5, NO_DFS, PSCAN_WWR | IS_ECM_CHAN }, 398 #define WG1_2472_2472 AFTER(WG2_2467_2467) 399 { 2472, 2472, 20, 0, 20, 5, NO_DFS, NO_PSCAN | IS_ECM_CHAN }, 400 #define WG2_2472_2472 AFTER(WG1_2472_2472) 401 }; 402 403 /* 404 * 2GHz Dynamic turbo tags 405 */ 406 static REG_DMN_FREQ_BAND regDmn2Ghz11gTurboFreq[] = { 407 { 2312, 2372, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 408 #define T1_2312_2372 0 409 { 2437, 2437, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 410 #define T1_2437_2437 AFTER(T1_2312_2372) 411 { 2437, 2437, 20, 6, 40, 40, NO_DFS, NO_PSCAN }, 412 #define T2_2437_2437 AFTER(T1_2437_2437) 413 { 2437, 2437, 18, 6, 40, 40, NO_DFS, PSCAN_WWR }, 414 #define T3_2437_2437 AFTER(T2_2437_2437) 415 { 2512, 2732, 5, 6, 40, 40, NO_DFS, NO_PSCAN }, 416 #define T1_2512_2732 AFTER(T3_2437_2437) 417 }; 418 419 #endif 420