1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2004 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 #include "ah_desc.h" 24 25 #include "ar5210/ar5210.h" 26 #include "ar5210/ar5210reg.h" 27 #include "ar5210/ar5210desc.h" 28 29 /* 30 * Return the hardware NextTBTT in TSF 31 */ 32 uint64_t 33 ar5210GetNextTBTT(struct ath_hal *ah) 34 { 35 #define TU_TO_TSF(_tu) (((uint64_t)(_tu)) << 10) 36 return TU_TO_TSF(OS_REG_READ(ah, AR_TIMER0)); 37 #undef TU_TO_TSF 38 } 39 40 /* 41 * Initialize all of the hardware registers used to send beacons. 42 */ 43 void 44 ar5210SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt) 45 { 46 47 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt); 48 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba); 49 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba); 50 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim); 51 /* 52 * Set the Beacon register after setting all timers. 53 */ 54 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval); 55 } 56 57 /* 58 * Legacy api to Initialize all of the beacon registers. 59 */ 60 void 61 ar5210BeaconInit(struct ath_hal *ah, 62 uint32_t next_beacon, uint32_t beacon_period) 63 { 64 HAL_BEACON_TIMERS bt; 65 66 bzero(&bt, sizeof(bt)); 67 bt.bt_nexttbtt = next_beacon; 68 69 if (AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) { 70 bt.bt_nextdba = (next_beacon - 71 ah->ah_config.ah_dma_beacon_response_time) << 3; /* 1/8 TU */ 72 bt.bt_nextswba = (next_beacon - 73 ah->ah_config.ah_sw_beacon_response_time) << 3; /* 1/8 TU */ 74 /* 75 * The SWBA interrupt is not used for beacons in ad hoc mode 76 * as we don't yet support ATIMs. So since the beacon never 77 * changes, the beacon descriptor is set up once and read 78 * into a special HW buffer, from which it will be 79 * automagically retrieved at each DMA Beacon Alert (DBA). 80 */ 81 82 /* Set the ATIM window */ 83 bt.bt_nextatim = next_beacon + 0; /* NB: no ATIMs */ 84 } else { 85 bt.bt_nextdba = ~0; 86 bt.bt_nextswba = ~0; 87 bt.bt_nextatim = 1; 88 } 89 bt.bt_intval = beacon_period & 90 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN); 91 ar5210SetBeaconTimers(ah, &bt); 92 } 93 94 void 95 ar5210ResetStaBeaconTimers(struct ath_hal *ah) 96 { 97 uint32_t val; 98 99 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */ 100 val = OS_REG_READ(ah, AR_STA_ID1); 101 val |= AR_STA_ID1_NO_PSPOLL; /* XXX */ 102 /* tell the h/w that the associated AP is not PCF capable */ 103 OS_REG_WRITE(ah, AR_STA_ID1, 104 val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 105 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD); 106 } 107 108 /* 109 * Set all the beacon related bits on the h/w for stations 110 * i.e. initializes the corresponding h/w timers; 111 * also tells the h/w whether to anticipate PCF beacons 112 * 113 * dtim_count and cfp_count from the current beacon - their current 114 * values aren't necessarily maintained in the device struct 115 */ 116 void 117 ar5210SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) 118 { 119 struct ath_hal_5210 *ahp = AH5210(ah); 120 121 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__); 122 123 HALASSERT(bs->bs_intval != 0); 124 /* if the AP will do PCF */ 125 if (bs->bs_cfpmaxduration != 0) { 126 /* tell the h/w that the associated AP is PCF capable */ 127 OS_REG_WRITE(ah, AR_STA_ID1, 128 (OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_DEFAULT_ANTENNA) 129 | AR_STA_ID1_PCF); 130 131 /* set CFP_PERIOD(1.024ms) register */ 132 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod); 133 134 /* set CFP_DUR(1.024ms) register to max cfp duration */ 135 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration); 136 137 /* set TIMER2(128us) to anticipated time of next CFP */ 138 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3); 139 } else { 140 /* tell the h/w that the associated AP is not PCF capable */ 141 OS_REG_WRITE(ah, AR_STA_ID1, 142 OS_REG_READ(ah, AR_STA_ID1) &~ (AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF)); 143 } 144 145 /* 146 * Set TIMER0(1.024ms) to the anticipated time of the next beacon. 147 */ 148 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt); 149 150 /* 151 * Start the beacon timers by setting the BEACON register 152 * to the beacon interval; also write the tim offset which 153 * we should know by now. The code, in ar5211WriteAssocid, 154 * also sets the tim offset once the AID is known which can 155 * be left as such for now. 156 */ 157 OS_REG_WRITE(ah, AR_BEACON, 158 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM)) 159 | SM(bs->bs_intval, AR_BEACON_PERIOD) 160 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM) 161 ); 162 163 /* 164 * Configure the BMISS interrupt. Note that we 165 * assume the caller blocks interrupts while enabling 166 * the threshold. 167 */ 168 169 /* 170 * Interrupt works only on Crete. 171 */ 172 if (AH_PRIVATE(ah)->ah_macRev < AR_SREV_CRETE) 173 return; 174 /* 175 * Counter is only 3-bits. 176 * Count of 0 with BMISS interrupt enabled will hang the system 177 * with too many interrupts 178 */ 179 if (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_CRETE && 180 (bs->bs_bmissthreshold&7) == 0) { 181 #ifdef AH_DEBUG 182 ath_hal_printf(ah, "%s: invalid beacon miss threshold %u\n", 183 __func__, bs->bs_bmissthreshold); 184 #endif 185 return; 186 } 187 #define BMISS_MAX (AR_RSSI_THR_BM_THR >> AR_RSSI_THR_BM_THR_S) 188 /* 189 * Configure the BMISS interrupt. Note that we 190 * assume the caller blocks interrupts while enabling 191 * the threshold. 192 * 193 * NB: the beacon miss count field is only 3 bits which 194 * is much smaller than what's found on later parts; 195 * clamp overflow values as a safeguard. 196 */ 197 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR) 198 | SM(bs->bs_bmissthreshold > BMISS_MAX ? 199 BMISS_MAX : bs->bs_bmissthreshold, 200 AR_RSSI_THR_BM_THR); 201 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 202 #undef BMISS_MAX 203 } 204