1 /* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2004 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD$ 18 */ 19 #include "opt_ah.h" 20 21 #include "ah.h" 22 #include "ah_internal.h" 23 24 #include "ar5210/ar5210.h" 25 #include "ar5210/ar5210reg.h" 26 #include "ar5210/ar5210phy.h" 27 28 #include "ah_eeprom_v1.h" 29 30 #define AR_NUM_GPIO 6 /* 6 GPIO bits */ 31 #define AR_GPIOD_MASK 0x2f /* 6-bit mask */ 32 33 void 34 ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac) 35 { 36 struct ath_hal_5210 *ahp = AH5210(ah); 37 38 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 39 } 40 41 HAL_BOOL 42 ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac) 43 { 44 struct ath_hal_5210 *ahp = AH5210(ah); 45 46 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 47 return AH_TRUE; 48 } 49 50 void 51 ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask) 52 { 53 static const uint8_t ones[IEEE80211_ADDR_LEN] = 54 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 55 OS_MEMCPY(mask, ones, IEEE80211_ADDR_LEN); 56 } 57 58 HAL_BOOL 59 ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask) 60 { 61 return AH_FALSE; 62 } 63 64 /* 65 * Read 16 bits of data from the specified EEPROM offset. 66 */ 67 HAL_BOOL 68 ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data) 69 { 70 (void) OS_REG_READ(ah, AR_EP_AIR(off)); /* activate read op */ 71 if (!ath_hal_wait(ah, AR_EP_STA, 72 AR_EP_STA_RDCMPLT | AR_EP_STA_RDERR, AR_EP_STA_RDCMPLT)) { 73 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n", 74 __func__, AR_EP_AIR(off)); 75 return AH_FALSE; 76 } 77 *data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff; 78 return AH_TRUE; 79 } 80 81 #ifdef AH_SUPPORT_WRITE_EEPROM 82 /* 83 * Write 16 bits of data to the specified EEPROM offset. 84 */ 85 HAL_BOOL 86 ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data) 87 { 88 return AH_FALSE; 89 } 90 #endif /* AH_SUPPORT_WRITE_EEPROM */ 91 92 /* 93 * Attempt to change the cards operating regulatory domain to the given value 94 */ 95 HAL_BOOL 96 ar5210SetRegulatoryDomain(struct ath_hal *ah, 97 uint16_t regDomain, HAL_STATUS *status) 98 { 99 HAL_STATUS ecode; 100 101 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) { 102 ecode = HAL_EINVAL; 103 goto bad; 104 } 105 /* 106 * Check if EEPROM is configured to allow this; must 107 * be a proper version and the protection bits must 108 * permit re-writing that segment of the EEPROM. 109 */ 110 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) { 111 ecode = HAL_EEWRITE; 112 goto bad; 113 } 114 ecode = HAL_EIO; /* disallow all writes */ 115 bad: 116 if (status) 117 *status = ecode; 118 return AH_FALSE; 119 } 120 121 /* 122 * Return the wireless modes (a,b,g,t) supported by hardware. 123 * 124 * This value is what is actually supported by the hardware 125 * and is unaffected by regulatory/country code settings. 126 * 127 */ 128 u_int 129 ar5210GetWirelessModes(struct ath_hal *ah) 130 { 131 /* XXX could enable turbo mode but can't do all rates */ 132 return HAL_MODE_11A; 133 } 134 135 /* 136 * Called if RfKill is supported (according to EEPROM). Set the interrupt and 137 * GPIO values so the ISR and can disable RF on a switch signal 138 */ 139 void 140 ar5210EnableRfKill(struct ath_hal *ah) 141 { 142 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent; 143 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL); 144 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY); 145 146 /* 147 * If radio disable switch connection to GPIO bit 0 is enabled 148 * program GPIO interrupt. 149 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 150 * verified that it is a later version of eeprom, it has a place for 151 * rfkill bit and it is set to 1, indicating that GPIO bit 0 hardware 152 * connection is present. 153 */ 154 ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity)); 155 } 156 157 /* 158 * Configure GPIO Output lines 159 */ 160 HAL_BOOL 161 ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) 162 { 163 HALASSERT(gpio < AR_NUM_GPIO); 164 165 OS_REG_WRITE(ah, AR_GPIOCR, 166 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio)) 167 | AR_GPIOCR_OUT1(gpio)); 168 169 return AH_TRUE; 170 } 171 172 /* 173 * Configure GPIO Input lines 174 */ 175 HAL_BOOL 176 ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio) 177 { 178 HALASSERT(gpio < AR_NUM_GPIO); 179 180 OS_REG_WRITE(ah, AR_GPIOCR, 181 (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio)) 182 | AR_GPIOCR_IN(gpio)); 183 184 return AH_TRUE; 185 } 186 187 /* 188 * Once configured for I/O - set output lines 189 */ 190 HAL_BOOL 191 ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val) 192 { 193 uint32_t reg; 194 195 HALASSERT(gpio < AR_NUM_GPIO); 196 197 reg = OS_REG_READ(ah, AR_GPIODO); 198 reg &= ~(1 << gpio); 199 reg |= (val&1) << gpio; 200 201 OS_REG_WRITE(ah, AR_GPIODO, reg); 202 return AH_TRUE; 203 } 204 205 /* 206 * Once configured for I/O - get input lines 207 */ 208 uint32_t 209 ar5210GpioGet(struct ath_hal *ah, uint32_t gpio) 210 { 211 if (gpio < AR_NUM_GPIO) { 212 uint32_t val = OS_REG_READ(ah, AR_GPIODI); 213 val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1; 214 return val; 215 } else { 216 return 0xffffffff; 217 } 218 } 219 220 /* 221 * Set the GPIO 0 Interrupt 222 */ 223 void 224 ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) 225 { 226 uint32_t val = OS_REG_READ(ah, AR_GPIOCR); 227 228 /* Clear the bits that we will modify. */ 229 val &= ~(AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_SELH | AR_GPIOCR_INT_ENA | 230 AR_GPIOCR_ALL(gpio)); 231 232 val |= AR_GPIOCR_INT_SEL(gpio) | AR_GPIOCR_INT_ENA; 233 if (ilevel) 234 val |= AR_GPIOCR_INT_SELH; 235 236 /* Don't need to change anything for low level interrupt. */ 237 OS_REG_WRITE(ah, AR_GPIOCR, val); 238 239 /* Change the interrupt mask. */ 240 ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO); 241 } 242 243 /* 244 * Change the LED blinking pattern to correspond to the connectivity 245 */ 246 void 247 ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state) 248 { 249 uint32_t val; 250 251 val = OS_REG_READ(ah, AR_PCICFG); 252 switch (state) { 253 case HAL_LED_INIT: 254 val &= ~(AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT); 255 break; 256 case HAL_LED_RUN: 257 /* normal blink when connected */ 258 val &= ~AR_PCICFG_LED_PEND; 259 val |= AR_PCICFG_LED_ACT; 260 break; 261 default: 262 val |= AR_PCICFG_LED_PEND; 263 val &= ~AR_PCICFG_LED_ACT; 264 break; 265 } 266 OS_REG_WRITE(ah, AR_PCICFG, val); 267 } 268 269 /* 270 * Return 1 or 2 for the corresponding antenna that is in use 271 */ 272 u_int 273 ar5210GetDefAntenna(struct ath_hal *ah) 274 { 275 uint32_t val = OS_REG_READ(ah, AR_STA_ID1); 276 return (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1); 277 } 278 279 void 280 ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna) 281 { 282 uint32_t val = OS_REG_READ(ah, AR_STA_ID1); 283 284 if (antenna != (val & AR_STA_ID1_DEFAULT_ANTENNA ? 2 : 1)) { 285 /* 286 * Antenna change requested, force a toggle of the default. 287 */ 288 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA); 289 } 290 } 291 292 HAL_ANT_SETTING 293 ar5210GetAntennaSwitch(struct ath_hal *ah) 294 { 295 return HAL_ANT_VARIABLE; 296 } 297 298 HAL_BOOL 299 ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 300 { 301 /* XXX not sure how to fix antenna */ 302 return (settings == HAL_ANT_VARIABLE); 303 } 304 305 /* 306 * Change association related fields programmed into the hardware. 307 * Writing a valid BSSID to the hardware effectively enables the hardware 308 * to synchronize its TSF to the correct beacons and receive frames coming 309 * from that BSSID. It is called by the SME JOIN operation. 310 */ 311 void 312 ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId) 313 { 314 struct ath_hal_5210 *ahp = AH5210(ah); 315 316 /* XXX save bssid for possible re-use on reset */ 317 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 318 ahp->ah_associd = assocId; 319 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 320 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | 321 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S)); 322 if (assocId == 0) 323 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL); 324 else 325 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL); 326 } 327 328 /* 329 * Get the current hardware tsf for stamlme. 330 */ 331 uint64_t 332 ar5210GetTsf64(struct ath_hal *ah) 333 { 334 uint32_t low1, low2, u32; 335 336 /* sync multi-word read */ 337 low1 = OS_REG_READ(ah, AR_TSF_L32); 338 u32 = OS_REG_READ(ah, AR_TSF_U32); 339 low2 = OS_REG_READ(ah, AR_TSF_L32); 340 if (low2 < low1) { /* roll over */ 341 /* 342 * If we are not preempted this will work. If we are 343 * then we re-reading AR_TSF_U32 does no good as the 344 * low bits will be meaningless. Likewise reading 345 * L32, U32, U32, then comparing the last two reads 346 * to check for rollover doesn't help if preempted--so 347 * we take this approach as it costs one less PCI 348 * read which can be noticeable when doing things 349 * like timestamping packets in monitor mode. 350 */ 351 u32++; 352 } 353 return (((uint64_t) u32) << 32) | ((uint64_t) low2); 354 } 355 356 /* 357 * Get the current hardware tsf for stamlme. 358 */ 359 uint32_t 360 ar5210GetTsf32(struct ath_hal *ah) 361 { 362 return OS_REG_READ(ah, AR_TSF_L32); 363 } 364 365 /* 366 * Reset the current hardware tsf for stamlme 367 */ 368 void 369 ar5210ResetTsf(struct ath_hal *ah) 370 { 371 uint32_t val = OS_REG_READ(ah, AR_BEACON); 372 373 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); 374 } 375 376 /* 377 * Grab a semi-random value from hardware registers - may not 378 * change often 379 */ 380 uint32_t 381 ar5210GetRandomSeed(struct ath_hal *ah) 382 { 383 uint32_t nf; 384 385 nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff; 386 if (nf & 0x100) 387 nf = 0 - ((nf ^ 0x1ff) + 1); 388 return (OS_REG_READ(ah, AR_TSF_U32) ^ 389 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 390 } 391 392 /* 393 * Detect if our card is present 394 */ 395 HAL_BOOL 396 ar5210DetectCardPresent(struct ath_hal *ah) 397 { 398 /* 399 * Read the Silicon Revision register and compare that 400 * to what we read at attach time. If the same, we say 401 * a card/device is present. 402 */ 403 return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff)); 404 } 405 406 /* 407 * Update MIB Counters 408 */ 409 void 410 ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats) 411 { 412 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 413 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 414 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 415 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 416 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 417 } 418 419 HAL_BOOL 420 ar5210SetSifsTime(struct ath_hal *ah, u_int us) 421 { 422 struct ath_hal_5210 *ahp = AH5210(ah); 423 424 if (us > ath_hal_mac_usec(ah, 0x7ff)) { 425 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n", 426 __func__, us); 427 ahp->ah_sifstime = (u_int) -1; /* restore default handling */ 428 return AH_FALSE; 429 } else { 430 /* convert to system clocks */ 431 OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS, 432 ath_hal_mac_clks(ah, us)); 433 ahp->ah_sifstime = us; 434 return AH_TRUE; 435 } 436 } 437 438 u_int 439 ar5210GetSifsTime(struct ath_hal *ah) 440 { 441 u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff; 442 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 443 } 444 445 HAL_BOOL 446 ar5210SetSlotTime(struct ath_hal *ah, u_int us) 447 { 448 struct ath_hal_5210 *ahp = AH5210(ah); 449 450 if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) { 451 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n", 452 __func__, us); 453 ahp->ah_slottime = (u_int) -1; /* restore default handling */ 454 return AH_FALSE; 455 } else { 456 /* convert to system clocks */ 457 OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us)); 458 ahp->ah_slottime = us; 459 return AH_TRUE; 460 } 461 } 462 463 u_int 464 ar5210GetSlotTime(struct ath_hal *ah) 465 { 466 u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff; 467 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 468 } 469 470 HAL_BOOL 471 ar5210SetAckTimeout(struct ath_hal *ah, u_int us) 472 { 473 struct ath_hal_5210 *ahp = AH5210(ah); 474 475 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 476 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n", 477 __func__, us); 478 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */ 479 return AH_FALSE; 480 } else { 481 /* convert to system clocks */ 482 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, 483 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us)); 484 ahp->ah_acktimeout = us; 485 return AH_TRUE; 486 } 487 } 488 489 u_int 490 ar5210GetAckTimeout(struct ath_hal *ah) 491 { 492 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 493 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 494 } 495 496 u_int 497 ar5210GetAckCTSRate(struct ath_hal *ah) 498 { 499 return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0); 500 } 501 502 HAL_BOOL 503 ar5210SetAckCTSRate(struct ath_hal *ah, u_int high) 504 { 505 struct ath_hal_5210 *ahp = AH5210(ah); 506 507 if (high) { 508 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); 509 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB; 510 } else { 511 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); 512 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB; 513 } 514 return AH_TRUE; 515 } 516 517 HAL_BOOL 518 ar5210SetCTSTimeout(struct ath_hal *ah, u_int us) 519 { 520 struct ath_hal_5210 *ahp = AH5210(ah); 521 522 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 523 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n", 524 __func__, us); 525 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */ 526 return AH_FALSE; 527 } else { 528 /* convert to system clocks */ 529 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, 530 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us)); 531 ahp->ah_ctstimeout = us; 532 return AH_TRUE; 533 } 534 } 535 536 u_int 537 ar5210GetCTSTimeout(struct ath_hal *ah) 538 { 539 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); 540 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ 541 } 542 543 HAL_BOOL 544 ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) 545 { 546 /* nothing to do */ 547 return AH_TRUE; 548 } 549 550 void 551 ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) 552 { 553 } 554 555 /* 556 * Control Adaptive Noise Immunity Parameters 557 */ 558 HAL_BOOL 559 ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) 560 { 561 return AH_FALSE; 562 } 563 564 void 565 ar5210RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats, 566 const struct ieee80211_channel *chan) 567 { 568 } 569 570 void 571 ar5210AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan) 572 { 573 } 574 575 void 576 ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats) 577 { 578 } 579 580 HAL_STATUS 581 ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 582 uint32_t capability, uint32_t *result) 583 { 584 585 switch (type) { 586 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 587 #if 0 588 return (capability == HAL_CIPHER_WEP ? HAL_OK : HAL_ENOTSUPP); 589 #else 590 return HAL_ENOTSUPP; 591 #endif 592 default: 593 return ath_hal_getcapability(ah, type, capability, result); 594 } 595 } 596 597 HAL_BOOL 598 ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 599 uint32_t capability, uint32_t setting, HAL_STATUS *status) 600 { 601 602 switch (type) { 603 case HAL_CAP_DIAG: /* hardware diagnostic support */ 604 /* 605 * NB: could split this up into virtual capabilities, 606 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 607 * seems worth the additional complexity. 608 */ 609 #ifdef AH_DEBUG 610 AH_PRIVATE(ah)->ah_diagreg = setting; 611 #else 612 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 613 #endif 614 ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg); 615 return AH_TRUE; 616 case HAL_CAP_RXORN_FATAL: /* HAL_INT_RXORN treated as fatal */ 617 return AH_FALSE; /* NB: disallow */ 618 default: 619 return ath_hal_setcapability(ah, type, capability, 620 setting, status); 621 } 622 } 623 624 HAL_BOOL 625 ar5210GetDiagState(struct ath_hal *ah, int request, 626 const void *args, uint32_t argsize, 627 void **result, uint32_t *resultsize) 628 { 629 #ifdef AH_PRIVATE_DIAG 630 uint32_t pcicfg; 631 HAL_BOOL ok; 632 633 switch (request) { 634 case HAL_DIAG_EEPROM: 635 /* XXX */ 636 break; 637 case HAL_DIAG_EEREAD: 638 if (argsize != sizeof(uint16_t)) 639 return AH_FALSE; 640 pcicfg = OS_REG_READ(ah, AR_PCICFG); 641 OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL); 642 ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result); 643 OS_REG_WRITE(ah, AR_PCICFG, pcicfg); 644 if (ok) 645 *resultsize = sizeof(uint16_t); 646 return ok; 647 } 648 #endif 649 return ath_hal_getdiagstate(ah, request, 650 args, argsize, result, resultsize); 651 } 652 653 /* 654 * Return what percentage of the extension channel is busy. 655 * This is always disabled for AR5210 series NICs. 656 */ 657 uint32_t 658 ar5210Get11nExtBusy(struct ath_hal *ah) 659 { 660 661 return (0); 662 } 663 664 /* 665 * There's no channel survey support for the AR5210. 666 */ 667 HAL_BOOL 668 ar5210GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) 669 { 670 671 return (AH_FALSE); 672 } 673 674 void 675 ar5210SetChainMasks(struct ath_hal *ah, uint32_t txchainmask, 676 uint32_t rxchainmask) 677 { 678 } 679 680 void 681 ar5210EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 682 { 683 } 684 685 void 686 ar5210GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) 687 { 688 } 689 690 /* 691 * Update the diagnostic register. 692 * 693 * This merges in the diagnostic register setting with the default 694 * value, which may or may not involve disabling hardware encryption. 695 */ 696 void 697 ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val) 698 { 699 700 /* Disable all hardware encryption */ 701 val |= AR_DIAG_SW_DIS_CRYPTO; 702 OS_REG_WRITE(ah, AR_DIAG_SW, val); 703 } 704